ralink: fix rcu_sched stalls on mt7621

there were 2 bugs
*) core1 came up with a bad bogo mips, looks like the clock needed time to stabilize
*) HPT frequency was not set making r4k timers not come up properly

Backport of 9551d91b1d6 "ralink: fix rcu_sched stalls on mt7621".

Signed-off-by: John Crispin <john@phrozen.org>

diff --git a/target/linux/ramips/patches-4.4/101-mt7621-timer.patch b/target/linux/ramips/patches-4.4/101-mt7621-timer.patch
new file mode 100644 (file)
index 0000000..02497bc
--- /dev/null
+++ b/target/linux/ramips/patches-4.4/101-mt7621-timer.patch
@@ -0,0 +1,98 @@
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -18,6 +18,7 @@
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/mt7621.h>
+ #include <asm/mips-boards/launch.h>
++#include <asm/delay.h>
+ 
+ #include <pinmux.h>
+ 
+@@ -179,6 +180,58 @@ bool plat_cpu_core_present(int core)
+       return true;
+ }
+ 
++#define LPS_PREC 8
++/*
++*  Re-calibration lpj(loop-per-jiffy).
++*  (derived from kernel/calibrate.c)
++*/
++static int udelay_recal(void)
++{
++      unsigned int i, lpj = 0;
++      unsigned long ticks, loopbit;
++      int lps_precision = LPS_PREC;
++
++      lpj = (1<<12);
++
++      while ((lpj <<= 1) != 0) {
++              /* wait for "start of" clock tick */
++              ticks = jiffies;
++              while (ticks == jiffies)
++                      /* nothing */;
++
++              /* Go .. */
++              ticks = jiffies;
++              __delay(lpj);
++              ticks = jiffies - ticks;
++              if (ticks)
++                      break;
++      }
++
++      /*
++       * Do a binary approximation to get lpj set to
++       * equal one clock (up to lps_precision bits)
++       */
++      lpj >>= 1;
++      loopbit = lpj;
++      while (lps_precision-- && (loopbit >>= 1)) {
++              lpj |= loopbit;
++              ticks = jiffies;
++              while (ticks == jiffies)
++                      /* nothing */;
++              ticks = jiffies;
++              __delay(lpj);
++              if (jiffies != ticks)   /* longer than 1 tick */
++                      lpj &= ~loopbit;
++      }
++      printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
++
++      for(i=0; i< NR_CPUS; i++)
++              cpu_data[i].udelay_val = lpj;
++
++      return 0;
++}
++device_initcall(udelay_recal);
++
+ void prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+       void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -56,6 +56,7 @@ choice
+               select COMMON_CLK
+               select CLKSRC_MIPS_GIC
+               select HW_HAS_PCI
++              select GENERIC_CLOCKEVENTS_BROADCAST
+ endchoice
+ 
+ choice
+--- a/arch/mips/ralink/timer-gic.c
++++ b/arch/mips/ralink/timer-gic.c
+@@ -12,6 +12,7 @@
+ #include <linux/of.h>
+ #include <linux/clk-provider.h>
+ #include <linux/clocksource.h>
++#include <asm/time.h>
+ 
+ #include "common.h"
+ 
+@@ -19,6 +20,8 @@ void __init plat_time_init(void)
+ {
+       ralink_of_remap();
+ 
++      mips_hpt_frequency = 880000000 / 2;
++
+       of_clk_init(NULL);
+       clocksource_probe();
+ }