--- /dev/null
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __PLAT_CONFIG_H__
+#define __PLAT_CONFIG_H__
+
+#define CONFIG_GICC_BASE_OFFSET 0x4
+
+
+#ifndef __ASSEMBLY__
+
+#include <cassert.h>
+
+
+enum plat_config_flags {
+ /* Whether CPUECTLR SMP bit should be enabled */
+ CONFIG_CPUECTLR_SMP_BIT = 0x1,
+ /* Whether Base FVP memory map is in use */
+ CONFIG_BASE_MMAP = 0x2,
+ /* Whether CCI should be enabled */
+ CONFIG_HAS_CCI = 0x4,
+ /* Whether TZC should be configured */
+ CONFIG_HAS_TZC = 0x8
+};
+
+typedef struct plat_config {
+ unsigned int gicd_base;
+ unsigned int gicc_base;
+ unsigned int gich_base;
+ unsigned int gicv_base;
+ unsigned int max_aff0;
+ unsigned int max_aff1;
+ unsigned long flags;
+} plat_config_t;
+
+inline const plat_config_t *get_plat_config();
+
+
+CASSERT(CONFIG_GICC_BASE_OFFSET == __builtin_offsetof(
+ plat_config_t, gicc_base),
+ assert_gicc_base_offset_mismatch);
+
+/* If used, plat_config must be defined and populated in the platform port*/
+extern plat_config_t plat_config;
+
+inline const plat_config_t *get_plat_config()
+{
+ return &plat_config;
+}
+
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __PLAT_CONFIG_H__ */
#include <debug.h>
#include <mmio.h>
#include <platform.h>
+#include <plat_config.h>
#include <xlat_tables.h>
#include "../fvp_def.h"
/*******************************************************************************
- * This array holds the characteristics of the differences between the three
+ * plat_config holds the characteristics of the differences between the three
* FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
* boot at each boot stage by the primary before enabling the MMU (to allow cci
* configuration) & used thereafter. Each BL will have its own copy to allow
* independent operation.
******************************************************************************/
-static unsigned long fvp_config[CONFIG_LIMIT];
+plat_config_t plat_config;
/*
* Table of regions to map using the MMU.
DEFINE_CONFIGURE_MMU_EL(1)
DEFINE_CONFIGURE_MMU_EL(3)
-/* Simple routine which returns a configuration variable value */
-unsigned long fvp_get_cfgvar(unsigned int var_id)
-{
- assert(var_id < CONFIG_LIMIT);
- return fvp_config[var_id];
-}
-
/*******************************************************************************
* A single boot loader stack is expected to work on both the Foundation FVP
* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
*/
switch (bld) {
case BLD_GIC_VE_MMAP:
- fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
- fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
- fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
- fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
+ plat_config.gicd_base = VE_GICD_BASE;
+ plat_config.gicc_base = VE_GICC_BASE;
+ plat_config.gich_base = VE_GICH_BASE;
+ plat_config.gicv_base = VE_GICV_BASE;
break;
case BLD_GIC_A53A57_MMAP:
- fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
- fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
- fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
- fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
+ plat_config.gicd_base = BASE_GICD_BASE;
+ plat_config.gicc_base = BASE_GICC_BASE;
+ plat_config.gich_base = BASE_GICH_BASE;
+ plat_config.gicv_base = BASE_GICV_BASE;
break;
default:
ERROR("Unsupported board build %x\n", bld);
*/
switch (hbi) {
case HBI_FOUNDATION:
- fvp_config[CONFIG_MAX_AFF0] = 4;
- fvp_config[CONFIG_MAX_AFF1] = 1;
- fvp_config[CONFIG_CPU_SETUP] = 0;
- fvp_config[CONFIG_BASE_MMAP] = 0;
- fvp_config[CONFIG_HAS_CCI] = 0;
- fvp_config[CONFIG_HAS_TZC] = 0;
+ plat_config.max_aff0 = 4;
+ plat_config.max_aff1 = 1;
+ plat_config.flags = 0;
/*
* Check for supported revisions of Foundation FVP
break;
case HBI_FVP_BASE:
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
- if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
- fvp_config[CONFIG_CPU_SETUP] = 1;
- else
- fvp_config[CONFIG_CPU_SETUP] = 0;
+ plat_config.flags =
+ ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
+ ? CONFIG_CPUECTLR_SMP_BIT : 0;
- fvp_config[CONFIG_MAX_AFF0] = 4;
- fvp_config[CONFIG_MAX_AFF1] = 2;
- fvp_config[CONFIG_BASE_MMAP] = 1;
- fvp_config[CONFIG_HAS_CCI] = 1;
- fvp_config[CONFIG_HAS_TZC] = 1;
+ plat_config.max_aff0 = 4;
+ plat_config.max_aff1 = 2;
+ plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
+ CONFIG_HAS_TZC;
/*
* Check for supported revisions
void fvp_cci_setup(void)
{
- unsigned long cci_setup;
-
/*
* Enable CCI-400 for this cluster. No need
* for locks as no other cpu is active at the
* moment
*/
- cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
- if (cci_setup)
+ if (plat_config.flags & CONFIG_HAS_CCI)
cci_enable_coherency(read_mpidr());
}
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
-/* Constants for accessing platform configuration */
-#define CONFIG_GICD_ADDR 0
-#define CONFIG_GICC_ADDR 1
-#define CONFIG_GICH_ADDR 2
-#define CONFIG_GICV_ADDR 3
-#define CONFIG_MAX_AFF0 4
-#define CONFIG_MAX_AFF1 5
-/* Indicate whether the CPUECTLR SMP bit should be enabled. */
-#define CONFIG_CPU_SETUP 6
-#define CONFIG_BASE_MMAP 7
-/* Indicates whether CCI should be enabled on the platform. */
-#define CONFIG_HAS_CCI 8
-#define CONFIG_HAS_TZC 9
-#define CONFIG_LIMIT 10
-
/*******************************************************************************
* FVP memory map related constants
******************************************************************************/
#include <gic_v3.h>
#include <interrupt_mgmt.h>
#include <platform.h>
+#include <plat_config.h>
#include <stdint.h>
#include "fvp_def.h"
#include "fvp_private.h"
void gic_setup(void)
{
- unsigned int gicd_base, gicc_base;
-
- gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
- gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
-
- gic_cpuif_setup(gicc_base);
- gic_distif_setup(gicd_base);
+ gic_cpuif_setup(get_plat_config()->gicc_base);
+ gic_distif_setup(get_plat_config()->gicd_base);
}
/*******************************************************************************
******************************************************************************/
uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
{
- uint32_t gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
+ uint32_t gicc_base = get_plat_config()->gicc_base;
assert(type == INTR_TYPE_S_EL1 ||
type == INTR_TYPE_EL3 ||
******************************************************************************/
uint32_t plat_ic_get_pending_interrupt_type(void)
{
- uint32_t id, gicc_base;
+ uint32_t id;
- gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
- id = gicc_read_hppir(gicc_base);
+ id = gicc_read_hppir(get_plat_config()->gicc_base);
/* Assume that all secure interrupts are S-EL1 interrupts */
if (id < 1022)
{
uint32_t id, gicc_base;
- gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = get_plat_config()->gicc_base;
id = gicc_read_hppir(gicc_base);
if (id < 1022)
******************************************************************************/
uint32_t plat_ic_acknowledge_interrupt(void)
{
- return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
+ return gicc_read_IAR(get_plat_config()->gicc_base);
}
/*******************************************************************************
******************************************************************************/
void plat_ic_end_of_interrupt(uint32_t id)
{
- gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id);
+ gicc_write_EOIR(get_plat_config()->gicc_base, id);
return;
}
{
uint32_t group;
- group = gicd_get_igroupr(fvp_get_cfgvar(CONFIG_GICD_ADDR), id);
+ group = gicd_get_igroupr(get_plat_config()->gicd_base, id);
/* Assume that all secure interrupts are S-EL1 interrupts */
if (group == GRP0)
#include <cci400.h>
#include <mmio.h>
#include <platform.h>
+#include <plat_config.h>
#include <platform_def.h>
#include <psci.h>
#include "drivers/pwrc/fvp_pwrc.h"
{
int rc = PSCI_E_SUCCESS;
unsigned int gicc_base, ectlr;
- unsigned long cpu_setup, cci_setup;
switch (afflvl) {
case MPIDR_AFFLVL1:
* Disable coherency if this cluster is to be
* turned off
*/
- cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
- if (cci_setup) {
+ if (get_plat_config()->flags & CONFIG_HAS_CCI)
cci_disable_coherency(mpidr);
- }
/*
* Program the power controller to turn the
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
- cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
- if (cpu_setup) {
+ if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
write_cpuectlr(ectlr);
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = get_plat_config()->gicc_base;
gic_cpuif_deactivate(gicc_base);
/*
{
int rc = PSCI_E_SUCCESS;
unsigned int gicc_base, ectlr;
- unsigned long cpu_setup, cci_setup, linear_id;
+ unsigned long linear_id;
mailbox_t *fvp_mboxes;
switch (afflvl) {
* Disable coherency if this cluster is to be
* turned off
*/
- cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
- if (cci_setup) {
+ if (get_plat_config()->flags & CONFIG_HAS_CCI)
cci_disable_coherency(mpidr);
- }
/*
* Program the power controller to turn the
* Take this cpu out of intra-cluster coherency if
* the FVP flavour supports the SMP bit.
*/
- cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
- if (cpu_setup) {
+ if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
ectlr = read_cpuectlr();
ectlr &= ~CPUECTLR_SMP_BIT;
write_cpuectlr(ectlr);
* Prevent interrupts from spuriously waking up
* this cpu
*/
- gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
+ gicc_base = get_plat_config()->gicc_base;
gic_cpuif_deactivate(gicc_base);
/*
unsigned int state)
{
int rc = PSCI_E_SUCCESS;
- unsigned long linear_id, cpu_setup;
+ unsigned long linear_id;
mailbox_t *fvp_mboxes;
unsigned int gicd_base, gicc_base, ectlr;
* Turn on intra-cluster coherency if the FVP flavour supports
* it.
*/
- cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
- if (cpu_setup) {
+ if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
ectlr = read_cpuectlr();
ectlr |= CPUECTLR_SMP_BIT;
write_cpuectlr(ectlr);
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
- gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
- gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
-
/* Enable the gic cpu interface */
+ gicc_base = get_plat_config()->gicc_base;
gic_cpuif_setup(gicc_base);
/* TODO: This setup is needed only after a cold boot */
+ gicd_base = get_plat_config()->gicd_base;
gic_pcpu_distif_setup(gicd_base);
break;
unsigned long,
unsigned long,
unsigned long);
-unsigned long fvp_get_cfgvar(unsigned int);
int fvp_config_setup(void);
void fvp_cci_setup(void);
#include <assert.h>
#include <debug.h>
+#include <plat_config.h>
#include <tzc400.h>
#include "fvp_def.h"
#include "fvp_private.h"
* configurations, those would be configured here.
*/
- if (!fvp_get_cfgvar(CONFIG_HAS_TZC))
+ if (!(get_plat_config()->flags & CONFIG_HAS_TZC))
return;
/*
*/
#include <gic_v2.h>
-#include "../fvp_def.h"
+#include <plat_config.h>
.section .rodata.gic_reg_name, "aS"
gic_regs: .asciz "gic_iar", "gic_ctlr", ""
* ---------------------------------------------
*/
.macro plat_print_gic_regs
- mov x0, #CONFIG_GICC_ADDR
- bl fvp_get_cfgvar
+ adr x0, plat_config;
+ ldr w0, [x0, #CONFIG_GICC_BASE_OFFSET]
/* gic base address is now in x0 */
ldr w1, [x0, #GICC_IAR]
ldr w2, [x0, #GICC_CTLR]
projects / project / bcm63xx / atf.git / commitdiff