drm/amd/display: Add unknown clk state.
authorYongqiang Sun <yongqiang.sun@amd.com>
Thu, 26 Sep 2019 18:08:41 +0000 (14:08 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 25 Oct 2019 20:50:07 +0000 (16:50 -0400)
[Why]
System hang during S0i3 if DP only connected due to clk is disabled when
doing link training.
During S0i3, clk is disabled while the clk state is updated when ini_hw
called, and at the moment clk is still disabled which indicating a wrong
state for next time trying to enable clk.

[How]
Add an unknown state and initialize it during int_hw, make sure enable clk
command be sent to smu.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
drivers/gpu/drm/amd/display/dc/dc.h

index b647e0320e4bf964c16dce9e0a22b1fde3f6762b..6212b407cd01c060b0710dd1b1af7d2f210cbe4d 100644 (file)
@@ -114,22 +114,22 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
         */
        if (safe_to_lower) {
                /* check that we're not already in lower */
-               if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_OPTIMIZED) {
+               if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 
                        display_count = rn_get_active_display_cnt_wa(dc, context);
                        /* if we can go lower, go lower */
                        if (display_count == 0) {
-                               rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_OPTIMIZED);
+                               rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
                                /* update power state */
-                               clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_OPTIMIZED;
+                               clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
                        }
                }
        } else {
-               /* check that we're not already in the normal state */
-               if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_NORMAL) {
-                       rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_NORMAL);
+               /* check that we're not already in D0 */
+               if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
+                       rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
                        /* update power state */
-                       clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_NORMAL;
+                       clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
                }
        }
 
@@ -393,7 +393,7 @@ void rn_init_clocks(struct clk_mgr *clk_mgr)
        // Assumption is that boot state always supports pstate
        clk_mgr->clks.p_state_change_support = true;
        clk_mgr->clks.prev_p_state_change_support = true;
-       clk_mgr->clks.pwr_state = DCN_PWR_STATE_NORMAL;
+       clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 }
 
 static struct clk_mgr_funcs dcn21_funcs = {
index 5647fcf10717089054ac79047feec679f372fe10..cb7c0e8b7e1b01379b591ac757a8f915bb38dcf6 100644 (file)
@@ -170,7 +170,7 @@ void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum
 {
        int disp_count;
 
-       if (state == DCN_PWR_STATE_OPTIMIZED)
+       if (state == DCN_PWR_STATE_LOW_POWER)
                disp_count = 0;
        else
                disp_count = 1;
index b7e7181bad78530c8515783250e5f663942716ea..2e1d34882684390b1ea3c4896dea8bc48c5999c8 100644 (file)
@@ -257,8 +257,9 @@ enum dtm_pstate{
 };
 
 enum dcn_pwr_state {
-       DCN_PWR_STATE_OPTIMIZED = 0,
-       DCN_PWR_STATE_NORMAL = 1
+       DCN_PWR_STATE_UNKNOWN = -1,
+       DCN_PWR_STATE_MISSION_MODE = 0,
+       DCN_PWR_STATE_LOW_POWER = 3,
 };
 
 /*