drm/i915: set phase sync pointer override enable before setting phase sync pointer

We need to unlock the phase sync pointer enable bit before we can
actually enable the phase sync pointer workaround on Ironlake.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 53ddacc907b98817a08d0dfe1d01050db834d4ba..e6b106bb87b6e951ae8e0778e7cf76263c208ae1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3005,7 +3005,8 @@
 
 #define FDI_RXA_CHICKEN         0xc200c
 #define FDI_RXB_CHICKEN         0xc2010
-#define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)
+#define  FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
+#define  FDI_RX_PHASE_SYNC_POINTER_EN  (1<<0)
 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)
 
 #define SOUTH_DSPCLK_GATE_D    0xc2020

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aee2abae81ec10f7558baaa8f39c0ebb9dd2dd9b..2842dbe3ec0d3c2ca6209c25959f85443600b607 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2273,7 +2273,11 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
        udelay(150);
 
        /* Ironlake workaround, enable clock pointer after FDI enable*/
-       I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
+       if (HAS_PCH_IBX(dev)) {
+               I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
+               I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
+                          FDI_RX_PHASE_SYNC_POINTER_EN);
+       }
 
        reg = FDI_RX_IIR(pipe);
        for (tries = 0; tries < 5; tries++) {
@@ -2516,10 +2520,12 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
        udelay(100);
 
        /* Ironlake workaround, disable clock pointer after downing FDI */
-       if (HAS_PCH_IBX(dev))
+       if (HAS_PCH_IBX(dev)) {
+               I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
                I915_WRITE(FDI_RX_CHICKEN(pipe),
                           I915_READ(FDI_RX_CHICKEN(pipe) &
-                                    ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
+                                    ~FDI_RX_PHASE_SYNC_POINTER_EN));
+       }
 
        /* still set train pattern 1 */
        reg = FDI_TX_CTL(pipe);