omap4: Properly enable USB PHY clocks

This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 1cc20728ee8382b63f1b4b9a321844a7cdb1639a..02c06c157760853a35684aa6099500e7077a74df 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -380,6 +380,10 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
                        USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
 
+       /* Enable 32 KHz clock for USB PHY */
+       setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
+                       USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
        do_enable_clocks(clk_domains_essential,
                         clk_modules_hw_auto_essential,
                         clk_modules_explicit_en_essential,

diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c
index a09581e55b7e6aa75bb2dd051fd81ab0d13375d5..2f0e1e851ac1ed46bde8e4234aea4ece808e6f54 100644 (file)
--- a/arch/arm/cpu/armv7/omap4/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c
@@ -129,6 +129,7 @@ struct prcm_regs const omap4_prcm = {
        .cm_div_m2_dpll_unipro = 0x4a0081d0,
        .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
        .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+       .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
 
        /* cm2.core */
        .cm_l3_1_clkstctrl = 0x4a008700,

diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h
index f3a682a19715675b0c5ad9ef202df7145d7dcc3c..a408c0cd411dd5b220a4918b55fcbe8af387718c 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/clock.h
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -134,8 +134,11 @@
 /* CM_DSS_DSS_CLKCTRL */
 #define DSS_CLKCTRL_OPTFCLKEN_MASK             0xF00
 
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K   (1 << 8)
+
 /* CM_L3INIT_USBPHY_CLKCTRL */
-#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK  8
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK  (1 << 8)
 
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24