const enum omap_display_type *ports;
int num_ports;
const struct dss_ops *ops;
+ struct dss_reg_field dispc_clk_switch;
};
static struct {
static void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
{
int b;
- u8 start, end;
/*
* We always use PRCM clock as the DISPC func clock, except on DSS3,
return;
}
- dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
-
- REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
+ REG_FLD_MOD(DSS_CONTROL, b, /* DISPC_CLK_SWITCH */
+ dss.feat->dispc_clk_switch.start,
+ dss.feat->dispc_clk_switch.end);
dss.dispc_clk_source = clk_src;
}
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
.ops = &dss_ops_omap2_omap3,
+ .dispc_clk_switch = { 0, 0 },
};
static const struct dss_features omap34xx_dss_feats = {
.ports = omap34xx_ports,
.num_ports = ARRAY_SIZE(omap34xx_ports),
.ops = &dss_ops_omap2_omap3,
+ .dispc_clk_switch = { 0, 0 },
};
static const struct dss_features omap3630_dss_feats = {
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
.ops = &dss_ops_omap2_omap3,
+ .dispc_clk_switch = { 0, 0 },
};
static const struct dss_features omap44xx_dss_feats = {
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
.ops = &dss_ops_omap4,
+ .dispc_clk_switch = { 9, 8 },
};
static const struct dss_features omap54xx_dss_feats = {
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
.ops = &dss_ops_omap5,
+ .dispc_clk_switch = { 9, 7 },
};
static const struct dss_features am43xx_dss_feats = {
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
.ops = &dss_ops_omap2_omap3,
+ .dispc_clk_switch = { 0, 0 },
};
static const struct dss_features dra7xx_dss_feats = {
.ports = dra7xx_ports,
.num_ports = ARRAY_SIZE(dra7xx_ports),
.ops = &dss_ops_dra7,
+ .dispc_clk_switch = { 9, 7 },
};
static int dss_init_ports(struct platform_device *pdev)
#include "dss.h"
#include "dss_features.h"
-/* Defines a generic omap register field */
-struct dss_reg_field {
- u8 start, end;
-};
-
struct dss_param_range {
int min, max;
};
[FEAT_REG_FIFOSIZE] = { 8, 0 },
[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
[FEAT_REG_VERTICALACCU] = { 25, 16 },
- [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
};
static const struct dss_reg_field omap3_dss_reg_fields[] = {
[FEAT_REG_FIFOSIZE] = { 10, 0 },
[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
[FEAT_REG_VERTICALACCU] = { 25, 16 },
- [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
};
static const struct dss_reg_field am43xx_dss_reg_fields[] = {
[FEAT_REG_FIFOSIZE] = { 10, 0 },
[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
[FEAT_REG_VERTICALACCU] = { 25, 16 },
- [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
};
static const struct dss_reg_field omap4_dss_reg_fields[] = {
[FEAT_REG_FIFOSIZE] = { 15, 0 },
[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
[FEAT_REG_VERTICALACCU] = { 26, 16 },
- [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
};
static const struct dss_reg_field omap5_dss_reg_fields[] = {
[FEAT_REG_FIFOSIZE] = { 15, 0 },
[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
[FEAT_REG_VERTICALACCU] = { 26, 16 },
- [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
};
static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {