ppc/8xxx: Misc DDR related fixes

* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 5e63c5df3ad410acdc87df3e7d1e5894ef3271a2..250504145045b0bb8c55daba0add464eb91cacd9 100644 (file)
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -675,12 +675,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
        esdmode = (0
                | ((qoff & 0x1) << 12)
                | ((tdqs_en & 0x1) << 11)
-               | ((rtt & 0x4) << 9)   /* rtt field is split */
+               | ((rtt & 0x4) << 7)   /* rtt field is split */
                | ((wrlvl_en & 0x1) << 7)
-               | ((rtt & 0x2) << 6)   /* rtt field is split */
-               | ((dic & 0x2) << 5)   /* DIC field is split */
+               | ((rtt & 0x2) << 5)   /* rtt field is split */
+               | ((dic & 0x2) << 4)   /* DIC field is split */
                | ((al & 0x3) << 3)
-               | ((rtt & 0x1) << 2)   /* rtt field is split */
+               | ((rtt & 0x1) << 2)  /* rtt field is split */
                | ((dic & 0x1) << 1)   /* DIC field is split */
                | ((dll_en & 0x1) << 0)
                );

diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 13d234e9331542eb8d56780cf971ac0bdd26ead0..d4199baa82c55c712141255faa3ff3ab646b407d 100644 (file)
--- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *     Dave Liu <daveliu@freescale.com>
  *
  * calculate the organization and timing parameter
@@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
        bsize = 1ULL << (nbit_sdram_cap_bsize - 3
                    + nbit_primary_bus_width - nbit_sdram_width);
 
-       debug("DDR: DDR III rank density = 0x%08x\n", bsize);
+       debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
 
        return bsize;
 }