drm/msm/dsi: Update generated headers for 10nm PLL/PHY

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 479086ccf180242958869c50eac6715a6c0693d1..f6a9471b70c8ddafaa5383f6a7237cba25a02c93 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -8,19 +8,10 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  33004 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2017-05-17 13:21:27)
-- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  41799 bytes, from 2017-06-16 12:32:42)
-- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2017-05-17 13:21:27)
-
-Copyright (C) 2013-2017 by the following authors:
+- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/dsi/dsi.xml    (  37239 bytes, from 2018-01-12 09:09:22)
+- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2016-05-09 06:32:54)
+
+Copyright (C) 2013-2018 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
 
@@ -1556,5 +1547,175 @@ static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00
 
 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP                       0x00000108
 
+#define REG_DSI_10nm_PHY_CMN_REVISION_ID0                      0x00000000
+
+#define REG_DSI_10nm_PHY_CMN_REVISION_ID1                      0x00000004
+
+#define REG_DSI_10nm_PHY_CMN_REVISION_ID2                      0x00000008
+
+#define REG_DSI_10nm_PHY_CMN_REVISION_ID3                      0x0000000c
+
+#define REG_DSI_10nm_PHY_CMN_CLK_CFG0                          0x00000010
+
+#define REG_DSI_10nm_PHY_CMN_CLK_CFG1                          0x00000014
+
+#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL                         0x00000018
+
+#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL                         0x0000001c
+
+#define REG_DSI_10nm_PHY_CMN_VREG_CTRL                         0x00000020
+
+#define REG_DSI_10nm_PHY_CMN_CTRL_0                            0x00000024
+
+#define REG_DSI_10nm_PHY_CMN_CTRL_1                            0x00000028
+
+#define REG_DSI_10nm_PHY_CMN_CTRL_2                            0x0000002c
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CFG0                         0x00000030
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CFG1                         0x00000034
+
+#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL                         0x00000038
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0                                0x00000098
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1                                0x0000009c
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2                                0x000000a0
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3                                0x000000a4
+
+#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4                                0x000000a8
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0                     0x000000ac
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1                     0x000000b0
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2                     0x000000b4
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3                     0x000000b8
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4                     0x000000bc
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5                     0x000000c0
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6                     0x000000c4
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7                     0x000000c8
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8                     0x000000cc
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9                     0x000000d0
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10                    0x000000d4
+
+#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11                    0x000000d8
+
+#define REG_DSI_10nm_PHY_CMN_PHY_STATUS                                0x000000ec
+
+#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0                      0x000000f4
+
+#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1                      0x000000f8
+
+static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
+
+#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE               0x00000000
+
+#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO               0x00000004
+
+#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE             0x00000010
+
+#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER                       0x0000001c
+
+#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER                  0x00000020
+
+#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES                      0x00000024
+
+#define REG_DSI_10nm_PHY_PLL_CMODE                             0x0000002c
+
+#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS              0x00000030
+
+#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE       0x00000054
+
+#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE          0x00000064
+
+#define REG_DSI_10nm_PHY_PLL_PFILT                             0x0000007c
+
+#define REG_DSI_10nm_PHY_PLL_IFILT                             0x00000080
+
+#define REG_DSI_10nm_PHY_PLL_OUTDIV                            0x00000094
+
+#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE                     0x000000a4
+
+#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE               0x000000a8
+
+#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO            0x000000b4
+
+#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1               0x000000cc
+
+#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1              0x000000d0
+
+#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1              0x000000d4
+
+#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1             0x000000d8
+
+#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1                        0x0000010c
+
+#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1               0x00000110
+
+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1                 0x00000114
+
+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1                        0x00000118
+
+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1              0x0000011c
+
+#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1             0x00000120
+
+#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL                       0x0000013c
+
+#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE                   0x00000140
+
+#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1                        0x00000144
+
+#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1              0x0000014c
+
+#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1               0x00000154
+
+#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1         0x0000015c
+
+#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1      0x00000164
+
+#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE                 0x00000180
+
+#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY                    0x00000184
+
+#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS                   0x0000018c
+
+#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE                 0x000001a0
+
 
 #endif /* DSI_XML */