drm/amdgpu/gfx: switch to amdgpu_gfx_ras_late_init helper function

amdgpu_gfx_ras_late_init is used to init gfx specfic
ras debugfs/sysfs node and gfx specific interrupt handler.
It can be shared among gfx generations

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index f9bef3154b99833eff9a5f595c39a9a269176a79..6e15d1845892ff32322e9b23ca6dbd6bf2eab84a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -26,6 +26,7 @@
 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
 #include "amdgpu_rlc.h"
+#include "amdgpu_ras.h"
 
 /* delay 0.1 second to enable gfx off feature */
 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
@@ -569,3 +570,51 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 
        mutex_unlock(&adev->gfx.gfx_off_mutex);
 }
+
+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+                            void *ras_ih_info)
+{
+       int r;
+       struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
+       struct ras_fs_if fs_info = {
+               .sysfs_name = "gfx_err_count",
+               .debugfs_name = "gfx_err_inject",
+       };
+
+       if (!ih_info)
+               return -EINVAL;
+
+       if (!adev->gfx.ras_if) {
+               adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+               if (!adev->gfx.ras_if)
+                       return -ENOMEM;
+               adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
+               adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+               adev->gfx.ras_if->sub_block_index = 0;
+               strcpy(adev->gfx.ras_if->name, "gfx");
+       }
+       fs_info.head = ih_info->head = *adev->gfx.ras_if;
+
+       r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
+                                &fs_info, ih_info);
+       if (r)
+               goto free;
+
+       if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
+               r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
+               if (r)
+                       goto late_fini;
+       } else {
+               /* free gfx ras_if if ras is not supported */
+               r = 0;
+               goto free;
+       }
+
+       return 0;
+late_fini:
+       amdgpu_ras_late_fini(adev, adev->gfx.ras_if, ih_info);
+free:
+       kfree(adev->gfx.ras_if);
+       adev->gfx.ras_if = NULL;
+       return r;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 554a59b3c4a65cf964bbaf6d0635ddb1f6fc0106..6ed0560d729997e3911ec80b595fe33a90ca406e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -383,5 +383,6 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
                                    int pipe, int queue);
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
-
+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
+                            void *ras_ih_info);
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e40c34d30bd420e26a31f0f815d5c1169a58bcd9..a289e2631df0f212032b3c06fbee9952ecb01afd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4409,22 +4409,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
        struct ras_ih_if ih_info = {
                .cb = gfx_v9_0_process_ras_data_cb,
        };
-       struct ras_fs_if fs_info = {
-               .sysfs_name = "gfx_err_count",
-               .debugfs_name = "gfx_err_inject",
-       };
        int r;
 
-       if (!adev->gfx.ras_if) {
-               adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
-               if (!adev->gfx.ras_if)
-                       return -ENOMEM;
-               adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
-               adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
-               adev->gfx.ras_if->sub_block_index = 0;
-               strcpy(adev->gfx.ras_if->name, "gfx");
-       }
-       fs_info.head = ih_info.head = *adev->gfx.ras_if;
+       r = amdgpu_gfx_ras_late_init(adev, &ih_info);
+       if (r)
+               return r;
 
        r = gfx_v9_0_do_edc_gds_workarounds(adev);
        if (r)
@@ -4435,27 +4424,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
        if (r)
                return r;
 
-       r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
-                                &fs_info, &ih_info);
-       if (r)
-               goto free;
-
-       if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
-               r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
-               if (r)
-                       goto late_fini;
-       } else {
-               r = 0;
-               goto free;
-       }
-
        return 0;
-late_fini:
-       amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
-free:
-       kfree(adev->gfx.ras_if);
-       adev->gfx.ras_if = NULL;
-       return r;
 }
 
 static int gfx_v9_0_late_init(void *handle)