drm/amd/display: rename display clock block to dccg

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index fca22550417a941976fd33383dba833ea52e1f1e..c5fc5250e2bfc43980bda04c7078721e814f14dc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1948,7 +1948,7 @@ void dc_resource_state_construct(
                const struct dc *dc,
                struct dc_state *dst_ctx)
 {
-       dst_ctx->dis_clk = dc->res_pool->display_clock;
+       dst_ctx->dis_clk = dc->res_pool->dccg;
 }
 
 enum dc_status dc_validate_global_state(

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index d3bbac85dff1863c49f93bdffa6cc0bf9e36a0cf..890a3ec68d49e422aa6a1ff08a1cec5ee8532f34 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -38,7 +38,7 @@
 #include "dal_asic_id.h"
 
 #define TO_DCE_CLOCKS(clocks)\
-       container_of(clocks, struct dce_disp_clk, base)
+       container_of(clocks, struct dce_dccg, base)
 
 #define REG(reg) \
        (clk_dce->regs->reg)
@@ -187,9 +187,9 @@ static int dce_divider_range_get_divider(
        return div;
 }
 
-static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
+static int dce_clocks_get_dp_ref_freq(struct dccg *clk)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
        int dprefclk_wdivider;
        int dprefclk_src_sel;
        int dp_ref_clk_khz = 600000;
@@ -250,9 +250,9 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
  * or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit
  * clock implementation
  */
-static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
+static int dce_clocks_get_dp_ref_freq_wrkaround(struct dccg *clk)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
        int dp_ref_clk_khz = 600000;
 
        if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
@@ -274,10 +274,10 @@ static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
        return dp_ref_clk_khz;
 }
 static enum dm_pp_clocks_state dce_get_required_clocks_state(
-       struct display_clock *clk,
+       struct dccg *clk,
        struct dc_clocks *req_clocks)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
        int i;
        enum dm_pp_clocks_state low_req_clk;
 
@@ -306,10 +306,10 @@ static enum dm_pp_clocks_state dce_get_required_clocks_state(
 }
 
 static int dce_set_clock(
-       struct display_clock *clk,
+       struct dccg *clk,
        int requested_clk_khz)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
        struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
        struct dc_bios *bp = clk->ctx->dc_bios;
        int actual_clock = requested_clk_khz;
@@ -341,10 +341,10 @@ static int dce_set_clock(
 }
 
 static int dce_psr_set_clock(
-       struct display_clock *clk,
+       struct dccg *clk,
        int requested_clk_khz)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
        struct dc_context *ctx = clk_dce->base.ctx;
        struct dc *core_dc = ctx->dc;
        struct dmcu *dmcu = core_dc->res_pool->dmcu;
@@ -357,10 +357,10 @@ static int dce_psr_set_clock(
 }
 
 static int dce112_set_clock(
-       struct display_clock *clk,
+       struct dccg *clk,
        int requested_clk_khz)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
        struct bp_set_dce_clock_parameters dce_clk_params;
        struct dc_bios *bp = clk->ctx->dc_bios;
        struct dc *core_dc = clk->ctx->dc;
@@ -409,7 +409,7 @@ static int dce112_set_clock(
        return actual_clock;
 }
 
-static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
+static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce)
 {
        struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
        struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
@@ -467,7 +467,7 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
                        clk_dce->dfs_bypass_enabled = true;
 }
 
-static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
+static void dce_clock_read_ss_info(struct dce_dccg *clk_dce)
 {
        struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
        int ss_info_num = bp->funcs->get_ss_entry_number(
@@ -523,7 +523,7 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
        }
 }
 
-static void dce12_update_clocks(struct display_clock *dccg,
+static void dce12_update_clocks(struct dccg *dccg,
                        struct dc_clocks *new_clocks,
                        bool safe_to_lower)
 {
@@ -549,7 +549,7 @@ static void dce12_update_clocks(struct display_clock *dccg,
        }
 }
 
-static void dcn_update_clocks(struct display_clock *dccg,
+static void dcn_update_clocks(struct dccg *dccg,
                        struct dc_clocks *new_clocks,
                        bool safe_to_lower)
 {
@@ -628,7 +628,7 @@ static void dcn_update_clocks(struct display_clock *dccg,
 #endif
 }
 
-static void dce_update_clocks(struct display_clock *dccg,
+static void dce_update_clocks(struct dccg *dccg,
                        struct dc_clocks *new_clocks,
                        bool safe_to_lower)
 {
@@ -679,14 +679,14 @@ static const struct display_clock_funcs dce_funcs = {
        .update_clocks = dce_update_clocks
 };
 
-static void dce_disp_clk_construct(
-       struct dce_disp_clk *clk_dce,
+static void dce_dccg_construct(
+       struct dce_dccg *clk_dce,
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask)
 {
-       struct display_clock *base = &clk_dce->base;
+       struct dccg *base = &clk_dce->base;
 
        base->ctx = ctx;
        base->funcs = &dce_funcs;
@@ -727,13 +727,13 @@ static void dce_disp_clk_construct(
                DIVIDER_RANGE_MAX_DIVIDER_ID);
 }
 
-struct display_clock *dce_disp_clk_create(
+struct dccg *dce_dccg_create(
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask)
 {
-       struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
+       struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 
        if (clk_dce == NULL) {
                BREAK_TO_DEBUGGER();
@@ -744,19 +744,19 @@ struct display_clock *dce_disp_clk_create(
                dce80_max_clks_by_state,
                sizeof(dce80_max_clks_by_state));
 
-       dce_disp_clk_construct(
+       dce_dccg_construct(
                clk_dce, ctx, regs, clk_shift, clk_mask);
 
        return &clk_dce->base;
 }
 
-struct display_clock *dce110_disp_clk_create(
+struct dccg *dce110_dccg_create(
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask)
 {
-       struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
+       struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 
        if (clk_dce == NULL) {
                BREAK_TO_DEBUGGER();
@@ -767,7 +767,7 @@ struct display_clock *dce110_disp_clk_create(
                dce110_max_clks_by_state,
                sizeof(dce110_max_clks_by_state));
 
-       dce_disp_clk_construct(
+       dce_dccg_construct(
                clk_dce, ctx, regs, clk_shift, clk_mask);
 
        clk_dce->base.funcs = &dce110_funcs;
@@ -775,13 +775,13 @@ struct display_clock *dce110_disp_clk_create(
        return &clk_dce->base;
 }
 
-struct display_clock *dce112_disp_clk_create(
+struct dccg *dce112_dccg_create(
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask)
 {
-       struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
+       struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 
        if (clk_dce == NULL) {
                BREAK_TO_DEBUGGER();
@@ -792,7 +792,7 @@ struct display_clock *dce112_disp_clk_create(
                dce112_max_clks_by_state,
                sizeof(dce112_max_clks_by_state));
 
-       dce_disp_clk_construct(
+       dce_dccg_construct(
                clk_dce, ctx, regs, clk_shift, clk_mask);
 
        clk_dce->base.funcs = &dce112_funcs;
@@ -800,9 +800,9 @@ struct display_clock *dce112_disp_clk_create(
        return &clk_dce->base;
 }
 
-struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
+struct dccg *dce120_dccg_create(struct dc_context *ctx)
 {
-       struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
+       struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 
        if (clk_dce == NULL) {
                BREAK_TO_DEBUGGER();
@@ -813,7 +813,7 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
                dce120_max_clks_by_state,
                sizeof(dce120_max_clks_by_state));
 
-       dce_disp_clk_construct(
+       dce_dccg_construct(
                clk_dce, ctx, NULL, NULL, NULL);
 
        clk_dce->base.funcs = &dce120_funcs;
@@ -821,9 +821,9 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
        return &clk_dce->base;
 }
 
-struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)
+struct dccg *dcn_dccg_create(struct dc_context *ctx)
 {
-       struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
+       struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
 
        if (clk_dce == NULL) {
                BREAK_TO_DEBUGGER();
@@ -831,7 +831,7 @@ struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)
        }
 
        /* TODO strip out useful stuff out of dce constructor */
-       dce_disp_clk_construct(
+       dce_dccg_construct(
                clk_dce, ctx, NULL, NULL, NULL);
 
        clk_dce->base.funcs = &dcn_funcs;
@@ -839,10 +839,10 @@ struct display_clock *dcn_disp_clk_create(struct dc_context *ctx)
        return &clk_dce->base;
 }
 
-void dce_disp_clk_destroy(struct display_clock **disp_clk)
+void dce_dccg_destroy(struct dccg **dccg)
 {
-       struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk);
+       struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg);
 
        kfree(clk_dce);
-       *disp_clk = NULL;
+       *dccg = NULL;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index f9b002015255d124d0cb9ef5734cb740cd8c537b..c695b9c9bcb552b4f7687b8aed3ea6c04c398371 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -82,8 +82,8 @@ struct dce_divider_range {
        int did_max;
 };
 
-struct dce_disp_clk {
-       struct display_clock base;
+struct dce_dccg {
+       struct dccg base;
        const struct dce_disp_clk_registers *regs;
        const struct dce_disp_clk_shift *clk_shift;
        const struct dce_disp_clk_mask *clk_mask;
@@ -108,28 +108,28 @@ struct dce_disp_clk {
 };
 
 
-struct display_clock *dce_disp_clk_create(
+struct dccg *dce_dccg_create(
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask);
 
-struct display_clock *dce110_disp_clk_create(
+struct dccg *dce110_dccg_create(
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask);
 
-struct display_clock *dce112_disp_clk_create(
+struct dccg *dce112_dccg_create(
        struct dc_context *ctx,
        const struct dce_disp_clk_registers *regs,
        const struct dce_disp_clk_shift *clk_shift,
        const struct dce_disp_clk_mask *clk_mask);
 
-struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
+struct dccg *dce120_dccg_create(struct dc_context *ctx);
 
-struct display_clock *dcn_disp_clk_create(struct dc_context *ctx);
+struct dccg *dcn_dccg_create(struct dc_context *ctx);
 
-void dce_disp_clk_destroy(struct display_clock **disp_clk);
+void dce_dccg_destroy(struct dccg **dccg);
 
 #endif /* _DCE_CLOCKS_H_ */

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
index aabf7ca9b241057e726b8bbc912c97564451febf..ec3221333011be4f0f2922b139282f969aea98fd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
@@ -168,8 +168,8 @@ void dce100_set_bandwidth(
 
        dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
 
-       dc->res_pool->display_clock->funcs->update_clocks(
-                       dc->res_pool->display_clock,
+       dc->res_pool->dccg->funcs->update_clocks(
+                       dc->res_pool->dccg,
                        &req_clks,
                        decrease_allowed);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 38ec0d609297f832362d45397a2080918e4937c0..856d3fe8e6a0f726f3400430b8c579726e7d576d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -644,8 +644,8 @@ static void destruct(struct dce110_resource_pool *pool)
                        dce_aud_destroy(&pool->base.audios[i]);
        }
 
-       if (pool->base.display_clock != NULL)
-               dce_disp_clk_destroy(&pool->base.display_clock);
+       if (pool->base.dccg != NULL)
+               dce_dccg_destroy(&pool->base.dccg);
 
        if (pool->base.abm != NULL)
                                dce_abm_destroy(&pool->base.abm);
@@ -817,11 +817,11 @@ static bool construct(
                }
        }
 
-       pool->base.display_clock = dce_disp_clk_create(ctx,
+       pool->base.dccg = dce_dccg_create(ctx,
                        &disp_clk_regs,
                        &disp_clk_shift,
                        &disp_clk_mask);
-       if (pool->base.display_clock == NULL) {
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto res_create_fail;
@@ -851,7 +851,7 @@ static bool construct(
         * max_clock_state
         */
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-               pool->base.display_clock->max_clks_state =
+               pool->base.dccg->max_clks_state =
                                        static_clk_info.max_clocks_state;
        {
                struct irq_service_init_data init_data;

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 02aa0a2ec87506964d82ba4ab0d98e81ac530e11..34eb7a33851b2b34e6c8ec77ee82eeaa581e6281 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2569,8 +2569,8 @@ static void dce110_set_bandwidth(
        else
                dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
 
-       dc->res_pool->display_clock->funcs->update_clocks(
-                       dc->res_pool->display_clock,
+       dc->res_pool->dccg->funcs->update_clocks(
+                       dc->res_pool->dccg,
                        &req_clks,
                        decrease_allowed);
        pplib_apply_display_requirements(dc, context);

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 20c0290895515b775bb7a5e4f15548e4d4a3eae9..71a401f73a58cdb83db6e21facf4c9f40f919d9e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -679,8 +679,8 @@ static void destruct(struct dce110_resource_pool *pool)
        if (pool->base.dmcu != NULL)
                dce_dmcu_destroy(&pool->base.dmcu);
 
-       if (pool->base.display_clock != NULL)
-               dce_disp_clk_destroy(&pool->base.display_clock);
+       if (pool->base.dccg != NULL)
+               dce_dccg_destroy(&pool->base.dccg);
 
        if (pool->base.irqs != NULL) {
                dal_irq_service_destroy(&pool->base.irqs);
@@ -1179,11 +1179,11 @@ static bool construct(
                }
        }
 
-       pool->base.display_clock = dce110_disp_clk_create(ctx,
+       pool->base.dccg = dce110_dccg_create(ctx,
                        &disp_clk_regs,
                        &disp_clk_shift,
                        &disp_clk_mask);
-       if (pool->base.display_clock == NULL) {
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto res_create_fail;
@@ -1213,7 +1213,7 @@ static bool construct(
         * max_clock_state
         */
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-               pool->base.display_clock->max_clks_state =
+               pool->base.dccg->max_clks_state =
                                static_clk_info.max_clocks_state;
 
        {

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 00c0a1ef15ebd5d602d97c1f6b724814ccbc260b..ae5b19de559cd713166cab530d0354decc8032f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -668,8 +668,8 @@ static void destruct(struct dce110_resource_pool *pool)
        if (pool->base.dmcu != NULL)
                dce_dmcu_destroy(&pool->base.dmcu);
 
-       if (pool->base.display_clock != NULL)
-               dce_disp_clk_destroy(&pool->base.display_clock);
+       if (pool->base.dccg != NULL)
+               dce_dccg_destroy(&pool->base.dccg);
 
        if (pool->base.irqs != NULL) {
                dal_irq_service_destroy(&pool->base.irqs);
@@ -1124,11 +1124,11 @@ static bool construct(
                }
        }
 
-       pool->base.display_clock = dce112_disp_clk_create(ctx,
+       pool->base.dccg = dce112_dccg_create(ctx,
                        &disp_clk_regs,
                        &disp_clk_shift,
                        &disp_clk_mask);
-       if (pool->base.display_clock == NULL) {
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto res_create_fail;
@@ -1158,7 +1158,7 @@ static bool construct(
         * max_clock_state
         */
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-               pool->base.display_clock->max_clks_state =
+               pool->base.dccg->max_clks_state =
                                static_clk_info.max_clocks_state;
 
        {

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 2d58daccc0056cb4b95cd73fc09326ea31dac05c..13c388a608c448a77ff623099ee31d47408863ad 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -494,8 +494,8 @@ static void destruct(struct dce110_resource_pool *pool)
        if (pool->base.dmcu != NULL)
                dce_dmcu_destroy(&pool->base.dmcu);
 
-       if (pool->base.display_clock != NULL)
-               dce_disp_clk_destroy(&pool->base.display_clock);
+       if (pool->base.dccg != NULL)
+               dce_dccg_destroy(&pool->base.dccg);
 }
 
 static void read_dce_straps(
@@ -894,11 +894,11 @@ static bool construct(
                }
        }
 
-       pool->base.display_clock = dce120_disp_clk_create(ctx);
-       if (pool->base.display_clock == NULL) {
+       pool->base.dccg = dce120_dccg_create(ctx);
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
-               goto disp_clk_create_fail;
+               goto dccg_create_fail;
        }
 
        pool->base.dmcu = dce_dmcu_create(ctx,
@@ -1011,7 +1011,7 @@ static bool construct(
 
 irqs_create_fail:
 controller_create_fail:
-disp_clk_create_fail:
+dccg_create_fail:
 clk_src_create_fail:
 res_create_fail:
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 48a0689647225720a9d3f136201a33bd9a5cb2a1..70700530aec29d54a5dcdb3e39794897784a6356 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -683,8 +683,8 @@ static void destruct(struct dce110_resource_pool *pool)
                }
        }
 
-       if (pool->base.display_clock != NULL)
-               dce_disp_clk_destroy(&pool->base.display_clock);
+       if (pool->base.dccg != NULL)
+               dce_dccg_destroy(&pool->base.dccg);
 
        if (pool->base.irqs != NULL) {
                dal_irq_service_destroy(&pool->base.irqs);
@@ -822,11 +822,11 @@ static bool dce80_construct(
                }
        }
 
-       pool->base.display_clock = dce_disp_clk_create(ctx,
+       pool->base.dccg = dce_dccg_create(ctx,
                        &disp_clk_regs,
                        &disp_clk_shift,
                        &disp_clk_mask);
-       if (pool->base.display_clock == NULL) {
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto res_create_fail;
@@ -852,7 +852,7 @@ static bool dce80_construct(
                goto res_create_fail;
        }
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-               pool->base.display_clock->max_clks_state =
+               pool->base.dccg->max_clks_state =
                                        static_clk_info.max_clocks_state;
 
        {
@@ -1006,11 +1006,11 @@ static bool dce81_construct(
                }
        }
 
-       pool->base.display_clock = dce_disp_clk_create(ctx,
+       pool->base.dccg = dce_dccg_create(ctx,
                        &disp_clk_regs,
                        &disp_clk_shift,
                        &disp_clk_mask);
-       if (pool->base.display_clock == NULL) {
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto res_create_fail;
@@ -1037,7 +1037,7 @@ static bool dce81_construct(
        }
 
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-               pool->base.display_clock->max_clks_state =
+               pool->base.dccg->max_clks_state =
                                        static_clk_info.max_clocks_state;
 
        {
@@ -1187,11 +1187,11 @@ static bool dce83_construct(
                }
        }
 
-       pool->base.display_clock = dce_disp_clk_create(ctx,
+       pool->base.dccg = dce_dccg_create(ctx,
                        &disp_clk_regs,
                        &disp_clk_shift,
                        &disp_clk_mask);
-       if (pool->base.display_clock == NULL) {
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto res_create_fail;
@@ -1218,7 +1218,7 @@ static bool dce83_construct(
        }
 
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-               pool->base.display_clock->max_clks_state =
+               pool->base.dccg->max_clks_state =
                                        static_clk_info.max_clocks_state;
 
        {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7f1a7ec9ff5f631808ced3dda10915284ab4b45b..f519b98f4b2323768e4438b5a12952b5bf5a3e12 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2424,8 +2424,8 @@ static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
        int dispclk_to_dpp_threshold = determine_dppclk_threshold(dc, context);
 
        /* set disp clk to dpp clk threshold */
-       dc->res_pool->display_clock->funcs->set_dispclk(
-                       dc->res_pool->display_clock,
+       dc->res_pool->dccg->funcs->set_dispclk(
+                       dc->res_pool->dccg,
                        dispclk_to_dpp_threshold);
 
        /* update request dpp clk division option */
@@ -2443,8 +2443,8 @@ static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
 
        /* If target clk not same as dppclk threshold, set to target clock */
        if (dispclk_to_dpp_threshold != context->bw.dcn.calc_clk.dispclk_khz) {
-               dc->res_pool->display_clock->funcs->set_dispclk(
-                               dc->res_pool->display_clock,
+               dc->res_pool->dccg->funcs->set_dispclk(
+                               dc->res_pool->dccg,
                                context->bw.dcn.calc_clk.dispclk_khz);
        }
 
@@ -2473,8 +2473,8 @@ static void dcn10_set_bandwidth(
        if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
                return;
 
-       dc->res_pool->display_clock->funcs->update_clocks(
-                       dc->res_pool->display_clock,
+       dc->res_pool->dccg->funcs->update_clocks(
+                       dc->res_pool->dccg,
                        &context->bw.dcn.calc_clk,
                        decrease_allowed);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 870eb0aabcc9e321488dba86b86497f106343c15..8f1ceffa809b70d90293541206327ef8a79cce7e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -791,8 +791,8 @@ static void destruct(struct dcn10_resource_pool *pool)
        if (pool->base.dmcu != NULL)
                dce_dmcu_destroy(&pool->base.dmcu);
 
-       if (pool->base.display_clock != NULL)
-               dce_disp_clk_destroy(&pool->base.display_clock);
+       if (pool->base.dccg != NULL)
+               dce_dccg_destroy(&pool->base.dccg);
 
        kfree(pool->base.pp_smu);
 }
@@ -1072,8 +1072,8 @@ static bool construct(
                }
        }
 
-       pool->base.display_clock = dcn_disp_clk_create(ctx);
-       if (pool->base.display_clock == NULL) {
+       pool->base.dccg = dcn_dccg_create(ctx);
+       if (pool->base.dccg == NULL) {
                dm_error("DC: failed to create display clock!\n");
                BREAK_TO_DEBUGGER();
                goto fail;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 4beddca0180c314ed910c294d445c93055c2e8b6..44c48f3d0a1de10c942f278fe9f49294ef7ef761 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -163,7 +163,7 @@ struct resource_pool {
        unsigned int audio_count;
        struct audio_support audio_support;
 
-       struct display_clock *display_clock;
+       struct dccg *dccg;
        struct irq_service *irqs;
 
        struct abm *abm;
@@ -282,7 +282,7 @@ struct dc_state {
        struct dcn_bw_internal_vars dcn_bw_vars;
 #endif
 
-       struct display_clock *dis_clk;
+       struct dccg *dis_clk;
 
        struct kref refcount;
 };

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
index 8ce106f156476d7b5d05bab3c9f048a011a41404..3c7ccb68ecdb58c90ff25d68b3aaf7d6c602530d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
@@ -36,7 +36,7 @@ struct state_dependent_clocks {
        int pixel_clk_khz;
 };
 
-struct display_clock {
+struct dccg {
        struct dc_context *ctx;
        const struct display_clock_funcs *funcs;
 
@@ -46,13 +46,13 @@ struct display_clock {
 };
 
 struct display_clock_funcs {
-       void (*update_clocks)(struct display_clock *dccg,
+       void (*update_clocks)(struct dccg *dccg,
                        struct dc_clocks *new_clocks,
                        bool safe_to_lower);
-       int (*set_dispclk)(struct display_clock *disp_clk,
+       int (*set_dispclk)(struct dccg *dccg,
                int requested_clock_khz);
 
-       int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
+       int (*get_dp_ref_clk_frequency)(struct dccg *dccg);
 };
 
 #endif /* __DISPLAY_CLOCK_H__ */