+#include <linux/delay.h>
+#include <lantiq_soc.h>
+
-+#define LTQ_PCI_MEM_BASE 0x18000000
-+
+struct ath_fixup {
+ u16 *cal_data;
+ unsigned slot;
+ u16 cmd;
+ u32 bar0;
+ u32 val;
++ u32 base;
+ unsigned i;
+
+ for (i = 0; i < ath_num_fixups; i++) {
+
+ pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+
-+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
++ base = dev->resource[0].start;
++ mem = ioremap(base, 0x10000);
+ if (!mem) {
+ pr_err("pci %s: ioremap error\n", pci_name(dev));
+ return;
+ }
+
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
-+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+#include <linux/delay.h>
+#include <lantiq_soc.h>
+
-+#define LTQ_PCI_MEM_BASE 0x18000000
-+
+struct ath_fixup {
+ u16 *cal_data;
+ unsigned slot;
+ u16 cmd;
+ u32 bar0;
+ u32 val;
++ u32 base;
+ unsigned i;
+
+ for (i = 0; i < ath_num_fixups; i++) {
+
+ pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+
-+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000);
++ base = dev->resource[0].start;
++ mem = ioremap(base, 0x10000);
+ if (!mem) {
+ pr_err("pci %s: ioremap error\n", pci_name(dev));
+ return;
+ }
+
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
-+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE);
++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base);
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(dev, PCI_COMMAND, cmd);