+------------------------------+---------+---------+
------ -- 3) MIDR_EL1 - Main ID Register
++++++ ++ 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
++++++ ++ +------------------------------+---------+---------+
++++++ ++ | Name | bits | visible |
++++++ ++ +------------------------------+---------+---------+
++++++ ++ | SSBS | [7-4] | y |
++++++ ++ +------------------------------+---------+---------+
+
+ ++++ ++
++++++ ++ 4) MIDR_EL1 - Main ID Register
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
return (need_wa > 0);
}
--------#ifdef CONFIG_HARDEN_EL2_VECTORS
++++++++static const __maybe_unused struct midr_range tx2_family_cpus[] = {
++++++++ MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
++++++++ MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
++++++++ {},
++++++++};
++++++++
++++++++static bool __maybe_unused
++++++++needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
++++++++ int scope)
++++++++{
++++++++ int i;
++++++++
++++++++ if (!is_affected_midr_range_list(entry, scope) ||
++++++++ !is_hyp_mode_available())
++++++++ return false;
++++++++
++++++++ for_each_possible_cpu(i) {
++++++++ if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
++++++++ return true;
++++++++ }
++++++++
++++++++ return false;
++++++++}
++++++++
++++++++static bool __maybe_unused
++++++++has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
++++++++ int scope)
++++++++{
++++++++ u32 midr = read_cpuid_id();
++++++++ bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
++++++++ const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
+
- ------static const struct midr_range arm64_harden_el2_vectors[] = {
++++++++ WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
++++++++ return is_midr_in_range(midr, &range) && has_dic;
++++++++}
++++++++
++++++++#if defined(CONFIG_HARDEN_EL2_VECTORS) || defined(CONFIG_ARM64_ERRATUM_1319367)
+ ++++++
- static const struct midr_range arm64_harden_el2_vectors[] = {
++++++++static const struct midr_range ca57_a72[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
{},