(regs->cp0_cause & 0x7f) >> 2);
}
-static asmlinkage void do_default_vi(void)
-{
- show_regs(get_irq_regs());
- panic("Caught unexpected vectored interrupt.");
-}
-
/*
* Some MIPS CPUs can enable/disable for cache parity detection, but do
* it different ways.
clear_bit(set, &sr->sr_allocated);
}
+static asmlinkage void do_default_vi(void)
+{
+ show_regs(get_irq_regs());
+ panic("Caught unexpected vectored interrupt.");
+}
+
static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
{
unsigned long handler;