ixgbe: X540 devices RX PFC frames pause traffic even if disabled
authorJohn Fastabend <john.r.fastabend@intel.com>
Wed, 21 Sep 2011 14:44:10 +0000 (14:44 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Thu, 6 Oct 2011 10:24:10 +0000 (03:24 -0700)
Receiving PFC (priority flow control) frames while the feature
is off should not pause the traffic class. On the X540 devices
the traffic class react to frames if it was previously enabled
because the field is incorrectly cleared.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

index 45fe710304556c3ef269cde49cad58dd2f9578c6..32cd97bc794d1e5f726ed99adc0f1f63b59f841e 100644 (file)
@@ -271,13 +271,23 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
                reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
 
                if (hw->mac.type == ixgbe_mac_X540) {
-                       reg &= ~(IXGBE_MFLCN_RPFCE_MASK | 0x10);
+                       reg &= ~IXGBE_MFLCN_RPFCE_MASK;
                        reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
                }
 
                IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
 
        } else {
+               /* X540 devices have a RX bit that should be cleared
+                * if PFC is disabled on all TCs but PFC features is
+                * enabled.
+                */
+               if (hw->mac.type == ixgbe_mac_X540) {
+                       reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+                       reg &= ~IXGBE_MFLCN_RPFCE_MASK;
+                       IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
+               }
+
                for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
                        hw->mac.ops.fc_enable(hw, i);
        }
index 4ea909c7951b7303ca0bcd74c0db555331053dbf..d1d689471523a1155c4285288ba1f588c95c6058 100644 (file)
@@ -1850,7 +1850,7 @@ enum {
 #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
-#define IXGBE_MFLCN_RPFCE_MASK 0x00000FE0 /* Receive FC Mask */
+#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF0 /* Receive FC Mask */
 
 #define IXGBE_MFLCN_RPFCE_SHIFT                 4