Add ISR_EL1 to crash report

Bring ISR bits definition as a mnemonic for troublershooters as well.

Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>

diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index ff915728a16236d00cad5b99d51226a21a153862..b22ce71ef280c7619f6e2f3b5260ad2cb023a607 100644 (file)
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -70,7 +70,8 @@ non_el3_sys_regs:
                "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\
                "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\
                "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\
-               "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", ""
+               "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\
+               "isr_el1", ""
 
 panic_msg:
        .asciz "PANIC in EL3 at x30 = 0x"
@@ -338,6 +339,7 @@ func do_crash_reporting
        mrs     x8, cntkctl_el1
        mrs     x9, fpexc32_el2
        mrs     x10, sp_el0
+       mrs     x11, isr_el1
        bl      str_in_crash_buf_print
 
        /* Get the cpu specific registers to report */

diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index a9b2dbb254eeac5a519a9350f10b03ad60314424..f9b8ed6a52d3deaadd8bc19d9dfe801488d6d40e 100644 (file)
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -186,6 +186,11 @@
 #define HCR_IMO_BIT            (1 << 4)
 #define HCR_FMO_BIT            (1 << 3)
 
+/* ISR definitions */
+#define ISR_A_SHIFT            8
+#define ISR_I_SHIFT            7
+#define ISR_F_SHIFT            6
+
 /* CNTHCTL_EL2 definitions */
 #define EVNTEN_BIT             (1 << 2)
 #define EL1PCEN_BIT            (1 << 1)