octeontx2-af: Enable packet length and csum validation

Config NPC layer info from KPU profile into protocol
checker to identify outer L2/IPv4/TCP/UDP headers in a
packet. And enable IPv4 checksum validation.

L3/L4 and L4 CSUM validation will be enabled by PF/VF
drivers by configuring NIX_AF_LF(0..127)_RX_CFG via mbox
i.e 'nix_lf_alloc_req->rx_cfg'

Also enable setting of NPC_RESULT_S[L2B] when an outer
L2 broadcast address is detected. This will help in
installing NPC MCAM rules for broadcast packets.

Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 7de5417277e6830df8f11d75a72fc057b2326dca..02e1d16cf670001e96e9520ea4e8318a1631fdeb 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -14,6 +14,7 @@
 #include "rvu_struct.h"
 #include "rvu_reg.h"
 #include "rvu.h"
+#include "npc.h"
 #include "cgx.h"
 
 static int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add);
@@ -1630,6 +1631,19 @@ int rvu_nix_init(struct rvu *rvu)
                err = nix_setup_mcast(rvu, hw->nix0, blkaddr);
                if (err)
                        return err;
+
+               /* Config Outer L2, IP, TCP and UDP's NPC layer info.
+                * This helps HW protocol checker to identify headers
+                * and validate length and checksums.
+                */
+               rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2,
+                           (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F);
+               rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP,
+                           (NPC_LID_LD << 8) | (NPC_LT_LD_UDP << 4) | 0x0F);
+               rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP,
+                           (NPC_LID_LD << 8) | (NPC_LT_LD_TCP << 4) | 0x0F);
+               rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4,
+                           (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F);
        }
        return 0;
 }

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index a9738958aaa6e3b6004814f64d2a639ef8460345..cc1d8c9e8495afb65ca558fbb4c86f7db0e5c0b1 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
@@ -220,6 +220,20 @@ int rvu_npc_init(struct rvu *rvu)
        /* Configure KPU profile */
        npc_parser_profile_init(rvu, blkaddr);
 
+       /* Config Outer L2, IPv4's NPC layer info */
+       rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
+                   (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F);
+       rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
+                   (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F);
+
+       /* Enable below for Rx pkts.
+        * - Outer IPv4 header checksum validation.
+        * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M].
+        */
+       rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
+                   rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
+                   BIT_ULL(6) | BIT_ULL(2));
+
        return 0;
 }