crypto: cavium/nitrox - fix firmware assignment to AE cores

This patch fixes assigning UCD block number of Asymmetric crypto
firmware to AE cores of CNN55XX device.

Fixes: a7268c4d4205 ("crypto: cavium/nitrox - Add support for loading asymmetric crypto firmware")
Signed-off-by: Phani Kiran Hemadri <phemadri@marvell.com>
Reviewed-by: Srikanth Jampala <jsrikanth@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c
index bc924980e10c036c03ce3bb4785c4a0698800963..c4632d84c9a11891731b900d07444780fec5b703 100644 (file)
--- a/drivers/crypto/cavium/nitrox/nitrox_main.c
+++ b/drivers/crypto/cavium/nitrox/nitrox_main.c
@@ -103,8 +103,7 @@ static void write_to_ucd_unit(struct nitrox_device *ndev, u32 ucode_size,
        offset = UCD_UCODE_LOAD_BLOCK_NUM;
        nitrox_write_csr(ndev, offset, block_num);
 
-       code_size = ucode_size;
-       code_size = roundup(code_size, 8);
+       code_size = roundup(ucode_size, 16);
        while (code_size) {
                data = ucode_data[i];
                /* write 8 bytes at a time */
@@ -220,11 +219,11 @@ static int nitrox_load_fw(struct nitrox_device *ndev)
 
        /* write block number and firmware length
         * bit:<2:0> block number
-        * bit:3 is set SE uses 32KB microcode
-        * bit:3 is clear SE uses 64KB microcode
+        * bit:3 is set AE uses 32KB microcode
+        * bit:3 is clear AE uses 64KB microcode
         */
        core_2_eid_val.value = 0ULL;
-       core_2_eid_val.ucode_blk = 0;
+       core_2_eid_val.ucode_blk = 2;
        if (ucode_size <= CNN55XX_UCD_BLOCK_SIZE)
                core_2_eid_val.ucode_len = 1;
        else