drm: rcar-du: Support up to 4 CRTCs

The Gen3 R8A7795 DU has 4 CRTCs, support them all.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index a862cf5568cdafdbe8a3f21522d84cbf401750d7..a8ebb344b6521c0fba856a151908d825b4e4b6cd 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -571,7 +571,7 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 {
        static const unsigned int mmio_offsets[] = {
-               DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
+               DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
        };
 
        struct rcar_du_device *rcdu = rgrp->dev;

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index a81eb3281e7f2748d7794577f4dde2e5b89cd74b..ce359edc9ab9e92b8086543391f53566cc3c0a8a 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -67,7 +67,7 @@ struct rcar_du_device_info {
        unsigned int num_lvds;
 };
 
-#define RCAR_DU_MAX_CRTCS              3
+#define RCAR_DU_MAX_CRTCS              4
 #define RCAR_DU_MAX_GROUPS             DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2)
 #define RCAR_DU_MAX_LVDS               2
 #define RCAR_DU_MAX_VSPS               4

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
index ac9c3e511e797931ff506056766137fdc53da20e..95add71a33c8438128b9e880351b320cb7502ddb 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
@@ -16,6 +16,7 @@
 #define DU0_REG_OFFSET         0x00000
 #define DU1_REG_OFFSET         0x30000
 #define DU2_REG_OFFSET         0x40000
+#define DU3_REG_OFFSET         0x70000
 
 /* -----------------------------------------------------------------------------
  * Display Control Registers