Tegra: Fix the delay loop used during SC7 exit

This patch fixes the delay loop used to wake up the BPMP during SC7 exit.
The earlier loop would fail just when the timer was about to wrap-around
(e.g. when TEGRA_TMRUS_BASE is 0xfffffffe, the target value becomes 0,
which would cause the loop to exit before it's expiry).

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
index a36cf2d73a0a0035a07048fc601e554f4ff6162b..b473dd6560a8d5047fe00d9ef1a9d3a360335d4a 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
+++ b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
@@ -31,6 +31,7 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <debug.h>
+#include <delay_timer.h>
 #include <mmio.h>
 #include <pmc.h>
 #include <cortex_a53.h>
@@ -230,10 +231,7 @@ void tegra_fc_reset_bpmp(void)
                ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
 
        /* Wait for 2us before de-asserting the reset signal. */
-       val = mmio_read_32(TEGRA_TMRUS_BASE);
-       val += 2;
-       while (val > mmio_read_32(TEGRA_TMRUS_BASE))
-               ; /* wait for 2us */
+       udelay(2);
 
        /* De-assert BPMP reset */
        mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST);