dma: apbh: Add special circular mode for LCD

Add special function that executes a specially crafted circular
DMA descriptor. The function doesn't wait for the descriptor to
finish the transfer, since the descritor never finishes. This is
useful when operating a SmartLCD through the LCDIF interface, as
the LCDIF does not give us any means to have continuous refresh
of the SmartLCD. Instead, the RUN bit in the LCDIF CTRL register
must be triggered manually. This can be worked around by starting
an DMA transfer which continuously sets the RUN bit. This function
allows starting exactly such transfer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index 5f516ef6e04186a6962ada6759ff1898002c4aee..d5c1f7f255a3c5f6eee70634d6dd747ac5639530 100644 (file)
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -161,4 +161,6 @@ void mxs_dma_init(void);
 int mxs_dma_init_channel(int chan);
 int mxs_dma_release(int chan);
 
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
+
 #endif /* __DMA_H__ */

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 96d4c9bb19960c943fa0666768e30212d996f139..22defcd7d9223be898b18cdc8ae1236a38272671 100644 (file)
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -544,6 +544,28 @@ int mxs_dma_go(int chan)
        return ret;
 }
 
+/*
+ * Execute a continuously running circular DMA descriptor.
+ * NOTE: This is not intended for general use, but rather
+ *      for the LCD driver in Smart-LCD mode. It allows
+ *      continuous triggering of the RUN bit there.
+ */
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc)
+{
+       struct mxs_apbh_regs *apbh_regs =
+               (struct mxs_apbh_regs *)MXS_APBH_BASE;
+
+       mxs_dma_flush_desc(pdesc);
+
+       mxs_dma_enable_irq(chan, 1);
+
+       writel(mxs_dma_cmd_address(pdesc),
+               &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);
+       writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);
+       writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
+               &apbh_regs->hw_apbh_ctrl0_clr);
+}
+
 /*
  * Initialize the DMA hardware
  */