drm/nouveau/clk: switch to new-style timer macros
authorBen Skeggs <bskeggs@redhat.com>
Thu, 20 Aug 2015 04:54:11 +0000 (14:54 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 28 Aug 2015 02:40:20 +0000 (12:40 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c

index f7aac3702c2348f64b777247da1ec0ad1a5641d3..c90f7d68f412eeec16be6608f7f2786d487cd9bf 100644 (file)
@@ -345,7 +345,10 @@ gf100_clk_prog_1(struct gf100_clk *clk, int idx)
 {
        struct nvkm_device *device = clk->base.subdev.device;
        nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
-       nv_wait(clk, 0x137100, (1 << idx), 0x00000000);
+       nvkm_msec(device, 2000,
+               if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
+                       break;
+       );
 }
 
 static void
@@ -360,7 +363,10 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx)
                if (info->coef) {
                        nvkm_wr32(device, addr + 0x04, info->coef);
                        nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
-                       nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000);
+                       nvkm_msec(device, 2000,
+                               if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
+                                       break;
+                       );
                        nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
                }
        }
@@ -373,7 +379,11 @@ gf100_clk_prog_3(struct gf100_clk *clk, int idx)
        struct nvkm_device *device = clk->base.subdev.device;
        if (info->ssel) {
                nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
-               nv_wait(clk, 0x137100, (1 << idx), info->ssel);
+               nvkm_msec(device, 2000,
+                       u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
+                       if (tmp == info->ssel)
+                               break;
+               );
        }
 }
 
index d2b7d6ec1c2b5455f0ce6cbca783de186b7b1951..ad166aaf609bd5a840eba60634d37866baaff0b2 100644 (file)
@@ -366,7 +366,10 @@ gk104_clk_prog_1_0(struct gk104_clk *clk, int idx)
 {
        struct nvkm_device *device = clk->base.subdev.device;
        nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
-       nv_wait(clk, 0x137100, (1 << idx), 0x00000000);
+       nvkm_msec(device, 2000,
+               if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
+                       break;
+       );
 }
 
 static void
@@ -387,7 +390,10 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
        if (info->coef) {
                nvkm_wr32(device, addr + 0x04, info->coef);
                nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
-               nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000);
+               nvkm_msec(device, 2000,
+                       if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
+                               break;
+               );
                nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
        }
 }
@@ -410,7 +416,11 @@ gk104_clk_prog_4_0(struct gk104_clk *clk, int idx)
        struct nvkm_device *device = clk->base.subdev.device;
        if (info->ssel) {
                nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
-               nv_wait(clk, 0x137100, (1 << idx), info->ssel);
+               nvkm_msec(device, 2000,
+                       u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
+                       if (tmp == info->ssel)
+                               break;
+               );
        }
 }
 
index 6d36d094b8f2e6de48b5c0a11f2f747127a5afa5..49659bce68e36d1977374b0201305dee0c87a5b4 100644 (file)
@@ -405,11 +405,11 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
                nvkm_wr32(device, GPCPLL_CFG, val);
        }
 
-       if (!nvkm_timer_wait_eq(clk, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK,
-                               GPCPLL_CFG_LOCK)) {
-               nv_error(clk, "%s: timeout waiting for pllg lock\n", __func__);
+       if (nvkm_usec(device, 300,
+               if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK)
+                       break;
+       ) < 0)
                return -ETIMEDOUT;
-       }
 
        /* switch to VCO mode */
        nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
index 364c9b0df728a19678fa101fe6272e1f08bd9aa1..6992cbb8c2d84c95519b5407b834bfe5ac20892e 100644 (file)
@@ -302,21 +302,32 @@ int
 gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags)
 {
        struct nvkm_device *device = clk->subdev.device;
-       struct nvkm_fifo *fifo = nvkm_fifo(clk);
+       struct nvkm_fifo *fifo = device->fifo;
 
        /* halt and idle execution engines */
        nvkm_mask(device, 0x020060, 0x00070000, 0x00000000);
        nvkm_mask(device, 0x002504, 0x00000001, 0x00000001);
        /* Wait until the interrupt handler is finished */
-       if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000))
+       if (nvkm_msec(device, 2000,
+               if (!nvkm_rd32(device, 0x000100))
+                       break;
+       ) < 0)
                return -EBUSY;
 
        if (fifo)
                fifo->pause(fifo, flags);
 
-       if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010))
+       if (nvkm_msec(device, 2000,
+               if (nvkm_rd32(device, 0x002504) & 0x00000010)
+                       break;
+       ) < 0)
                return -EIO;
-       if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f))
+
+       if (nvkm_msec(device, 2000,
+               u32 tmp = nvkm_rd32(device, 0x002504) & 0x0000003f;
+               if (tmp == 0x0000003f)
+                       break;
+       ) < 0)
                return -EIO;
 
        return 0;
@@ -367,7 +378,10 @@ prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom)
                nvkm_wr32(device, coef, info->pll);
                nvkm_mask(device, ctrl, 0x00000015, 0x00000015);
                nvkm_mask(device, ctrl, 0x00000010, 0x00000000);
-               if (!nv_wait(clk, ctrl, 0x00020000, 0x00020000)) {
+               if (nvkm_msec(device, 2000,
+                       if (nvkm_rd32(device, ctrl) & 0x00020000)
+                               break;
+               ) < 0) {
                        nvkm_mask(device, ctrl, 0x00000010, 0x00000010);
                        nvkm_mask(device, src0, 0x00000101, 0x00000000);
                        return;
index 9d7c118e978454180fdb4830b333a24e77940925..05d2a1bc55cf3fdba4bebb629746d53bb54e6764 100644 (file)
@@ -349,10 +349,12 @@ mcp77_clk_prog(struct nvkm_clk *obj)
                goto resume;
        }
 
-       if (!nv_wait(clk, 0x004080, pllmask, pllmask)) {
-               nv_warn(clk,"Reclocking failed: unstable PLLs\n");
+       if (nvkm_msec(device, 2000,
+               u32 tmp = nvkm_rd32(device, 0x004080) & pllmask;
+               if (tmp == pllmask)
+                       break;
+       ) < 0)
                goto resume;
-       }
 
        switch (clk->vsrc) {
        case nv_clk_src_cclk: