clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index cee062c588dec2c2471b55c4c2b60a44d20ec42f..55300142188bc1702352c9bd21056de298d040cb 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
        FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
                        100000000),
        /* PHY clocks from HDMI_PHY */
-       FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
-       FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
+       FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
+                       NULL, CLK_IS_ROOT, 300000000),
+       FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
+                       NULL, CLK_IS_ROOT, 166000000),
 };
 
 static struct samsung_mux_clock disp_mux_clks[] __initdata = {

diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 5bd80d5ecd0f85c34c1d01e83b697f460d3323c7..4f0d5667ee9d5676edf48480dc9be255f0b7c711 100644 (file)
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -765,7 +765,10 @@
 #define CLK_SCLK_RGB_VCLK                              109
 #define CLK_SCLK_RGB_TV_VCLK                           110
 
-#define DISP_NR_CLK                                    111
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY              111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY               112
+
+#define DISP_NR_CLK                                    113
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER                          1