if (tx_q->dirty_tx != tx_q->cur_tx)
return -EBUSY; /* still unfinished work */
-@@ -1309,7 +1309,7 @@ static void stmmac_display_rx_rings(stru
+@@ -1310,7 +1310,7 @@ static void stmmac_display_rx_rings(stru
/* Display RX rings */
for (queue = 0; queue < rx_cnt; queue++) {
pr_info("\tRX Queue %u rings\n", queue);
-@@ -1322,7 +1322,7 @@ static void stmmac_display_rx_rings(stru
+@@ -1323,7 +1323,7 @@ static void stmmac_display_rx_rings(stru
}
/* Display RX ring */
rx_q->dma_rx_phy, desc_size);
}
}
-@@ -1336,7 +1336,7 @@ static void stmmac_display_tx_rings(stru
+@@ -1337,7 +1337,7 @@ static void stmmac_display_tx_rings(stru
/* Display TX rings */
for (queue = 0; queue < tx_cnt; queue++) {
pr_info("\tTX Queue %d rings\n", queue);
-@@ -1351,7 +1351,7 @@ static void stmmac_display_tx_rings(stru
+@@ -1352,7 +1352,7 @@ static void stmmac_display_tx_rings(stru
desc_size = sizeof(struct dma_desc);
}
tx_q->dma_tx_phy, desc_size);
}
}
-@@ -1392,21 +1392,21 @@ static int stmmac_set_bfsize(int mtu, in
+@@ -1393,21 +1393,21 @@ static int stmmac_set_bfsize(int mtu, in
*/
static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
{
}
/**
-@@ -1418,12 +1418,12 @@ static void stmmac_clear_rx_descriptors(
+@@ -1419,12 +1419,12 @@ static void stmmac_clear_rx_descriptors(
*/
static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
{
struct dma_desc *p;
if (priv->extend_desc)
-@@ -1471,7 +1471,7 @@ static void stmmac_clear_descriptors(str
+@@ -1472,7 +1472,7 @@ static void stmmac_clear_descriptors(str
static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
int i, gfp_t flags, u32 queue)
{
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
if (!buf->page) {
-@@ -1496,7 +1496,7 @@ static int stmmac_init_rx_buffers(struct
+@@ -1497,7 +1497,7 @@ static int stmmac_init_rx_buffers(struct
buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
stmmac_set_desc_addr(priv, p, buf->addr);
stmmac_init_desc3(priv, p);
return 0;
-@@ -1510,7 +1510,7 @@ static int stmmac_init_rx_buffers(struct
+@@ -1511,7 +1511,7 @@ static int stmmac_init_rx_buffers(struct
*/
static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
{
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
if (buf->page)
-@@ -1530,7 +1530,7 @@ static void stmmac_free_rx_buffer(struct
+@@ -1531,7 +1531,7 @@ static void stmmac_free_rx_buffer(struct
*/
static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
{
if (tx_q->tx_skbuff_dma[i].buf &&
tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
-@@ -1575,17 +1575,17 @@ static void dma_free_rx_skbufs(struct st
+@@ -1576,17 +1576,17 @@ static void dma_free_rx_skbufs(struct st
{
int i;
struct dma_desc *p;
int ret;
-@@ -1612,10 +1612,10 @@ static int stmmac_alloc_rx_buffers(struc
+@@ -1613,10 +1613,10 @@ static int stmmac_alloc_rx_buffers(struc
*/
static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
{
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
if (!buf->xdp)
-@@ -1628,10 +1628,10 @@ static void dma_free_rx_xskbufs(struct s
+@@ -1629,10 +1629,10 @@ static void dma_free_rx_xskbufs(struct s
static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
{
struct stmmac_rx_buffer *buf;
dma_addr_t dma_addr;
struct dma_desc *p;
-@@ -1674,7 +1674,7 @@ static struct xsk_buff_pool *stmmac_get_
+@@ -1675,7 +1675,7 @@ static struct xsk_buff_pool *stmmac_get_
*/
static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
{
int ret;
netif_dbg(priv, probe, priv->dev,
-@@ -1720,11 +1720,11 @@ static int __init_dma_rx_desc_rings(stru
+@@ -1721,11 +1721,11 @@ static int __init_dma_rx_desc_rings(stru
if (priv->extend_desc)
stmmac_mode_init(priv, rx_q->dma_erx,
rx_q->dma_rx_phy,
}
return 0;
-@@ -1751,7 +1751,7 @@ static int init_dma_rx_desc_rings(struct
+@@ -1752,7 +1752,7 @@ static int init_dma_rx_desc_rings(struct
err_init_rx_buffers:
while (queue >= 0) {
if (rx_q->xsk_pool)
dma_free_rx_xskbufs(priv, queue);
-@@ -1780,7 +1780,7 @@ err_init_rx_buffers:
+@@ -1781,7 +1781,7 @@ err_init_rx_buffers:
*/
static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
{
int i;
netif_dbg(priv, probe, priv->dev,
-@@ -1792,16 +1792,16 @@ static int __init_dma_tx_desc_rings(stru
+@@ -1793,16 +1793,16 @@ static int __init_dma_tx_desc_rings(stru
if (priv->extend_desc)
stmmac_mode_init(priv, tx_q->dma_etx,
tx_q->dma_tx_phy,
struct dma_desc *p;
if (priv->extend_desc)
-@@ -1871,12 +1871,12 @@ static int init_dma_desc_rings(struct ne
+@@ -1872,12 +1872,12 @@ static int init_dma_desc_rings(struct ne
*/
static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
{
stmmac_free_tx_buffer(priv, queue, i);
if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
-@@ -1906,7 +1906,7 @@ static void stmmac_free_tx_skbufs(struct
+@@ -1907,7 +1907,7 @@ static void stmmac_free_tx_skbufs(struct
*/
static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
/* Release the DMA RX socket buffers */
if (rx_q->xsk_pool)
-@@ -1919,11 +1919,11 @@ static void __free_dma_rx_desc_resources
+@@ -1920,11 +1920,11 @@ static void __free_dma_rx_desc_resources
/* Free DMA regions of consistent memory previously allocated */
if (!priv->extend_desc)
sizeof(struct dma_extended_desc),
rx_q->dma_erx, rx_q->dma_rx_phy);
-@@ -1952,7 +1952,7 @@ static void free_dma_rx_desc_resources(s
+@@ -1953,7 +1953,7 @@ static void free_dma_rx_desc_resources(s
*/
static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
size_t size;
void *addr;
-@@ -1970,7 +1970,7 @@ static void __free_dma_tx_desc_resources
+@@ -1971,7 +1971,7 @@ static void __free_dma_tx_desc_resources
addr = tx_q->dma_tx;
}
dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
-@@ -1999,7 +1999,7 @@ static void free_dma_tx_desc_resources(s
+@@ -2000,7 +2000,7 @@ static void free_dma_tx_desc_resources(s
*/
static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
struct stmmac_channel *ch = &priv->channel[queue];
bool xdp_prog = stmmac_xdp_is_enabled(priv);
struct page_pool_params pp_params = { 0 };
-@@ -2011,8 +2011,8 @@ static int __alloc_dma_rx_desc_resources
+@@ -2012,8 +2012,8 @@ static int __alloc_dma_rx_desc_resources
rx_q->priv_data = priv;
pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
pp_params.order = ilog2(num_pages);
pp_params.nid = dev_to_node(priv->device);
pp_params.dev = priv->device;
-@@ -2027,7 +2027,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2028,7 +2028,7 @@ static int __alloc_dma_rx_desc_resources
return ret;
}
sizeof(*rx_q->buf_pool),
GFP_KERNEL);
if (!rx_q->buf_pool)
-@@ -2035,7 +2035,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2036,7 +2036,7 @@ static int __alloc_dma_rx_desc_resources
if (priv->extend_desc) {
rx_q->dma_erx = dma_alloc_coherent(priv->device,
sizeof(struct dma_extended_desc),
&rx_q->dma_rx_phy,
GFP_KERNEL);
-@@ -2044,7 +2044,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2045,7 +2045,7 @@ static int __alloc_dma_rx_desc_resources
} else {
rx_q->dma_rx = dma_alloc_coherent(priv->device,
sizeof(struct dma_desc),
&rx_q->dma_rx_phy,
GFP_KERNEL);
-@@ -2101,20 +2101,20 @@ err_dma:
+@@ -2102,20 +2102,20 @@ err_dma:
*/
static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
{
sizeof(struct sk_buff *),
GFP_KERNEL);
if (!tx_q->tx_skbuff)
-@@ -2127,7 +2127,7 @@ static int __alloc_dma_tx_desc_resources
+@@ -2128,7 +2128,7 @@ static int __alloc_dma_tx_desc_resources
else
size = sizeof(struct dma_desc);
addr = dma_alloc_coherent(priv->device, size,
&tx_q->dma_tx_phy, GFP_KERNEL);
-@@ -2371,7 +2371,7 @@ static void stmmac_dma_operation_mode(st
+@@ -2372,7 +2372,7 @@ static void stmmac_dma_operation_mode(st
/* configure all channels */
for (chan = 0; chan < rx_channels_count; chan++) {
u32 buf_size;
qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
-@@ -2386,7 +2386,7 @@ static void stmmac_dma_operation_mode(st
+@@ -2387,7 +2387,7 @@ static void stmmac_dma_operation_mode(st
chan);
} else {
stmmac_set_dma_bfsize(priv, priv->ioaddr,
chan);
}
}
-@@ -2402,7 +2402,7 @@ static void stmmac_dma_operation_mode(st
+@@ -2403,7 +2403,7 @@ static void stmmac_dma_operation_mode(st
static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
{
struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
struct xsk_buff_pool *pool = tx_q->xsk_pool;
unsigned int entry = tx_q->cur_tx;
struct dma_desc *tx_desc = NULL;
-@@ -2477,7 +2477,7 @@ static bool stmmac_xdp_xmit_zc(struct st
+@@ -2478,7 +2478,7 @@ static bool stmmac_xdp_xmit_zc(struct st
stmmac_enable_dma_transmission(priv, priv->ioaddr);
entry = tx_q->cur_tx;
}
-@@ -2503,7 +2503,7 @@ static bool stmmac_xdp_xmit_zc(struct st
+@@ -2504,7 +2504,7 @@ static bool stmmac_xdp_xmit_zc(struct st
*/
static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
{
unsigned int bytes_compl = 0, pkts_compl = 0;
unsigned int entry, xmits = 0, count = 0;
-@@ -2516,7 +2516,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2517,7 +2517,7 @@ static int stmmac_tx_clean(struct stmmac
entry = tx_q->dirty_tx;
/* Try to clean all TX complete frame in 1 shot */
struct xdp_frame *xdpf;
struct sk_buff *skb;
struct dma_desc *p;
-@@ -2616,7 +2616,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2617,7 +2617,7 @@ static int stmmac_tx_clean(struct stmmac
stmmac_release_tx_desc(priv, p, priv->mode);
}
tx_q->dirty_tx = entry;
-@@ -2681,7 +2681,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2682,7 +2682,7 @@ static int stmmac_tx_clean(struct stmmac
*/
static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
{
netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
-@@ -2748,8 +2748,8 @@ static int stmmac_napi_check(struct stmm
+@@ -2749,8 +2749,8 @@ static int stmmac_napi_check(struct stmm
{
int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
&priv->xstats, chan, dir);
struct stmmac_channel *ch = &priv->channel[chan];
struct napi_struct *rx_napi;
struct napi_struct *tx_napi;
-@@ -2925,7 +2925,7 @@ static int stmmac_init_dma_engine(struct
+@@ -2926,7 +2926,7 @@ static int stmmac_init_dma_engine(struct
/* DMA RX Channel Configuration */
for (chan = 0; chan < rx_channels_count; chan++) {
stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
rx_q->dma_rx_phy, chan);
-@@ -2939,7 +2939,7 @@ static int stmmac_init_dma_engine(struct
+@@ -2940,7 +2940,7 @@ static int stmmac_init_dma_engine(struct
/* DMA TX Channel Configuration */
for (chan = 0; chan < tx_channels_count; chan++) {
stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
tx_q->dma_tx_phy, chan);
-@@ -2954,7 +2954,7 @@ static int stmmac_init_dma_engine(struct
+@@ -2955,7 +2955,7 @@ static int stmmac_init_dma_engine(struct
static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
{
hrtimer_start(&tx_q->txtimer,
STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
-@@ -3004,7 +3004,7 @@ static void stmmac_init_coalesce(struct
+@@ -3005,7 +3005,7 @@ static void stmmac_init_coalesce(struct
u32 chan;
for (chan = 0; chan < tx_channel_count; chan++) {
priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
-@@ -3026,12 +3026,12 @@ static void stmmac_set_rings_length(stru
+@@ -3027,12 +3027,12 @@ static void stmmac_set_rings_length(stru
/* set TX ring length */
for (chan = 0; chan < tx_channels_count; chan++)
stmmac_set_tx_ring_len(priv, priv->ioaddr,
}
/**
-@@ -3366,7 +3366,7 @@ static int stmmac_hw_setup(struct net_de
+@@ -3367,7 +3367,7 @@ static int stmmac_hw_setup(struct net_de
/* Enable TSO */
if (priv->tso) {
for (chan = 0; chan < tx_cnt; chan++) {
/* TSO and TBS cannot co-exist */
if (tx_q->tbs & STMMAC_TBS_AVAIL)
-@@ -3388,7 +3388,7 @@ static int stmmac_hw_setup(struct net_de
+@@ -3389,7 +3389,7 @@ static int stmmac_hw_setup(struct net_de
/* TBS */
for (chan = 0; chan < tx_cnt; chan++) {
int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
-@@ -3432,7 +3432,7 @@ static void stmmac_free_irq(struct net_d
+@@ -3433,7 +3433,7 @@ static void stmmac_free_irq(struct net_d
for (j = irq_idx - 1; j >= 0; j--) {
if (priv->tx_irq[j] > 0) {
irq_set_affinity_hint(priv->tx_irq[j], NULL);
}
}
irq_idx = priv->plat->rx_queues_to_use;
-@@ -3441,7 +3441,7 @@ static void stmmac_free_irq(struct net_d
+@@ -3442,7 +3442,7 @@ static void stmmac_free_irq(struct net_d
for (j = irq_idx - 1; j >= 0; j--) {
if (priv->rx_irq[j] > 0) {
irq_set_affinity_hint(priv->rx_irq[j], NULL);
}
}
-@@ -3574,7 +3574,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3575,7 +3575,7 @@ static int stmmac_request_irq_multi_msi(
sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
ret = request_irq(priv->rx_irq[i],
stmmac_msi_intr_rx,
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc rx-%d MSI %d (error: %d)\n",
-@@ -3597,7 +3597,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3598,7 +3598,7 @@ static int stmmac_request_irq_multi_msi(
sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
ret = request_irq(priv->tx_irq[i],
stmmac_msi_intr_tx,
if (unlikely(ret < 0)) {
netdev_err(priv->dev,
"%s: alloc tx-%d MSI %d (error: %d)\n",
-@@ -3728,21 +3728,21 @@ static int stmmac_open(struct net_device
+@@ -3729,21 +3729,21 @@ static int stmmac_open(struct net_device
bfsize = 0;
if (bfsize < BUF_SIZE_16KiB)
int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
/* Setup per-TXQ tbs flag before TX descriptor alloc */
-@@ -3800,7 +3800,7 @@ irq_error:
+@@ -3801,7 +3801,7 @@ irq_error:
phylink_stop(priv->phylink);
for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
stmmac_hw_teardown(dev);
init_error:
-@@ -3842,7 +3842,7 @@ static int stmmac_release(struct net_dev
+@@ -3843,7 +3843,7 @@ static int stmmac_release(struct net_dev
stmmac_disable_all_queues(priv);
for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
netif_tx_disable(dev);
-@@ -3906,7 +3906,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3907,7 +3907,7 @@ static bool stmmac_vlan_insert(struct st
return false;
stmmac_set_tx_owner(priv, p);
return true;
}
-@@ -3924,7 +3924,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3925,7 +3925,7 @@ static bool stmmac_vlan_insert(struct st
static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
int total_len, bool last_segment, u32 queue)
{
struct dma_desc *desc;
u32 buff_size;
int tmp_len;
-@@ -3935,7 +3935,7 @@ static void stmmac_tso_allocator(struct
+@@ -3936,7 +3936,7 @@ static void stmmac_tso_allocator(struct
dma_addr_t curr_addr;
tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
if (tx_q->tbs & STMMAC_TBS_AVAIL)
-@@ -3963,7 +3963,7 @@ static void stmmac_tso_allocator(struct
+@@ -3964,7 +3964,7 @@ static void stmmac_tso_allocator(struct
static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
{
int desc_size;
if (likely(priv->extend_desc))
-@@ -4025,7 +4025,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4026,7 +4026,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
dma_addr_t des;
int i;
first_tx = tx_q->cur_tx;
/* Compute header lengths */
-@@ -4065,7 +4065,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4066,7 +4066,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
stmmac_set_mss(priv, mss_desc, mss);
tx_q->mss = mss;
tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
}
-@@ -4177,7 +4177,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4178,7 +4178,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
* ndo_start_xmit will fill this descriptor the next time it's
* called and stmmac_tx_clean may clean up to this descriptor.
*/
if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
-@@ -4265,7 +4265,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4266,7 +4266,7 @@ static netdev_tx_t stmmac_xmit(struct sk
int entry, first_tx;
dma_addr_t des;
first_tx = tx_q->cur_tx;
if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
-@@ -4328,7 +4328,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4329,7 +4329,7 @@ static netdev_tx_t stmmac_xmit(struct sk
int len = skb_frag_size(frag);
bool last_segment = (i == (nfrags - 1));
WARN_ON(tx_q->tx_skbuff[entry]);
if (likely(priv->extend_desc))
-@@ -4399,7 +4399,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4400,7 +4400,7 @@ static netdev_tx_t stmmac_xmit(struct sk
* ndo_start_xmit will fill this descriptor the next time it's
* called and stmmac_tx_clean may clean up to this descriptor.
*/
tx_q->cur_tx = entry;
if (netif_msg_pktdata(priv)) {
-@@ -4514,7 +4514,7 @@ static void stmmac_rx_vlan(struct net_de
+@@ -4512,7 +4512,7 @@ static void stmmac_rx_vlan(struct net_de
*/
static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
{
int dirty = stmmac_rx_dirty(priv, queue);
unsigned int entry = rx_q->dirty_rx;
-@@ -4564,7 +4564,7 @@ static inline void stmmac_rx_refill(stru
+@@ -4562,7 +4562,7 @@ static inline void stmmac_rx_refill(stru
dma_wmb();
stmmac_set_rx_owner(priv, p, use_rx_wd);
}
rx_q->dirty_rx = entry;
rx_q->rx_tail_addr = rx_q->dma_rx_phy +
-@@ -4592,12 +4592,12 @@ static unsigned int stmmac_rx_buf1_len(s
+@@ -4590,12 +4590,12 @@ static unsigned int stmmac_rx_buf1_len(s
/* First descriptor, not last descriptor and not split header */
if (status & rx_not_ls)
}
static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
-@@ -4613,7 +4613,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4611,7 +4611,7 @@ static unsigned int stmmac_rx_buf2_len(s
/* Not last descriptor */
if (status & rx_not_ls)
plen = stmmac_get_rx_frame_len(priv, p, coe);
-@@ -4624,7 +4624,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4622,7 +4622,7 @@ static unsigned int stmmac_rx_buf2_len(s
static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
struct xdp_frame *xdpf, bool dma_map)
{
unsigned int entry = tx_q->cur_tx;
struct dma_desc *tx_desc;
dma_addr_t dma_addr;
-@@ -4687,7 +4687,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
+@@ -4685,7 +4685,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
stmmac_enable_dma_transmission(priv, priv->ioaddr);
tx_q->cur_tx = entry;
return STMMAC_XDP_TX;
-@@ -4861,7 +4861,7 @@ static void stmmac_dispatch_skb_zc(struc
+@@ -4859,7 +4859,7 @@ static void stmmac_dispatch_skb_zc(struc
static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
{
unsigned int entry = rx_q->dirty_rx;
struct dma_desc *rx_desc = NULL;
bool ret = true;
-@@ -4904,7 +4904,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4902,7 +4902,7 @@ static bool stmmac_rx_refill_zc(struct s
dma_wmb();
stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
}
if (rx_desc) {
-@@ -4919,7 +4919,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4917,7 +4917,7 @@ static bool stmmac_rx_refill_zc(struct s
static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
{
unsigned int count = 0, error = 0, len = 0;
int dirty = stmmac_rx_dirty(priv, queue);
unsigned int next_entry = rx_q->cur_rx;
-@@ -4941,7 +4941,7 @@ static int stmmac_rx_zc(struct stmmac_pr
+@@ -4939,7 +4939,7 @@ static int stmmac_rx_zc(struct stmmac_pr
desc_size = sizeof(struct dma_desc);
}
rx_q->dma_rx_phy, desc_size);
}
while (count < limit) {
-@@ -4988,7 +4988,7 @@ read_again:
+@@ -4986,7 +4986,7 @@ read_again:
/* Prefetch the next RX descriptor */
rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
next_entry = rx_q->cur_rx;
if (priv->extend_desc)
-@@ -5109,7 +5109,7 @@ read_again:
+@@ -5107,7 +5107,7 @@ read_again:
*/
static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
{
struct stmmac_channel *ch = &priv->channel[queue];
unsigned int count = 0, error = 0, len = 0;
int status = 0, coe = priv->hw->rx_csum;
-@@ -5122,7 +5122,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5120,7 +5120,7 @@ static int stmmac_rx(struct stmmac_priv
int buf_sz;
dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
if (netif_msg_rx_status(priv)) {
void *rx_head;
-@@ -5136,7 +5136,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5134,7 +5134,7 @@ static int stmmac_rx(struct stmmac_priv
desc_size = sizeof(struct dma_desc);
}
rx_q->dma_rx_phy, desc_size);
}
while (count < limit) {
-@@ -5180,7 +5180,7 @@ read_again:
+@@ -5178,7 +5178,7 @@ read_again:
break;
rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
next_entry = rx_q->cur_rx;
if (priv->extend_desc)
-@@ -5314,7 +5314,7 @@ read_again:
+@@ -5312,7 +5312,7 @@ read_again:
buf1_len, dma_dir);
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
buf->page, buf->page_offset, buf1_len,
/* Data payload appended into SKB */
page_pool_release_page(rx_q->page_pool, buf->page);
-@@ -5326,7 +5326,7 @@ read_again:
+@@ -5324,7 +5324,7 @@ read_again:
buf2_len, dma_dir);
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
buf->sec_page, 0, buf2_len,
/* Data payload appended into SKB */
page_pool_release_page(rx_q->page_pool, buf->sec_page);
-@@ -5768,11 +5768,13 @@ static irqreturn_t stmmac_safety_interru
+@@ -5767,11 +5767,13 @@ static irqreturn_t stmmac_safety_interru
static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
{
struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
if (unlikely(!data)) {
netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
-@@ -5812,10 +5814,12 @@ static irqreturn_t stmmac_msi_intr_tx(in
+@@ -5811,10 +5813,12 @@ static irqreturn_t stmmac_msi_intr_tx(in
static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
{
struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
if (unlikely(!data)) {
netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
-@@ -5846,10 +5850,10 @@ static void stmmac_poll_controller(struc
+@@ -5845,10 +5849,10 @@ static void stmmac_poll_controller(struc
if (priv->plat->multi_msi_en) {
for (i = 0; i < priv->plat->rx_queues_to_use; i++)
} else {
disable_irq(dev->irq);
stmmac_interrupt(dev->irq, dev);
-@@ -6030,34 +6034,34 @@ static int stmmac_rings_status_show(stru
+@@ -6029,34 +6033,34 @@ static int stmmac_rings_status_show(stru
return 0;
for (queue = 0; queue < rx_count; queue++) {
}
}
-@@ -6404,7 +6408,7 @@ void stmmac_disable_rx_queue(struct stmm
+@@ -6403,7 +6407,7 @@ void stmmac_disable_rx_queue(struct stmm
void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
{
struct stmmac_channel *ch = &priv->channel[queue];
unsigned long flags;
u32 buf_size;
-@@ -6441,7 +6445,7 @@ void stmmac_enable_rx_queue(struct stmma
+@@ -6440,7 +6444,7 @@ void stmmac_enable_rx_queue(struct stmma
rx_q->queue_index);
} else {
stmmac_set_dma_bfsize(priv, priv->ioaddr,
rx_q->queue_index);
}
-@@ -6467,7 +6471,7 @@ void stmmac_disable_tx_queue(struct stmm
+@@ -6466,7 +6470,7 @@ void stmmac_disable_tx_queue(struct stmm
void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
{
struct stmmac_channel *ch = &priv->channel[queue];
unsigned long flags;
int ret;
-@@ -6517,7 +6521,7 @@ void stmmac_xdp_release(struct net_devic
+@@ -6516,7 +6520,7 @@ void stmmac_xdp_release(struct net_devic
stmmac_disable_all_queues(priv);
for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
/* Free the IRQ lines */
stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
-@@ -6576,7 +6580,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6575,7 +6579,7 @@ int stmmac_xdp_open(struct net_device *d
/* DMA RX Channel Configuration */
for (chan = 0; chan < rx_cnt; chan++) {
stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
rx_q->dma_rx_phy, chan);
-@@ -6594,7 +6598,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6593,7 +6597,7 @@ int stmmac_xdp_open(struct net_device *d
rx_q->queue_index);
} else {
stmmac_set_dma_bfsize(priv, priv->ioaddr,
rx_q->queue_index);
}
-@@ -6603,7 +6607,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6602,7 +6606,7 @@ int stmmac_xdp_open(struct net_device *d
/* DMA TX Channel Configuration */
for (chan = 0; chan < tx_cnt; chan++) {
stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
tx_q->dma_tx_phy, chan);
-@@ -6636,7 +6640,7 @@ int stmmac_xdp_open(struct net_device *d
+@@ -6635,7 +6639,7 @@ int stmmac_xdp_open(struct net_device *d
irq_error:
for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
stmmac_hw_teardown(dev);
init_error:
-@@ -6663,8 +6667,8 @@ int stmmac_xsk_wakeup(struct net_device
+@@ -6662,8 +6666,8 @@ int stmmac_xsk_wakeup(struct net_device
queue >= priv->plat->tx_queues_to_use)
return -EINVAL;
ch = &priv->channel[queue];
if (!rx_q->xsk_pool && !tx_q->xsk_pool)
-@@ -6924,8 +6928,8 @@ int stmmac_reinit_ringparam(struct net_d
+@@ -6923,8 +6927,8 @@ int stmmac_reinit_ringparam(struct net_d
if (netif_running(dev))
stmmac_release(dev);
if (netif_running(dev))
ret = stmmac_open(dev);
-@@ -7357,7 +7361,7 @@ int stmmac_suspend(struct device *dev)
+@@ -7359,7 +7363,7 @@ int stmmac_suspend(struct device *dev)
stmmac_disable_all_queues(priv);
for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
if (priv->eee_enabled) {
priv->tx_path_in_lpi_mode = false;
-@@ -7408,7 +7412,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
+@@ -7411,7 +7415,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
{
rx_q->cur_rx = 0;
rx_q->dirty_rx = 0;
-@@ -7416,7 +7420,7 @@ static void stmmac_reset_rx_queue(struct
+@@ -7419,7 +7423,7 @@ static void stmmac_reset_rx_queue(struct
static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
{
if (i >= priv->plat->tx_queues_to_use)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c
-@@ -970,13 +970,13 @@ static int tc_setup_etf(struct stmmac_pr
+@@ -971,13 +971,13 @@ static int tc_setup_etf(struct stmmac_pr
return -EOPNOTSUPP;
if (qopt->queue >= priv->plat->tx_queues_to_use)
return -EINVAL;
+ &gpll0_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -429,9 +86,8 @@ static struct clk_alpha_pll_postdiv gpll
+ },
+@@ -428,9 +85,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
},
-@@ -445,8 +101,9 @@ static struct clk_alpha_pll gpll2_main =
+@@ -444,8 +100,9 @@ static struct clk_alpha_pll gpll2_main =
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gpll2_main",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
-@@ -461,9 +118,8 @@ static struct clk_alpha_pll_postdiv gpll
+@@ -460,9 +117,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll2",
+ &gpll2_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -478,8 +134,9 @@ static struct clk_alpha_pll gpll4_main =
+ },
+@@ -476,8 +132,9 @@ static struct clk_alpha_pll gpll4_main =
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_main",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
-@@ -494,9 +151,8 @@ static struct clk_alpha_pll_postdiv gpll
+@@ -492,9 +149,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
+ &gpll4_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -512,8 +168,9 @@ static struct clk_alpha_pll gpll6_main =
+ },
+@@ -509,8 +165,9 @@ static struct clk_alpha_pll gpll6_main =
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_main",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
-@@ -528,9 +185,8 @@ static struct clk_alpha_pll_postdiv gpll
+@@ -525,9 +182,8 @@ static struct clk_alpha_pll_postdiv gpll
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
+ &gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -542,9 +198,8 @@ static struct clk_fixed_factor gpll6_out
+ },
+@@ -538,9 +194,8 @@ static struct clk_fixed_factor gpll6_out
.div = 2,
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_main_div2",
+ &gpll6_main.clkr.hw },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -560,8 +215,9 @@ static struct clk_alpha_pll ubi32_pll_ma
+ },
+@@ -555,8 +210,9 @@ static struct clk_alpha_pll ubi32_pll_ma
.enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){
.name = "ubi32_pll_main",
},
.num_parents = 1,
.ops = &clk_alpha_pll_huayra_ops,
-@@ -575,9 +231,8 @@ static struct clk_alpha_pll_postdiv ubi3
+@@ -570,9 +226,8 @@ static struct clk_alpha_pll_postdiv ubi3
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi32_pll",
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -592,8 +247,9 @@ static struct clk_alpha_pll nss_crypto_p
+@@ -587,8 +242,9 @@ static struct clk_alpha_pll nss_crypto_p
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll_main",
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
-@@ -607,9 +263,8 @@ static struct clk_alpha_pll_postdiv nss_
+@@ -602,9 +258,8 @@ static struct clk_alpha_pll_postdiv nss_
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_pll",
+ &nss_crypto_pll_main.clkr.hw },
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -623,6 +278,18 @@ static const struct freq_tbl ftbl_pcnoc_
+ },
+@@ -617,6 +272,18 @@ static const struct freq_tbl ftbl_pcnoc_
{ }
};
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
.cmd_rcgr = 0x27000,
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
-@@ -630,8 +297,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
+@@ -624,8 +291,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcnoc_bfdcd_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
-@@ -642,9 +309,8 @@ static struct clk_fixed_factor pcnoc_clk
+@@ -636,9 +303,8 @@ static struct clk_fixed_factor pcnoc_clk
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "pcnoc_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -658,8 +324,9 @@ static struct clk_branch gcc_sleep_clk_s
+@@ -652,8 +318,9 @@ static struct clk_branch gcc_sleep_clk_s
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_sleep_clk_src",
},
.num_parents = 1,
.ops = &clk_branch2_ops,
-@@ -682,8 +349,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
+@@ -676,8 +343,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -708,8 +375,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
+@@ -702,8 +369,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -721,8 +388,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
+@@ -715,8 +382,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -735,8 +402,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
+@@ -729,8 +396,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -748,8 +415,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
+@@ -742,8 +409,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -762,8 +429,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
+@@ -756,8 +423,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -775,8 +442,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
+@@ -769,8 +436,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -789,8 +456,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
+@@ -783,8 +450,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -802,8 +469,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
+@@ -796,8 +463,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_i2c_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -816,8 +483,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
+@@ -810,8 +477,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup5_spi_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -829,8 +496,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
+@@ -823,8 +490,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_i2c_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -843,8 +510,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
+@@ -837,8 +504,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup6_spi_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -877,8 +544,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
+@@ -871,8 +538,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -891,8 +558,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
+@@ -885,8 +552,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -905,8 +572,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
+@@ -899,8 +566,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -919,8 +586,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
+@@ -913,8 +580,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart4_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -933,8 +600,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
+@@ -927,8 +594,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart5_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -947,8 +614,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
+@@ -941,8 +608,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart6_apps_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -958,6 +625,11 @@ static const struct clk_parent_data gcc_
+@@ -952,6 +619,11 @@ static const struct clk_parent_data gcc_
{ .hw = &gpll0.clkr.hw },
};
static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
-@@ -972,7 +644,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
+@@ -966,7 +638,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.ops = &clk_rcg2_ops,
},
};
-@@ -981,6 +653,18 @@ static const struct freq_tbl ftbl_pcie_a
+@@ -975,6 +647,18 @@ static const struct freq_tbl ftbl_pcie_a
F(19200000, P_XO, 1, 0, 0),
};
static struct clk_rcg2 pcie0_aux_clk_src = {
.cmd_rcgr = 0x75024,
.freq_tbl = ftbl_pcie_aux_clk_src,
-@@ -989,12 +673,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
+@@ -983,12 +667,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_aux_clk_src",
static struct clk_regmap_mux pcie0_pipe_clk_src = {
.reg = 0x7501c,
.shift = 8,
-@@ -1003,8 +697,8 @@ static struct clk_regmap_mux pcie0_pipe_
+@@ -997,8 +691,8 @@ static struct clk_regmap_mux pcie0_pipe_
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie0_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1019,7 +713,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
+@@ -1013,7 +707,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_axi_clk_src",
.parent_data = gcc_xo_gpll0,
.ops = &clk_rcg2_ops,
},
};
-@@ -1032,12 +726,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
+@@ -1026,12 +720,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie1_aux_clk_src",
static struct clk_regmap_mux pcie1_pipe_clk_src = {
.reg = 0x7601c,
.shift = 8,
-@@ -1046,8 +750,8 @@ static struct clk_regmap_mux pcie1_pipe_
+@@ -1040,8 +744,8 @@ static struct clk_regmap_mux pcie1_pipe_
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1066,6 +770,20 @@ static const struct freq_tbl ftbl_sdcc_a
+@@ -1060,6 +764,20 @@ static const struct freq_tbl ftbl_sdcc_a
{ }
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
.cmd_rcgr = 0x42004,
.freq_tbl = ftbl_sdcc_apps_clk_src,
-@@ -1074,8 +792,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
+@@ -1068,8 +786,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.ops = &clk_rcg2_floor_ops,
},
};
-@@ -1086,6 +804,20 @@ static const struct freq_tbl ftbl_sdcc_i
+@@ -1080,6 +798,20 @@ static const struct freq_tbl ftbl_sdcc_i
F(308570000, P_GPLL6, 3.5, 0, 0),
};
static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0x5d000,
.freq_tbl = ftbl_sdcc_ice_core_clk_src,
-@@ -1094,8 +826,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
+@@ -1088,8 +820,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1108,8 +840,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
+@@ -1102,8 +834,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.ops = &clk_rcg2_floor_ops,
},
};
-@@ -1121,6 +853,18 @@ static const struct freq_tbl ftbl_usb_ma
+@@ -1115,6 +847,18 @@ static const struct freq_tbl ftbl_usb_ma
{ }
};
static struct clk_rcg2 usb0_master_clk_src = {
.cmd_rcgr = 0x3e00c,
.freq_tbl = ftbl_usb_master_clk_src,
-@@ -1129,8 +873,8 @@ static struct clk_rcg2 usb0_master_clk_s
+@@ -1123,8 +867,8 @@ static struct clk_rcg2 usb0_master_clk_s
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_master_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1148,8 +892,8 @@ static struct clk_rcg2 usb0_aux_clk_src
+@@ -1142,8 +886,8 @@ static struct clk_rcg2 usb0_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_aux_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1161,6 +905,20 @@ static const struct freq_tbl ftbl_usb_mo
+@@ -1155,6 +899,20 @@ static const struct freq_tbl ftbl_usb_mo
{ }
};
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
.cmd_rcgr = 0x3e020,
.freq_tbl = ftbl_usb_mock_utmi_clk_src,
-@@ -1169,12 +927,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+@@ -1163,12 +921,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb0_mock_utmi_clk_src",
static struct clk_regmap_mux usb0_pipe_clk_src = {
.reg = 0x3e048,
.shift = 8,
-@@ -1183,8 +951,8 @@ static struct clk_regmap_mux usb0_pipe_c
+@@ -1177,8 +945,8 @@ static struct clk_regmap_mux usb0_pipe_c
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb0_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1199,8 +967,8 @@ static struct clk_rcg2 usb1_master_clk_s
+@@ -1193,8 +961,8 @@ static struct clk_rcg2 usb1_master_clk_s
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_master_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1213,8 +981,8 @@ static struct clk_rcg2 usb1_aux_clk_src
+@@ -1207,8 +975,8 @@ static struct clk_rcg2 usb1_aux_clk_src
.parent_map = gcc_xo_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_aux_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1227,12 +995,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
+@@ -1221,12 +989,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb1_mock_utmi_clk_src",
static struct clk_regmap_mux usb1_pipe_clk_src = {
.reg = 0x3f048,
.shift = 8,
-@@ -1241,8 +1019,8 @@ static struct clk_regmap_mux usb1_pipe_c
+@@ -1235,8 +1013,8 @@ static struct clk_regmap_mux usb1_pipe_c
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "usb1_pipe_clk_src",
.ops = &clk_regmap_mux_closest_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1256,8 +1034,9 @@ static struct clk_branch gcc_xo_clk_src
+@@ -1250,8 +1028,9 @@ static struct clk_branch gcc_xo_clk_src
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_clk_src",
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-@@ -1271,9 +1050,8 @@ static struct clk_fixed_factor gcc_xo_di
+@@ -1265,9 +1044,8 @@ static struct clk_fixed_factor gcc_xo_di
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "gcc_xo_div4_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1291,6 +1069,20 @@ static const struct freq_tbl ftbl_system
+@@ -1285,6 +1063,20 @@ static const struct freq_tbl ftbl_system
{ }
};
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x26004,
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
-@@ -1298,8 +1090,8 @@ static struct clk_rcg2 system_noc_bfdcd_
+@@ -1292,8 +1084,8 @@ static struct clk_rcg2 system_noc_bfdcd_
.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "system_noc_bfdcd_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_IS_CRITICAL,
},
-@@ -1310,9 +1102,8 @@ static struct clk_fixed_factor system_no
+@@ -1304,9 +1096,8 @@ static struct clk_fixed_factor system_no
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "system_noc_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1333,7 +1124,7 @@ static struct clk_rcg2 nss_ce_clk_src =
+@@ -1327,7 +1118,7 @@ static struct clk_rcg2 nss_ce_clk_src =
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ce_clk_src",
.parent_data = gcc_xo_gpll0,
.ops = &clk_rcg2_ops,
},
};
-@@ -1344,6 +1135,20 @@ static const struct freq_tbl ftbl_nss_no
+@@ -1338,6 +1129,20 @@ static const struct freq_tbl ftbl_nss_no
{ }
};
static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
.cmd_rcgr = 0x68088,
.freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
-@@ -1351,8 +1156,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
+@@ -1345,8 +1150,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
.parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_noc_bfdcd_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1362,9 +1167,8 @@ static struct clk_fixed_factor nss_noc_c
+@@ -1356,9 +1161,8 @@ static struct clk_fixed_factor nss_noc_c
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "nss_noc_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1377,6 +1181,18 @@ static const struct freq_tbl ftbl_nss_cr
+@@ -1371,6 +1175,18 @@ static const struct freq_tbl ftbl_nss_cr
{ }
};
static struct clk_rcg2 nss_crypto_clk_src = {
.cmd_rcgr = 0x68144,
.freq_tbl = ftbl_nss_crypto_clk_src,
-@@ -1385,8 +1201,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
+@@ -1379,8 +1195,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_crypto_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1400,6 +1216,24 @@ static const struct freq_tbl ftbl_nss_ub
+@@ -1394,6 +1210,24 @@ static const struct freq_tbl ftbl_nss_ub
{ }
};
static struct clk_rcg2 nss_ubi0_clk_src = {
.cmd_rcgr = 0x68104,
.freq_tbl = ftbl_nss_ubi_clk_src,
-@@ -1407,8 +1241,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
+@@ -1401,8 +1235,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1421,9 +1255,8 @@ static struct clk_regmap_div nss_ubi0_di
+@@ -1415,9 +1249,8 @@ static struct clk_regmap_div nss_ubi0_di
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi0_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1438,8 +1271,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
+@@ -1432,8 +1265,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_clk_src",
.ops = &clk_rcg2_ops,
.flags = CLK_SET_RATE_PARENT,
},
-@@ -1452,9 +1285,8 @@ static struct clk_regmap_div nss_ubi1_di
+@@ -1446,9 +1279,8 @@ static struct clk_regmap_div nss_ubi1_di
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_ubi1_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1468,6 +1300,16 @@ static const struct freq_tbl ftbl_ubi_mp
+@@ -1462,6 +1294,16 @@ static const struct freq_tbl ftbl_ubi_mp
{ }
};
static struct clk_rcg2 ubi_mpt_clk_src = {
.cmd_rcgr = 0x68090,
.freq_tbl = ftbl_ubi_mpt_clk_src,
-@@ -1475,8 +1317,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
+@@ -1469,8 +1311,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
.parent_map = gcc_xo_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "ubi_mpt_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1487,6 +1329,18 @@ static const struct freq_tbl ftbl_nss_im
+@@ -1481,6 +1323,18 @@ static const struct freq_tbl ftbl_nss_im
{ }
};
static struct clk_rcg2 nss_imem_clk_src = {
.cmd_rcgr = 0x68158,
.freq_tbl = ftbl_nss_imem_clk_src,
-@@ -1494,8 +1348,8 @@ static struct clk_rcg2 nss_imem_clk_src
+@@ -1488,8 +1342,8 @@ static struct clk_rcg2 nss_imem_clk_src
.parent_map = gcc_xo_gpll0_gpll4_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_imem_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1506,6 +1360,24 @@ static const struct freq_tbl ftbl_nss_pp
+@@ -1500,6 +1354,24 @@ static const struct freq_tbl ftbl_nss_pp
{ }
};
static struct clk_rcg2 nss_ppe_clk_src = {
.cmd_rcgr = 0x68080,
.freq_tbl = ftbl_nss_ppe_clk_src,
-@@ -1513,8 +1385,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
+@@ -1507,8 +1379,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_ppe_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1524,9 +1396,8 @@ static struct clk_fixed_factor nss_ppe_c
+@@ -1518,9 +1390,8 @@ static struct clk_fixed_factor nss_ppe_c
.div = 4,
.hw.init = &(struct clk_init_data){
.name = "nss_ppe_cdiv_clk_src",
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1540,6 +1411,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1534,6 +1405,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port1_rx_clk_src = {
.cmd_rcgr = 0x68020,
.freq_tbl = ftbl_nss_port1_rx_clk_src,
-@@ -1547,8 +1434,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
+@@ -1541,8 +1428,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1560,9 +1447,8 @@ static struct clk_regmap_div nss_port1_r
+@@ -1554,9 +1441,8 @@ static struct clk_regmap_div nss_port1_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1577,6 +1463,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1571,6 +1457,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port1_tx_clk_src = {
.cmd_rcgr = 0x68028,
.freq_tbl = ftbl_nss_port1_tx_clk_src,
-@@ -1584,8 +1486,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
+@@ -1578,8 +1480,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1597,9 +1499,8 @@ static struct clk_regmap_div nss_port1_t
+@@ -1591,9 +1493,8 @@ static struct clk_regmap_div nss_port1_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port1_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1614,8 +1515,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
+@@ -1608,8 +1509,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1627,9 +1528,8 @@ static struct clk_regmap_div nss_port2_r
+@@ -1621,9 +1522,8 @@ static struct clk_regmap_div nss_port2_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1644,8 +1544,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
+@@ -1638,8 +1538,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1657,9 +1557,8 @@ static struct clk_regmap_div nss_port2_t
+@@ -1651,9 +1551,8 @@ static struct clk_regmap_div nss_port2_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port2_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1674,8 +1573,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
+@@ -1668,8 +1567,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1687,9 +1586,8 @@ static struct clk_regmap_div nss_port3_r
+@@ -1681,9 +1580,8 @@ static struct clk_regmap_div nss_port3_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1704,8 +1602,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
+@@ -1698,8 +1596,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1717,9 +1615,8 @@ static struct clk_regmap_div nss_port3_t
+@@ -1711,9 +1609,8 @@ static struct clk_regmap_div nss_port3_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port3_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1734,8 +1631,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
+@@ -1728,8 +1625,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1747,9 +1644,8 @@ static struct clk_regmap_div nss_port4_r
+@@ -1741,9 +1638,8 @@ static struct clk_regmap_div nss_port4_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1764,8 +1660,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
+@@ -1758,8 +1654,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1777,9 +1673,8 @@ static struct clk_regmap_div nss_port4_t
+@@ -1771,9 +1667,8 @@ static struct clk_regmap_div nss_port4_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port4_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1799,6 +1694,27 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1793,6 +1688,27 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port5_rx_clk_src = {
.cmd_rcgr = 0x68060,
.freq_tbl = ftbl_nss_port5_rx_clk_src,
-@@ -1806,8 +1722,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
+@@ -1800,8 +1716,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1819,9 +1735,8 @@ static struct clk_regmap_div nss_port5_r
+@@ -1813,9 +1729,8 @@ static struct clk_regmap_div nss_port5_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1841,6 +1756,27 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1835,6 +1750,27 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port5_tx_clk_src = {
.cmd_rcgr = 0x68068,
.freq_tbl = ftbl_nss_port5_tx_clk_src,
-@@ -1848,8 +1784,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
+@@ -1842,8 +1778,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1861,9 +1797,8 @@ static struct clk_regmap_div nss_port5_t
+@@ -1855,9 +1791,8 @@ static struct clk_regmap_div nss_port5_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port5_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1883,6 +1818,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1877,6 +1812,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port6_rx_clk_src = {
.cmd_rcgr = 0x68070,
.freq_tbl = ftbl_nss_port6_rx_clk_src,
-@@ -1890,8 +1841,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
+@@ -1884,8 +1835,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1903,9 +1854,8 @@ static struct clk_regmap_div nss_port6_r
+@@ -1897,9 +1848,8 @@ static struct clk_regmap_div nss_port6_r
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_rx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1925,6 +1875,22 @@ static const struct freq_tbl ftbl_nss_po
+@@ -1919,6 +1869,22 @@ static const struct freq_tbl ftbl_nss_po
{ }
};
static struct clk_rcg2 nss_port6_tx_clk_src = {
.cmd_rcgr = 0x68078,
.freq_tbl = ftbl_nss_port6_tx_clk_src,
-@@ -1932,8 +1898,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
+@@ -1926,8 +1892,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1945,9 +1911,8 @@ static struct clk_regmap_div nss_port6_t
+@@ -1939,9 +1905,8 @@ static struct clk_regmap_div nss_port6_t
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "nss_port6_tx_div_clk_src",
.num_parents = 1,
.ops = &clk_regmap_div_ops,
.flags = CLK_SET_RATE_PARENT,
-@@ -1970,8 +1935,8 @@ static struct clk_rcg2 crypto_clk_src =
+@@ -1964,8 +1929,8 @@ static struct clk_rcg2 crypto_clk_src =
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "crypto_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -1981,6 +1946,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
+@@ -1975,6 +1940,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
{ }
};
static struct clk_rcg2 gp1_clk_src = {
.cmd_rcgr = 0x08004,
.freq_tbl = ftbl_gp_clk_src,
-@@ -1989,8 +1970,8 @@ static struct clk_rcg2 gp1_clk_src = {
+@@ -1983,8 +1964,8 @@ static struct clk_rcg2 gp1_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -2003,8 +1984,8 @@ static struct clk_rcg2 gp2_clk_src = {
+@@ -1997,8 +1978,8 @@ static struct clk_rcg2 gp2_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -2017,8 +1998,8 @@ static struct clk_rcg2 gp3_clk_src = {
+@@ -2011,8 +1992,8 @@ static struct clk_rcg2 gp3_clk_src = {
.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.ops = &clk_rcg2_ops,
},
};
-@@ -2030,9 +2011,8 @@ static struct clk_branch gcc_blsp1_ahb_c
+@@ -2024,9 +2005,8 @@ static struct clk_branch gcc_blsp1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2047,9 +2027,8 @@ static struct clk_branch gcc_blsp1_qup1_
+@@ -2041,9 +2021,8 @@ static struct clk_branch gcc_blsp1_qup1_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2064,9 +2043,8 @@ static struct clk_branch gcc_blsp1_qup1_
+@@ -2058,9 +2037,8 @@ static struct clk_branch gcc_blsp1_qup1_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2081,9 +2059,8 @@ static struct clk_branch gcc_blsp1_qup2_
+@@ -2075,9 +2053,8 @@ static struct clk_branch gcc_blsp1_qup2_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2098,9 +2075,8 @@ static struct clk_branch gcc_blsp1_qup2_
+@@ -2092,9 +2069,8 @@ static struct clk_branch gcc_blsp1_qup2_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2115,9 +2091,8 @@ static struct clk_branch gcc_blsp1_qup3_
+@@ -2109,9 +2085,8 @@ static struct clk_branch gcc_blsp1_qup3_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2132,9 +2107,8 @@ static struct clk_branch gcc_blsp1_qup3_
+@@ -2126,9 +2101,8 @@ static struct clk_branch gcc_blsp1_qup3_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2149,9 +2123,8 @@ static struct clk_branch gcc_blsp1_qup4_
+@@ -2143,9 +2117,8 @@ static struct clk_branch gcc_blsp1_qup4_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2166,9 +2139,8 @@ static struct clk_branch gcc_blsp1_qup4_
+@@ -2160,9 +2133,8 @@ static struct clk_branch gcc_blsp1_qup4_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2183,9 +2155,8 @@ static struct clk_branch gcc_blsp1_qup5_
+@@ -2177,9 +2149,8 @@ static struct clk_branch gcc_blsp1_qup5_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2200,9 +2171,8 @@ static struct clk_branch gcc_blsp1_qup5_
+@@ -2194,9 +2165,8 @@ static struct clk_branch gcc_blsp1_qup5_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup5_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2217,9 +2187,8 @@ static struct clk_branch gcc_blsp1_qup6_
+@@ -2211,9 +2181,8 @@ static struct clk_branch gcc_blsp1_qup6_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_i2c_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2234,9 +2203,8 @@ static struct clk_branch gcc_blsp1_qup6_
+@@ -2228,9 +2197,8 @@ static struct clk_branch gcc_blsp1_qup6_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup6_spi_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2251,9 +2219,8 @@ static struct clk_branch gcc_blsp1_uart1
+@@ -2245,9 +2213,8 @@ static struct clk_branch gcc_blsp1_uart1
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2268,9 +2235,8 @@ static struct clk_branch gcc_blsp1_uart2
+@@ -2262,9 +2229,8 @@ static struct clk_branch gcc_blsp1_uart2
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2285,9 +2251,8 @@ static struct clk_branch gcc_blsp1_uart3
+@@ -2279,9 +2245,8 @@ static struct clk_branch gcc_blsp1_uart3
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2302,9 +2267,8 @@ static struct clk_branch gcc_blsp1_uart4
+@@ -2296,9 +2261,8 @@ static struct clk_branch gcc_blsp1_uart4
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2319,9 +2283,8 @@ static struct clk_branch gcc_blsp1_uart5
+@@ -2313,9 +2277,8 @@ static struct clk_branch gcc_blsp1_uart5
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart5_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2336,9 +2299,8 @@ static struct clk_branch gcc_blsp1_uart6
+@@ -2330,9 +2293,8 @@ static struct clk_branch gcc_blsp1_uart6
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart6_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2354,9 +2316,8 @@ static struct clk_branch gcc_prng_ahb_cl
+@@ -2348,9 +2310,8 @@ static struct clk_branch gcc_prng_ahb_cl
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "gcc_prng_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2371,9 +2332,8 @@ static struct clk_branch gcc_qpic_ahb_cl
+@@ -2365,9 +2326,8 @@ static struct clk_branch gcc_qpic_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2388,9 +2348,8 @@ static struct clk_branch gcc_qpic_clk =
+@@ -2382,9 +2342,8 @@ static struct clk_branch gcc_qpic_clk =
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_qpic_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2405,9 +2364,8 @@ static struct clk_branch gcc_pcie0_ahb_c
+@@ -2399,9 +2358,8 @@ static struct clk_branch gcc_pcie0_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2422,9 +2380,8 @@ static struct clk_branch gcc_pcie0_aux_c
+@@ -2416,9 +2374,8 @@ static struct clk_branch gcc_pcie0_aux_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2439,9 +2396,8 @@ static struct clk_branch gcc_pcie0_axi_m
+@@ -2433,9 +2390,8 @@ static struct clk_branch gcc_pcie0_axi_m
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_m_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2456,9 +2412,8 @@ static struct clk_branch gcc_pcie0_axi_s
+@@ -2450,9 +2406,8 @@ static struct clk_branch gcc_pcie0_axi_s
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_axi_s_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2474,9 +2429,8 @@ static struct clk_branch gcc_pcie0_pipe_
+@@ -2468,9 +2423,8 @@ static struct clk_branch gcc_pcie0_pipe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2491,9 +2445,8 @@ static struct clk_branch gcc_sys_noc_pci
+@@ -2485,9 +2439,8 @@ static struct clk_branch gcc_sys_noc_pci
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie0_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2508,9 +2461,8 @@ static struct clk_branch gcc_pcie1_ahb_c
+@@ -2502,9 +2455,8 @@ static struct clk_branch gcc_pcie1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2525,9 +2477,8 @@ static struct clk_branch gcc_pcie1_aux_c
+@@ -2519,9 +2471,8 @@ static struct clk_branch gcc_pcie1_aux_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2542,9 +2493,8 @@ static struct clk_branch gcc_pcie1_axi_m
+@@ -2536,9 +2487,8 @@ static struct clk_branch gcc_pcie1_axi_m
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_m_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2559,9 +2509,8 @@ static struct clk_branch gcc_pcie1_axi_s
+@@ -2553,9 +2503,8 @@ static struct clk_branch gcc_pcie1_axi_s
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_axi_s_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2577,9 +2526,8 @@ static struct clk_branch gcc_pcie1_pipe_
+@@ -2571,9 +2520,8 @@ static struct clk_branch gcc_pcie1_pipe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2594,9 +2542,8 @@ static struct clk_branch gcc_sys_noc_pci
+@@ -2588,9 +2536,8 @@ static struct clk_branch gcc_sys_noc_pci
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_pcie1_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2611,9 +2558,8 @@ static struct clk_branch gcc_usb0_aux_cl
+@@ -2605,9 +2552,8 @@ static struct clk_branch gcc_usb0_aux_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2628,9 +2574,8 @@ static struct clk_branch gcc_sys_noc_usb
+@@ -2622,9 +2568,8 @@ static struct clk_branch gcc_sys_noc_usb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb0_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2645,9 +2590,8 @@ static struct clk_branch gcc_usb0_master
+@@ -2639,9 +2584,8 @@ static struct clk_branch gcc_usb0_master
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_master_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2662,9 +2606,8 @@ static struct clk_branch gcc_usb0_mock_u
+@@ -2656,9 +2600,8 @@ static struct clk_branch gcc_usb0_mock_u
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_mock_utmi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2679,9 +2622,8 @@ static struct clk_branch gcc_usb0_phy_cf
+@@ -2673,9 +2616,8 @@ static struct clk_branch gcc_usb0_phy_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_phy_cfg_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2697,9 +2639,8 @@ static struct clk_branch gcc_usb0_pipe_c
+@@ -2691,9 +2633,8 @@ static struct clk_branch gcc_usb0_pipe_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2714,9 +2655,8 @@ static struct clk_branch gcc_usb0_sleep_
+@@ -2708,9 +2649,8 @@ static struct clk_branch gcc_usb0_sleep_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb0_sleep_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2731,9 +2671,8 @@ static struct clk_branch gcc_usb1_aux_cl
+@@ -2725,9 +2665,8 @@ static struct clk_branch gcc_usb1_aux_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_aux_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2748,9 +2687,8 @@ static struct clk_branch gcc_sys_noc_usb
+@@ -2742,9 +2681,8 @@ static struct clk_branch gcc_sys_noc_usb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb1_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2765,9 +2703,8 @@ static struct clk_branch gcc_usb1_master
+@@ -2759,9 +2697,8 @@ static struct clk_branch gcc_usb1_master
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_master_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2782,9 +2719,8 @@ static struct clk_branch gcc_usb1_mock_u
+@@ -2776,9 +2713,8 @@ static struct clk_branch gcc_usb1_mock_u
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_mock_utmi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2799,9 +2735,8 @@ static struct clk_branch gcc_usb1_phy_cf
+@@ -2793,9 +2729,8 @@ static struct clk_branch gcc_usb1_phy_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_phy_cfg_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2817,9 +2752,8 @@ static struct clk_branch gcc_usb1_pipe_c
+@@ -2811,9 +2746,8 @@ static struct clk_branch gcc_usb1_pipe_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_pipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2834,9 +2768,8 @@ static struct clk_branch gcc_usb1_sleep_
+@@ -2828,9 +2762,8 @@ static struct clk_branch gcc_usb1_sleep_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb1_sleep_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2851,9 +2784,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
+@@ -2845,9 +2778,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2868,9 +2800,8 @@ static struct clk_branch gcc_sdcc1_apps_
+@@ -2862,9 +2794,8 @@ static struct clk_branch gcc_sdcc1_apps_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2885,9 +2816,8 @@ static struct clk_branch gcc_sdcc1_ice_c
+@@ -2879,9 +2810,8 @@ static struct clk_branch gcc_sdcc1_ice_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2902,9 +2832,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
+@@ -2896,9 +2826,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2919,9 +2848,8 @@ static struct clk_branch gcc_sdcc2_apps_
+@@ -2913,9 +2842,8 @@ static struct clk_branch gcc_sdcc2_apps_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2936,9 +2864,8 @@ static struct clk_branch gcc_mem_noc_nss
+@@ -2930,9 +2858,8 @@ static struct clk_branch gcc_mem_noc_nss
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mem_noc_nss_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2953,9 +2880,8 @@ static struct clk_branch gcc_nss_ce_apb_
+@@ -2947,9 +2874,8 @@ static struct clk_branch gcc_nss_ce_apb_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_apb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2970,9 +2896,8 @@ static struct clk_branch gcc_nss_ce_axi_
+@@ -2964,9 +2890,8 @@ static struct clk_branch gcc_nss_ce_axi_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ce_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -2987,9 +2912,8 @@ static struct clk_branch gcc_nss_cfg_clk
+@@ -2981,9 +2906,8 @@ static struct clk_branch gcc_nss_cfg_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3004,9 +2928,8 @@ static struct clk_branch gcc_nss_crypto_
+@@ -2998,9 +2922,8 @@ static struct clk_branch gcc_nss_crypto_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_crypto_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3021,9 +2944,8 @@ static struct clk_branch gcc_nss_csr_clk
+@@ -3015,9 +2938,8 @@ static struct clk_branch gcc_nss_csr_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_csr_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3038,9 +2960,8 @@ static struct clk_branch gcc_nss_edma_cf
+@@ -3032,9 +2954,8 @@ static struct clk_branch gcc_nss_edma_cf
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3055,9 +2976,8 @@ static struct clk_branch gcc_nss_edma_cl
+@@ -3049,9 +2970,8 @@ static struct clk_branch gcc_nss_edma_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_edma_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3072,9 +2992,8 @@ static struct clk_branch gcc_nss_imem_cl
+@@ -3066,9 +2986,8 @@ static struct clk_branch gcc_nss_imem_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_imem_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3089,9 +3008,8 @@ static struct clk_branch gcc_nss_noc_clk
+@@ -3083,9 +3002,8 @@ static struct clk_branch gcc_nss_noc_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_noc_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3106,9 +3024,8 @@ static struct clk_branch gcc_nss_ppe_btq
+@@ -3100,9 +3018,8 @@ static struct clk_branch gcc_nss_ppe_btq
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_btq_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3123,9 +3040,8 @@ static struct clk_branch gcc_nss_ppe_cfg
+@@ -3117,9 +3034,8 @@ static struct clk_branch gcc_nss_ppe_cfg
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3140,9 +3056,8 @@ static struct clk_branch gcc_nss_ppe_clk
+@@ -3134,9 +3050,8 @@ static struct clk_branch gcc_nss_ppe_clk
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3157,9 +3072,8 @@ static struct clk_branch gcc_nss_ppe_ipe
+@@ -3151,9 +3066,8 @@ static struct clk_branch gcc_nss_ppe_ipe
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ppe_ipe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3174,9 +3088,8 @@ static struct clk_branch gcc_nss_ptp_ref
+@@ -3168,9 +3082,8 @@ static struct clk_branch gcc_nss_ptp_ref
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_ptp_ref_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3192,9 +3105,8 @@ static struct clk_branch gcc_crypto_ppe_
+@@ -3186,9 +3099,8 @@ static struct clk_branch gcc_crypto_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ppe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3209,9 +3121,8 @@ static struct clk_branch gcc_nssnoc_ce_a
+@@ -3203,9 +3115,8 @@ static struct clk_branch gcc_nssnoc_ce_a
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_apb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3226,9 +3137,8 @@ static struct clk_branch gcc_nssnoc_ce_a
+@@ -3220,9 +3131,8 @@ static struct clk_branch gcc_nssnoc_ce_a
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ce_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3243,9 +3153,8 @@ static struct clk_branch gcc_nssnoc_cryp
+@@ -3237,9 +3147,8 @@ static struct clk_branch gcc_nssnoc_cryp
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_crypto_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3260,9 +3169,8 @@ static struct clk_branch gcc_nssnoc_ppe_
+@@ -3254,9 +3163,8 @@ static struct clk_branch gcc_nssnoc_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_cfg_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3277,9 +3185,8 @@ static struct clk_branch gcc_nssnoc_ppe_
+@@ -3271,9 +3179,8 @@ static struct clk_branch gcc_nssnoc_ppe_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ppe_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3294,9 +3201,8 @@ static struct clk_branch gcc_nssnoc_qosg
+@@ -3288,9 +3195,8 @@ static struct clk_branch gcc_nssnoc_qosg
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_qosgen_ref_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3311,9 +3217,8 @@ static struct clk_branch gcc_nssnoc_snoc
+@@ -3305,9 +3211,8 @@ static struct clk_branch gcc_nssnoc_snoc
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_snoc_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3328,9 +3233,8 @@ static struct clk_branch gcc_nssnoc_time
+@@ -3322,9 +3227,8 @@ static struct clk_branch gcc_nssnoc_time
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_timeout_ref_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3345,9 +3249,8 @@ static struct clk_branch gcc_nssnoc_ubi0
+@@ -3339,9 +3243,8 @@ static struct clk_branch gcc_nssnoc_ubi0
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3362,9 +3265,8 @@ static struct clk_branch gcc_nssnoc_ubi1
+@@ -3356,9 +3259,8 @@ static struct clk_branch gcc_nssnoc_ubi1
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nssnoc_ubi1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3380,9 +3282,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
+@@ -3374,9 +3276,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3398,9 +3299,8 @@ static struct clk_branch gcc_ubi0_axi_cl
+@@ -3392,9 +3293,8 @@ static struct clk_branch gcc_ubi0_axi_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3416,9 +3316,8 @@ static struct clk_branch gcc_ubi0_nc_axi
+@@ -3410,9 +3310,8 @@ static struct clk_branch gcc_ubi0_nc_axi
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_nc_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3434,9 +3333,8 @@ static struct clk_branch gcc_ubi0_core_c
+@@ -3428,9 +3327,8 @@ static struct clk_branch gcc_ubi0_core_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_core_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3452,9 +3350,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
+@@ -3446,9 +3344,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi0_mpt_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3470,9 +3367,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
+@@ -3464,9 +3361,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3488,9 +3384,8 @@ static struct clk_branch gcc_ubi1_axi_cl
+@@ -3482,9 +3378,8 @@ static struct clk_branch gcc_ubi1_axi_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3506,9 +3401,8 @@ static struct clk_branch gcc_ubi1_nc_axi
+@@ -3500,9 +3395,8 @@ static struct clk_branch gcc_ubi1_nc_axi
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_nc_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3524,9 +3418,8 @@ static struct clk_branch gcc_ubi1_core_c
+@@ -3518,9 +3412,8 @@ static struct clk_branch gcc_ubi1_core_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_core_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3542,9 +3435,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
+@@ -3536,9 +3429,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ubi1_mpt_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3559,9 +3451,8 @@ static struct clk_branch gcc_cmn_12gpll_
+@@ -3553,9 +3445,8 @@ static struct clk_branch gcc_cmn_12gpll_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3576,9 +3467,8 @@ static struct clk_branch gcc_cmn_12gpll_
+@@ -3570,9 +3461,8 @@ static struct clk_branch gcc_cmn_12gpll_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cmn_12gpll_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3593,9 +3483,8 @@ static struct clk_branch gcc_mdio_ahb_cl
+@@ -3587,9 +3477,8 @@ static struct clk_branch gcc_mdio_ahb_cl
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdio_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3610,9 +3499,8 @@ static struct clk_branch gcc_uniphy0_ahb
+@@ -3604,9 +3493,8 @@ static struct clk_branch gcc_uniphy0_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3627,9 +3515,8 @@ static struct clk_branch gcc_uniphy0_sys
+@@ -3621,9 +3509,8 @@ static struct clk_branch gcc_uniphy0_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3644,9 +3531,8 @@ static struct clk_branch gcc_uniphy1_ahb
+@@ -3638,9 +3525,8 @@ static struct clk_branch gcc_uniphy1_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3661,9 +3547,8 @@ static struct clk_branch gcc_uniphy1_sys
+@@ -3655,9 +3541,8 @@ static struct clk_branch gcc_uniphy1_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3678,9 +3563,8 @@ static struct clk_branch gcc_uniphy2_ahb
+@@ -3672,9 +3557,8 @@ static struct clk_branch gcc_uniphy2_ahb
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3695,9 +3579,8 @@ static struct clk_branch gcc_uniphy2_sys
+@@ -3689,9 +3573,8 @@ static struct clk_branch gcc_uniphy2_sys
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_sys_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3712,9 +3595,8 @@ static struct clk_branch gcc_nss_port1_r
+@@ -3706,9 +3589,8 @@ static struct clk_branch gcc_nss_port1_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3729,9 +3611,8 @@ static struct clk_branch gcc_nss_port1_t
+@@ -3723,9 +3605,8 @@ static struct clk_branch gcc_nss_port1_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port1_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3746,9 +3627,8 @@ static struct clk_branch gcc_nss_port2_r
+@@ -3740,9 +3621,8 @@ static struct clk_branch gcc_nss_port2_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3763,9 +3643,8 @@ static struct clk_branch gcc_nss_port2_t
+@@ -3757,9 +3637,8 @@ static struct clk_branch gcc_nss_port2_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port2_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3780,9 +3659,8 @@ static struct clk_branch gcc_nss_port3_r
+@@ -3774,9 +3653,8 @@ static struct clk_branch gcc_nss_port3_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3797,9 +3675,8 @@ static struct clk_branch gcc_nss_port3_t
+@@ -3791,9 +3669,8 @@ static struct clk_branch gcc_nss_port3_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port3_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3814,9 +3691,8 @@ static struct clk_branch gcc_nss_port4_r
+@@ -3808,9 +3685,8 @@ static struct clk_branch gcc_nss_port4_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3831,9 +3707,8 @@ static struct clk_branch gcc_nss_port4_t
+@@ -3825,9 +3701,8 @@ static struct clk_branch gcc_nss_port4_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port4_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3848,9 +3723,8 @@ static struct clk_branch gcc_nss_port5_r
+@@ -3842,9 +3717,8 @@ static struct clk_branch gcc_nss_port5_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3865,9 +3739,8 @@ static struct clk_branch gcc_nss_port5_t
+@@ -3859,9 +3733,8 @@ static struct clk_branch gcc_nss_port5_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port5_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3882,9 +3755,8 @@ static struct clk_branch gcc_nss_port6_r
+@@ -3876,9 +3749,8 @@ static struct clk_branch gcc_nss_port6_r
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3899,9 +3771,8 @@ static struct clk_branch gcc_nss_port6_t
+@@ -3893,9 +3765,8 @@ static struct clk_branch gcc_nss_port6_t
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_nss_port6_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3916,9 +3787,8 @@ static struct clk_branch gcc_port1_mac_c
+@@ -3910,9 +3781,8 @@ static struct clk_branch gcc_port1_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port1_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3933,9 +3803,8 @@ static struct clk_branch gcc_port2_mac_c
+@@ -3927,9 +3797,8 @@ static struct clk_branch gcc_port2_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port2_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3950,9 +3819,8 @@ static struct clk_branch gcc_port3_mac_c
+@@ -3944,9 +3813,8 @@ static struct clk_branch gcc_port3_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port3_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3967,9 +3835,8 @@ static struct clk_branch gcc_port4_mac_c
+@@ -3961,9 +3829,8 @@ static struct clk_branch gcc_port4_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port4_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -3984,9 +3851,8 @@ static struct clk_branch gcc_port5_mac_c
+@@ -3978,9 +3845,8 @@ static struct clk_branch gcc_port5_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port5_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4001,9 +3867,8 @@ static struct clk_branch gcc_port6_mac_c
+@@ -3995,9 +3861,8 @@ static struct clk_branch gcc_port6_mac_c
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_port6_mac_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4018,9 +3883,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4012,9 +3877,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4035,9 +3899,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4029,9 +3893,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port1_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4052,9 +3915,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4046,9 +3909,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4069,9 +3931,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4063,9 +3925,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port2_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4086,9 +3947,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4080,9 +3941,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4103,9 +3963,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4097,9 +3957,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port3_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4120,9 +3979,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4114,9 +3973,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4137,9 +3995,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4131,9 +3989,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port4_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4154,9 +4011,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4148,9 +4005,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4171,9 +4027,8 @@ static struct clk_branch gcc_uniphy0_por
+@@ -4165,9 +4021,8 @@ static struct clk_branch gcc_uniphy0_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy0_port5_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4188,9 +4043,8 @@ static struct clk_branch gcc_uniphy1_por
+@@ -4182,9 +4037,8 @@ static struct clk_branch gcc_uniphy1_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4205,9 +4059,8 @@ static struct clk_branch gcc_uniphy1_por
+@@ -4199,9 +4053,8 @@ static struct clk_branch gcc_uniphy1_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy1_port5_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4222,9 +4075,8 @@ static struct clk_branch gcc_uniphy2_por
+@@ -4216,9 +4069,8 @@ static struct clk_branch gcc_uniphy2_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_rx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4239,9 +4091,8 @@ static struct clk_branch gcc_uniphy2_por
+@@ -4233,9 +4085,8 @@ static struct clk_branch gcc_uniphy2_por
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_uniphy2_port6_tx_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4257,9 +4108,8 @@ static struct clk_branch gcc_crypto_ahb_
+@@ -4251,9 +4102,8 @@ static struct clk_branch gcc_crypto_ahb_
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_ahb_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4275,9 +4125,8 @@ static struct clk_branch gcc_crypto_axi_
+@@ -4269,9 +4119,8 @@ static struct clk_branch gcc_crypto_axi_
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_axi_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4293,9 +4142,8 @@ static struct clk_branch gcc_crypto_clk
+@@ -4287,9 +4136,8 @@ static struct clk_branch gcc_crypto_clk
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "gcc_crypto_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4310,9 +4158,8 @@ static struct clk_branch gcc_gp1_clk = {
+@@ -4304,9 +4152,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4327,9 +4174,8 @@ static struct clk_branch gcc_gp2_clk = {
+@@ -4321,9 +4168,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4344,9 +4190,8 @@ static struct clk_branch gcc_gp3_clk = {
+@@ -4338,9 +4184,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
-@@ -4368,7 +4213,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
+@@ -4362,7 +4207,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie0_rchng_clk_src",
.parent_data = gcc_xo_gpll0,