ar71xx: connect GMAC0 to the internal switch on DB120

Because the external switch has no driver yet, connect GMAC0
to the PHY4 of the internal switch for now. This allows to
use the DB120 board as a router with 4LAN+1WAN ports.

SVN-Revision: 29557

diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/network b/target/linux/ar71xx/base-files/etc/uci-defaults/network
index f9419b9866ee718c1c53ea6621292871109840c6..c35df463f3bedc93d862db1ed86d70c4756a7512 100755 (executable)
--- a/target/linux/ar71xx/base-files/etc/uci-defaults/network
+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/network
@@ -19,6 +19,12 @@ all0258n)
        ucidef_set_interface_lan "eth0 eth1"
        ;;
 
+db120)
+       ucidef_set_interfaces_lan_wan "eth1" "eth0"
+       ucidef_add_switch "switch0" "1" "1"
+       ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4"
+       ;;
+
 dir-825-b1)
        ucidef_set_interfaces_lan_wan "eth0.1" "eth1"
        ucidef_add_switch "rtl8366s" "1" "1"

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-db120.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-db120.c
index 1d59f7478625ddfdd13e0d4ef99c8ad5e4b3f6b4..3a95fa26dd09fd4733e4d390fcd75c153b325888 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-db120.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-db120.c
@@ -2,6 +2,7 @@
  *  Atheros DB120 board (WASP SoC) support
  *
  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
@@ -10,6 +11,7 @@
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-ar71xx/ar71xx.h>
 
@@ -112,6 +114,21 @@ static struct gpio_keys_button db120_gpio_keys[] __initdata = {
        }
 };
 
+static void __init db120_gmac_setup(void)
+{
+       void __iomem *base;
+       u32 t;
+
+       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
+              AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
+       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+
+       iounmap(base);
+}
+
 static void __init db120_setup(void)
 {
        u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
@@ -129,14 +146,25 @@ static void __init db120_setup(void)
                                         ARRAY_SIZE(db120_gpio_keys),
                                         db120_gpio_keys);
 
+       db120_gmac_setup();
+
        ar71xx_add_device_mdio(0, 0x0);
        ar71xx_add_device_mdio(1, 0x0);
 
-       /* GMAC0 is connected to an AR8327 switch */
        ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
+#if 0
+       /* GMAC0 is connected to an AR8327 switch */
        ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
        ar71xx_eth0_data.speed = SPEED_1000;
        ar71xx_eth0_data.duplex = DUPLEX_FULL;
+#else
+       /* GMAC0 is connected to PHY4 of the internal switch */
+       ar71xx_switch_data.phy4_mii_en = 1;
+
+       ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+       ar71xx_eth0_data.phy_mask = BIT(4);
+       ar71xx_eth0_data.mii_bus_dev = &ar71xx_mdio1_device.dev;
+#endif
 
        ar71xx_add_device_eth(0);