for (i = 0; i < 32; i++) {
/* MSB first */
- gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31));
+ gpio_set_value(GPIO_OUTDT6, MOSI, data & (1U << 31));
gpio_set_value(GPIO_OUTDT6, SCLK, 1);
data <<= 1;
gpio_set_value(GPIO_OUTDT6, SCLK, 0);
reg = mmio_read_32(RCAR_PRR);
- if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
+ if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
return RCAR_CLUSTER_CA57;
- if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+ if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
return RCAR_CLUSTER_CA53;
return RCAR_CLUSTER_A53A57;
count_ca57:
if (IS_A53A57(c) || IS_CA57(c)) {
- if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+ if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
goto done;
for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
#define PWKUPR_WEN (1ull << 31)
-#define PSYSR_AFF_L2 (1 << 31)
+#define PSYSR_AFF_L2 (1U << 31)
#define PSYSR_AFF_L1 (1 << 30)
#define PSYSR_AFF_L0 (1 << 29)
#define PSYSR_WEN (1 << 28)
#define MSTP318 (1 << 18)
#define MSTP319 (1 << 19)
#define PMSR 0x5c
-#define PMSR_L1FAEG (1 << 31)
+#define PMSR_L1FAEG (1U << 31)
#define PMSR_PMEL1RX (1 << 23)
#define PMCTLR 0x60
-#define PMSR_L1IATN (1 << 31)
+#define PMSR_L1IATN (1U << 31)
static int rcar_pcie_fixup(unsigned int controller)
{