Update patches with their upstream versions.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 37098
--- /dev/null
+From 1a66581c94ad3966a823f2efaf8a5cc514895318 Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Mon, 31 Oct 2011 11:52:10 -0700
+Subject: [PATCH 2/3] MIPS: BCM63XX: Handle SW IRQs 0-1
+
+MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI)
+on BMIPS SMP. Make the board support code aware of them.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+[jogo@openwrt.org: move sw irqs behind timer irq]
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -294,6 +294,10 @@ asmlinkage void plat_irq_dispatch(void)
+
+ if (cause & CAUSEF_IP7)
+ do_IRQ(7);
++ if (cause & CAUSEF_IP0)
++ do_IRQ(0);
++ if (cause & CAUSEF_IP1)
++ do_IRQ(1);
+ if (cause & CAUSEF_IP2)
+ dispatch_internal();
+ if (!is_ext_irq_cascaded) {
--- /dev/null
+From 158a11f25e070a6ed99cf8faa985da1f2669230f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 21 Apr 2013 14:44:00 +0200
+Subject: [PATCH 3/3] MIPS: BCM63XX: select BMIPS4350 and default to 2 CPUs
+ for supported SoCs
+
+All BCM63XX SoCs starting with BCM6358 have a BMIPS4350 instead of a
+BMIPS3300, so select it unless support for any of the older SoCs is
+selected.
+All BMIPS4350 have only two CPUs, so select the appropriate default.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -129,6 +129,8 @@ config BCM63XX
+ select DMA_NONCOHERENT
+ select IRQ_CPU
+ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
++ select NR_CPUS_DEFAULT_2
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_EARLY_PRINTK
--- /dev/null
+From 373eb1a286bf31b41f966d5d3826cfe63e826c92 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:39 +0000
+Subject: [PATCH 1/6] MIPS: BCM63XX: select BOOT_RAW
+
+Enabling BOOT_RAW is mandatory to get a binary image (objcopy from ELF
+to binary) to work. This does not affect the ELF kernels which are used
+by CFE on BCM63XX DSL platforms, but is going to be necessary to support
+BCM63XX on Cable Modem chips such as BCM3368.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Patchwork: https://patchwork.linux-mips.org/patch/5500/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -124,6 +124,7 @@ config BCM47XX
+
+ config BCM63XX
+ bool "Broadcom BCM63XX based boards"
++ select BOOT_RAW
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
--- /dev/null
+From 31c761c9c1fa91bf4ed83d75dcbc4e426ea2b670 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:40 +0000
+Subject: [PATCH 2/6] MIPS: BCM63XX: add support for BCM3368 Cable Modem
+
+The Broadcom BCM3368 Cable Modem SoC is extremely similar to the
+existing BCM63xx DSL SoCs, in particular BCM6358, therefore little effort
+in the existing code base is required to get it supported. This patch adds
+support for the following on-chip peripherals:
+
+- two UARTS
+- GPIO
+- Ethernet
+- SPI
+- PCI
+- NOR Flash
+
+The most noticeable difference with 3368 is that it has its peripheral
+register at 0xfff8_0000 we check that separately in ioremap.h. Since
+3368 is identical to 6358 for its clock and reset bits, we use them
+verbatim.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Patchwork: https://patchwork.linux-mips.org/patch/5499/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/Kconfig | 4 +
+ arch/mips/bcm63xx/clk.c | 18 ++--
+ arch/mips/bcm63xx/cpu.c | 28 +++++-
+ arch/mips/bcm63xx/dev-flash.c | 1 +
+ arch/mips/bcm63xx/dev-spi.c | 6 +-
+ arch/mips/bcm63xx/dev-uart.c | 3 +-
+ arch/mips/bcm63xx/irq.c | 19 ++++
+ arch/mips/bcm63xx/prom.c | 4 +-
+ arch/mips/bcm63xx/reset.c | 29 +++++-
+ arch/mips/bcm63xx/setup.c | 3 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 110 +++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 1 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 45 ++++++++-
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h | 4 +
+ arch/mips/pci/pci-bcm63xx.c | 3 +-
+ 15 files changed, 259 insertions(+), 19 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -1,6 +1,10 @@
+ menu "CPU support"
+ depends on BCM63XX
+
++config BCM63XX_CPU_3368
++ bool "support 3368 CPU"
++ select HW_HAS_PCI
++
+ config BCM63XX_CPU_6328
+ bool "support 6328 CPU"
+ select HW_HAS_PCI
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, i
+ else
+ clk_disable_unlocked(&clk_enet_misc);
+
+- if (BCMCPU_IS_6358()) {
++ if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
+ u32 mask;
+
+ if (clk->id == 0)
+@@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
+ */
+ static void ephy_set(struct clk *clk, int enable)
+ {
+- if (!BCMCPU_IS_6358())
+- return;
+- bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
++ if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
++ bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
+ }
+
+
+@@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
+ */
+ static void pcm_set(struct clk *clk, int enable)
+ {
+- if (!BCMCPU_IS_6358())
+- return;
+- bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
++ if (BCMCPU_IS_3368())
++ bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
++ if (BCMCPU_IS_6358())
++ bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
+ }
+
+ static struct clk clk_pcm = {
+@@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int
+ mask = CKCTL_6338_SPI_EN;
+ else if (BCMCPU_IS_6348())
+ mask = CKCTL_6348_SPI_EN;
+- else if (BCMCPU_IS_6358())
++ else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
+ mask = CKCTL_6358_SPI_EN;
+ else if (BCMCPU_IS_6362())
+ mask = CKCTL_6362_SPI_EN;
+@@ -338,7 +338,7 @@ struct clk *clk_get(struct device *dev,
+ return &clk_xtm;
+ if (!strcmp(id, "periph"))
+ return &clk_periph;
+- if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
++ if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
+ return &clk_pcm;
+ if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
+ return &clk_ipsec;
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
+ static unsigned int bcm63xx_cpu_freq;
+ static unsigned int bcm63xx_memory_size;
+
++static const unsigned long bcm3368_regs_base[] = {
++ __GEN_CPU_REGS_TABLE(3368)
++};
++
++static const int bcm3368_irqs[] = {
++ __GEN_CPU_IRQ_TABLE(3368)
++};
++
+ static const unsigned long bcm6328_regs_base[] = {
+ __GEN_CPU_REGS_TABLE(6328)
+ };
+@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(voi
+ static unsigned int detect_cpu_clock(void)
+ {
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM3368_CPU_ID:
++ return 300000000;
++
+ case BCM6328_CPU_ID:
+ {
+ unsigned int tmp, mips_pll_fcvo;
+@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(v
+ banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
+ }
+
+- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
++ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+ val = bcm_memc_readl(MEMC_CFG_REG);
+ rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
+ cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
+@@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
+ chipid_reg = BCM_6345_PERF_BASE;
+ break;
+ case CPU_BMIPS4350:
+- if ((read_c0_prid() & 0xf0) == 0x10)
++ switch ((read_c0_prid() & 0xff)) {
++ case 0x04:
++ chipid_reg = BCM_3368_PERF_BASE;
++ break;
++ case 0x10:
+ chipid_reg = BCM_6345_PERF_BASE;
+- else
++ break;
++ default:
+ chipid_reg = BCM_6368_PERF_BASE;
++ break;
++ }
+ break;
+ }
+
+@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
+ bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
+
+ switch (bcm63xx_cpu_id) {
++ case BCM3368_CPU_ID:
++ bcm63xx_regs_base = bcm3368_regs_base;
++ bcm63xx_irqs = bcm3368_irqs;
++ break;
+ case BCM6328_CPU_ID:
+ bcm63xx_regs_base = bcm6328_regs_base;
+ bcm63xx_irqs = bcm6328_irqs;
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_t
+ case BCM6348_CPU_ID:
+ /* no way to auto detect so assume parallel */
+ return BCM63XX_FLASH_TYPE_PARALLEL;
++ case BCM3368_CPU_ID:
+ case BCM6358_CPU_ID:
+ val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
+ if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init
+ {
+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
+ bcm63xx_regs_spi = bcm6348_regs_spi;
+- if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
++ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
++ BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ bcm63xx_regs_spi = bcm6358_regs_spi;
+ }
+ #else
+@@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void)
+ spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
+ }
+
+- if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
++ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
++ BCMCPU_IS_6368()) {
+ spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+ spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
+ spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
+--- a/arch/mips/bcm63xx/dev-uart.c
++++ b/arch/mips/bcm63xx/dev-uart.c
+@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
+ if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
+ return -ENODEV;
+
+- if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
++ if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() &&
++ !BCMCPU_IS_6368()))
+ return -ENODEV;
+
+ if (id == 0) {
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
+ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+
+ #ifndef BCMCPU_RUNTIME_DETECT
++#ifdef CONFIG_BCM63XX_CPU_3368
++#define irq_stat_reg PERF_IRQSTAT_3368_REG
++#define irq_mask_reg PERF_IRQMASK_3368_REG
++#define irq_bits 32
++#define is_ext_irq_cascaded 0
++#define ext_irq_start 0
++#define ext_irq_end 0
++#define ext_irq_count 4
++#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
++#define ext_irq_cfg_reg2 0
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ #define irq_stat_reg PERF_IRQSTAT_6328_REG
+ #define irq_mask_reg PERF_IRQMASK_6328_REG
+@@ -140,6 +151,13 @@ static void bcm63xx_init_irq(void)
+ irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM3368_CPU_ID:
++ irq_stat_addr += PERF_IRQSTAT_3368_REG;
++ irq_mask_addr += PERF_IRQMASK_3368_REG;
++ irq_bits = 32;
++ ext_irq_count = 4;
++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
++ break;
+ case BCM6328_CPU_ID:
+ irq_stat_addr += PERF_IRQSTAT_6328_REG;
+ irq_mask_addr += PERF_IRQMASK_6328_REG;
+@@ -479,6 +497,7 @@ static int bcm63xx_external_irq_set_type
+ reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+ break;
+
++ case BCM3368_CPU_ID:
+ case BCM6328_CPU_ID:
+ case BCM6338_CPU_ID:
+ case BCM6345_CPU_ID:
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -26,7 +26,9 @@ void __init prom_init(void)
+ bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
+
+ /* disable all hardware blocks clock for now */
+- if (BCMCPU_IS_6328())
++ if (BCMCPU_IS_3368())
++ mask = CKCTL_3368_ALL_SAFE_EN;
++ else if (BCMCPU_IS_6328())
+ mask = CKCTL_6328_ALL_SAFE_EN;
+ else if (BCMCPU_IS_6338())
+ mask = CKCTL_6338_ALL_SAFE_EN;
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -30,6 +30,19 @@
+ [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
+ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
+
++#define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
++#define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
++#define BCM3368_RESET_USBH 0
++#define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK
++#define BCM3368_RESET_DSL 0
++#define BCM3368_RESET_SAR 0
++#define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK
++#define BCM3368_RESET_ENETSW 0
++#define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK
++#define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
++#define BCM3368_RESET_PCIE 0
++#define BCM3368_RESET_PCIE_EXT 0
++
+ #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
+ #define BCM6328_RESET_ENET 0
+ #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
+@@ -117,6 +130,10 @@
+ /*
+ * core reset bits
+ */
++static const u32 bcm3368_reset_bits[] = {
++ __GEN_RESET_BITS_TABLE(3368)
++};
++
+ static const u32 bcm6328_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6328)
+ };
+@@ -146,7 +163,10 @@ static int reset_reg;
+
+ static int __init bcm63xx_reset_bits_init(void)
+ {
+- if (BCMCPU_IS_6328()) {
++ if (BCMCPU_IS_3368()) {
++ reset_reg = PERF_SOFTRESET_6358_REG;
++ bcm63xx_reset_bits = bcm3368_reset_bits;
++ } else if (BCMCPU_IS_6328()) {
+ reset_reg = PERF_SOFTRESET_6328_REG;
+ bcm63xx_reset_bits = bcm6328_reset_bits;
+ } else if (BCMCPU_IS_6338()) {
+@@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_ini
+ }
+ #else
+
++#ifdef CONFIG_BCM63XX_CPU_3368
++static const u32 bcm63xx_reset_bits[] = {
++ __GEN_RESET_BITS_TABLE(3368)
++};
++#define reset_reg PERF_SOFTRESET_6358_REG
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ static const u32 bcm63xx_reset_bits[] = {
+ __GEN_RESET_BITS_TABLE(6328)
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
+
+ /* mask and clear all external irq */
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM3368_CPU_ID:
++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
++ break;
+ case BCM6328_CPU_ID:
+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
+ break;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -9,6 +9,7 @@
+ * compile time if only one CPU support is enabled (idea stolen from
+ * arm mach-types)
+ */
++#define BCM3368_CPU_ID 0x3368
+ #define BCM6328_CPU_ID 0x6328
+ #define BCM6338_CPU_ID 0x6338
+ #define BCM6345_CPU_ID 0x6345
+@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
+ u8 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+
++#ifdef CONFIG_BCM63XX_CPU_3368
++# ifdef bcm63xx_get_cpu_id
++# undef bcm63xx_get_cpu_id
++# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
++# define BCMCPU_RUNTIME_DETECT
++# else
++# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
++# endif
++# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
++#else
++# define BCMCPU_IS_3368() (0)
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ # ifdef bcm63xx_get_cpu_id
+ # undef bcm63xx_get_cpu_id
+@@ -191,6 +205,53 @@ enum bcm63xx_regs_set {
+ #define RSET_RNG_SIZE 20
+
+ /*
++ * 3368 register sets base address
++ */
++#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
++#define BCM_3368_PERF_BASE (0xfff8c000)
++#define BCM_3368_TIMER_BASE (0xfff8c040)
++#define BCM_3368_WDT_BASE (0xfff8c080)
++#define BCM_3368_UART0_BASE (0xfff8c100)
++#define BCM_3368_UART1_BASE (0xfff8c120)
++#define BCM_3368_GPIO_BASE (0xfff8c080)
++#define BCM_3368_SPI_BASE (0xfff8c800)
++#define BCM_3368_HSSPI_BASE (0xdeadbeef)
++#define BCM_3368_UDC0_BASE (0xdeadbeef)
++#define BCM_3368_USBDMA_BASE (0xdeadbeef)
++#define BCM_3368_OHCI0_BASE (0xdeadbeef)
++#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
++#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
++#define BCM_3368_USBD_BASE (0xdeadbeef)
++#define BCM_3368_MPI_BASE (0xfff80000)
++#define BCM_3368_PCMCIA_BASE (0xfff80054)
++#define BCM_3368_PCIE_BASE (0xdeadbeef)
++#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
++#define BCM_3368_DSL_BASE (0xdeadbeef)
++#define BCM_3368_UBUS_BASE (0xdeadbeef)
++#define BCM_3368_ENET0_BASE (0xfff98000)
++#define BCM_3368_ENET1_BASE (0xfff98800)
++#define BCM_3368_ENETDMA_BASE (0xfff99800)
++#define BCM_3368_ENETDMAC_BASE (0xfff99900)
++#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
++#define BCM_3368_ENETSW_BASE (0xdeadbeef)
++#define BCM_3368_EHCI0_BASE (0xdeadbeef)
++#define BCM_3368_SDRAM_BASE (0xdeadbeef)
++#define BCM_3368_MEMC_BASE (0xfff84000)
++#define BCM_3368_DDR_BASE (0xdeadbeef)
++#define BCM_3368_M2M_BASE (0xdeadbeef)
++#define BCM_3368_ATM_BASE (0xdeadbeef)
++#define BCM_3368_XTM_BASE (0xdeadbeef)
++#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
++#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
++#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
++#define BCM_3368_PCM_BASE (0xfff9c200)
++#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
++#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
++#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
++#define BCM_3368_RNG_BASE (0xdeadbeef)
++#define BCM_3368_MISC_BASE (0xdeadbeef)
++
++/*
+ * 6328 register sets base address
+ */
+ #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
+@@ -620,6 +681,9 @@ static inline unsigned long bcm63xx_regs
+ #ifdef BCMCPU_RUNTIME_DETECT
+ return bcm63xx_regs_base[set];
+ #else
++#ifdef CONFIG_BCM63XX_CPU_3368
++ __GEN_RSET(3368)
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ __GEN_RSET(6328)
+ #endif
+@@ -687,6 +751,52 @@ enum bcm63xx_irq {
+ };
+
+ /*
++ * 3368 irqs
++ */
++#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
++#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
++#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
++#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
++#define BCM_3368_DSL_IRQ 0
++#define BCM_3368_UDC0_IRQ 0
++#define BCM_3368_OHCI0_IRQ 0
++#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
++#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
++#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
++#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
++#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
++#define BCM_3368_HSSPI_IRQ 0
++#define BCM_3368_EHCI0_IRQ 0
++#define BCM_3368_USBD_IRQ 0
++#define BCM_3368_USBD_RXDMA0_IRQ 0
++#define BCM_3368_USBD_TXDMA0_IRQ 0
++#define BCM_3368_USBD_RXDMA1_IRQ 0
++#define BCM_3368_USBD_TXDMA1_IRQ 0
++#define BCM_3368_USBD_RXDMA2_IRQ 0
++#define BCM_3368_USBD_TXDMA2_IRQ 0
++#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
++#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
++#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
++#define BCM_3368_PCMCIA_IRQ 0
++#define BCM_3368_ATM_IRQ 0
++#define BCM_3368_ENETSW_RXDMA0_IRQ 0
++#define BCM_3368_ENETSW_RXDMA1_IRQ 0
++#define BCM_3368_ENETSW_RXDMA2_IRQ 0
++#define BCM_3368_ENETSW_RXDMA3_IRQ 0
++#define BCM_3368_ENETSW_TXDMA0_IRQ 0
++#define BCM_3368_ENETSW_TXDMA1_IRQ 0
++#define BCM_3368_ENETSW_TXDMA2_IRQ 0
++#define BCM_3368_ENETSW_TXDMA3_IRQ 0
++#define BCM_3368_XTM_IRQ 0
++#define BCM_3368_XTM_DMA0_IRQ 0
++
++#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
++#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
++#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
++#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
++
++
++/*
+ * 6328 irqs
+ */
+ #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio
+ switch (bcm63xx_get_cpu_id()) {
+ case BCM6328_CPU_ID:
+ return 32;
++ case BCM3368_CPU_ID:
+ case BCM6358_CPU_ID:
+ return 40;
+ case BCM6338_CPU_ID:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -15,6 +15,39 @@
+ /* Clock Control register */
+ #define PERF_CKCTL_REG 0x4
+
++#define CKCTL_3368_MAC_EN (1 << 3)
++#define CKCTL_3368_TC_EN (1 << 5)
++#define CKCTL_3368_US_TOP_EN (1 << 6)
++#define CKCTL_3368_DS_TOP_EN (1 << 7)
++#define CKCTL_3368_APM_EN (1 << 8)
++#define CKCTL_3368_SPI_EN (1 << 9)
++#define CKCTL_3368_USBS_EN (1 << 10)
++#define CKCTL_3368_BMU_EN (1 << 11)
++#define CKCTL_3368_PCM_EN (1 << 12)
++#define CKCTL_3368_NTP_EN (1 << 13)
++#define CKCTL_3368_ACP_B_EN (1 << 14)
++#define CKCTL_3368_ACP_A_EN (1 << 15)
++#define CKCTL_3368_EMUSB_EN (1 << 17)
++#define CKCTL_3368_ENET0_EN (1 << 18)
++#define CKCTL_3368_ENET1_EN (1 << 19)
++#define CKCTL_3368_USBU_EN (1 << 20)
++#define CKCTL_3368_EPHY_EN (1 << 21)
++
++#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
++ CKCTL_3368_TC_EN | \
++ CKCTL_3368_US_TOP_EN | \
++ CKCTL_3368_DS_TOP_EN | \
++ CKCTL_3368_APM_EN | \
++ CKCTL_3368_SPI_EN | \
++ CKCTL_3368_USBS_EN | \
++ CKCTL_3368_BMU_EN | \
++ CKCTL_3368_PCM_EN | \
++ CKCTL_3368_NTP_EN | \
++ CKCTL_3368_ACP_B_EN | \
++ CKCTL_3368_ACP_A_EN | \
++ CKCTL_3368_EMUSB_EN | \
++ CKCTL_3368_USBU_EN)
++
+ #define CKCTL_6328_PHYMIPS_EN (1 << 0)
+ #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
+ #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
+@@ -181,6 +214,7 @@
+ #define SYS_PLL_SOFT_RESET 0x1
+
+ /* Interrupt Mask register */
++#define PERF_IRQMASK_3368_REG 0xc
+ #define PERF_IRQMASK_6328_REG 0x20
+ #define PERF_IRQMASK_6338_REG 0xc
+ #define PERF_IRQMASK_6345_REG 0xc
+@@ -190,6 +224,7 @@
+ #define PERF_IRQMASK_6368_REG 0x20
+
+ /* Interrupt Status register */
++#define PERF_IRQSTAT_3368_REG 0x10
+ #define PERF_IRQSTAT_6328_REG 0x28
+ #define PERF_IRQSTAT_6338_REG 0x10
+ #define PERF_IRQSTAT_6345_REG 0x10
+@@ -199,6 +234,7 @@
+ #define PERF_IRQSTAT_6368_REG 0x28
+
+ /* External Interrupt Configuration register */
++#define PERF_EXTIRQ_CFG_REG_3368 0x14
+ #define PERF_EXTIRQ_CFG_REG_6328 0x18
+ #define PERF_EXTIRQ_CFG_REG_6338 0x14
+ #define PERF_EXTIRQ_CFG_REG_6345 0x14
+@@ -236,6 +272,13 @@
+ #define PERF_SOFTRESET_6362_REG 0x10
+ #define PERF_SOFTRESET_6368_REG 0x10
+
++#define SOFTRESET_3368_SPI_MASK (1 << 0)
++#define SOFTRESET_3368_ENET_MASK (1 << 2)
++#define SOFTRESET_3368_MPI_MASK (1 << 3)
++#define SOFTRESET_3368_EPHY_MASK (1 << 6)
++#define SOFTRESET_3368_USBS_MASK (1 << 11)
++#define SOFTRESET_3368_PCM_MASK (1 << 13)
++
+ #define SOFTRESET_6328_SPI_MASK (1 << 0)
+ #define SOFTRESET_6328_EPHY_MASK (1 << 1)
+ #define SOFTRESET_6328_SAR_MASK (1 << 2)
+@@ -1293,7 +1336,7 @@
+ #define SPI_6348_RX_DATA 0x80
+ #define SPI_6348_RX_DATA_SIZE 0x3f
+
+-/* BCM 6358/6262/6368 SPI core */
++/* BCM 3368/6358/6262/6368 SPI core */
+ #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
+ #define SPI_6358_MSG_CTL_WIDTH 16
+ #define SPI_6358_MSG_DATA 0x02
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(
+ static inline int is_bcm63xx_internal_registers(phys_t offset)
+ {
+ switch (bcm63xx_get_cpu_id()) {
++ case BCM3368_CPU_ID:
++ if (offset >= 0xfff80000)
++ return 1;
++ break;
+ case BCM6338_CPU_ID:
+ case BCM6345_CPU_ID:
+ case BCM6348_CPU_ID:
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(v
+ /* setup PCI to local bus access, used by PCI device to target
+ * local RAM while bus mastering */
+ bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
+- if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
++ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
+ val = MPI_SP0_REMAP_ENABLE_MASK;
+ else
+ val = 0;
+@@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
+ case BCM6328_CPU_ID:
+ case BCM6362_CPU_ID:
+ return bcm63xx_register_pcie();
++ case BCM3368_CPU_ID:
+ case BCM6348_CPU_ID:
+ case BCM6358_CPU_ID:
+ case BCM6368_CPU_ID:
--- /dev/null
+From f3b3faafe7b5a1c07b12d18e96c36bc8a0eecaed Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:41 +0000
+Subject: [PATCH 3/6] MIPS: BCM63XX: recognize Cable Modem firmware format
+
+Add the firmware header format which is used by Broadcom Cable Modem
+SoCs such as the BCM3368 SoC. We export the bcm_hcs firmware format
+structure because it is used by user-land tools to create firmware
+images for these SoCs and will later be used by a corresponding MTD
+parser.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Patchwork: https://patchwork.linux-mips.org/patch/5496/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 14 ++++++++++++--
+ include/uapi/linux/Kbuild | 1 +
+ include/uapi/linux/bcm933xx_hcs.h | 24 ++++++++++++++++++++++++
+ 3 files changed, 37 insertions(+), 2 deletions(-)
+ create mode 100644 include/uapi/linux/bcm933xx_hcs.h
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -28,8 +28,12 @@
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+
++#include <uapi/linux/bcm933xx_hcs.h>
++
+ #define PFX "board_bcm963xx: "
+
++#define HCS_OFFSET_128K 0x20000
++
+ static struct board_info board;
+
+ /*
+@@ -722,8 +726,9 @@ void __init board_prom_init(void)
+ unsigned int i;
+ u8 *boot_addr, *cfe;
+ char cfe_version[32];
+- char *board_name;
++ char *board_name = NULL;
+ u32 val;
++ struct bcm_hcs *hcs;
+
+ /* read base address of boot chip select (0)
+ * 6328/6362 do not have MPI but boot from a fixed address
+@@ -747,7 +752,12 @@ void __init board_prom_init(void)
+
+ bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
+
+- board_name = bcm63xx_nvram_get_name();
++ if (BCMCPU_IS_3368()) {
++ hcs = (struct bcm_hcs *)boot_addr;
++ board_name = hcs->filename;
++ } else {
++ board_name = bcm63xx_nvram_get_name();
++ }
+ /* find board by name */
+ for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
+ if (strncmp(board_name, bcm963xx_boards[i]->name, 16))
+--- a/include/uapi/linux/Kbuild
++++ b/include/uapi/linux/Kbuild
+@@ -62,6 +62,7 @@ header-y += auxvec.h
+ header-y += ax25.h
+ header-y += b1lli.h
+ header-y += baycom.h
++header-y += bcm933xx_hcs.h
+ header-y += bfs_fs.h
+ header-y += binfmts.h
+ header-y += blkpg.h
+--- /dev/null
++++ b/include/uapi/linux/bcm933xx_hcs.h
+@@ -0,0 +1,24 @@
++/*
++ * Broadcom Cable Modem firmware format
++ */
++
++#ifndef __BCM933XX_HCS_H
++#define __BCM933XX_HCS_H
++
++#include <linux/types.h>
++
++struct bcm_hcs {
++ __u16 magic;
++ __u16 control;
++ __u16 rev_maj;
++ __u16 rev_min;
++ __u32 build_date;
++ __u32 filelen;
++ __u32 ldaddress;
++ char filename[64];
++ __u16 hcs;
++ __u16 her_znaet_chto;
++ __u32 crc;
++};
++
++#endif /* __BCM933XX_HCS */
--- /dev/null
+From 404fdc457082772ff52e22988e09e82c0d6e8780 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:42 +0000
+Subject: [PATCH 4/6] MIPS: BCM63XX: provide a MAC address for BCM3368 chips
+
+The BCM3368 SoC uses a NVRAM format which is not compatible with the one
+used by CFE, provide a default MAC address which is suitable for use and
+which is the default one also being used by the bootloader on these
+chips.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Patchwork: https://patchwork.linux-mips.org/patch/5498/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/nvram.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/mips/bcm63xx/nvram.c
++++ b/arch/mips/bcm63xx/nvram.c
+@@ -45,6 +45,7 @@ void __init bcm63xx_nvram_init(void *add
+ {
+ unsigned int check_len;
+ u32 crc, expected_crc;
++ u8 hcs_mac_addr[ETH_ALEN] = { 0x00, 0x10, 0x18, 0xff, 0xff, 0xff };
+
+ /* extract nvram data */
+ memcpy(&nvram, addr, sizeof(nvram));
+@@ -65,6 +66,15 @@ void __init bcm63xx_nvram_init(void *add
+ if (crc != expected_crc)
+ pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
+ expected_crc, crc);
++
++ /* Cable modems have a different NVRAM which is embedded in the eCos
++ * firmware and not easily extractible, give at least a MAC address
++ * pool.
++ */
++ if (BCMCPU_IS_3368()) {
++ memcpy(nvram.mac_addr_base, hcs_mac_addr, ETH_ALEN);
++ nvram.mac_addr_count = 2;
++ }
+ }
+
+ u8 *bcm63xx_nvram_get_name(void)
--- /dev/null
+From 0a97aafe7fe50ed183e7fa0121fa7838e2e20306 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:43 +0000
+Subject: [PATCH 5/6] MIPS: BCM63XX: let board specify an external GPIO to
+ reset PHY
+
+Some boards may need to reset their external PHY or switch they are
+attached to, add a hook for doing this along with providing custom
+linux/gpio.h flags for doing this.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Cc: Florian Fainelli <florian@openwrt.org>
+Patchwork: https://patchwork.linux-mips.org/patch/5501/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++
+ arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 6 ++++++
+ 2 files changed, 10 insertions(+)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -883,5 +883,9 @@ int __init board_register_devices(void)
+
+ platform_device_register(&bcm63xx_gpio_leds);
+
++ if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)
++ gpio_request_one(board.ephy_reset_gpio,
++ board.ephy_reset_gpio_flags, "ephy-reset");
++
+ return 0;
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -45,6 +45,12 @@ struct board_info {
+
+ /* GPIO LEDs */
+ struct gpio_led leds[5];
++
++ /* External PHY reset GPIO */
++ unsigned int ephy_reset_gpio;
++
++ /* External PHY reset GPIO flags from gpio.h */
++ unsigned long ephy_reset_gpio_flags;
+ };
+
+ #endif /* ! BOARD_BCM963XX_H_ */
--- /dev/null
+From 04760855f0d99a1cdc67ae0152d95bcc4525cff5 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:44 +0000
+Subject: [PATCH 6/6] MIPS: BCM63XX: add support for the Netgear CVG834G
+
+Add support for the Netgear CVG834G and enable the two UARTs, Ethernet
+on the first MAC, PCI and the two leds.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Cc: Florian Fainelli <florian@openwrt.org>
+Patchwork: https://patchwork.linux-mips.org/patch/5502/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 35 +++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -37,6 +37,38 @@
+ static struct board_info board;
+
+ /*
++ * known 3368 boards
++ */
++#ifdef CONFIG_BCM63XX_CPU_3368
++static struct board_info __initdata board_cvg834g = {
++ .name = "CVG834G_E15R3921",
++ .expected_cpu_id = 0x3368,
++
++ .has_uart0 = 1,
++ .has_uart1 = 1,
++
++ .has_enet0 = 1,
++ .has_pci = 1,
++
++ .enet0 = {
++ .has_phy = 1,
++ .use_internal_phy = 1,
++ },
++
++ .leds = {
++ {
++ .name = "CVG834G:green:power",
++ .gpio = 37,
++ .default_trigger= "default-on",
++ },
++ },
++
++ .ephy_reset_gpio = 36,
++ .ephy_reset_gpio_flags = GPIOF_INIT_HIGH,
++};
++#endif
++
++/*
+ * known 6328 boards
+ */
+ #ifdef CONFIG_BCM63XX_CPU_6328
+@@ -643,6 +675,9 @@ static struct board_info __initdata boar
+ * all boards
+ */
+ static const struct board_info __initconst *bcm963xx_boards[] = {
++#ifdef CONFIG_BCM63XX_CPU_3368
++ &board_cvg834g,
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ &board_96328avng,
+ #endif
--- /dev/null
+From 318883517ebc56e1f9068597e9875f578016e225 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Tue, 18 Jun 2013 16:55:38 +0000
+Subject: [PATCH] MIPS: BCM63XX: remove bogus Kconfig selects
+
+Remove the bogus selects on USB-related symbols for 6345 and 6338, not
+only we do not yet support USB on BCM63XX, but they also cause the
+following warnings:
+
+warning: (BCM63XX_CPU_6338 && BCM63XX_CPU_6345) selects
+USB_OHCI_BIG_ENDIAN_MMIO which has unmet direct dependencies
+(USB_SUPPORT && USB && USB_OHCI_HCD)
+warning: (BCM63XX_CPU_6338 && BCM63XX_CPU_6345) selects
+USB_OHCI_BIG_ENDIAN_DESC which has unmet direct dependencies
+(USB_SUPPORT && USB && USB_OHCI_HCD)
+make[4]: Leaving directory `/home/florian/dev/linux'
+
+Just get rid of these bogus Kconfig selects because neither 6345 nor
+6338 actually have built-in USB host controllers.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Patchwork: http://patchwork.linux-mips.org/patch/5497/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/Kconfig | 5 -----
+ 1 file changed, 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -12,14 +12,9 @@ config BCM63XX_CPU_6328
+ config BCM63XX_CPU_6338
+ bool "support 6338 CPU"
+ select HW_HAS_PCI
+- select USB_ARCH_HAS_OHCI
+- select USB_OHCI_BIG_ENDIAN_DESC
+- select USB_OHCI_BIG_ENDIAN_MMIO
+
+ config BCM63XX_CPU_6345
+ bool "support 6345 CPU"
+- select USB_OHCI_BIG_ENDIAN_DESC
+- select USB_OHCI_BIG_ENDIAN_MMIO
+
+ config BCM63XX_CPU_6348
+ bool "support 6348 CPU"
--- /dev/null
+From 672d6bea85c7c9c63c086a9423e6d4e5fc286152 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 26 Jun 2013 18:11:56 +0000
+Subject: [PATCH] MIPS: BMIPS: support booting from physical CPU other than 0
+
+BMIPS43xx CPUs have two hardware threads, and on some SoCs such as 3368,
+the bootloader has configured the system to boot from TP1 instead of the
+more usual TP0. Create the physical to logical CPU mapping to cope with
+that, do not remap the software interrupts to be cross CPUs such that we
+do not have to do use the logical CPU mapping further down the code, and
+finally, reset the slave TP1 only if booted from TP0.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: blogic@openwrt.org
+Cc: cernekee@gmail.com
+Patchwork: https://patchwork.linux-mips.org/patch/5553/
+Patchwork: https://patchwork.linux-mips.org/patch/5556/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/kernel/smp-bmips.c | 29 +++++++++++++++++++++++------
+ 1 file changed, 23 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -63,7 +63,7 @@ static irqreturn_t bmips_ipi_interrupt(i
+
+ static void __init bmips_smp_setup(void)
+ {
+- int i;
++ int i, cpu = 1, boot_cpu = 0;
+
+ #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+ /* arbitration priority */
+@@ -72,13 +72,22 @@ static void __init bmips_smp_setup(void)
+ /* NBK and weak order flags */
+ set_c0_brcm_config_0(0x30000);
+
++ /* Find out if we are running on TP0 or TP1 */
++ boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
++
+ /*
+ * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
+ * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+ * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
++ *
++ * If booting from TP1, leave the existing CMT interrupt routing
++ * such that TP0 responds to SW1 and TP1 responds to SW0.
+ */
+- change_c0_brcm_cmt_intr(0xf8018000,
+- (0x02 << 27) | (0x03 << 15));
++ if (boot_cpu == 0)
++ change_c0_brcm_cmt_intr(0xf8018000,
++ (0x02 << 27) | (0x03 << 15));
++ else
++ change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
+
+ /* single core, 2 threads (2 pipelines) */
+ max_cpus = 2;
+@@ -106,9 +115,15 @@ static void __init bmips_smp_setup(void)
+ if (!board_ebase_setup)
+ board_ebase_setup = &bmips_ebase_setup;
+
++ __cpu_number_map[boot_cpu] = 0;
++ __cpu_logical_map[0] = boot_cpu;
++
+ for (i = 0; i < max_cpus; i++) {
+- __cpu_number_map[i] = 1;
+- __cpu_logical_map[i] = 1;
++ if (i != boot_cpu) {
++ __cpu_number_map[i] = cpu;
++ __cpu_logical_map[cpu] = i;
++ cpu++;
++ }
+ set_cpu_possible(i, 1);
+ set_cpu_present(i, 1);
+ }
+@@ -157,7 +172,9 @@ static void bmips_boot_secondary(int cpu
+ bmips_send_ipi_single(cpu, 0);
+ else {
+ #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+- set_c0_brcm_cmt_ctrl(0x01);
++ /* Reset slave TP1 if booting from TP0 */
++ if (cpu_logical_map(cpu) == 0)
++ set_c0_brcm_cmt_ctrl(0x01);
+ #elif defined(CONFIG_CPU_BMIPS5000)
+ if (cpu & 0x01)
+ write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
--- /dev/null
+From 7c44eabf20cba12049bf9eebfa192afcc2053b2d Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Sat, 9 Jul 2011 12:15:06 -0700
+Subject: [PATCH V2 1/2] MIPS: BCM63XX: Add SMP support to prom.c
+
+This involves two changes to the BSP code:
+
+1) register_smp_ops() for BMIPS SMP
+
+2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with
+the special interrupt vector (IV). Move it to 0x8000_0380 at boot time,
+to resolve the conflict.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+[jogo@openwrt.org: moved SMP ops registration into ifdef guard,
+ changed ifdef guards to if (IS_ENABLED())]
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+V1 -> V2:
+ * changed ifdef guards to if (IS_ENABLED())
+
+ arch/mips/bcm63xx/prom.c | 41 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -8,7 +8,11 @@
+
+ #include <linux/init.h>
+ #include <linux/bootmem.h>
++#include <linux/smp.h>
+ #include <asm/bootinfo.h>
++#include <asm/bmips.h>
++#include <asm/smp-ops.h>
++#include <asm/mipsregs.h>
+ #include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_io.h>
+@@ -54,6 +58,43 @@ void __init prom_init(void)
+
+ /* do low level board init */
+ board_prom_init();
++
++ if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
++ /* set up SMP */
++ register_smp_ops(&bmips_smp_ops);
++
++ /*
++ * BCM6328 might not have its second CPU enabled, while BCM6358
++ * needs special handling for its shared TLB, so disable SMP
++ * for now.
++ */
++ if (BCMCPU_IS_6328()) {
++ bmips_smp_enabled = 0;
++ } else if (BCMCPU_IS_6358()) {
++ bmips_smp_enabled = 0;
++ }
++
++ if (!bmips_smp_enabled)
++ return;
++
++ /*
++ * The bootloader has set up the CPU1 reset vector at
++ * 0xa000_0200.
++ * This conflicts with the special interrupt vector (IV).
++ * The bootloader has also set up CPU1 to respond to the wrong
++ * IPI interrupt.
++ * Here we will start up CPU1 in the background and ask it to
++ * reconfigure itself then go back to sleep.
++ */
++ memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
++ __sync();
++ set_c0_cause(C_SW0);
++ cpumask_set_cpu(1, &bmips_booted_mask);
++
++ /*
++ * FIXME: we really should have some sort of hazard barrier here
++ */
++ }
+ }
+
+ void __init prom_free_prom_memory(void)
--- /dev/null
+From 41fa6dec9df9b4e55ac522c899270a72e51a9b4b Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 9 Jul 2011 12:15:06 -0700
+Subject: [PATCH V2 2/2] MIPS: BCM63XX: Enable second core SMP on BCM6328 if
+ available
+
+BCM6328 has a OTP which tells us if the second core is available.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/prom.c | 6 +++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 ++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 7 +++++++
+ 3 files changed, 14 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -69,7 +69,11 @@ void __init prom_init(void)
+ * for now.
+ */
+ if (BCMCPU_IS_6328()) {
+- bmips_smp_enabled = 0;
++ reg = bcm_readl(BCM_6328_OTP_BASE +
++ OTP_USER_BITS_6328_REG(3));
++
++ if (reg & OTP_6328_REG3_TP1_DISABLED)
++ bmips_smp_enabled = 0;
+ } else if (BCMCPU_IS_6358()) {
+ bmips_smp_enabled = 0;
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -296,6 +296,8 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
+ #define BCM_6328_RNG_BASE (0xdeadbeef)
+ #define BCM_6328_MISC_BASE (0xb0001800)
++#define BCM_6328_OTP_BASE (0xb0000600)
++
+ /*
+ * 6338 register sets base address
+ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1477,4 +1477,11 @@
+
+ #define PCIE_DEVICE_OFFSET 0x8000
+
++/*************************************************************************
++ * _REG relative to RSET_OTP
++ *************************************************************************/
++
++#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
++#define OTP_6328_REG3_TP1_DISABLED BIT(9)
++
+ #endif /* BCM63XX_REGS_H_ */
--- /dev/null
+From a15c33450df64f183c8ab5de8ef113091081679d Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Tue, 4 Jun 2013 20:53:33 +0000
+Subject: [PATCH 1/3] bcm63xx_enet: implement reset autoneg ethtool callback
+
+Implement the rset_nway ethtool callback which uses libphy generic
+autonegotiation restart function.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1330,6 +1330,20 @@ static void bcm_enet_get_ethtool_stats(s
+ mutex_unlock(&priv->mib_update_lock);
+ }
+
++static int bcm_enet_nway_reset(struct net_device *dev)
++{
++ struct bcm_enet_priv *priv;
++
++ priv = netdev_priv(dev);
++ if (priv->has_phy) {
++ if (!priv->phydev)
++ return -ENODEV;
++ return genphy_restart_aneg(priv->phydev);
++ }
++
++ return -EOPNOTSUPP;
++}
++
+ static int bcm_enet_get_settings(struct net_device *dev,
+ struct ethtool_cmd *cmd)
+ {
+@@ -1472,6 +1486,7 @@ static const struct ethtool_ops bcm_enet
+ .get_strings = bcm_enet_get_strings,
+ .get_sset_count = bcm_enet_get_sset_count,
+ .get_ethtool_stats = bcm_enet_get_ethtool_stats,
++ .nway_reset = bcm_enet_nway_reset,
+ .get_settings = bcm_enet_get_settings,
+ .set_settings = bcm_enet_set_settings,
+ .get_drvinfo = bcm_enet_get_drvinfo,
--- /dev/null
+From 33cab1696444a8e333cf0490bfe04c32d583fd51 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Tue, 4 Jun 2013 20:53:34 +0000
+Subject: [PATCH 2/3] bcm63xx_enet: split DMA channel register accesses
+
+The current bcm63xx_enet driver always uses bcmenet_shared_base whenever
+it needs to access DMA channel configuration space or access the DMA
+channel state RAM. Split these register in 3 parts to be more accurate:
+
+- global DMA configuration
+- per DMA channel configuration space
+- per DMA channel state RAM space
+
+This is preliminary to support new chips where the global DMA
+configuration remains the same, but there is a varying number of DMA
+channels located at a different memory offset.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/dev-enet.c | 23 +++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 +-
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 139 +++++++++++++---------
+ 3 files changed, 105 insertions(+), 61 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -19,6 +19,16 @@ static struct resource shared_res[] = {
+ .end = -1, /* filled at runtime */
+ .flags = IORESOURCE_MEM,
+ },
++ {
++ .start = -1, /* filled at runtime */
++ .end = -1, /* filled at runtime */
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = -1, /* filled at runtime */
++ .end = -1, /* filled at runtime */
++ .flags = IORESOURCE_MEM,
++ },
+ };
+
+ static struct platform_device bcm63xx_enet_shared_device = {
+@@ -110,10 +120,15 @@ int __init bcm63xx_enet_register(int uni
+ if (!shared_device_registered) {
+ shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
+ shared_res[0].end = shared_res[0].start;
+- if (BCMCPU_IS_6338())
+- shared_res[0].end += (RSET_ENETDMA_SIZE / 2) - 1;
+- else
+- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
++ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
++
++ shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
++ shared_res[1].end = shared_res[1].start;
++ shared_res[1].end += RSET_ENETDMAC_SIZE(16) - 1;
++
++ shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
++ shared_res[2].end = shared_res[2].start;
++ shared_res[2].end += RSET_ENETDMAS_SIZE(16) - 1;
+
+ ret = platform_device_register(&bcm63xx_enet_shared_device);
+ if (ret)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -187,7 +187,9 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_RSET_SPI_SIZE 1804
+ #define BCM_6368_RSET_SPI_SIZE 1804
+ #define RSET_ENET_SIZE 2048
+-#define RSET_ENETDMA_SIZE 2048
++#define RSET_ENETDMA_SIZE 256
++#define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
++#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
+ #define RSET_ENETSW_SIZE 65536
+ #define RSET_UART_SIZE 24
+ #define RSET_UDC_SIZE 256
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -41,8 +41,8 @@ static int copybreak __read_mostly = 128
+ module_param(copybreak, int, 0);
+ MODULE_PARM_DESC(copybreak, "Receive copy threshold");
+
+-/* io memory shared between all devices */
+-static void __iomem *bcm_enet_shared_base;
++/* io registers memory shared between all devices */
++static void __iomem *bcm_enet_shared_base[3];
+
+ /*
+ * io helpers to access mac registers
+@@ -63,13 +63,35 @@ static inline void enet_writel(struct bc
+ */
+ static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
+ {
+- return bcm_readl(bcm_enet_shared_base + off);
++ return bcm_readl(bcm_enet_shared_base[0] + off);
+ }
+
+ static inline void enet_dma_writel(struct bcm_enet_priv *priv,
+ u32 val, u32 off)
+ {
+- bcm_writel(val, bcm_enet_shared_base + off);
++ bcm_writel(val, bcm_enet_shared_base[0] + off);
++}
++
++static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
++{
++ return bcm_readl(bcm_enet_shared_base[1] + off);
++}
++
++static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
++ u32 val, u32 off)
++{
++ bcm_writel(val, bcm_enet_shared_base[1] + off);
++}
++
++static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
++{
++ return bcm_readl(bcm_enet_shared_base[2] + off);
++}
++
++static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
++ u32 val, u32 off)
++{
++ bcm_writel(val, bcm_enet_shared_base[2] + off);
+ }
+
+ /*
+@@ -353,8 +375,8 @@ static int bcm_enet_receive_queue(struct
+ bcm_enet_refill_rx(dev);
+
+ /* kick rx dma */
+- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+- ENETDMA_CHANCFG_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++ ENETDMAC_CHANCFG_REG(priv->rx_chan));
+ }
+
+ return processed;
+@@ -429,10 +451,10 @@ static int bcm_enet_poll(struct napi_str
+ dev = priv->net_dev;
+
+ /* ack interrupts */
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IR_REG(priv->rx_chan));
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IR_REG(priv->tx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IR_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IR_REG(priv->tx_chan));
+
+ /* reclaim sent skb */
+ tx_work_done = bcm_enet_tx_reclaim(dev, 0);
+@@ -451,10 +473,10 @@ static int bcm_enet_poll(struct napi_str
+ napi_complete(napi);
+
+ /* restore rx/tx interrupt */
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IRMASK_REG(priv->rx_chan));
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IRMASK_REG(priv->tx_chan));
+
+ return rx_work_done;
+ }
+@@ -497,8 +519,8 @@ static irqreturn_t bcm_enet_isr_dma(int
+ priv = netdev_priv(dev);
+
+ /* mask rx/tx interrupts */
+- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
+
+ napi_schedule(&priv->napi);
+
+@@ -557,8 +579,8 @@ static int bcm_enet_start_xmit(struct sk
+ wmb();
+
+ /* kick tx dma */
+- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+- ENETDMA_CHANCFG_REG(priv->tx_chan));
++ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++ ENETDMAC_CHANCFG_REG(priv->tx_chan));
+
+ /* stop queue if no more desc available */
+ if (!priv->tx_desc_count)
+@@ -833,8 +855,8 @@ static int bcm_enet_open(struct net_devi
+
+ /* mask all interrupts and request them */
+ enet_writel(priv, 0, ENET_IRMASK_REG);
+- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
+
+ ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
+ if (ret)
+@@ -921,28 +943,28 @@ static int bcm_enet_open(struct net_devi
+ }
+
+ /* write rx & tx ring addresses */
+- enet_dma_writel(priv, priv->rx_desc_dma,
+- ENETDMA_RSTART_REG(priv->rx_chan));
+- enet_dma_writel(priv, priv->tx_desc_dma,
+- ENETDMA_RSTART_REG(priv->tx_chan));
++ enet_dmas_writel(priv, priv->rx_desc_dma,
++ ENETDMAS_RSTART_REG(priv->rx_chan));
++ enet_dmas_writel(priv, priv->tx_desc_dma,
++ ENETDMAS_RSTART_REG(priv->tx_chan));
+
+ /* clear remaining state ram for rx & tx channel */
+- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
+
+ /* set max rx/tx length */
+ enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
+ enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
+
+ /* set dma maximum burst len */
+- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+- ENETDMA_MAXBURST_REG(priv->rx_chan));
+- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+- ENETDMA_MAXBURST_REG(priv->tx_chan));
++ enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ ENETDMAC_MAXBURST_REG(priv->rx_chan));
++ enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ ENETDMAC_MAXBURST_REG(priv->tx_chan));
+
+ /* set correct transmit fifo watermark */
+ enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
+@@ -960,26 +982,26 @@ static int bcm_enet_open(struct net_devi
+ val |= ENET_CTL_ENABLE_MASK;
+ enet_writel(priv, val, ENET_CTL_REG);
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+- ENETDMA_CHANCFG_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++ ENETDMAC_CHANCFG_REG(priv->rx_chan));
+
+ /* watch "mib counters about to overflow" interrupt */
+ enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
+ enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
+
+ /* watch "packet transferred" interrupt in rx and tx */
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IR_REG(priv->rx_chan));
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IR_REG(priv->tx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IR_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IR_REG(priv->tx_chan));
+
+ /* make sure we enable napi before rx interrupt */
+ napi_enable(&priv->napi);
+
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IRMASK_REG(priv->rx_chan));
+- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+- ENETDMA_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IRMASK_REG(priv->tx_chan));
+
+ if (priv->has_phy)
+ phy_start(priv->phydev);
+@@ -1059,14 +1081,14 @@ static void bcm_enet_disable_dma(struct
+ {
+ int limit;
+
+- enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
+
+ limit = 1000;
+ do {
+ u32 val;
+
+- val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
+- if (!(val & ENETDMA_CHANCFG_EN_MASK))
++ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
++ if (!(val & ENETDMAC_CHANCFG_EN_MASK))
+ break;
+ udelay(1);
+ } while (limit--);
+@@ -1092,8 +1114,8 @@ static int bcm_enet_stop(struct net_devi
+
+ /* mask all interrupts */
+ enet_writel(priv, 0, ENET_IRMASK_REG);
+- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
+
+ /* make sure no mib update is scheduled */
+ cancel_work_sync(&priv->mib_update_task);
+@@ -1638,7 +1660,7 @@ static int bcm_enet_probe(struct platfor
+
+ /* stop if shared driver failed, assume driver->probe will be
+ * called in the same order we register devices (correct ?) */
+- if (!bcm_enet_shared_base)
++ if (!bcm_enet_shared_base[0])
+ return -ENODEV;
+
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -1884,14 +1906,19 @@ struct platform_driver bcm63xx_enet_driv
+ static int bcm_enet_shared_probe(struct platform_device *pdev)
+ {
+ struct resource *res;
++ void __iomem *p[3];
++ unsigned int i;
+
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res)
+- return -ENODEV;
++ memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
+
+- bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res);
+- if (!bcm_enet_shared_base)
+- return -ENOMEM;
++ for (i = 0; i < 3; i++) {
++ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
++ p[i] = devm_ioremap_resource(&pdev->dev, res);
++ if (!p[i])
++ return -ENOMEM;
++ }
++
++ memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
+
+ return 0;
+ }
--- /dev/null
+From 85b2e40acd7b33409a0d889cd3d0b964c9df4b13 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Tue, 4 Jun 2013 20:53:35 +0000
+Subject: [PATCH 3/3] bcm63xx_enet: add support for Broadcom BCM63xx
+ integrated gigabit switch
+
+Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch
+which needs to be driven slightly differently from the traditional
+external switches. This patch introduces changes in arch/mips/bcm63xx in order
+to:
+
+- register a bcm63xx_enetsw driver instead of bcm63xx_enet driver
+- update DMA channels configuration & state RAM base addresses
+- add a new platform data configuration knob to define the number of
+ ports per switch/device and force link on some ports
+- define the required switch registers
+
+On the driver side, the following changes are required:
+
+- the switch ports need to be polled to ensure the link is up and
+ running and RX/TX can properly work
+- basic switch configuration needs to be performed for the switch to
+ forward packets to the CPU
+- update the MIB counters since the integrated
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 +
+ arch/mips/bcm63xx/dev-enet.c | 113 ++-
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 28 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 50 +
+ .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 +
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 995 +++++++++++++++++++-
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 71 ++
+ 7 files changed, 1205 insertions(+), 58 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -890,6 +890,10 @@ int __init board_register_devices(void)
+ !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
+ bcm63xx_enet_register(1, &board.enet1);
+
++ if (board.has_enetsw &&
++ !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
++ bcm63xx_enetsw_register(&board.enetsw);
++
+ if (board.has_usbd)
+ bcm63xx_usbd_register(&board.usbd);
+
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -104,6 +104,64 @@ static struct platform_device bcm63xx_en
+ },
+ };
+
++static struct resource enetsw_res[] = {
++ {
++ /* start & end filled at runtime */
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ /* start filled at runtime */
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ /* start filled at runtime */
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct bcm63xx_enetsw_platform_data enetsw_pd;
++
++static struct platform_device bcm63xx_enetsw_device = {
++ .name = "bcm63xx_enetsw",
++ .num_resources = ARRAY_SIZE(enetsw_res),
++ .resource = enetsw_res,
++ .dev = {
++ .platform_data = &enetsw_pd,
++ },
++};
++
++static int __init register_shared(void)
++{
++ int ret, chan_count;
++
++ if (shared_device_registered)
++ return 0;
++
++ shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
++ shared_res[0].end = shared_res[0].start;
++ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
++
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
++ chan_count = 32;
++ else
++ chan_count = 16;
++
++ shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
++ shared_res[1].end = shared_res[1].start;
++ shared_res[1].end += RSET_ENETDMAC_SIZE(chan_count) - 1;
++
++ shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
++ shared_res[2].end = shared_res[2].start;
++ shared_res[2].end += RSET_ENETDMAS_SIZE(chan_count) - 1;
++
++ ret = platform_device_register(&bcm63xx_enet_shared_device);
++ if (ret)
++ return ret;
++ shared_device_registered = 1;
++
++ return 0;
++}
++
+ int __init bcm63xx_enet_register(int unit,
+ const struct bcm63xx_enet_platform_data *pd)
+ {
+@@ -117,24 +175,9 @@ int __init bcm63xx_enet_register(int uni
+ if (unit == 1 && BCMCPU_IS_6338())
+ return -ENODEV;
+
+- if (!shared_device_registered) {
+- shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
+- shared_res[0].end = shared_res[0].start;
+- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
+-
+- shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
+- shared_res[1].end = shared_res[1].start;
+- shared_res[1].end += RSET_ENETDMAC_SIZE(16) - 1;
+-
+- shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
+- shared_res[2].end = shared_res[2].start;
+- shared_res[2].end += RSET_ENETDMAS_SIZE(16) - 1;
+-
+- ret = platform_device_register(&bcm63xx_enet_shared_device);
+- if (ret)
+- return ret;
+- shared_device_registered = 1;
+- }
++ ret = register_shared();
++ if (ret)
++ return ret;
+
+ if (unit == 0) {
+ enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
+@@ -175,3 +218,37 @@ int __init bcm63xx_enet_register(int uni
+ return ret;
+ return 0;
+ }
++
++int __init
++bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd)
++{
++ int ret;
++
++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++ return -ENODEV;
++
++ ret = register_shared();
++ if (ret)
++ return ret;
++
++ enetsw_res[0].start = bcm63xx_regset_address(RSET_ENETSW);
++ enetsw_res[0].end = enetsw_res[0].start;
++ enetsw_res[0].end += RSET_ENETSW_SIZE - 1;
++ enetsw_res[1].start = bcm63xx_get_irq_number(IRQ_ENETSW_RXDMA0);
++ enetsw_res[2].start = bcm63xx_get_irq_number(IRQ_ENETSW_TXDMA0);
++ if (!enetsw_res[2].start)
++ enetsw_res[2].start = -1;
++
++ memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
++
++ if (BCMCPU_IS_6328())
++ enetsw_pd.num_ports = ENETSW_PORTS_6328;
++ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
++ enetsw_pd.num_ports = ENETSW_PORTS_6368;
++
++ ret = platform_device_register(&bcm63xx_enetsw_device);
++ if (ret)
++ return ret;
++
++ return 0;
++}
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -39,7 +39,35 @@ struct bcm63xx_enet_platform_data {
+ int phy_id, int reg, int val));
+ };
+
++/*
++ * on board ethernet switch platform data
++ */
++#define ENETSW_MAX_PORT 8
++#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
++#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
++
++#define ENETSW_RGMII_PORT0 4
++
++struct bcm63xx_enetsw_port {
++ int used;
++ int phy_id;
++
++ int bypass_link;
++ int force_speed;
++ int force_duplex_full;
++
++ const char *name;
++};
++
++struct bcm63xx_enetsw_platform_data {
++ char mac_addr[ETH_ALEN];
++ int num_ports;
++ struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
++};
++
+ int __init bcm63xx_enet_register(int unit,
+ const struct bcm63xx_enet_platform_data *pd);
+
++int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
++
+ #endif /* ! BCM63XX_DEV_ENET_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -873,10 +873,60 @@
+ * _REG relative to RSET_ENETSW
+ *************************************************************************/
+
++/* Port traffic control */
++#define ENETSW_PTCTRL_REG(x) (0x0 + (x))
++#define ENETSW_PTCTRL_RXDIS_MASK (1 << 0)
++#define ENETSW_PTCTRL_TXDIS_MASK (1 << 1)
++
++/* Switch mode register */
++#define ENETSW_SWMODE_REG (0xb)
++#define ENETSW_SWMODE_FWD_EN_MASK (1 << 1)
++
++/* IMP override Register */
++#define ENETSW_IMPOV_REG (0xe)
++#define ENETSW_IMPOV_FORCE_MASK (1 << 7)
++#define ENETSW_IMPOV_TXFLOW_MASK (1 << 5)
++#define ENETSW_IMPOV_RXFLOW_MASK (1 << 4)
++#define ENETSW_IMPOV_1000_MASK (1 << 3)
++#define ENETSW_IMPOV_100_MASK (1 << 2)
++#define ENETSW_IMPOV_FDX_MASK (1 << 1)
++#define ENETSW_IMPOV_LINKUP_MASK (1 << 0)
++
++/* Port override Register */
++#define ENETSW_PORTOV_REG(x) (0x58 + (x))
++#define ENETSW_PORTOV_ENABLE_MASK (1 << 6)
++#define ENETSW_PORTOV_TXFLOW_MASK (1 << 5)
++#define ENETSW_PORTOV_RXFLOW_MASK (1 << 4)
++#define ENETSW_PORTOV_1000_MASK (1 << 3)
++#define ENETSW_PORTOV_100_MASK (1 << 2)
++#define ENETSW_PORTOV_FDX_MASK (1 << 1)
++#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
++
++/* MDIO control register */
++#define ENETSW_MDIOC_REG (0xb0)
++#define ENETSW_MDIOC_EXT_MASK (1 << 16)
++#define ENETSW_MDIOC_REG_SHIFT 20
++#define ENETSW_MDIOC_PHYID_SHIFT 25
++#define ENETSW_MDIOC_RD_MASK (1 << 30)
++#define ENETSW_MDIOC_WR_MASK (1 << 31)
++
++/* MDIO data register */
++#define ENETSW_MDIOD_REG (0xb4)
++
++/* Global Management Configuration Register */
++#define ENETSW_GMCR_REG (0x200)
++#define ENETSW_GMCR_RST_MIB_MASK (1 << 0)
++
+ /* MIB register */
+ #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
+ #define ENETSW_MIB_REG_COUNT 47
+
++/* Jumbo control register port mask register */
++#define ENETSW_JMBCTL_PORT_REG (0x4004)
++
++/* Jumbo control mib good frame register */
++#define ENETSW_JMBCTL_MAXSIZE_REG (0x4008)
++
+
+ /*************************************************************************
+ * _REG relative to RSET_OHCI_PRIV
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -24,6 +24,7 @@ struct board_info {
+ /* enabled feature/device */
+ unsigned int has_enet0:1;
+ unsigned int has_enet1:1;
++ unsigned int has_enetsw:1;
+ unsigned int has_pci:1;
+ unsigned int has_pccard:1;
+ unsigned int has_ohci0:1;
+@@ -36,6 +37,7 @@ struct board_info {
+ /* ethernet config */
+ struct bcm63xx_enet_platform_data enet0;
+ struct bcm63xx_enet_platform_data enet1;
++ struct bcm63xx_enetsw_platform_data enetsw;
+
+ /* USB config */
+ struct bcm63xx_usbd_platform_data usbd;
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -59,8 +59,43 @@ static inline void enet_writel(struct bc
+ }
+
+ /*
+- * io helpers to access shared registers
++ * io helpers to access switch registers
+ */
++static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
++{
++ return bcm_readl(priv->base + off);
++}
++
++static inline void enetsw_writel(struct bcm_enet_priv *priv,
++ u32 val, u32 off)
++{
++ bcm_writel(val, priv->base + off);
++}
++
++static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
++{
++ return bcm_readw(priv->base + off);
++}
++
++static inline void enetsw_writew(struct bcm_enet_priv *priv,
++ u16 val, u32 off)
++{
++ bcm_writew(val, priv->base + off);
++}
++
++static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
++{
++ return bcm_readb(priv->base + off);
++}
++
++static inline void enetsw_writeb(struct bcm_enet_priv *priv,
++ u8 val, u32 off)
++{
++ bcm_writeb(val, priv->base + off);
++}
++
++
++/* io helpers to access shared registers */
+ static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
+ {
+ return bcm_readl(bcm_enet_shared_base[0] + off);
+@@ -218,7 +253,6 @@ static int bcm_enet_refill_rx(struct net
+ if (!skb)
+ break;
+ priv->rx_skb[desc_idx] = skb;
+-
+ p = dma_map_single(&priv->pdev->dev, skb->data,
+ priv->rx_skb_size,
+ DMA_FROM_DEVICE);
+@@ -321,7 +355,8 @@ static int bcm_enet_receive_queue(struct
+ }
+
+ /* recycle packet if it's marked as bad */
+- if (unlikely(len_stat & DMADESC_ERR_MASK)) {
++ if (!priv->enet_is_sw &&
++ unlikely(len_stat & DMADESC_ERR_MASK)) {
+ dev->stats.rx_errors++;
+
+ if (len_stat & DMADESC_OVSIZE_MASK)
+@@ -552,6 +587,26 @@ static int bcm_enet_start_xmit(struct sk
+ goto out_unlock;
+ }
+
++ /* pad small packets sent on a switch device */
++ if (priv->enet_is_sw && skb->len < 64) {
++ int needed = 64 - skb->len;
++ char *data;
++
++ if (unlikely(skb_tailroom(skb) < needed)) {
++ struct sk_buff *nskb;
++
++ nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
++ if (!nskb) {
++ ret = NETDEV_TX_BUSY;
++ goto out_unlock;
++ }
++ dev_kfree_skb(skb);
++ skb = nskb;
++ }
++ data = skb_put(skb, needed);
++ memset(data, 0, needed);
++ }
++
+ /* point to the next available desc */
+ desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
+ priv->tx_skb[priv->tx_curr_desc] = skb;
+@@ -961,9 +1016,9 @@ static int bcm_enet_open(struct net_devi
+ enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
+
+ /* set dma maximum burst len */
+- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ enet_dmac_writel(priv, priv->dma_maxburst,
+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
+- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++ enet_dmac_writel(priv, priv->dma_maxburst,
+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
+
+ /* set correct transmit fifo watermark */
+@@ -1569,7 +1624,7 @@ static int compute_hw_mtu(struct bcm_ene
+ * it's appended
+ */
+ priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
+- BCMENET_DMA_MAXBURST * 4);
++ priv->dma_maxburst * 4);
+ return 0;
+ }
+
+@@ -1676,6 +1731,9 @@ static int bcm_enet_probe(struct platfor
+ return -ENOMEM;
+ priv = netdev_priv(dev);
+
++ priv->enet_is_sw = false;
++ priv->dma_maxburst = BCMENET_DMA_MAXBURST;
++
+ ret = compute_hw_mtu(priv, dev->mtu);
+ if (ret)
+ goto out;
+@@ -1901,60 +1959,916 @@ struct platform_driver bcm63xx_enet_driv
+ };
+
+ /*
+- * reserve & remap memory space shared between all macs
++ * switch mii access callbacks
+ */
+-static int bcm_enet_shared_probe(struct platform_device *pdev)
++static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
++ int ext, int phy_id, int location)
+ {
+- struct resource *res;
+- void __iomem *p[3];
+- unsigned int i;
++ u32 reg;
++ int ret;
+
+- memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
++ spin_lock_bh(&priv->enetsw_mdio_lock);
++ enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
+
+- for (i = 0; i < 3; i++) {
+- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+- p[i] = devm_ioremap_resource(&pdev->dev, res);
+- if (!p[i])
+- return -ENOMEM;
+- }
++ reg = ENETSW_MDIOC_RD_MASK |
++ (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
++ (location << ENETSW_MDIOC_REG_SHIFT);
++
++ if (ext)
++ reg |= ENETSW_MDIOC_EXT_MASK;
++
++ enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
++ udelay(50);
++ ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
++ spin_unlock_bh(&priv->enetsw_mdio_lock);
++ return ret;
++}
+
+- memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
++static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
++ int ext, int phy_id, int location,
++ uint16_t data)
++{
++ u32 reg;
+
+- return 0;
++ spin_lock_bh(&priv->enetsw_mdio_lock);
++ enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
++
++ reg = ENETSW_MDIOC_WR_MASK |
++ (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
++ (location << ENETSW_MDIOC_REG_SHIFT);
++
++ if (ext)
++ reg |= ENETSW_MDIOC_EXT_MASK;
++
++ reg |= data;
++
++ enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
++ udelay(50);
++ spin_unlock_bh(&priv->enetsw_mdio_lock);
+ }
+
+-static int bcm_enet_shared_remove(struct platform_device *pdev)
++static inline int bcm_enet_port_is_rgmii(int portid)
+ {
+- return 0;
++ return portid >= ENETSW_RGMII_PORT0;
+ }
+
+ /*
+- * this "shared" driver is needed because both macs share a single
+- * address space
++ * enet sw PHY polling
+ */
+-struct platform_driver bcm63xx_enet_shared_driver = {
+- .probe = bcm_enet_shared_probe,
+- .remove = bcm_enet_shared_remove,
+- .driver = {
+- .name = "bcm63xx_enet_shared",
+- .owner = THIS_MODULE,
+- },
+-};
++static void swphy_poll_timer(unsigned long data)
++{
++ struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
++ unsigned int i;
++
++ for (i = 0; i < priv->num_ports; i++) {
++ struct bcm63xx_enetsw_port *port;
++ int val, j, up, advertise, lpa, lpa2, speed, duplex, media;
++ int external_phy = bcm_enet_port_is_rgmii(i);
++ u8 override;
++
++ port = &priv->used_ports[i];
++ if (!port->used)
++ continue;
++
++ if (port->bypass_link)
++ continue;
++
++ /* dummy read to clear */
++ for (j = 0; j < 2; j++)
++ val = bcmenet_sw_mdio_read(priv, external_phy,
++ port->phy_id, MII_BMSR);
++
++ if (val == 0xffff)
++ continue;
++
++ up = (val & BMSR_LSTATUS) ? 1 : 0;
++ if (!(up ^ priv->sw_port_link[i]))
++ continue;
++
++ priv->sw_port_link[i] = up;
++
++ /* link changed */
++ if (!up) {
++ dev_info(&priv->pdev->dev, "link DOWN on %s\n",
++ port->name);
++ enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
++ ENETSW_PORTOV_REG(i));
++ enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
++ ENETSW_PTCTRL_TXDIS_MASK,
++ ENETSW_PTCTRL_REG(i));
++ continue;
++ }
++
++ advertise = bcmenet_sw_mdio_read(priv, external_phy,
++ port->phy_id, MII_ADVERTISE);
++
++ lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
++ MII_LPA);
++
++ lpa2 = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
++ MII_STAT1000);
++
++ /* figure out media and duplex from advertise and LPA values */
++ media = mii_nway_result(lpa & advertise);
++ duplex = (media & ADVERTISE_FULL) ? 1 : 0;
++ if (lpa2 & LPA_1000FULL)
++ duplex = 1;
++
++ if (lpa2 & (LPA_1000FULL | LPA_1000HALF))
++ speed = 1000;
++ else {
++ if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
++ speed = 100;
++ else
++ speed = 10;
++ }
++
++ dev_info(&priv->pdev->dev,
++ "link UP on %s, %dMbps, %s-duplex\n",
++ port->name, speed, duplex ? "full" : "half");
++
++ override = ENETSW_PORTOV_ENABLE_MASK |
++ ENETSW_PORTOV_LINKUP_MASK;
++
++ if (speed == 1000)
++ override |= ENETSW_IMPOV_1000_MASK;
++ else if (speed == 100)
++ override |= ENETSW_IMPOV_100_MASK;
++ if (duplex)
++ override |= ENETSW_IMPOV_FDX_MASK;
++
++ enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
++ enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
++ }
++
++ priv->swphy_poll.expires = jiffies + HZ;
++ add_timer(&priv->swphy_poll);
++}
+
+ /*
+- * entry point
++ * open callback, allocate dma rings & buffers and start rx operation
+ */
+-static int __init bcm_enet_init(void)
++static int bcm_enetsw_open(struct net_device *dev)
+ {
+- int ret;
++ struct bcm_enet_priv *priv;
++ struct device *kdev;
++ int i, ret;
++ unsigned int size;
++ void *p;
++ u32 val;
+
+- ret = platform_driver_register(&bcm63xx_enet_shared_driver);
+- if (ret)
+- return ret;
++ priv = netdev_priv(dev);
++ kdev = &priv->pdev->dev;
+
+- ret = platform_driver_register(&bcm63xx_enet_driver);
++ /* mask all interrupts and request them */
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++
++ ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
++ IRQF_DISABLED, dev->name, dev);
+ if (ret)
+- platform_driver_unregister(&bcm63xx_enet_shared_driver);
++ goto out_freeirq;
++
++ if (priv->irq_tx != -1) {
++ ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
++ IRQF_DISABLED, dev->name, dev);
++ if (ret)
++ goto out_freeirq_rx;
++ }
++
++ /* allocate rx dma ring */
++ size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
++ p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
++ if (!p) {
++ dev_err(kdev, "cannot allocate rx ring %u\n", size);
++ ret = -ENOMEM;
++ goto out_freeirq_tx;
++ }
++
++ memset(p, 0, size);
++ priv->rx_desc_alloc_size = size;
++ priv->rx_desc_cpu = p;
++
++ /* allocate tx dma ring */
++ size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
++ p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
++ if (!p) {
++ dev_err(kdev, "cannot allocate tx ring\n");
++ ret = -ENOMEM;
++ goto out_free_rx_ring;
++ }
++
++ memset(p, 0, size);
++ priv->tx_desc_alloc_size = size;
++ priv->tx_desc_cpu = p;
++
++ priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
++ GFP_KERNEL);
++ if (!priv->tx_skb) {
++ dev_err(kdev, "cannot allocate rx skb queue\n");
++ ret = -ENOMEM;
++ goto out_free_tx_ring;
++ }
++
++ priv->tx_desc_count = priv->tx_ring_size;
++ priv->tx_dirty_desc = 0;
++ priv->tx_curr_desc = 0;
++ spin_lock_init(&priv->tx_lock);
++
++ /* init & fill rx ring with skbs */
++ priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
++ GFP_KERNEL);
++ if (!priv->rx_skb) {
++ dev_err(kdev, "cannot allocate rx skb queue\n");
++ ret = -ENOMEM;
++ goto out_free_tx_skb;
++ }
++
++ priv->rx_desc_count = 0;
++ priv->rx_dirty_desc = 0;
++ priv->rx_curr_desc = 0;
++
++ /* disable all ports */
++ for (i = 0; i < priv->num_ports; i++) {
++ enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
++ ENETSW_PORTOV_REG(i));
++ enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
++ ENETSW_PTCTRL_TXDIS_MASK,
++ ENETSW_PTCTRL_REG(i));
++
++ priv->sw_port_link[i] = 0;
++ }
++
++ /* reset mib */
++ val = enetsw_readb(priv, ENETSW_GMCR_REG);
++ val |= ENETSW_GMCR_RST_MIB_MASK;
++ enetsw_writeb(priv, val, ENETSW_GMCR_REG);
++ mdelay(1);
++ val &= ~ENETSW_GMCR_RST_MIB_MASK;
++ enetsw_writeb(priv, val, ENETSW_GMCR_REG);
++ mdelay(1);
++
++ /* force CPU port state */
++ val = enetsw_readb(priv, ENETSW_IMPOV_REG);
++ val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
++ enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
++
++ /* enable switch forward engine */
++ val = enetsw_readb(priv, ENETSW_SWMODE_REG);
++ val |= ENETSW_SWMODE_FWD_EN_MASK;
++ enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
++
++ /* enable jumbo on all ports */
++ enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
++ enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
++
++ /* initialize flow control buffer allocation */
++ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
++ ENETDMA_BUFALLOC_REG(priv->rx_chan));
++
++ if (bcm_enet_refill_rx(dev)) {
++ dev_err(kdev, "cannot allocate rx skb queue\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* write rx & tx ring addresses */
++ enet_dmas_writel(priv, priv->rx_desc_dma,
++ ENETDMAS_RSTART_REG(priv->rx_chan));
++ enet_dmas_writel(priv, priv->tx_desc_dma,
++ ENETDMAS_RSTART_REG(priv->tx_chan));
++
++ /* clear remaining state ram for rx & tx channel */
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
++
++ /* set dma maximum burst len */
++ enet_dmac_writel(priv, priv->dma_maxburst,
++ ENETDMAC_MAXBURST_REG(priv->rx_chan));
++ enet_dmac_writel(priv, priv->dma_maxburst,
++ ENETDMAC_MAXBURST_REG(priv->tx_chan));
++
++ /* set flow control low/high threshold to 1/3 / 2/3 */
++ val = priv->rx_ring_size / 3;
++ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
++ val = (priv->rx_ring_size * 2) / 3;
++ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
++
++ /* all set, enable mac and interrupts, start dma engine and
++ * kick rx dma channel
++ */
++ wmb();
++ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
++ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++ ENETDMAC_CHANCFG_REG(priv->rx_chan));
++
++ /* watch "packet transferred" interrupt in rx and tx */
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IR_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IR_REG(priv->tx_chan));
++
++ /* make sure we enable napi before rx interrupt */
++ napi_enable(&priv->napi);
++
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++ ENETDMAC_IRMASK_REG(priv->tx_chan));
++
++ netif_carrier_on(dev);
++ netif_start_queue(dev);
++
++ /* apply override config for bypass_link ports here. */
++ for (i = 0; i < priv->num_ports; i++) {
++ struct bcm63xx_enetsw_port *port;
++ u8 override;
++ port = &priv->used_ports[i];
++ if (!port->used)
++ continue;
++
++ if (!port->bypass_link)
++ continue;
++
++ override = ENETSW_PORTOV_ENABLE_MASK |
++ ENETSW_PORTOV_LINKUP_MASK;
++
++ switch (port->force_speed) {
++ case 1000:
++ override |= ENETSW_IMPOV_1000_MASK;
++ break;
++ case 100:
++ override |= ENETSW_IMPOV_100_MASK;
++ break;
++ case 10:
++ break;
++ default:
++ pr_warn("invalid forced speed on port %s: assume 10\n",
++ port->name);
++ break;
++ }
++
++ if (port->force_duplex_full)
++ override |= ENETSW_IMPOV_FDX_MASK;
++
++
++ enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
++ enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
++ }
++
++ /* start phy polling timer */
++ init_timer(&priv->swphy_poll);
++ priv->swphy_poll.function = swphy_poll_timer;
++ priv->swphy_poll.data = (unsigned long)priv;
++ priv->swphy_poll.expires = jiffies;
++ add_timer(&priv->swphy_poll);
++ return 0;
++
++out:
++ for (i = 0; i < priv->rx_ring_size; i++) {
++ struct bcm_enet_desc *desc;
++
++ if (!priv->rx_skb[i])
++ continue;
++
++ desc = &priv->rx_desc_cpu[i];
++ dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
++ DMA_FROM_DEVICE);
++ kfree_skb(priv->rx_skb[i]);
++ }
++ kfree(priv->rx_skb);
++
++out_free_tx_skb:
++ kfree(priv->tx_skb);
++
++out_free_tx_ring:
++ dma_free_coherent(kdev, priv->tx_desc_alloc_size,
++ priv->tx_desc_cpu, priv->tx_desc_dma);
++
++out_free_rx_ring:
++ dma_free_coherent(kdev, priv->rx_desc_alloc_size,
++ priv->rx_desc_cpu, priv->rx_desc_dma);
++
++out_freeirq_tx:
++ if (priv->irq_tx != -1)
++ free_irq(priv->irq_tx, dev);
++
++out_freeirq_rx:
++ free_irq(priv->irq_rx, dev);
++
++out_freeirq:
++ return ret;
++}
++
++/* stop callback */
++static int bcm_enetsw_stop(struct net_device *dev)
++{
++ struct bcm_enet_priv *priv;
++ struct device *kdev;
++ int i;
++
++ priv = netdev_priv(dev);
++ kdev = &priv->pdev->dev;
++
++ del_timer_sync(&priv->swphy_poll);
++ netif_stop_queue(dev);
++ napi_disable(&priv->napi);
++ del_timer_sync(&priv->rx_timeout);
++
++ /* mask all interrupts */
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++
++ /* disable dma & mac */
++ bcm_enet_disable_dma(priv, priv->tx_chan);
++ bcm_enet_disable_dma(priv, priv->rx_chan);
++
++ /* force reclaim of all tx buffers */
++ bcm_enet_tx_reclaim(dev, 1);
++
++ /* free the rx skb ring */
++ for (i = 0; i < priv->rx_ring_size; i++) {
++ struct bcm_enet_desc *desc;
++
++ if (!priv->rx_skb[i])
++ continue;
++
++ desc = &priv->rx_desc_cpu[i];
++ dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
++ DMA_FROM_DEVICE);
++ kfree_skb(priv->rx_skb[i]);
++ }
++
++ /* free remaining allocated memory */
++ kfree(priv->rx_skb);
++ kfree(priv->tx_skb);
++ dma_free_coherent(kdev, priv->rx_desc_alloc_size,
++ priv->rx_desc_cpu, priv->rx_desc_dma);
++ dma_free_coherent(kdev, priv->tx_desc_alloc_size,
++ priv->tx_desc_cpu, priv->tx_desc_dma);
++ if (priv->irq_tx != -1)
++ free_irq(priv->irq_tx, dev);
++ free_irq(priv->irq_rx, dev);
++
++ return 0;
++}
++
++/* try to sort out phy external status by walking the used_port field
++ * in the bcm_enet_priv structure. in case the phy address is not
++ * assigned to any physical port on the switch, assume it is external
++ * (and yell at the user).
++ */
++static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
++{
++ int i;
++
++ for (i = 0; i < priv->num_ports; ++i) {
++ if (!priv->used_ports[i].used)
++ continue;
++ if (priv->used_ports[i].phy_id == phy_id)
++ return bcm_enet_port_is_rgmii(i);
++ }
++
++ printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
++ phy_id);
++ return 1;
++}
++
++/* can't use bcmenet_sw_mdio_read directly as we need to sort out
++ * external/internal status of the given phy_id first.
++ */
++static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
++ int location)
++{
++ struct bcm_enet_priv *priv;
++
++ priv = netdev_priv(dev);
++ return bcmenet_sw_mdio_read(priv,
++ bcm_enetsw_phy_is_external(priv, phy_id),
++ phy_id, location);
++}
++
++/* can't use bcmenet_sw_mdio_write directly as we need to sort out
++ * external/internal status of the given phy_id first.
++ */
++static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
++ int location,
++ int val)
++{
++ struct bcm_enet_priv *priv;
++
++ priv = netdev_priv(dev);
++ bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
++ phy_id, location, val);
++}
++
++static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++ struct mii_if_info mii;
++
++ mii.dev = dev;
++ mii.mdio_read = bcm_enetsw_mii_mdio_read;
++ mii.mdio_write = bcm_enetsw_mii_mdio_write;
++ mii.phy_id = 0;
++ mii.phy_id_mask = 0x3f;
++ mii.reg_num_mask = 0x1f;
++ return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
++
++}
++
++static const struct net_device_ops bcm_enetsw_ops = {
++ .ndo_open = bcm_enetsw_open,
++ .ndo_stop = bcm_enetsw_stop,
++ .ndo_start_xmit = bcm_enet_start_xmit,
++ .ndo_change_mtu = bcm_enet_change_mtu,
++ .ndo_do_ioctl = bcm_enetsw_ioctl,
++};
++
++
++static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
++ { "rx_packets", DEV_STAT(rx_packets), -1 },
++ { "tx_packets", DEV_STAT(tx_packets), -1 },
++ { "rx_bytes", DEV_STAT(rx_bytes), -1 },
++ { "tx_bytes", DEV_STAT(tx_bytes), -1 },
++ { "rx_errors", DEV_STAT(rx_errors), -1 },
++ { "tx_errors", DEV_STAT(tx_errors), -1 },
++ { "rx_dropped", DEV_STAT(rx_dropped), -1 },
++ { "tx_dropped", DEV_STAT(tx_dropped), -1 },
++
++ { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
++ { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
++ { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
++ { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
++ { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
++ { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
++ { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
++ { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
++ { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
++ { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
++ ETHSW_MIB_RX_1024_1522 },
++ { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
++ ETHSW_MIB_RX_1523_2047 },
++ { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
++ ETHSW_MIB_RX_2048_4095 },
++ { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
++ ETHSW_MIB_RX_4096_8191 },
++ { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
++ ETHSW_MIB_RX_8192_9728 },
++ { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
++ { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
++ { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
++ { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
++ { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
++
++ { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
++ { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
++ { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
++ { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
++ { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
++ { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
++
++};
++
++#define BCM_ENETSW_STATS_LEN \
++ (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
++
++static void bcm_enetsw_get_strings(struct net_device *netdev,
++ u32 stringset, u8 *data)
++{
++ int i;
++
++ switch (stringset) {
++ case ETH_SS_STATS:
++ for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
++ memcpy(data + i * ETH_GSTRING_LEN,
++ bcm_enetsw_gstrings_stats[i].stat_string,
++ ETH_GSTRING_LEN);
++ }
++ break;
++ }
++}
++
++static int bcm_enetsw_get_sset_count(struct net_device *netdev,
++ int string_set)
++{
++ switch (string_set) {
++ case ETH_SS_STATS:
++ return BCM_ENETSW_STATS_LEN;
++ default:
++ return -EINVAL;
++ }
++}
++
++static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
++ struct ethtool_drvinfo *drvinfo)
++{
++ strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
++ strncpy(drvinfo->version, bcm_enet_driver_version, 32);
++ strncpy(drvinfo->fw_version, "N/A", 32);
++ strncpy(drvinfo->bus_info, "bcm63xx", 32);
++ drvinfo->n_stats = BCM_ENETSW_STATS_LEN;
++}
++
++static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
++ struct ethtool_stats *stats,
++ u64 *data)
++{
++ struct bcm_enet_priv *priv;
++ int i;
++
++ priv = netdev_priv(netdev);
++
++ for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
++ const struct bcm_enet_stats *s;
++ u32 lo, hi;
++ char *p;
++ int reg;
++
++ s = &bcm_enetsw_gstrings_stats[i];
++
++ reg = s->mib_reg;
++ if (reg == -1)
++ continue;
++
++ lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
++ p = (char *)priv + s->stat_offset;
++
++ if (s->sizeof_stat == sizeof(u64)) {
++ hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
++ *(u64 *)p = ((u64)hi << 32 | lo);
++ } else {
++ *(u32 *)p = lo;
++ }
++ }
++
++ for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
++ const struct bcm_enet_stats *s;
++ char *p;
++
++ s = &bcm_enetsw_gstrings_stats[i];
++
++ if (s->mib_reg == -1)
++ p = (char *)&netdev->stats + s->stat_offset;
++ else
++ p = (char *)priv + s->stat_offset;
++
++ data[i] = (s->sizeof_stat == sizeof(u64)) ?
++ *(u64 *)p : *(u32 *)p;
++ }
++}
++
++static void bcm_enetsw_get_ringparam(struct net_device *dev,
++ struct ethtool_ringparam *ering)
++{
++ struct bcm_enet_priv *priv;
++
++ priv = netdev_priv(dev);
++
++ /* rx/tx ring is actually only limited by memory */
++ ering->rx_max_pending = 8192;
++ ering->tx_max_pending = 8192;
++ ering->rx_mini_max_pending = 0;
++ ering->rx_jumbo_max_pending = 0;
++ ering->rx_pending = priv->rx_ring_size;
++ ering->tx_pending = priv->tx_ring_size;
++}
++
++static int bcm_enetsw_set_ringparam(struct net_device *dev,
++ struct ethtool_ringparam *ering)
++{
++ struct bcm_enet_priv *priv;
++ int was_running;
++
++ priv = netdev_priv(dev);
++
++ was_running = 0;
++ if (netif_running(dev)) {
++ bcm_enetsw_stop(dev);
++ was_running = 1;
++ }
++
++ priv->rx_ring_size = ering->rx_pending;
++ priv->tx_ring_size = ering->tx_pending;
++
++ if (was_running) {
++ int err;
++
++ err = bcm_enetsw_open(dev);
++ if (err)
++ dev_close(dev);
++ }
++ return 0;
++}
++
++static struct ethtool_ops bcm_enetsw_ethtool_ops = {
++ .get_strings = bcm_enetsw_get_strings,
++ .get_sset_count = bcm_enetsw_get_sset_count,
++ .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
++ .get_drvinfo = bcm_enetsw_get_drvinfo,
++ .get_ringparam = bcm_enetsw_get_ringparam,
++ .set_ringparam = bcm_enetsw_set_ringparam,
++};
++
++/* allocate netdevice, request register memory and register device. */
++static int bcm_enetsw_probe(struct platform_device *pdev)
++{
++ struct bcm_enet_priv *priv;
++ struct net_device *dev;
++ struct bcm63xx_enetsw_platform_data *pd;
++ struct resource *res_mem;
++ int ret, irq_rx, irq_tx;
++
++ /* stop if shared driver failed, assume driver->probe will be
++ * called in the same order we register devices (correct ?)
++ */
++ if (!bcm_enet_shared_base[0])
++ return -ENODEV;
++
++ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ irq_rx = platform_get_irq(pdev, 0);
++ irq_tx = platform_get_irq(pdev, 1);
++ if (!res_mem || irq_rx < 0)
++ return -ENODEV;
++
++ ret = 0;
++ dev = alloc_etherdev(sizeof(*priv));
++ if (!dev)
++ return -ENOMEM;
++ priv = netdev_priv(dev);
++ memset(priv, 0, sizeof(*priv));
++
++ /* initialize default and fetch platform data */
++ priv->enet_is_sw = true;
++ priv->irq_rx = irq_rx;
++ priv->irq_tx = irq_tx;
++ priv->rx_ring_size = BCMENET_DEF_RX_DESC;
++ priv->tx_ring_size = BCMENET_DEF_TX_DESC;
++ priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
++
++ pd = pdev->dev.platform_data;
++ if (pd) {
++ memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
++ memcpy(priv->used_ports, pd->used_ports,
++ sizeof(pd->used_ports));
++ priv->num_ports = pd->num_ports;
++ }
++
++ ret = compute_hw_mtu(priv, dev->mtu);
++ if (ret)
++ goto out;
++
++ if (!request_mem_region(res_mem->start, resource_size(res_mem),
++ "bcm63xx_enetsw")) {
++ ret = -EBUSY;
++ goto out;
++ }
++
++ priv->base = ioremap(res_mem->start, resource_size(res_mem));
++ if (priv->base == NULL) {
++ ret = -ENOMEM;
++ goto out_release_mem;
++ }
++
++ priv->mac_clk = clk_get(&pdev->dev, "enetsw");
++ if (IS_ERR(priv->mac_clk)) {
++ ret = PTR_ERR(priv->mac_clk);
++ goto out_unmap;
++ }
++ clk_enable(priv->mac_clk);
++
++ priv->rx_chan = 0;
++ priv->tx_chan = 1;
++ spin_lock_init(&priv->rx_lock);
++
++ /* init rx timeout (used for oom) */
++ init_timer(&priv->rx_timeout);
++ priv->rx_timeout.function = bcm_enet_refill_rx_timer;
++ priv->rx_timeout.data = (unsigned long)dev;
++
++ /* register netdevice */
++ dev->netdev_ops = &bcm_enetsw_ops;
++ netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
++ SET_ETHTOOL_OPS(dev, &bcm_enetsw_ethtool_ops);
++ SET_NETDEV_DEV(dev, &pdev->dev);
++
++ spin_lock_init(&priv->enetsw_mdio_lock);
++
++ ret = register_netdev(dev);
++ if (ret)
++ goto out_put_clk;
++
++ netif_carrier_off(dev);
++ platform_set_drvdata(pdev, dev);
++ priv->pdev = pdev;
++ priv->net_dev = dev;
++
++ return 0;
++
++out_put_clk:
++ clk_put(priv->mac_clk);
++
++out_unmap:
++ iounmap(priv->base);
++
++out_release_mem:
++ release_mem_region(res_mem->start, resource_size(res_mem));
++out:
++ free_netdev(dev);
++ return ret;
++}
++
++
++/* exit func, stops hardware and unregisters netdevice */
++static int bcm_enetsw_remove(struct platform_device *pdev)
++{
++ struct bcm_enet_priv *priv;
++ struct net_device *dev;
++ struct resource *res;
++
++ /* stop netdevice */
++ dev = platform_get_drvdata(pdev);
++ priv = netdev_priv(dev);
++ unregister_netdev(dev);
++
++ /* release device resources */
++ iounmap(priv->base);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ release_mem_region(res->start, resource_size(res));
++
++ platform_set_drvdata(pdev, NULL);
++ free_netdev(dev);
++ return 0;
++}
++
++struct platform_driver bcm63xx_enetsw_driver = {
++ .probe = bcm_enetsw_probe,
++ .remove = bcm_enetsw_remove,
++ .driver = {
++ .name = "bcm63xx_enetsw",
++ .owner = THIS_MODULE,
++ },
++};
++
++/* reserve & remap memory space shared between all macs */
++static int bcm_enet_shared_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ void __iomem *p[3];
++ unsigned int i;
++
++ memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
++
++ for (i = 0; i < 3; i++) {
++ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
++ p[i] = devm_ioremap_resource(&pdev->dev, res);
++ if (!p[i])
++ return -ENOMEM;
++ }
++
++ memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
++
++ return 0;
++}
++
++static int bcm_enet_shared_remove(struct platform_device *pdev)
++{
++ return 0;
++}
++
++/* this "shared" driver is needed because both macs share a single
++ * address space
++ */
++struct platform_driver bcm63xx_enet_shared_driver = {
++ .probe = bcm_enet_shared_probe,
++ .remove = bcm_enet_shared_remove,
++ .driver = {
++ .name = "bcm63xx_enet_shared",
++ .owner = THIS_MODULE,
++ },
++};
++
++/* entry point */
++static int __init bcm_enet_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&bcm63xx_enet_shared_driver);
++ if (ret)
++ return ret;
++
++ ret = platform_driver_register(&bcm63xx_enet_driver);
++ if (ret)
++ platform_driver_unregister(&bcm63xx_enet_shared_driver);
++
++ ret = platform_driver_register(&bcm63xx_enetsw_driver);
++ if (ret) {
++ platform_driver_unregister(&bcm63xx_enet_driver);
++ platform_driver_unregister(&bcm63xx_enet_shared_driver);
++ }
+
+ return ret;
+ }
+@@ -1962,6 +2876,7 @@ static int __init bcm_enet_init(void)
+ static void __exit bcm_enet_exit(void)
+ {
+ platform_driver_unregister(&bcm63xx_enet_driver);
++ platform_driver_unregister(&bcm63xx_enetsw_driver);
+ platform_driver_unregister(&bcm63xx_enet_shared_driver);
+ }
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+@@ -18,6 +18,7 @@
+
+ /* maximum burst len for dma (4 bytes unit) */
+ #define BCMENET_DMA_MAXBURST 16
++#define BCMENETSW_DMA_MAXBURST 8
+
+ /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
+ * must be low enough so that a DMA transfer of above burst length can
+@@ -84,11 +85,60 @@
+ #define ETH_MIB_RX_CNTRL 54
+
+
++/*
++ * SW MIB Counters register definitions
++*/
++#define ETHSW_MIB_TX_ALL_OCT 0
++#define ETHSW_MIB_TX_DROP_PKTS 2
++#define ETHSW_MIB_TX_QOS_PKTS 3
++#define ETHSW_MIB_TX_BRDCAST 4
++#define ETHSW_MIB_TX_MULT 5
++#define ETHSW_MIB_TX_UNI 6
++#define ETHSW_MIB_TX_COL 7
++#define ETHSW_MIB_TX_1_COL 8
++#define ETHSW_MIB_TX_M_COL 9
++#define ETHSW_MIB_TX_DEF 10
++#define ETHSW_MIB_TX_LATE 11
++#define ETHSW_MIB_TX_EX_COL 12
++#define ETHSW_MIB_TX_PAUSE 14
++#define ETHSW_MIB_TX_QOS_OCT 15
++
++#define ETHSW_MIB_RX_ALL_OCT 17
++#define ETHSW_MIB_RX_UND 19
++#define ETHSW_MIB_RX_PAUSE 20
++#define ETHSW_MIB_RX_64 21
++#define ETHSW_MIB_RX_65_127 22
++#define ETHSW_MIB_RX_128_255 23
++#define ETHSW_MIB_RX_256_511 24
++#define ETHSW_MIB_RX_512_1023 25
++#define ETHSW_MIB_RX_1024_1522 26
++#define ETHSW_MIB_RX_OVR 27
++#define ETHSW_MIB_RX_JAB 28
++#define ETHSW_MIB_RX_ALIGN 29
++#define ETHSW_MIB_RX_CRC 30
++#define ETHSW_MIB_RX_GD_OCT 31
++#define ETHSW_MIB_RX_DROP 33
++#define ETHSW_MIB_RX_UNI 34
++#define ETHSW_MIB_RX_MULT 35
++#define ETHSW_MIB_RX_BRDCAST 36
++#define ETHSW_MIB_RX_SA_CHANGE 37
++#define ETHSW_MIB_RX_FRAG 38
++#define ETHSW_MIB_RX_OVR_DISC 39
++#define ETHSW_MIB_RX_SYM 40
++#define ETHSW_MIB_RX_QOS_PKTS 41
++#define ETHSW_MIB_RX_QOS_OCT 42
++#define ETHSW_MIB_RX_1523_2047 44
++#define ETHSW_MIB_RX_2048_4095 45
++#define ETHSW_MIB_RX_4096_8191 46
++#define ETHSW_MIB_RX_8192_9728 47
++
++
+ struct bcm_enet_mib_counters {
+ u64 tx_gd_octets;
+ u32 tx_gd_pkts;
+ u32 tx_all_octets;
+ u32 tx_all_pkts;
++ u32 tx_unicast;
+ u32 tx_brdcast;
+ u32 tx_mult;
+ u32 tx_64;
+@@ -97,7 +147,12 @@ struct bcm_enet_mib_counters {
+ u32 tx_256_511;
+ u32 tx_512_1023;
+ u32 tx_1024_max;
++ u32 tx_1523_2047;
++ u32 tx_2048_4095;
++ u32 tx_4096_8191;
++ u32 tx_8192_9728;
+ u32 tx_jab;
++ u32 tx_drop;
+ u32 tx_ovr;
+ u32 tx_frag;
+ u32 tx_underrun;
+@@ -114,6 +169,7 @@ struct bcm_enet_mib_counters {
+ u32 rx_all_octets;
+ u32 rx_all_pkts;
+ u32 rx_brdcast;
++ u32 rx_unicast;
+ u32 rx_mult;
+ u32 rx_64;
+ u32 rx_65_127;
+@@ -197,6 +253,9 @@ struct bcm_enet_priv {
+ /* number of dma desc in tx ring */
+ int tx_ring_size;
+
++ /* maximum dma burst size */
++ int dma_maxburst;
++
+ /* cpu view of rx dma ring */
+ struct bcm_enet_desc *tx_desc_cpu;
+
+@@ -269,6 +328,18 @@ struct bcm_enet_priv {
+
+ /* maximum hardware transmit/receive size */
+ unsigned int hw_mtu;
++
++ bool enet_is_sw;
++
++ /* port mapping for switch devices */
++ int num_ports;
++ struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
++ int sw_port_link[ENETSW_MAX_PORT];
++
++ /* used to poll switch port state */
++ struct timer_list swphy_poll;
++ spinlock_t enetsw_mdio_lock;
+ };
+
++
+ #endif /* ! BCM63XX_ENET_H_ */
--- /dev/null
+From fb7e08ec47f7168b8f4f72d8e3b5bcf625e1089e Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 12 Jun 2013 18:53:05 +0000
+Subject: [PATCH] bcm63xx_enet: add support Broadcom BCM6345 Ethernet
+
+This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
+has a slightly different and older DMA engine which requires the
+following modifications:
+
+- the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
+ which means that the helpers enet_dma{c,s} need to account for this
+ channel width and we can no longer use macros
+
+- BCM6345 DMA engine does not have any internal SRAM for transfering
+ buffers
+
+- BCM6345 buffer allocation and flow control is not per-channel but
+ global (done in RSET_ENETDMA)
+
+- the DMA engine bits are right-shifted by 3 compared to other DMA
+ generations
+
+- the DMA enable/interrupt masks are a little different (we need to
+ enabled more bits for 6345)
+
+- some register have the same meaning but are offsetted in the ENET_DMAC
+ space so a lookup table is required to return the proper offset
+
+The MAC itself is identical and requires no modifications to work.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Acked-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/bcm63xx/dev-enet.c | 65 ++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +-
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 94 +++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 43 ++++-
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c | 200 ++++++++++++--------
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h | 15 ++
+ 6 files changed, 329 insertions(+), 91 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -9,10 +9,44 @@
+ #include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/platform_device.h>
++#include <linux/export.h>
+ #include <bcm63xx_dev_enet.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_regs.h>
+
++#ifdef BCMCPU_RUNTIME_DETECT
++static const unsigned long bcm6348_regs_enetdmac[] = {
++ [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
++ [ENETDMAC_IR] = ENETDMAC_IR_REG,
++ [ENETDMAC_IRMASK] = ENETDMAC_IRMASK_REG,
++ [ENETDMAC_MAXBURST] = ENETDMAC_MAXBURST_REG,
++};
++
++static const unsigned long bcm6345_regs_enetdmac[] = {
++ [ENETDMAC_CHANCFG] = ENETDMA_6345_CHANCFG_REG,
++ [ENETDMAC_IR] = ENETDMA_6345_IR_REG,
++ [ENETDMAC_IRMASK] = ENETDMA_6345_IRMASK_REG,
++ [ENETDMAC_MAXBURST] = ENETDMA_6345_MAXBURST_REG,
++ [ENETDMAC_BUFALLOC] = ENETDMA_6345_BUFALLOC_REG,
++ [ENETDMAC_RSTART] = ENETDMA_6345_RSTART_REG,
++ [ENETDMAC_FC] = ENETDMA_6345_FC_REG,
++ [ENETDMAC_LEN] = ENETDMA_6345_LEN_REG,
++};
++
++const unsigned long *bcm63xx_regs_enetdmac;
++EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
++
++static __init void bcm63xx_enetdmac_regs_init(void)
++{
++ if (BCMCPU_IS_6345())
++ bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
++ else
++ bcm63xx_regs_enetdmac = bcm6348_regs_enetdmac;
++}
++#else
++static __init void bcm63xx_enetdmac_regs_init(void) { }
++#endif
++
+ static struct resource shared_res[] = {
+ {
+ .start = -1, /* filled at runtime */
+@@ -137,12 +171,19 @@ static int __init register_shared(void)
+ if (shared_device_registered)
+ return 0;
+
++ bcm63xx_enetdmac_regs_init();
++
+ shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
+ shared_res[0].end = shared_res[0].start;
+- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
++ if (BCMCPU_IS_6345())
++ shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
++ else
++ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
+
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ chan_count = 32;
++ else if (BCMCPU_IS_6345())
++ chan_count = 8;
+ else
+ chan_count = 16;
+
+@@ -172,7 +213,7 @@ int __init bcm63xx_enet_register(int uni
+ if (unit > 1)
+ return -ENODEV;
+
+- if (unit == 1 && BCMCPU_IS_6338())
++ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
+ return -ENODEV;
+
+ ret = register_shared();
+@@ -213,6 +254,21 @@ int __init bcm63xx_enet_register(int uni
+ dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
+ }
+
++ dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
++ dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
++ if (BCMCPU_IS_6345()) {
++ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
++ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
++ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
++ dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
++ dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
++ dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
++ dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
++ } else {
++ dpd->dma_has_sram = true;
++ dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
++ }
++
+ ret = platform_device_register(pdev);
+ if (ret)
+ return ret;
+@@ -246,6 +302,11 @@ bcm63xx_enetsw_register(const struct bcm
+ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ enetsw_pd.num_ports = ENETSW_PORTS_6368;
+
++ enetsw_pd.dma_has_sram = true;
++ enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
++ enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
++ enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
++
+ ret = platform_device_register(&bcm63xx_enetsw_device);
+ if (ret)
+ return ret;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -188,6 +188,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_RSET_SPI_SIZE 1804
+ #define RSET_ENET_SIZE 2048
+ #define RSET_ENETDMA_SIZE 256
++#define RSET_6345_ENETDMA_SIZE 64
+ #define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
+ #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
+ #define RSET_ENETSW_SIZE 65536
+@@ -363,7 +364,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_USBDMA_BASE (0xfffe2800)
+ #define BCM_6345_ENET0_BASE (0xfffe1800)
+ #define BCM_6345_ENETDMA_BASE (0xfffe2800)
+-#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
++#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
+ #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
+ #define BCM_6345_ENETSW_BASE (0xdeadbeef)
+ #define BCM_6345_PCMCIA_BASE (0xfffe2028)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -4,6 +4,8 @@
+ #include <linux/if_ether.h>
+ #include <linux/init.h>
+
++#include <bcm63xx_regs.h>
++
+ /*
+ * on board ethernet platform data
+ */
+@@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
+ int phy_id, int reg),
+ void (*mii_write)(struct net_device *dev,
+ int phy_id, int reg, int val));
++
++ /* DMA channel enable mask */
++ u32 dma_chan_en_mask;
++
++ /* DMA channel interrupt mask */
++ u32 dma_chan_int_mask;
++
++ /* DMA engine has internal SRAM */
++ bool dma_has_sram;
++
++ /* DMA channel register width */
++ unsigned int dma_chan_width;
++
++ /* DMA descriptor shift */
++ unsigned int dma_desc_shift;
+ };
+
+ /*
+@@ -63,6 +80,18 @@ struct bcm63xx_enetsw_platform_data {
+ char mac_addr[ETH_ALEN];
+ int num_ports;
+ struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
++
++ /* DMA channel enable mask */
++ u32 dma_chan_en_mask;
++
++ /* DMA channel interrupt mask */
++ u32 dma_chan_int_mask;
++
++ /* DMA channel register width */
++ unsigned int dma_chan_width;
++
++ /* DMA engine has internal SRAM */
++ bool dma_has_sram;
+ };
+
+ int __init bcm63xx_enet_register(int unit,
+@@ -70,4 +99,69 @@ int __init bcm63xx_enet_register(int uni
+
+ int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
+
++enum bcm63xx_regs_enetdmac {
++ ENETDMAC_CHANCFG,
++ ENETDMAC_IR,
++ ENETDMAC_IRMASK,
++ ENETDMAC_MAXBURST,
++ ENETDMAC_BUFALLOC,
++ ENETDMAC_RSTART,
++ ENETDMAC_FC,
++ ENETDMAC_LEN,
++};
++
++static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
++{
++#ifdef BCMCPU_RUNTIME_DETECT
++ extern const unsigned long *bcm63xx_regs_enetdmac;
++
++ return bcm63xx_regs_enetdmac[reg];
++#else
++#ifdef CONFIG_BCM63XX_CPU_6345
++ switch (reg) {
++ case ENETDMAC_CHANCFG:
++ return ENETDMA_6345_CHANCFG_REG;
++ case ENETDMAC_IR:
++ return ENETDMA_6345_IR_REG;
++ case ENETDMAC_IRMASK:
++ return ENETDMA_6345_IRMASK_REG;
++ case ENETDMAC_MAXBURST:
++ return ENETDMA_6345_MAXBURST_REG;
++ case ENETDMAC_BUFALLOC:
++ return ENETDMA_6345_BUFALLOC_REG;
++ case ENETDMAC_RSTART:
++ return ENETDMA_6345_RSTART_REG;
++ case ENETDMAC_FC:
++ return ENETDMA_6345_FC_REG;
++ case ENETDMAC_LEN:
++ return ENETDMA_6345_LEN_REG;
++ }
++#endif
++#if defined(CONFIG_BCM63XX_CPU_6328) || \
++ defined(CONFIG_BCM63XX_CPU_6338) || \
++ defined(CONFIG_BCM63XX_CPU_6348) || \
++ defined(CONFIG_BCM63XX_CPU_6358) || \
++ defined(CONFIG_BCM63XX_CPU_6362) || \
++ defined(CONFIG_BCM63XX_CPU_6368)
++ switch (reg) {
++ case ENETDMAC_CHANCFG:
++ return ENETDMAC_CHANCFG_REG;
++ case ENETDMAC_IR:
++ return ENETDMAC_IR_REG;
++ case ENETDMAC_IRMASK:
++ return ENETDMAC_IRMASK_REG;
++ case ENETDMAC_MAXBURST:
++ return ENETDMAC_MAXBURST_REG;
++ case ENETDMAC_BUFALLOC:
++ case ENETDMAC_RSTART:
++ case ENETDMAC_FC:
++ case ENETDMAC_LEN:
++ return 0;
++ }
++#endif
++#endif
++ return 0;
++}
++
++
+ #endif /* ! BCM63XX_DEV_ENET_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -770,6 +770,8 @@
+ /*************************************************************************
+ * _REG relative to RSET_ENETDMA
+ *************************************************************************/
++#define ENETDMA_CHAN_WIDTH 0x10
++#define ENETDMA_6345_CHAN_WIDTH 0x40
+
+ /* Controller Configuration Register */
+ #define ENETDMA_CFG_REG (0x0)
+@@ -825,31 +827,56 @@
+ /* State Ram Word 4 */
+ #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
+
++/* Broadcom 6345 ENET DMA definitions */
++#define ENETDMA_6345_CHANCFG_REG (0x00)
++
++#define ENETDMA_6345_MAXBURST_REG (0x40)
++
++#define ENETDMA_6345_RSTART_REG (0x08)
++
++#define ENETDMA_6345_LEN_REG (0x0C)
++
++#define ENETDMA_6345_IR_REG (0x14)
++
++#define ENETDMA_6345_IRMASK_REG (0x18)
++
++#define ENETDMA_6345_FC_REG (0x1C)
++
++#define ENETDMA_6345_BUFALLOC_REG (0x20)
++
++/* Shift down for EOP, SOP and WRAP bits */
++#define ENETDMA_6345_DESC_SHIFT (3)
+
+ /*************************************************************************
+ * _REG relative to RSET_ENETDMAC
+ *************************************************************************/
+
+ /* Channel Configuration register */
+-#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
++#define ENETDMAC_CHANCFG_REG (0x0)
+ #define ENETDMAC_CHANCFG_EN_SHIFT 0
+ #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
+ #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
+ #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
+ #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
+ #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
++#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
++#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
++#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
++#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
++#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
++#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
+
+ /* Interrupt Control/Status register */
+-#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
++#define ENETDMAC_IR_REG (0x4)
+ #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
+ #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
+ #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
+
+ /* Interrupt Mask register */
+-#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
++#define ENETDMAC_IRMASK_REG (0x8)
+
+ /* Maximum Burst Length */
+-#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
++#define ENETDMAC_MAXBURST_REG (0xc)
+
+
+ /*************************************************************************
+@@ -857,16 +884,16 @@
+ *************************************************************************/
+
+ /* Ring Start Address register */
+-#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
++#define ENETDMAS_RSTART_REG (0x0)
+
+ /* State Ram Word 2 */
+-#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
++#define ENETDMAS_SRAM2_REG (0x4)
+
+ /* State Ram Word 3 */
+-#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
++#define ENETDMAS_SRAM3_REG (0x8)
+
+ /* State Ram Word 4 */
+-#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
++#define ENETDMAS_SRAM4_REG (0xc)
+
+
+ /*************************************************************************
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -107,26 +107,28 @@ static inline void enet_dma_writel(struc
+ bcm_writel(val, bcm_enet_shared_base[0] + off);
+ }
+
+-static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
++static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
+ {
+- return bcm_readl(bcm_enet_shared_base[1] + off);
++ return bcm_readl(bcm_enet_shared_base[1] +
++ bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
+ }
+
+ static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
+- u32 val, u32 off)
++ u32 val, u32 off, int chan)
+ {
+- bcm_writel(val, bcm_enet_shared_base[1] + off);
++ bcm_writel(val, bcm_enet_shared_base[1] +
++ bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
+ }
+
+-static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
++static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
+ {
+- return bcm_readl(bcm_enet_shared_base[2] + off);
++ return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
+ }
+
+ static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
+- u32 val, u32 off)
++ u32 val, u32 off, int chan)
+ {
+- bcm_writel(val, bcm_enet_shared_base[2] + off);
++ bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
+ }
+
+ /*
+@@ -262,7 +264,7 @@ static int bcm_enet_refill_rx(struct net
+ len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
+ len_stat |= DMADESC_OWNER_MASK;
+ if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
+- len_stat |= DMADESC_WRAP_MASK;
++ len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
+ priv->rx_dirty_desc = 0;
+ } else {
+ priv->rx_dirty_desc++;
+@@ -273,7 +275,10 @@ static int bcm_enet_refill_rx(struct net
+ priv->rx_desc_count++;
+
+ /* tell dma engine we allocated one buffer */
+- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
++ if (priv->dma_has_sram)
++ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
++ else
++ enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
+ }
+
+ /* If rx ring is still empty, set a timer to try allocating
+@@ -349,7 +354,8 @@ static int bcm_enet_receive_queue(struct
+
+ /* if the packet does not have start of packet _and_
+ * end of packet flag set, then just recycle it */
+- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
++ if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
++ (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
+ dev->stats.rx_dropped++;
+ continue;
+ }
+@@ -410,8 +416,8 @@ static int bcm_enet_receive_queue(struct
+ bcm_enet_refill_rx(dev);
+
+ /* kick rx dma */
+- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
+- ENETDMAC_CHANCFG_REG(priv->rx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_en_mask,
++ ENETDMAC_CHANCFG, priv->rx_chan);
+ }
+
+ return processed;
+@@ -486,10 +492,10 @@ static int bcm_enet_poll(struct napi_str
+ dev = priv->net_dev;
+
+ /* ack interrupts */
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IR_REG(priv->rx_chan));
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IR_REG(priv->tx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IR, priv->rx_chan);
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IR, priv->tx_chan);
+
+ /* reclaim sent skb */
+ tx_work_done = bcm_enet_tx_reclaim(dev, 0);
+@@ -508,10 +514,10 @@ static int bcm_enet_poll(struct napi_str
+ napi_complete(napi);
+
+ /* restore rx/tx interrupt */
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IRMASK, priv->tx_chan);
+
+ return rx_work_done;
+ }
+@@ -554,8 +560,8 @@ static irqreturn_t bcm_enet_isr_dma(int
+ priv = netdev_priv(dev);
+
+ /* mask rx/tx interrupts */
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
+
+ napi_schedule(&priv->napi);
+
+@@ -616,14 +622,14 @@ static int bcm_enet_start_xmit(struct sk
+ DMA_TO_DEVICE);
+
+ len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
+- len_stat |= DMADESC_ESOP_MASK |
++ len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
+ DMADESC_APPEND_CRC |
+ DMADESC_OWNER_MASK;
+
+ priv->tx_curr_desc++;
+ if (priv->tx_curr_desc == priv->tx_ring_size) {
+ priv->tx_curr_desc = 0;
+- len_stat |= DMADESC_WRAP_MASK;
++ len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
+ }
+ priv->tx_desc_count--;
+
+@@ -634,8 +640,8 @@ static int bcm_enet_start_xmit(struct sk
+ wmb();
+
+ /* kick tx dma */
+- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
+- ENETDMAC_CHANCFG_REG(priv->tx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_en_mask,
++ ENETDMAC_CHANCFG, priv->tx_chan);
+
+ /* stop queue if no more desc available */
+ if (!priv->tx_desc_count)
+@@ -763,6 +769,9 @@ static void bcm_enet_set_flow(struct bcm
+ val &= ~ENET_RXCFG_ENFLOW_MASK;
+ enet_writel(priv, val, ENET_RXCFG_REG);
+
++ if (!priv->dma_has_sram)
++ return;
++
+ /* tx flow control (pause frame generation) */
+ val = enet_dma_readl(priv, ENETDMA_CFG_REG);
+ if (tx_en)
+@@ -910,8 +919,8 @@ static int bcm_enet_open(struct net_devi
+
+ /* mask all interrupts and request them */
+ enet_writel(priv, 0, ENET_IRMASK_REG);
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
+
+ ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
+ if (ret)
+@@ -988,8 +997,12 @@ static int bcm_enet_open(struct net_devi
+ priv->rx_curr_desc = 0;
+
+ /* initialize flow control buffer allocation */
+- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
+- ENETDMA_BUFALLOC_REG(priv->rx_chan));
++ if (priv->dma_has_sram)
++ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
++ ENETDMA_BUFALLOC_REG(priv->rx_chan));
++ else
++ enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
++ ENETDMAC_BUFALLOC, priv->rx_chan);
+
+ if (bcm_enet_refill_rx(dev)) {
+ dev_err(kdev, "cannot allocate rx skb queue\n");
+@@ -998,18 +1011,30 @@ static int bcm_enet_open(struct net_devi
+ }
+
+ /* write rx & tx ring addresses */
+- enet_dmas_writel(priv, priv->rx_desc_dma,
+- ENETDMAS_RSTART_REG(priv->rx_chan));
+- enet_dmas_writel(priv, priv->tx_desc_dma,
+- ENETDMAS_RSTART_REG(priv->tx_chan));
++ if (priv->dma_has_sram) {
++ enet_dmas_writel(priv, priv->rx_desc_dma,
++ ENETDMAS_RSTART_REG, priv->rx_chan);
++ enet_dmas_writel(priv, priv->tx_desc_dma,
++ ENETDMAS_RSTART_REG, priv->tx_chan);
++ } else {
++ enet_dmac_writel(priv, priv->rx_desc_dma,
++ ENETDMAC_RSTART, priv->rx_chan);
++ enet_dmac_writel(priv, priv->tx_desc_dma,
++ ENETDMAC_RSTART, priv->tx_chan);
++ }
+
+ /* clear remaining state ram for rx & tx channel */
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
++ if (priv->dma_has_sram) {
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
++ } else {
++ enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
++ enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
++ }
+
+ /* set max rx/tx length */
+ enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
+@@ -1017,18 +1042,24 @@ static int bcm_enet_open(struct net_devi
+
+ /* set dma maximum burst len */
+ enet_dmac_writel(priv, priv->dma_maxburst,
+- ENETDMAC_MAXBURST_REG(priv->rx_chan));
++ ENETDMAC_MAXBURST, priv->rx_chan);
+ enet_dmac_writel(priv, priv->dma_maxburst,
+- ENETDMAC_MAXBURST_REG(priv->tx_chan));
++ ENETDMAC_MAXBURST, priv->tx_chan);
+
+ /* set correct transmit fifo watermark */
+ enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
+
+ /* set flow control low/high threshold to 1/3 / 2/3 */
+- val = priv->rx_ring_size / 3;
+- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
+- val = (priv->rx_ring_size * 2) / 3;
+- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
++ if (priv->dma_has_sram) {
++ val = priv->rx_ring_size / 3;
++ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
++ val = (priv->rx_ring_size * 2) / 3;
++ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
++ } else {
++ enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
++ enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
++ enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
++ }
+
+ /* all set, enable mac and interrupts, start dma engine and
+ * kick rx dma channel */
+@@ -1037,26 +1068,26 @@ static int bcm_enet_open(struct net_devi
+ val |= ENET_CTL_ENABLE_MASK;
+ enet_writel(priv, val, ENET_CTL_REG);
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
+- ENETDMAC_CHANCFG_REG(priv->rx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_en_mask,
++ ENETDMAC_CHANCFG, priv->rx_chan);
+
+ /* watch "mib counters about to overflow" interrupt */
+ enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
+ enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
+
+ /* watch "packet transferred" interrupt in rx and tx */
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IR_REG(priv->rx_chan));
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IR_REG(priv->tx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IR, priv->rx_chan);
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IR, priv->tx_chan);
+
+ /* make sure we enable napi before rx interrupt */
+ napi_enable(&priv->napi);
+
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, priv->dma_chan_int_mask,
++ ENETDMAC_IRMASK, priv->tx_chan);
+
+ if (priv->has_phy)
+ phy_start(priv->phydev);
+@@ -1136,13 +1167,13 @@ static void bcm_enet_disable_dma(struct
+ {
+ int limit;
+
+- enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
+
+ limit = 1000;
+ do {
+ u32 val;
+
+- val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
++ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
+ if (!(val & ENETDMAC_CHANCFG_EN_MASK))
+ break;
+ udelay(1);
+@@ -1169,8 +1200,8 @@ static int bcm_enet_stop(struct net_devi
+
+ /* mask all interrupts */
+ enet_writel(priv, 0, ENET_IRMASK_REG);
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
+
+ /* make sure no mib update is scheduled */
+ cancel_work_sync(&priv->mib_update_task);
+@@ -1784,6 +1815,11 @@ static int bcm_enet_probe(struct platfor
+ priv->pause_tx = pd->pause_tx;
+ priv->force_duplex_full = pd->force_duplex_full;
+ priv->force_speed_100 = pd->force_speed_100;
++ priv->dma_chan_en_mask = pd->dma_chan_en_mask;
++ priv->dma_chan_int_mask = pd->dma_chan_int_mask;
++ priv->dma_chan_width = pd->dma_chan_width;
++ priv->dma_has_sram = pd->dma_has_sram;
++ priv->dma_desc_shift = pd->dma_desc_shift;
+ }
+
+ if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
+@@ -2121,8 +2157,8 @@ static int bcm_enetsw_open(struct net_de
+ kdev = &priv->pdev->dev;
+
+ /* mask all interrupts and request them */
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
+
+ ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
+ IRQF_DISABLED, dev->name, dev);
+@@ -2234,23 +2270,23 @@ static int bcm_enetsw_open(struct net_de
+
+ /* write rx & tx ring addresses */
+ enet_dmas_writel(priv, priv->rx_desc_dma,
+- ENETDMAS_RSTART_REG(priv->rx_chan));
++ ENETDMAS_RSTART_REG, priv->rx_chan);
+ enet_dmas_writel(priv, priv->tx_desc_dma,
+- ENETDMAS_RSTART_REG(priv->tx_chan));
++ ENETDMAS_RSTART_REG, priv->tx_chan);
+
+ /* clear remaining state ram for rx & tx channel */
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
+- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
++ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
+
+ /* set dma maximum burst len */
+ enet_dmac_writel(priv, priv->dma_maxburst,
+- ENETDMAC_MAXBURST_REG(priv->rx_chan));
++ ENETDMAC_MAXBURST, priv->rx_chan);
+ enet_dmac_writel(priv, priv->dma_maxburst,
+- ENETDMAC_MAXBURST_REG(priv->tx_chan));
++ ENETDMAC_MAXBURST, priv->tx_chan);
+
+ /* set flow control low/high threshold to 1/3 / 2/3 */
+ val = priv->rx_ring_size / 3;
+@@ -2264,21 +2300,21 @@ static int bcm_enetsw_open(struct net_de
+ wmb();
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
+- ENETDMAC_CHANCFG_REG(priv->rx_chan));
++ ENETDMAC_CHANCFG, priv->rx_chan);
+
+ /* watch "packet transferred" interrupt in rx and tx */
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IR_REG(priv->rx_chan));
++ ENETDMAC_IR, priv->rx_chan);
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IR_REG(priv->tx_chan));
++ ENETDMAC_IR, priv->tx_chan);
+
+ /* make sure we enable napi before rx interrupt */
+ napi_enable(&priv->napi);
+
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IRMASK_REG(priv->rx_chan));
++ ENETDMAC_IRMASK, priv->rx_chan);
+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
+- ENETDMAC_IRMASK_REG(priv->tx_chan));
++ ENETDMAC_IRMASK, priv->tx_chan);
+
+ netif_carrier_on(dev);
+ netif_start_queue(dev);
+@@ -2380,8 +2416,8 @@ static int bcm_enetsw_stop(struct net_de
+ del_timer_sync(&priv->rx_timeout);
+
+ /* mask all interrupts */
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
+- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
++ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
+
+ /* disable dma & mac */
+ bcm_enet_disable_dma(priv, priv->tx_chan);
+@@ -2715,6 +2751,10 @@ static int bcm_enetsw_probe(struct platf
+ memcpy(priv->used_ports, pd->used_ports,
+ sizeof(pd->used_ports));
+ priv->num_ports = pd->num_ports;
++ priv->dma_has_sram = pd->dma_has_sram;
++ priv->dma_chan_en_mask = pd->dma_chan_en_mask;
++ priv->dma_chan_int_mask = pd->dma_chan_int_mask;
++ priv->dma_chan_width = pd->dma_chan_width;
+ }
+
+ ret = compute_hw_mtu(priv, dev->mtu);
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
+@@ -339,6 +339,21 @@ struct bcm_enet_priv {
+ /* used to poll switch port state */
+ struct timer_list swphy_poll;
+ spinlock_t enetsw_mdio_lock;
++
++ /* dma channel enable mask */
++ u32 dma_chan_en_mask;
++
++ /* dma channel interrupt mask */
++ u32 dma_chan_int_mask;
++
++ /* DMA engine has internal SRAM */
++ bool dma_has_sram;
++
++ /* dma channel width */
++ unsigned int dma_chan_width;
++
++ /* dma descriptor shift value */
++ unsigned int dma_desc_shift;
+ };
+
+
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
-@@ -1,37 +1,43 @@
- menu "CPU support"
- depends on BCM63XX
+@@ -5,9 +5,16 @@ config BCM63XX_CPU_3368
+ bool "support 3368 CPU"
+ select HW_HAS_PCI
+config BCM63XX_OHCI
+ bool
config BCM63XX_CPU_6338
bool "support 6338 CPU"
- select HW_HAS_PCI
-- select USB_ARCH_HAS_OHCI
-- select USB_OHCI_BIG_ENDIAN_DESC
-- select USB_OHCI_BIG_ENDIAN_MMIO
-
- config BCM63XX_CPU_6345
- bool "support 6345 CPU"
-- select USB_OHCI_BIG_ENDIAN_DESC
-- select USB_OHCI_BIG_ENDIAN_MMIO
-
+@@ -19,18 +26,22 @@ config BCM63XX_CPU_6345
config BCM63XX_CPU_6348
bool "support 6348 CPU"
select HW_HAS_PCI
#include <bcm63xx_dev_usb_usbd.h>
#include <board_bcm963xx.h>
-@@ -848,6 +849,9 @@ int __init board_register_devices(void)
+@@ -897,6 +898,9 @@ int __init board_register_devices(void)
if (board.has_usbd)
bcm63xx_usbd_register(&board.usbd);
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
-@@ -7,10 +7,17 @@ config BCM63XX_OHCI
+@@ -11,10 +11,17 @@ config BCM63XX_OHCI
select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD
select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD
config BCM63XX_CPU_6338
bool "support 6338 CPU"
-@@ -28,16 +35,19 @@ config BCM63XX_CPU_6358
+@@ -32,16 +39,19 @@ config BCM63XX_CPU_6358
bool "support 6358 CPU"
select HW_HAS_PCI
select BCM63XX_OHCI
#include <bcm63xx_dev_usb_ohci.h>
#include <bcm63xx_dev_usb_usbd.h>
#include <board_bcm963xx.h>
-@@ -849,6 +850,9 @@ int __init board_register_devices(void)
+@@ -898,6 +899,9 @@ int __init board_register_devices(void)
if (board.has_usbd)
bcm63xx_usbd_register(&board.usbd);
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
-@@ -32,6 +34,9 @@
+@@ -36,6 +38,9 @@
- #define PFX "board_bcm963xx: "
+ #define HCS_OFFSET_128K 0x20000
+#define BCM963XX_KEYS_POLL_INTERVAL 20
+#define BCM963XX_KEYS_DEBOUNCE_INTERVAL (BCM963XX_KEYS_POLL_INTERVAL * 3)
static struct board_info board;
/*
-@@ -343,6 +348,16 @@ static struct board_info __initdata boar
+@@ -379,6 +384,16 @@ static struct board_info __initdata boar
.active_low = 1,
},
},
};
static struct board_info __initdata board_96348gw = {
-@@ -401,6 +416,16 @@ static struct board_info __initdata boar
+@@ -437,6 +452,16 @@ static struct board_info __initdata boar
.active_low = 1,
},
},
};
static struct board_info __initdata board_FAST2404 = {
-@@ -825,11 +850,23 @@ static struct platform_device bcm63xx_gp
+@@ -870,11 +895,23 @@ static struct platform_device bcm63xx_gp
.dev.platform_data = &bcm63xx_led_data,
};
if (board.has_uart0)
bcm63xx_uart_register(0);
-@@ -881,5 +918,16 @@ int __init board_register_devices(void)
-
- platform_device_register(&bcm63xx_gpio_leds);
+@@ -934,5 +971,16 @@ int __init board_register_devices(void)
+ gpio_request_one(board.ephy_reset_gpio,
+ board.ephy_reset_gpio_flags, "ephy-reset");
+ /* count number of BUTTONs defined by this device */
+ while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc)
#include <linux/leds.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_usb_usbd.h>
-@@ -45,6 +46,9 @@ struct board_info {
-
+@@ -48,6 +49,9 @@ struct board_info {
/* GPIO LEDs */
struct gpio_led leds[5];
-+
+
+ /* Buttons */
+ struct gpio_keys_button buttons[4];
- };
++
+ /* External PHY reset GPIO */
+ unsigned int ephy_reset_gpio;
- #endif /* ! BOARD_BCM963XX_H_ */
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -866,6 +866,7 @@ static struct platform_device bcm63xx_gp
+@@ -911,6 +911,7 @@ static struct platform_device bcm63xx_gp
int __init board_register_devices(void)
{
int button_count = 0;
if (board.has_uart0)
bcm63xx_uart_register(0);
-@@ -913,10 +914,16 @@ int __init board_register_devices(void)
+@@ -962,10 +963,16 @@ int __init board_register_devices(void)
bcm63xx_flash_register();
+ platform_device_register(&bcm63xx_gpio_leds);
+ }
- /* count number of BUTTONs defined by this device */
- while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc)
+ if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)
+ gpio_request_one(board.ephy_reset_gpio,
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
-@@ -45,7 +45,7 @@ struct board_info {
+@@ -47,7 +47,7 @@ struct board_info {
struct bcm63xx_dsp_platform_data dsp;
/* GPIO LEDs */
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -912,6 +912,9 @@ int __init board_register_devices(void)
+@@ -961,6 +961,9 @@ int __init board_register_devices(void)
bcm63xx_spi_register();
/* count number of LEDs defined by this device */
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
-@@ -49,6 +49,10 @@ struct board_info {
+@@ -57,6 +57,10 @@ struct board_info {
- /* Buttons */
- struct gpio_keys_button buttons[4];
+ /* External PHY reset GPIO flags from gpio.h */
+ unsigned long ephy_reset_gpio_flags;
+
+ /* Additional platform devices */
+ struct platform_device **devs;
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
-@@ -915,6 +916,9 @@ int __init board_register_devices(void)
+@@ -964,6 +965,9 @@ int __init board_register_devices(void)
if (board.num_devs)
platform_add_devices(board.devs, board.num_devs);
/* count number of LEDs defined by this device */
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
-@@ -53,6 +53,10 @@ struct board_info {
+@@ -61,6 +61,10 @@ struct board_info {
/* Additional platform devices */
struct platform_device **devs;
unsigned int num_devs;
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -33,11 +33,16 @@
- #include <bcm63xx_dev_usb_usbd.h>
+@@ -34,6 +34,7 @@
#include <board_bcm963xx.h>
+ #include <uapi/linux/bcm933xx_hcs.h>
+#include <uapi/linux/bcm963xx_tag.h>
-+
+
#define PFX "board_bcm963xx: "
+@@ -42,6 +43,9 @@
#define BCM963XX_KEYS_POLL_INTERVAL 20
#define BCM963XX_KEYS_DEBOUNCE_INTERVAL (BCM963XX_KEYS_POLL_INTERVAL * 3)
static struct board_info board;
/*
-@@ -742,6 +747,30 @@ const char *board_get_name(void)
+@@ -781,6 +785,30 @@ const char *board_get_name(void)
return board.name;
}
/*
* early init callback, read nvram data from flash and checksum it
*/
-@@ -775,6 +804,11 @@ void __init board_prom_init(void)
-
- bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
-
-+ if (strcmp(cfe_version, "unknown") != 0) {
-+ /* cfe present */
-+ boardid_fixup(boot_addr);
-+ }
-+
- board_name = bcm63xx_nvram_get_name();
+@@ -819,6 +847,10 @@ void __init board_prom_init(void)
+ hcs = (struct bcm_hcs *)boot_addr;
+ board_name = hcs->filename;
+ } else {
++ if (strcmp(cfe_version, "unknown") != 0) {
++ /* cfe present */
++ boardid_fixup(boot_addr);
++ }
+ board_name = bcm63xx_nvram_get_name();
+ }
/* find board by name */
- for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
+++ /dev/null
-From c110865541e2d3782c412af9d48c016de5a64d9c Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jonas.gorski@gmail.com>
-Date: Tue, 14 Jun 2011 21:14:39 +0200
-Subject: [PATCH 42/79] MIPS: BCM63XX: allow second UART on BCM6328
-
-Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
----
- arch/mips/bcm63xx/dev-uart.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/mips/bcm63xx/dev-uart.c
-+++ b/arch/mips/bcm63xx/dev-uart.c
-@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
- if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
- return -ENODEV;
-
-- if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
-+ if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
-+ !BCMCPU_IS_6368())
- return -ENODEV;
-
- if (id == 0) {
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -131,6 +131,7 @@ enum bcm63xx_regs_set {
+@@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
RSET_UART1,
RSET_GPIO,
RSET_SPI,
RSET_UDC0,
RSET_OHCI0,
RSET_OHCI_PRIV,
-@@ -176,6 +177,7 @@ enum bcm63xx_regs_set {
- #define RSET_ENETDMA_SIZE 2048
+@@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
+ #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
#define RSET_ENETSW_SIZE 65536
#define RSET_UART_SIZE 24
+#define RSET_HSSPI_SIZE 1536
#define RSET_UDC_SIZE 256
#define RSET_OHCI_SIZE 256
#define RSET_EHCI_SIZE 256
-@@ -201,6 +203,7 @@ enum bcm63xx_regs_set {
+@@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
#define BCM_6328_UART1_BASE (0xb0000120)
#define BCM_6328_GPIO_BASE (0xb0000080)
#define BCM_6328_SPI_BASE (0xdeadbeef)
#define BCM_6328_UDC0_BASE (0xdeadbeef)
#define BCM_6328_USBDMA_BASE (0xb000c000)
#define BCM_6328_OHCI0_BASE (0xb0002600)
-@@ -247,6 +250,7 @@ enum bcm63xx_regs_set {
+@@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
#define BCM_6338_UART1_BASE (0xdeadbeef)
#define BCM_6338_GPIO_BASE (0xfffe0400)
#define BCM_6338_SPI_BASE (0xfffe0c00)
#define BCM_6338_UDC0_BASE (0xdeadbeef)
#define BCM_6338_USBDMA_BASE (0xfffe2400)
#define BCM_6338_OHCI0_BASE (0xdeadbeef)
-@@ -294,6 +298,7 @@ enum bcm63xx_regs_set {
+@@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_UART1_BASE (0xdeadbeef)
#define BCM_6345_GPIO_BASE (0xfffe0400)
#define BCM_6345_SPI_BASE (0xdeadbeef)
#define BCM_6345_UDC0_BASE (0xdeadbeef)
#define BCM_6345_USBDMA_BASE (0xfffe2800)
#define BCM_6345_ENET0_BASE (0xfffe1800)
-@@ -340,6 +345,7 @@ enum bcm63xx_regs_set {
+@@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
#define BCM_6348_UART1_BASE (0xdeadbeef)
#define BCM_6348_GPIO_BASE (0xfffe0400)
#define BCM_6348_SPI_BASE (0xfffe0c00)
#define BCM_6348_UDC0_BASE (0xfffe1000)
#define BCM_6348_USBDMA_BASE (0xdeadbeef)
#define BCM_6348_OHCI0_BASE (0xfffe1b00)
-@@ -385,6 +391,7 @@ enum bcm63xx_regs_set {
+@@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
#define BCM_6358_UART1_BASE (0xfffe0120)
#define BCM_6358_GPIO_BASE (0xfffe0080)
#define BCM_6358_SPI_BASE (0xfffe0800)
#define BCM_6358_UDC0_BASE (0xfffe0800)
#define BCM_6358_USBDMA_BASE (0xdeadbeef)
#define BCM_6358_OHCI0_BASE (0xfffe1400)
-@@ -487,6 +494,7 @@ enum bcm63xx_regs_set {
+@@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
#define BCM_6368_UART1_BASE (0xb0000120)
#define BCM_6368_GPIO_BASE (0xb0000080)
#define BCM_6368_SPI_BASE (0xb0000800)
#define BCM_6368_UDC0_BASE (0xdeadbeef)
#define BCM_6368_USBDMA_BASE (0xb0004800)
#define BCM_6368_OHCI0_BASE (0xb0001600)
-@@ -538,6 +546,7 @@ extern const unsigned long *bcm63xx_regs
+@@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs
__GEN_RSET_BASE(__cpu, UART1) \
__GEN_RSET_BASE(__cpu, GPIO) \
__GEN_RSET_BASE(__cpu, SPI) \
__GEN_RSET_BASE(__cpu, UDC0) \
__GEN_RSET_BASE(__cpu, OHCI0) \
__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
-@@ -581,6 +590,7 @@ extern const unsigned long *bcm63xx_regs
+@@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs
[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
-@@ -658,6 +668,7 @@ enum bcm63xx_irq {
+@@ -727,6 +737,7 @@ enum bcm63xx_irq {
IRQ_ENET0,
IRQ_ENET1,
IRQ_ENET_PHY,
IRQ_OHCI0,
IRQ_EHCI0,
IRQ_USBD,
-@@ -700,6 +711,7 @@ enum bcm63xx_irq {
+@@ -815,6 +826,7 @@ enum bcm63xx_irq {
#define BCM_6328_ENET0_IRQ 0
#define BCM_6328_ENET1_IRQ 0
#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
-@@ -745,6 +757,7 @@ enum bcm63xx_irq {
+@@ -860,6 +872,7 @@ enum bcm63xx_irq {
#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6338_ENET1_IRQ 0
#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6338_OHCI0_IRQ 0
#define BCM_6338_EHCI0_IRQ 0
#define BCM_6338_USBD_IRQ 0
-@@ -783,6 +796,7 @@ enum bcm63xx_irq {
+@@ -898,6 +911,7 @@ enum bcm63xx_irq {
#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6345_ENET1_IRQ 0
#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6345_OHCI0_IRQ 0
#define BCM_6345_EHCI0_IRQ 0
#define BCM_6345_USBD_IRQ 0
-@@ -821,6 +835,7 @@ enum bcm63xx_irq {
+@@ -936,6 +950,7 @@ enum bcm63xx_irq {
#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
#define BCM_6348_EHCI0_IRQ 0
#define BCM_6348_USBD_IRQ 0
-@@ -859,6 +874,7 @@ enum bcm63xx_irq {
+@@ -974,6 +989,7 @@ enum bcm63xx_irq {
#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
#define BCM_6358_USBD_IRQ 0
-@@ -971,6 +987,7 @@ enum bcm63xx_irq {
+@@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
#define BCM_6368_ENET0_IRQ 0
#define BCM_6368_ENET1_IRQ 0
#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
-@@ -1018,6 +1035,7 @@ extern const int *bcm63xx_irqs;
+@@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
[IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1434,4 +1434,51 @@
-
- #define PCIE_DEVICE_OFFSET 0x8000
+@@ -1561,4 +1561,51 @@
+ #define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
+ #define OTP_6328_REG3_TP1_DISABLED BIT(9)
+/*************************************************************************
+ * _REG relative to RSET_HSSPI
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -112,28 +112,28 @@ static struct board_info __initdata boar
+@@ -147,28 +147,28 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 1,
.active_low = 1,
}
-@@ -153,28 +153,28 @@ static struct board_info __initdata boar
+@@ -188,28 +188,28 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 1,
.active_low = 1,
},
-@@ -213,29 +213,29 @@ static struct board_info __initdata boar
+@@ -248,29 +248,29 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 1,
.active_low = 1,
},
-@@ -274,28 +274,28 @@ static struct board_info __initdata boar
+@@ -309,28 +309,28 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 1,
.active_low = 1,
},
-@@ -328,28 +328,28 @@ static struct board_info __initdata boar
+@@ -363,28 +363,28 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 1,
.active_low = 1,
},
-@@ -396,28 +396,28 @@ static struct board_info __initdata boar
+@@ -431,28 +431,28 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 1,
.active_low = 1,
},
-@@ -549,27 +549,27 @@ static struct board_info __initdata boar
+@@ -584,27 +584,27 @@ static struct board_info __initdata boar
.leds = {
{
.gpio = 5,
},
},
-@@ -601,22 +601,22 @@ static struct board_info __initdata boar
+@@ -636,22 +636,22 @@ static struct board_info __initdata boar
.leds = {
{
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -798,6 +798,8 @@ void __init board_prom_init(void)
+@@ -837,6 +837,8 @@ void __init board_prom_init(void)
if (!memcmp(cfe, "cfe-v", 5))
snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
+++ /dev/null
-From 10ea7fd6b854c3ecf745d053beba10c7e00c33c9 Mon Sep 17 00:00:00 2001
-From: Kevin Cernekee <cernekee@gmail.com>
-Date: Sat, 9 Jul 2011 12:15:06 -0700
-Subject: [PATCH 01/13] MIPS: BCM63XX: Add SMP support to prom.c
-
-This involves two changes to the BSP code:
-
-1) register_smp_ops() for BMIPS SMP
-
-2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with
-the special interrupt vector (IV). Move it to 0x8000_0380 at boot time,
-to resolve the conflict.
-
-Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
-[jogo@openwrt: move smp ops registration below #ifdef guard, don't enable
- smp for 6328/6358]
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/prom.c | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
---- a/arch/mips/bcm63xx/prom.c
-+++ b/arch/mips/bcm63xx/prom.c
-@@ -8,7 +8,11 @@
-
- #include <linux/init.h>
- #include <linux/bootmem.h>
-+#include <linux/smp.h>
- #include <asm/bootinfo.h>
-+#include <asm/bmips.h>
-+#include <asm/smp-ops.h>
-+#include <asm/mipsregs.h>
- #include <bcm63xx_board.h>
- #include <bcm63xx_cpu.h>
- #include <bcm63xx_io.h>
-@@ -52,6 +56,35 @@ void __init prom_init(void)
-
- /* do low level board init */
- board_prom_init();
-+
-+#if defined(CONFIG_CPU_BMIPS4350) && defined(CONFIG_SMP)
-+ /* set up SMP */
-+ register_smp_ops(&bmips_smp_ops);
-+
-+ /*
-+ * BCM6328 does not have its second CPU enabled, while BCM6358
-+ * needs special handling for its shared TLB, so disable SMP for now.
-+ */
-+ if (BCMCPU_IS_6328() || BCMCPU_IS_6358()) {
-+ bmips_smp_enabled = 0;
-+ return;
-+ }
-+
-+ /*
-+ * The bootloader has set up the CPU1 reset vector at 0xa000_0200.
-+ * This conflicts with the special interrupt vector (IV).
-+ * The bootloader has also set up CPU1 to respond to the wrong
-+ * IPI interrupt.
-+ * Here we will start up CPU1 in the background and ask it to
-+ * reconfigure itself then go back to sleep.
-+ */
-+ memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
-+ __sync();
-+ set_c0_cause(C_SW0);
-+ cpumask_set_cpu(1, &bmips_booted_mask);
-+
-+ /* FIXME: we really should have some sort of hazard barrier here */
-+#endif
- }
-
- void __init prom_free_prom_memory(void)
+++ /dev/null
-From 8e0bd819cc0f8815cad99feea98664172c0b1fe4 Mon Sep 17 00:00:00 2001
-From: Kevin Cernekee <cernekee@gmail.com>
-Date: Mon, 31 Oct 2011 11:52:10 -0700
-Subject: [PATCH 02/13] MIPS: BCM63XX: Handle SW IRQs 0-1
-
-MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI)
-on BMIPS SMP. Make the board support code aware of them.
-
-Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
-[jogo@openwrt.org: move sw irqs behind timer irq]
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/irq.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/mips/bcm63xx/irq.c
-+++ b/arch/mips/bcm63xx/irq.c
-@@ -294,6 +294,10 @@ asmlinkage void plat_irq_dispatch(void)
-
- if (cause & CAUSEF_IP7)
- do_IRQ(7);
-+ if (cause & CAUSEF_IP0)
-+ do_IRQ(0);
-+ if (cause & CAUSEF_IP1)
-+ do_IRQ(1);
- if (cause & CAUSEF_IP2)
- dispatch_internal();
- if (!is_ext_irq_cascaded) {
+++ /dev/null
-From 1923ce1435a5e89f9550e8c95db37a3ef1f92665 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Sun, 21 Apr 2013 14:44:00 +0200
-Subject: [PATCH 03/13] MIPS: BCM63XX: select SYS_HAS_CPU_BMIPS4350 for
- supported SoCs
-
-BCM6338, BCM6345 and BCM6348 have a BMIPS3300, everything following
-has a BMIPS4350.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -129,6 +129,7 @@ config BCM63XX
- select DMA_NONCOHERENT
- select IRQ_CPU
- select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_HAS_EARLY_PRINTK
-From bb2774da9598f3ea38099d3dcf753b585824a011 Mon Sep 17 00:00:00 2001
+From 3bc62bd6e8c8a37d64cb797d24955711e98de15c Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 21 Mar 2013 17:05:15 +0100
-Subject: [PATCH 04/13] MIPS: BCM63XX: rename __dispatch_internal to
+Subject: [PATCH 05/14] MIPS: BCM63XX: rename __dispatch_internal to
__dispatch_internal_32
Make it follow the same naming convention as the other functions.
static void __dispatch_internal_64(void) __maybe_unused;
static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
-@@ -106,7 +106,7 @@ static void __internal_irq_unmask_64(uns
+@@ -117,7 +117,7 @@ static void __internal_irq_unmask_64(uns
#endif
#if irq_bits == 32
#define internal_irq_mask __internal_irq_mask_32
#define internal_irq_unmask __internal_irq_unmask_32
#else
-@@ -207,7 +207,7 @@ static void bcm63xx_init_irq(void)
+@@ -225,7 +225,7 @@ static void bcm63xx_init_irq(void)
}
if (irq_bits == 32) {
internal_irq_mask = __internal_irq_mask_32;
internal_irq_unmask = __internal_irq_unmask_32;
} else {
-@@ -240,7 +240,7 @@ static inline void handle_internal(int i
+@@ -258,7 +258,7 @@ static inline void handle_internal(int i
* will resume the loop where it ended the last time we left this
* function.
*/
-From 661e02b8e2b9a4b48a809bc82dfe8f7b20ca750f Mon Sep 17 00:00:00 2001
+From 7447daa9a0768db157bbb64585f5411389712d59 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 18 Apr 2013 21:14:49 +0200
-Subject: [PATCH 05/13] MIPS: BCM63XX: replace irq dispatch code with a
+Subject: [PATCH 06/14] MIPS: BCM63XX: replace irq dispatch code with a
generic version
The generic version uses a variable length of u32 registers of u32/u64.
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
-@@ -240,47 +240,65 @@ static inline void handle_internal(int i
+@@ -258,47 +258,65 @@ static inline void handle_internal(int i
* will resume the loop where it ended the last time we left this
* function.
*/
asmlinkage void plat_irq_dispatch(void)
{
-@@ -317,42 +335,6 @@ asmlinkage void plat_irq_dispatch(void)
+@@ -335,42 +353,6 @@ asmlinkage void plat_irq_dispatch(void)
* internal IRQs operations: only mask/unmask on PERF irq mask
* register.
*/
-From 6ec70ebfccd31ae3668d99b5703e5c9ce38384b4 Mon Sep 17 00:00:00 2001
+From 46442450ffb95a869894b0dfd1e5b4f973d4b4ee Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 00:24:06 +0200
-Subject: [PATCH 06/13] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
+Subject: [PATCH 07/14] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
-For SMP affinity support we need to discrimnate between the registers
-for both CPUs.
+The SMP capable irq controllers have two interupt output pins which are
+controlled through separate registers.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 78 ++++++++++-----------
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++---
- 2 files changed, 47 insertions(+), 47 deletions(-)
+ arch/mips/bcm63xx/irq.c | 86 ++++++++++-----------
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 ++--
+ 2 files changed, 51 insertions(+), 51 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -28,8 +28,8 @@ static void __internal_irq_unmask_64(uns
#ifndef BCMCPU_RUNTIME_DETECT
+ #ifdef CONFIG_BCM63XX_CPU_3368
+-#define irq_stat_reg PERF_IRQSTAT_3368_REG
+-#define irq_mask_reg PERF_IRQMASK_3368_REG
++#define irq_stat_reg0 PERF_IRQSTAT_3368_REG
++#define irq_mask_reg0 PERF_IRQMASK_3368_REG
+ #define irq_bits 32
+ #define is_ext_irq_cascaded 0
+ #define ext_irq_start 0
+@@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2 0
+ #endif
#ifdef CONFIG_BCM63XX_CPU_6328
-#define irq_stat_reg PERF_IRQSTAT_6328_REG
-#define irq_mask_reg PERF_IRQMASK_6328_REG
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
+@@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6338
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
-@@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
+@@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
-@@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
+@@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
-@@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
+@@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
#define irq_bits 32
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
+@@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6362
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
+@@ -105,8 +105,8 @@ static void __internal_irq_unmask_64(uns
#define ext_irq_cfg_reg2 0
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -115,15 +115,15 @@ static void __internal_irq_unmask_64(uns
+@@ -126,15 +126,15 @@ static void __internal_irq_unmask_64(uns
#define internal_irq_unmask __internal_irq_unmask_64
#endif
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
-@@ -136,13 +136,13 @@ static void bcm63xx_init_irq(void)
+@@ -147,20 +147,20 @@ static void bcm63xx_init_irq(void)
{
int irq_bits;
+ irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
+ case BCM3368_CPU_ID:
+- irq_stat_addr += PERF_IRQSTAT_3368_REG;
+- irq_mask_addr += PERF_IRQMASK_3368_REG;
++ irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
++ irq_mask_addr0 += PERF_IRQMASK_3368_REG;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
+ break;
case BCM6328_CPU_ID:
- irq_stat_addr += PERF_IRQSTAT_6328_REG;
- irq_mask_addr += PERF_IRQMASK_6328_REG;
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
-@@ -151,29 +151,29 @@ static void bcm63xx_init_irq(void)
+@@ -169,29 +169,29 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
break;
case BCM6338_CPU_ID:
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
-@@ -182,8 +182,8 @@ static void bcm63xx_init_irq(void)
+@@ -200,8 +200,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
break;
case BCM6362_CPU_ID:
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
-@@ -192,8 +192,8 @@ static void bcm63xx_init_irq(void)
+@@ -210,8 +210,8 @@ static void bcm63xx_init_irq(void)
ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
break;
case BCM6368_CPU_ID:
irq_bits = 64;
ext_irq_count = 6;
is_ext_irq_cascaded = 1;
-@@ -253,8 +253,8 @@ void __dispatch_internal_##width(void)
+@@ -271,8 +271,8 @@ void __dispatch_internal_##width(void)
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
u32 val; \
\
pending[--tgt] = val; \
\
if (val) \
-@@ -281,9 +281,9 @@ static void __internal_irq_mask_##width(
+@@ -299,9 +299,9 @@ static void __internal_irq_mask_##width(
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
\
} \
\
static void __internal_irq_unmask_##width(unsigned int irq) \
-@@ -292,9 +292,9 @@ static void __internal_irq_unmask_##widt
+@@ -310,9 +310,9 @@ static void __internal_irq_unmask_##widt
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
\
BUILD_IPIC_INTERNAL(32);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -181,22 +181,22 @@
- #define SYS_PLL_SOFT_RESET 0x1
+@@ -215,23 +215,23 @@
/* Interrupt Mask register */
+ #define PERF_IRQMASK_3368_REG 0xc
-#define PERF_IRQMASK_6328_REG 0x20
+#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
#define PERF_IRQMASK_6338_REG 0xc
+#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
/* Interrupt Status register */
+ #define PERF_IRQSTAT_3368_REG 0x10
-#define PERF_IRQSTAT_6328_REG 0x28
+#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
#define PERF_IRQSTAT_6338_REG 0x10
+#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
/* External Interrupt Configuration register */
- #define PERF_EXTIRQ_CFG_REG_6328 0x18
+ #define PERF_EXTIRQ_CFG_REG_3368 0x14
-From b14de5c78d32f8f98535a99ea56bb924beb66810 Mon Sep 17 00:00:00 2001
+From 1a1769d6268c93b042f635b31b43024fea7feb30 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 00:31:29 +0200
-Subject: [PATCH 07/13] MIPS: BCM63XX: populate irq_{stat,mask}_addr for
- second CPU
-
-Populate it for all platforms with a BMIPS4350.
+Subject: [PATCH 08/14] MIPS: BCM63XX: populate irq_{stat,mask}_addr for
+ second pin
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 28 +++++++++++++++++++++++++++-
- 1 file changed, 27 insertions(+), 1 deletion(-)
+ arch/mips/bcm63xx/irq.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 42 insertions(+), 1 deletion(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -30,6 +30,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_3368
+ #define irq_stat_reg0 PERF_IRQSTAT_3368_REG
+ #define irq_mask_reg0 PERF_IRQMASK_3368_REG
++#define irq_stat_reg1 0
++#define irq_mask_reg1 0
+ #define irq_bits 32
+ #define is_ext_irq_cascaded 0
+ #define ext_irq_start 0
+@@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6328
#define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns
+@@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6338
#define irq_stat_reg0 PERF_IRQSTAT_6338_REG
#define irq_mask_reg0 PERF_IRQMASK_6338_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
-@@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns
+@@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6345
#define irq_stat_reg0 PERF_IRQSTAT_6345_REG
#define irq_mask_reg0 PERF_IRQMASK_6345_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
-@@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns
+@@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6348
#define irq_stat_reg0 PERF_IRQSTAT_6348_REG
#define irq_mask_reg0 PERF_IRQMASK_6348_REG
#define irq_bits 32
#define is_ext_irq_cascaded 0
#define ext_irq_start 0
-@@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns
+@@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6358
#define irq_stat_reg0 PERF_IRQSTAT_6358_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6358_REG(0)
#define irq_bits 32
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns
+@@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6362
#define irq_stat_reg0 PERF_IRQSTAT_6362_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6362_REG(0)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns
+@@ -107,6 +121,8 @@ static void __internal_irq_unmask_64(uns
#ifdef CONFIG_BCM63XX_CPU_6368
#define irq_stat_reg0 PERF_IRQSTAT_6368_REG(0)
#define irq_mask_reg0 PERF_IRQMASK_6368_REG(0)
#define irq_bits 64
#define is_ext_irq_cascaded 1
#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-@@ -117,13 +131,15 @@ static void __internal_irq_unmask_64(uns
+@@ -128,13 +144,20 @@ static void __internal_irq_unmask_64(uns
#define irq_stat_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
#define irq_mask_addr0 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
++#if (irq_stat_reg1 > 0) && (irq_mask_reg1 > 0)
+#define irq_stat_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg1)
+#define irq_mask_addr1 (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg1)
++#else
++#define irq_stat_addr1 0
++#define irq_mask_addr1 0
++#endif
static inline void bcm63xx_init_irq(void)
{
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
-@@ -138,11 +154,15 @@ static void bcm63xx_init_irq(void)
+@@ -149,11 +172,15 @@ static void bcm63xx_init_irq(void)
irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
+ irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
switch (bcm63xx_get_cpu_id()) {
+ case BCM3368_CPU_ID:
+ irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
+ irq_mask_addr0 += PERF_IRQMASK_3368_REG;
++ irq_stat_addr1 = 0;
++ irq_stat_addr1 = 0;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
+@@ -161,6 +188,8 @@ static void bcm63xx_init_irq(void)
case BCM6328_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
-@@ -174,6 +194,8 @@ static void bcm63xx_init_irq(void)
+@@ -171,6 +200,8 @@ static void bcm63xx_init_irq(void)
+ case BCM6338_CPU_ID:
+ irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
+ irq_mask_addr0 += PERF_IRQMASK_6338_REG;
++ irq_stat_addr1 = 0;
++ irq_mask_addr1 = 0;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
+@@ -178,6 +209,8 @@ static void bcm63xx_init_irq(void)
+ case BCM6345_CPU_ID:
+ irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
+ irq_mask_addr0 += PERF_IRQMASK_6345_REG;
++ irq_stat_addr1 = 0;
++ irq_mask_addr1 = 0;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
+@@ -185,6 +218,8 @@ static void bcm63xx_init_irq(void)
+ case BCM6348_CPU_ID:
+ irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
+ irq_mask_addr0 += PERF_IRQMASK_6348_REG;
++ irq_stat_addr1 = 0;
++ irq_mask_addr1 = 0;
+ irq_bits = 32;
+ ext_irq_count = 4;
+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
+@@ -192,6 +227,8 @@ static void bcm63xx_init_irq(void)
case BCM6358_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
irq_bits = 32;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
-@@ -184,6 +206,8 @@ static void bcm63xx_init_irq(void)
+@@ -202,6 +239,8 @@ static void bcm63xx_init_irq(void)
case BCM6362_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
irq_bits = 64;
ext_irq_count = 4;
is_ext_irq_cascaded = 1;
-@@ -194,6 +218,8 @@ static void bcm63xx_init_irq(void)
+@@ -212,6 +251,8 @@ static void bcm63xx_init_irq(void)
case BCM6368_CPU_ID:
irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
-From 7c9d3fe01034adbb890aab7c44534658f89c211b Mon Sep 17 00:00:00 2001
+From 353f07637d82cf485a9319d203a6ed9b38590526 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Thu, 25 Apr 2013 15:35:12 +0200
-Subject: [PATCH 08/13] MIPS: BCM63XX: use a helper for getting the right
+Subject: [PATCH 09/14] MIPS: BCM63XX: use a helper for getting the right
register address
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
-@@ -251,6 +251,20 @@ static inline u32 get_ext_irq_perf_reg(i
+@@ -284,6 +284,20 @@ static inline u32 get_ext_irq_perf_reg(i
return ext_irq_cfg_reg2;
}
-+static inline u32 get_irq_stat_addr(int cpu)
++static inline u32 get_irq_stat_addr(int pin)
+{
-+ if (cpu == 0)
++ if (pin == 0)
+ return irq_stat_addr0;
+ return irq_stat_addr1;
+}
+
-+static inline u32 get_irq_mask_addr(int cpu)
++static inline u32 get_irq_mask_addr(int pin)
+{
-+ if (cpu == 0)
++ if (pin == 0)
+ return irq_mask_addr0;
+ return irq_mask_addr1;
+}
static inline void handle_internal(int intbit)
{
if (is_ext_irq_cascaded &&
-@@ -274,13 +288,15 @@ void __dispatch_internal_##width(void)
+@@ -307,13 +321,15 @@ void __dispatch_internal_##width(void)
unsigned int src, tgt; \
bool irqs_pending = false; \
static int i; \
pending[--tgt] = val; \
\
if (val) \
-@@ -306,10 +322,11 @@ static void __internal_irq_mask_##width(
+@@ -339,10 +355,11 @@ static void __internal_irq_mask_##width(
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
} \
\
static void __internal_irq_unmask_##width(unsigned int irq) \
-@@ -317,10 +334,11 @@ static void __internal_irq_unmask_##widt
+@@ -350,10 +367,11 @@ static void __internal_irq_unmask_##widt
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
-From 398337c57ebe3c704e0df5f569e6bd860ffe8914 Mon Sep 17 00:00:00 2001
+From b6b668f780d62d41bc14bc7baba1692e17cabf84 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 11:21:16 +0200
-Subject: [PATCH 09/13] MIPS: BCM63XX: add cpu argument to dispatch internal
+Subject: [PATCH 10/14] MIPS: BCM63XX: add cpu argument to dispatch internal
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
+ arch/mips/bcm63xx/irq.c | 21 +++++++++++----------
+ 1 file changed, 11 insertions(+), 10 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
-@@ -140,7 +140,7 @@ static inline void bcm63xx_init_irq(void
+@@ -158,7 +158,7 @@ static inline void bcm63xx_init_irq(void
#else /* ! BCMCPU_RUNTIME_DETECT */
static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
-@@ -282,14 +282,14 @@ static inline void handle_internal(int i
+@@ -315,14 +315,15 @@ static inline void handle_internal(int i
*/
#define BUILD_IPIC_INTERNAL(width) \
u32 pending[width / 32]; \
unsigned int src, tgt; \
bool irqs_pending = false; \
- static int i; \
+- static int i; \
- u32 irq_stat_addr = get_irq_stat_addr(0); \
- u32 irq_mask_addr = get_irq_mask_addr(0); \
++ static int i[NR_CPUS]; \
+ u32 irq_stat_addr = get_irq_stat_addr(cpu); \
+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
++ int *next = &i[cpu]; \
\
/* read registers in reverse order */ \
for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
-@@ -361,7 +361,7 @@ asmlinkage void plat_irq_dispatch(void)
+@@ -340,9 +341,9 @@ void __dispatch_internal_##width(void)
+ return; \
+ \
+ while (1) { \
+- int to_call = i; \
++ int to_call = *next; \
+ \
+- i = (i + 1) & (width - 1); \
++ *next = (*next + 1) & (width - 1); \
+ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
+ handle_internal(to_call); \
+ break; \
+@@ -394,7 +395,7 @@ asmlinkage void plat_irq_dispatch(void)
if (cause & CAUSEF_IP1)
do_IRQ(1);
if (cause & CAUSEF_IP2)
+++ /dev/null
-From 7b8e7bc9806b61be2f07bf2bbb5e3ee6e0f333e9 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Sun, 21 Apr 2013 15:38:56 +0200
-Subject: [PATCH 10/13] MIPS: BCM63XX: protect irq register accesses with a
- spinlock
-
-Since IRQs can be handled on both CPUs, we need to ensure that we
-don't try to modify the IRQ registers at the same time.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/irq.c | 47 ++++++++++++++++++++++++++++++++++++++++++-----
- 1 file changed, 42 insertions(+), 5 deletions(-)
-
---- a/arch/mips/bcm63xx/irq.c
-+++ b/arch/mips/bcm63xx/irq.c
-@@ -12,6 +12,7 @@
- #include <linux/interrupt.h>
- #include <linux/module.h>
- #include <linux/irq.h>
-+#include <linux/spinlock.h>
- #include <asm/irq_cpu.h>
- #include <asm/mipsregs.h>
- #include <bcm63xx_cpu.h>
-@@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig
- static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
- static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
-
-+static DEFINE_SPINLOCK(ipic_lock);
-+static DEFINE_SPINLOCK(epic_lock);
-+
- #ifndef BCMCPU_RUNTIME_DETECT
- #ifdef CONFIG_BCM63XX_CPU_6328
- #define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
-@@ -290,7 +294,9 @@ void __dispatch_internal_##width(int cpu
- static int i; \
- u32 irq_stat_addr = get_irq_stat_addr(cpu); \
- u32 irq_mask_addr = get_irq_mask_addr(cpu); \
-+ unsigned long flags; \
- \
-+ spin_lock_irqsave(&ipic_lock, flags); \
- /* read registers in reverse order */ \
- for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
- u32 val; \
-@@ -302,6 +308,7 @@ void __dispatch_internal_##width(int cpu
- if (val) \
- irqs_pending = true; \
- } \
-+ spin_unlock_irqrestore(&ipic_lock, flags); \
- \
- if (!irqs_pending) \
- return; \
-@@ -381,12 +388,20 @@ asmlinkage void plat_irq_dispatch(void)
- */
- static void bcm63xx_internal_irq_mask(struct irq_data *d)
- {
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ipic_lock, flags);
- internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
-+ spin_unlock_irqrestore(&ipic_lock, flags);
- }
-
- static void bcm63xx_internal_irq_unmask(struct irq_data *d)
- {
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ipic_lock, flags);
- internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
-+ spin_unlock_irqrestore(&ipic_lock, flags);
- }
-
- /*
-@@ -397,8 +412,11 @@ static void bcm63xx_external_irq_mask(st
- {
- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
- u32 reg, regaddr;
-+ unsigned long flags;
-
- regaddr = get_ext_irq_perf_reg(irq);
-+
-+ spin_lock_irqsave(&epic_lock, flags);
- reg = bcm_perf_readl(regaddr);
-
- if (BCMCPU_IS_6348())
-@@ -407,16 +425,24 @@ static void bcm63xx_external_irq_mask(st
- reg &= ~EXTIRQ_CFG_MASK(irq % 4);
-
- bcm_perf_writel(reg, regaddr);
-- if (is_ext_irq_cascaded)
-- internal_irq_mask(irq + ext_irq_start);
-+ spin_unlock_irqrestore(&epic_lock, flags);
-+
-+ if (is_ext_irq_cascaded) {
-+ struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
-+
-+ bcm63xx_internal_irq_mask(cd);
-+ }
- }
-
- static void bcm63xx_external_irq_unmask(struct irq_data *d)
- {
- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
- u32 reg, regaddr;
-+ unsigned long flags;
-
- regaddr = get_ext_irq_perf_reg(irq);
-+
-+ spin_lock_irqsave(&epic_lock, flags);
- reg = bcm_perf_readl(regaddr);
-
- if (BCMCPU_IS_6348())
-@@ -425,16 +451,22 @@ static void bcm63xx_external_irq_unmask(
- reg |= EXTIRQ_CFG_MASK(irq % 4);
-
- bcm_perf_writel(reg, regaddr);
-+ spin_unlock_irqrestore(&epic_lock, flags);
-+
-+ if (is_ext_irq_cascaded) {
-+ struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
-
-- if (is_ext_irq_cascaded)
-- internal_irq_unmask(irq + ext_irq_start);
-+ bcm63xx_internal_irq_unmask(cd);
-+ }
- }
-
- static void bcm63xx_external_irq_clear(struct irq_data *d)
- {
- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
- u32 reg, regaddr;
-+ unsigned long flags;
-
-+ spin_lock_irqsave(&epic_lock, flags);
- regaddr = get_ext_irq_perf_reg(irq);
- reg = bcm_perf_readl(regaddr);
-
-@@ -444,6 +476,7 @@ static void bcm63xx_external_irq_clear(s
- reg |= EXTIRQ_CFG_CLEAR(irq % 4);
-
- bcm_perf_writel(reg, regaddr);
-+ spin_unlock_irqrestore(&epic_lock, flags);
- }
-
- static int bcm63xx_external_irq_set_type(struct irq_data *d,
-@@ -452,6 +485,7 @@ static int bcm63xx_external_irq_set_type
- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
- u32 reg, regaddr;
- int levelsense, sense, bothedge;
-+ unsigned long flags;
-
- flow_type &= IRQ_TYPE_SENSE_MASK;
-
-@@ -486,9 +520,11 @@ static int bcm63xx_external_irq_set_type
- }
-
- regaddr = get_ext_irq_perf_reg(irq);
-- reg = bcm_perf_readl(regaddr);
- irq %= 4;
-
-+ spin_lock_irqsave(&epic_lock, flags);
-+ reg = bcm_perf_readl(regaddr);
-+
- switch (bcm63xx_get_cpu_id()) {
- case BCM6348_CPU_ID:
- if (levelsense)
-@@ -529,6 +565,7 @@ static int bcm63xx_external_irq_set_type
- }
-
- bcm_perf_writel(reg, regaddr);
-+ spin_unlock_irqrestore(&epic_lock, flags);
-
- irqd_set_trigger_type(d, flow_type);
- if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
--- /dev/null
+From 05e32e9dc84ee96728596c0b8b86de7eae8de229 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 21 Apr 2013 15:38:56 +0200
+Subject: [PATCH 11/14] MIPS: BCM63XX: protect irq register accesses
+
+---
+ arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -12,6 +12,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/irq.h>
++#include <linux/spinlock.h>
+ #include <asm/irq_cpu.h>
+ #include <asm/mipsregs.h>
+ #include <bcm63xx_cpu.h>
+@@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig
+ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+
++static DEFINE_SPINLOCK(ipic_lock);
++static DEFINE_SPINLOCK(epic_lock);
++
+ #ifndef BCMCPU_RUNTIME_DETECT
+ #ifdef CONFIG_BCM63XX_CPU_3368
+ #define irq_stat_reg0 PERF_IRQSTAT_3368_REG
+@@ -324,8 +328,10 @@ void __dispatch_internal_##width(int cpu
+ u32 irq_stat_addr = get_irq_stat_addr(cpu); \
+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
+ int *next = &i[cpu]; \
++ unsigned long flags; \
+ \
+ /* read registers in reverse order */ \
++ spin_lock_irqsave(&ipic_lock, flags); \
+ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
+ u32 val; \
+ \
+@@ -336,6 +342,7 @@ void __dispatch_internal_##width(int cpu
+ if (val) \
+ irqs_pending = true; \
+ } \
++ spin_unlock_irqrestore(&ipic_lock, flags); \
+ \
+ if (!irqs_pending) \
+ return; \
+@@ -357,10 +364,13 @@ static void __internal_irq_mask_##width(
+ unsigned reg = (irq / 32) ^ (width/32 - 1); \
+ unsigned bit = irq & 0x1f; \
+ u32 irq_mask_addr = get_irq_mask_addr(0); \
++ unsigned long flags; \
+ \
++ spin_lock_irqsave(&ipic_lock, flags); \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val &= ~(1 << bit); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
++ spin_unlock_irqrestore(&ipic_lock, flags); \
+ } \
+ \
+ static void __internal_irq_unmask_##width(unsigned int irq) \
+@@ -369,10 +379,13 @@ static void __internal_irq_unmask_##widt
+ unsigned reg = (irq / 32) ^ (width/32 - 1); \
+ unsigned bit = irq & 0x1f; \
+ u32 irq_mask_addr = get_irq_mask_addr(0); \
++ unsigned long flags; \
+ \
++ spin_lock_irqsave(&ipic_lock, flags); \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val |= (1 << bit); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
++ spin_unlock_irqrestore(&ipic_lock, flags); \
+ }
+
+ BUILD_IPIC_INTERNAL(32);
+@@ -431,8 +444,10 @@ static void bcm63xx_external_irq_mask(st
+ {
+ unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+ u32 reg, regaddr;
++ unsigned long flags;
+
+ regaddr = get_ext_irq_perf_reg(irq);
++ spin_lock_irqsave(&epic_lock, flags);
+ reg = bcm_perf_readl(regaddr);
+
+ if (BCMCPU_IS_6348())
+@@ -441,6 +456,8 @@ static void bcm63xx_external_irq_mask(st
+ reg &= ~EXTIRQ_CFG_MASK(irq % 4);
+
+ bcm_perf_writel(reg, regaddr);
++ spin_unlock_irqrestore(&epic_lock, flags);
++
+ if (is_ext_irq_cascaded)
+ internal_irq_mask(irq + ext_irq_start);
+ }
+@@ -449,8 +466,10 @@ static void bcm63xx_external_irq_unmask(
+ {
+ unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+ u32 reg, regaddr;
++ unsigned long flags;
+
+ regaddr = get_ext_irq_perf_reg(irq);
++ spin_lock_irqsave(&epic_lock, flags);
+ reg = bcm_perf_readl(regaddr);
+
+ if (BCMCPU_IS_6348())
+@@ -459,6 +478,7 @@ static void bcm63xx_external_irq_unmask(
+ reg |= EXTIRQ_CFG_MASK(irq % 4);
+
+ bcm_perf_writel(reg, regaddr);
++ spin_unlock_irqrestore(&epic_lock, flags);
+
+ if (is_ext_irq_cascaded)
+ internal_irq_unmask(irq + ext_irq_start);
+@@ -468,8 +488,10 @@ static void bcm63xx_external_irq_clear(s
+ {
+ unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+ u32 reg, regaddr;
++ unsigned long flags;
+
+ regaddr = get_ext_irq_perf_reg(irq);
++ spin_lock_irqsave(&epic_lock, flags);
+ reg = bcm_perf_readl(regaddr);
+
+ if (BCMCPU_IS_6348())
+@@ -478,6 +500,7 @@ static void bcm63xx_external_irq_clear(s
+ reg |= EXTIRQ_CFG_CLEAR(irq % 4);
+
+ bcm_perf_writel(reg, regaddr);
++ spin_unlock_irqrestore(&epic_lock, flags);
+ }
+
+ static int bcm63xx_external_irq_set_type(struct irq_data *d,
+@@ -486,6 +509,7 @@ static int bcm63xx_external_irq_set_type
+ unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+ u32 reg, regaddr;
+ int levelsense, sense, bothedge;
++ unsigned long flags;
+
+ flow_type &= IRQ_TYPE_SENSE_MASK;
+
+@@ -520,6 +544,7 @@ static int bcm63xx_external_irq_set_type
+ }
+
+ regaddr = get_ext_irq_perf_reg(irq);
++ spin_lock_irqsave(&epic_lock, flags);
+ reg = bcm_perf_readl(regaddr);
+ irq %= 4;
+
+@@ -564,6 +589,7 @@ static int bcm63xx_external_irq_set_type
+ }
+
+ bcm_perf_writel(reg, regaddr);
++ spin_unlock_irqrestore(&epic_lock, flags);
+
+ irqd_set_trigger_type(d, flow_type);
+ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-From 1baec3216529f795905b6376f9c8e4f14b114ba2 Mon Sep 17 00:00:00 2001
+From 70c33fe0df8d14e40f3ca92ce56a668d66184858 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 12:03:15 +0200
-Subject: [PATCH 11/13] MIPS: BCM63XX: wire up the second CPU's irq line
+Subject: [PATCH 12/14] MIPS: BCM63XX: wire up the second cpu's irq line
-It's hardwired to IRQ3, so we don't need to actually check the CPU id.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 40 ++++++++++++++++++++++++++++++++--------
- 1 file changed, 32 insertions(+), 8 deletions(-)
+ arch/mips/bcm63xx/irq.c | 50 ++++++++++++++++++++++++++++++++++++++---------
+ 1 file changed, 41 insertions(+), 9 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
-@@ -329,11 +329,15 @@ static void __internal_irq_mask_##width(
+@@ -363,13 +363,20 @@ static void __internal_irq_mask_##width(
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
- u32 irq_mask_addr = get_irq_mask_addr(0); \
+ unsigned long flags; \
+ int cpu; \
\
+ spin_lock_irqsave(&ipic_lock, flags); \
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
- val &= ~(1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
-+ for_each_online_cpu(cpu) { \
++ for_each_present_cpu(cpu) { \
+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
+ \
++ if (!irq_mask_addr) \
++ break; \
++ \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+ val &= ~(1 << bit); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ } \
+ spin_unlock_irqrestore(&ipic_lock, flags); \
} \
\
- static void __internal_irq_unmask_##width(unsigned int irq) \
-@@ -341,11 +345,15 @@ static void __internal_irq_unmask_##widt
+@@ -378,13 +385,23 @@ static void __internal_irq_unmask_##widt
u32 val; \
unsigned reg = (irq / 32) ^ (width/32 - 1); \
unsigned bit = irq & 0x1f; \
- u32 irq_mask_addr = get_irq_mask_addr(0); \
+ unsigned long flags; \
+ int cpu; \
-+ \
-+ for_each_online_cpu(cpu) { \
-+ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
\
+ spin_lock_irqsave(&ipic_lock, flags); \
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
- val |= (1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
++ for_each_present_cpu(cpu) { \
++ u32 irq_mask_addr = get_irq_mask_addr(cpu); \
++ \
++ if (!irq_mask_addr) \
++ break; \
++ \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
-+ val |= (1 << bit); \
++ if (cpu_online(cpu)) \
++ val |= (1 << bit); \
++ else \
++ val &= ~(1 << bit); \
+ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
+ } \
+ spin_unlock_irqrestore(&ipic_lock, flags); \
}
- BUILD_IPIC_INTERNAL(32);
-@@ -369,6 +377,10 @@ asmlinkage void plat_irq_dispatch(void)
+@@ -409,7 +426,10 @@ asmlinkage void plat_irq_dispatch(void)
do_IRQ(1);
if (cause & CAUSEF_IP2)
dispatch_internal(0);
-+#ifdef CONFIG_SMP
-+ if (cause & CAUSEF_IP3)
-+ dispatch_internal(1);
-+#else
- if (!is_ext_irq_cascaded) {
+- if (!is_ext_irq_cascaded) {
++ if (is_ext_irq_cascaded) {
++ if (cause & CAUSEF_IP3)
++ dispatch_internal(1);
++ } else {
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);
-@@ -379,6 +391,7 @@ asmlinkage void plat_irq_dispatch(void)
- if (cause & CAUSEF_IP6)
- do_IRQ(IRQ_EXT_3);
- }
-+#endif
- } while (1);
- }
-
-@@ -598,6 +611,14 @@ static struct irqaction cpu_ip2_cascade_
+ if (cause & CAUSEF_IP4)
+@@ -622,6 +642,14 @@ static struct irqaction cpu_ip2_cascade_
.flags = IRQF_NO_THREAD,
};
static struct irqaction cpu_ext_cascade_action = {
.handler = no_action,
.name = "cascade_extirq",
-@@ -624,4 +645,7 @@ void __init arch_init_irq(void)
+@@ -648,4 +676,8 @@ void __init arch_init_irq(void)
}
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
+#ifdef CONFIG_SMP
-+ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
++ if (is_ext_irq_cascaded)
++ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
+#endif
}
+++ /dev/null
-From 8679976d2ec08db4e4a14ecdd1ee022b70e51fc6 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Tue, 30 Apr 2013 11:26:53 +0200
-Subject: [PATCH 12/13] MIPS: BCM63XX: add cpumask argument to unmask
-
-Allow selective unmasking of IPIC irqs.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/irq.c | 19 +++++++++++++------
- 1 file changed, 13 insertions(+), 6 deletions(-)
-
---- a/arch/mips/bcm63xx/irq.c
-+++ b/arch/mips/bcm63xx/irq.c
-@@ -24,8 +24,10 @@ static void __dispatch_internal_32(int c
- static void __dispatch_internal_64(int cpu) __maybe_unused;
- static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
- static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
--static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
--static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
-+static void __internal_irq_unmask_32(unsigned int irq,
-+ const struct cpumask *dest) __maybe_unused;
-+static void __internal_irq_unmask_64(unsigned int irq,
-+ const struct cpumask *dest) __maybe_unused;
-
- static DEFINE_SPINLOCK(ipic_lock);
- static DEFINE_SPINLOCK(epic_lock);
-@@ -150,7 +152,8 @@ static unsigned int ext_irq_count;
- static unsigned int ext_irq_start, ext_irq_end;
- static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
- static void (*internal_irq_mask)(unsigned int irq);
--static void (*internal_irq_unmask)(unsigned int irq);
-+static void (*internal_irq_unmask)(unsigned int irq,
-+ const struct cpumask *dest);
-
- static void bcm63xx_init_irq(void)
- {
-@@ -340,7 +343,8 @@ static void __internal_irq_mask_##width(
- } \
- } \
- \
--static void __internal_irq_unmask_##width(unsigned int irq) \
-+static void __internal_irq_unmask_##width(unsigned int irq, \
-+ const struct cpumask *dest) \
- { \
- u32 val; \
- unsigned reg = (irq / 32) ^ (width/32 - 1); \
-@@ -351,7 +355,10 @@ static void __internal_irq_unmask_##widt
- u32 irq_mask_addr = get_irq_mask_addr(cpu); \
- \
- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
-- val |= (1 << bit); \
-+ if (cpu_isset(cpu, *dest)) \
-+ val |= (1 << bit); \
-+ else \
-+ val &= ~(1 << bit); \
- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
- } \
- }
-@@ -413,7 +420,7 @@ static void bcm63xx_internal_irq_unmask(
- unsigned long flags;
-
- spin_lock_irqsave(&ipic_lock, flags);
-- internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
-+ internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE, cpu_online_mask);
- spin_unlock_irqrestore(&ipic_lock, flags);
- }
-
--- /dev/null
+From 0e692ab15a69ac4534c18e67ed3cb7685f728037 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 30 Apr 2013 11:26:53 +0200
+Subject: [PATCH 13/14] MIPS: BCM63XX: use irq_desc as argument for (un)mask
+
+In preparation for applying affinity, use the irq descriptor as the
+argument for (un)mask.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c | 26 ++++++++++++++------------
+ 1 file changed, 14 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -22,10 +22,10 @@
+
+ static void __dispatch_internal_32(int cpu) __maybe_unused;
+ static void __dispatch_internal_64(int cpu) __maybe_unused;
+-static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+-static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
++static void __internal_irq_mask_32(struct irq_data *d) __maybe_unused;
++static void __internal_irq_mask_64(struct irq_data *d) __maybe_unused;
++static void __internal_irq_unmask_32(struct irq_data *d) __maybe_unused;
++static void __internal_irq_unmask_64(struct irq_data *d) __maybe_unused;
+
+ static DEFINE_SPINLOCK(ipic_lock);
+ static DEFINE_SPINLOCK(epic_lock);
+@@ -167,8 +167,8 @@ static int is_ext_irq_cascaded;
+ static unsigned int ext_irq_count;
+ static unsigned int ext_irq_start, ext_irq_end;
+ static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+-static void (*internal_irq_mask)(unsigned int irq);
+-static void (*internal_irq_unmask)(unsigned int irq);
++static void (*internal_irq_mask)(struct irq_data *d);
++static void (*internal_irq_unmask)(struct irq_data *d);
+
+ static void bcm63xx_init_irq(void)
+ {
+@@ -358,9 +358,10 @@ void __dispatch_internal_##width(int cpu
+ } \
+ } \
+ \
+-static void __internal_irq_mask_##width(unsigned int irq) \
++static void __internal_irq_mask_##width(struct irq_data *d) \
+ { \
+ u32 val; \
++ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
+ unsigned reg = (irq / 32) ^ (width/32 - 1); \
+ unsigned bit = irq & 0x1f; \
+ unsigned long flags; \
+@@ -380,9 +381,10 @@ static void __internal_irq_mask_##width(
+ spin_unlock_irqrestore(&ipic_lock, flags); \
+ } \
+ \
+-static void __internal_irq_unmask_##width(unsigned int irq) \
++static void __internal_irq_unmask_##width(struct irq_data *d) \
+ { \
+ u32 val; \
++ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
+ unsigned reg = (irq / 32) ^ (width/32 - 1); \
+ unsigned bit = irq & 0x1f; \
+ unsigned long flags; \
+@@ -448,12 +450,12 @@ asmlinkage void plat_irq_dispatch(void)
+ */
+ static void bcm63xx_internal_irq_mask(struct irq_data *d)
+ {
+- internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
++ internal_irq_mask(d);
+ }
+
+ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+ {
+- internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
++ internal_irq_unmask(d);
+ }
+
+ /*
+@@ -479,7 +481,7 @@ static void bcm63xx_external_irq_mask(st
+ spin_unlock_irqrestore(&epic_lock, flags);
+
+ if (is_ext_irq_cascaded)
+- internal_irq_mask(irq + ext_irq_start);
++ internal_irq_mask(irq_get_irq_data(irq + ext_irq_start));
+ }
+
+ static void bcm63xx_external_irq_unmask(struct irq_data *d)
+@@ -501,7 +503,7 @@ static void bcm63xx_external_irq_unmask(
+ spin_unlock_irqrestore(&epic_lock, flags);
+
+ if (is_ext_irq_cascaded)
+- internal_irq_unmask(irq + ext_irq_start);
++ internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start));
+ }
+
+ static void bcm63xx_external_irq_clear(struct irq_data *d)
-From a8bb19e5ba9a3a73fe6a761295b67b641a7bc9df Mon Sep 17 00:00:00 2001
+From 9e341df1f67c3c64dc5ac668a30bbb6b5ab5f2b4 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Fri, 26 Apr 2013 12:06:03 +0200
-Subject: [PATCH 13/13] MIPS: BCM63XX: allow setting affinity for IPIC
-
-Add support for setting the SMP affinity for the IPIC IRQs.
+Subject: [PATCH 14/14] MIPS: BCM63XX: allow setting affinity for IPIC
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 27 ++++++++++++++++++++++++++-
- 1 file changed, 26 insertions(+), 1 deletion(-)
+ arch/mips/bcm63xx/irq.c | 49 +++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 41 insertions(+), 8 deletions(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
-@@ -418,9 +418,14 @@ static void bcm63xx_internal_irq_mask(st
- static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+@@ -24,8 +24,10 @@ static void __dispatch_internal_32(int c
+ static void __dispatch_internal_64(int cpu) __maybe_unused;
+ static void __internal_irq_mask_32(struct irq_data *d) __maybe_unused;
+ static void __internal_irq_mask_64(struct irq_data *d) __maybe_unused;
+-static void __internal_irq_unmask_32(struct irq_data *d) __maybe_unused;
+-static void __internal_irq_unmask_64(struct irq_data *d) __maybe_unused;
++static void __internal_irq_unmask_32(struct irq_data *d,
++ const struct cpumask *mask) __maybe_unused;
++static void __internal_irq_unmask_64(struct irq_data *d,
++ const struct cpumask *mask) __maybe_unused;
+
+ static DEFINE_SPINLOCK(ipic_lock);
+ static DEFINE_SPINLOCK(epic_lock);
+@@ -168,7 +170,7 @@ static unsigned int ext_irq_count;
+ static unsigned int ext_irq_start, ext_irq_end;
+ static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+ static void (*internal_irq_mask)(struct irq_data *d);
+-static void (*internal_irq_unmask)(struct irq_data *d);
++static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
+
+ static void bcm63xx_init_irq(void)
{
- unsigned long flags;
-+ const struct cpumask *dest = cpu_online_mask;
+@@ -311,6 +313,20 @@ static inline void handle_internal(int i
+ do_IRQ(intbit + IRQ_INTERNAL_BASE);
+ }
- spin_lock_irqsave(&ipic_lock, flags);
-- internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE, cpu_online_mask);
++static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
++ const struct cpumask *m)
++{
++ bool enable = cpu_online(cpu);
+#ifdef CONFIG_SMP
-+ if (irqd_affinity_was_set(d))
-+ dest = d->affinity;
++
++ if (m)
++ enable &= cpu_isset(cpu, *m);
++ else if (irqd_affinity_was_set(d))
++ enable &= cpu_isset(cpu, *d->affinity);
+#endif
-+ internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE, dest);
- spin_unlock_irqrestore(&ipic_lock, flags);
++ return enable;
++}
++
+ /*
+ * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
+ * prioritize any interrupt relatively to another. the static counter
+@@ -381,7 +397,8 @@ static void __internal_irq_mask_##width(
+ spin_unlock_irqrestore(&ipic_lock, flags); \
+ } \
+ \
+-static void __internal_irq_unmask_##width(struct irq_data *d) \
++static void __internal_irq_unmask_##width(struct irq_data *d, \
++ const struct cpumask *m) \
+ { \
+ u32 val; \
+ unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
+@@ -398,7 +415,7 @@ static void __internal_irq_unmask_##widt
+ break; \
+ \
+ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
+- if (cpu_online(cpu)) \
++ if (enable_irq_for_cpu(cpu, d, m)) \
+ val |= (1 << bit); \
+ else \
+ val &= ~(1 << bit); \
+@@ -455,7 +472,7 @@ static void bcm63xx_internal_irq_mask(st
+
+ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+ {
+- internal_irq_unmask(d);
++ internal_irq_unmask(d, NULL);
+ }
+
+ /*
+@@ -503,7 +520,8 @@ static void bcm63xx_external_irq_unmask(
+ spin_unlock_irqrestore(&epic_lock, flags);
+
+ if (is_ext_irq_cascaded)
+- internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start));
++ internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
++ NULL);
}
-@@ -596,10 +601,30 @@ static int bcm63xx_external_irq_set_type
+ static void bcm63xx_external_irq_clear(struct irq_data *d)
+@@ -622,6 +640,18 @@ static int bcm63xx_external_irq_set_type
return IRQ_SET_MASK_OK_NOCOPY;
}
+ const struct cpumask *dest,
+ bool force)
+{
-+ unsigned int irq = data->irq - IRQ_INTERNAL_BASE;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ipic_lock, flags);
+ if (!irqd_irq_disabled(data))
-+ internal_irq_unmask(irq, dest);
-+ spin_unlock_irqrestore(&ipic_lock, flags);
++ internal_irq_unmask(data, dest);
+
+ return 0;
+}
static struct irq_chip bcm63xx_internal_irq_chip = {
.name = "bcm63xx_ipic",
.irq_mask = bcm63xx_internal_irq_mask,
- .irq_unmask = bcm63xx_internal_irq_unmask,
-+#ifdef CONFIG_SMP
-+ .irq_set_affinity = bcm63xx_internal_set_affinity,
-+#endif
- };
+@@ -679,7 +709,10 @@ void __init arch_init_irq(void)
- static struct irq_chip bcm63xx_external_irq_chip = {
+ setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
+ #ifdef CONFIG_SMP
+- if (is_ext_irq_cascaded)
++ if (is_ext_irq_cascaded) {
+ setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
++ bcm63xx_internal_irq_chip.irq_set_affinity =
++ bcm63xx_internal_set_affinity;
++ }
+ #endif
+ }
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -1514,7 +1514,7 @@ static int compute_hw_mtu(struct bcm_ene
+@@ -1637,7 +1637,7 @@ static int compute_hw_mtu(struct bcm_ene
actual_mtu = mtu;
/* add ethernet header + vlan tag size */
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -859,6 +859,8 @@ void __init board_prom_init(void)
+@@ -902,6 +902,8 @@ void __init board_prom_init(void)
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G3_EXT_MII |
GPIO_MODE_6348_G0_EXT_MII;
bcm_gpio_writel(val, GPIO_MODE_REG);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -578,6 +578,8 @@
+@@ -621,6 +621,8 @@
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
#define GPIO_MODE_6358_UTOPIA (1 << 12)
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -784,10 +784,8 @@ static int bcm_enet_open(struct net_devi
+@@ -870,10 +870,8 @@ static int bcm_enet_open(struct net_devi
struct bcm_enet_priv *priv;
struct sockaddr addr;
struct device *kdev;
void *p;
u32 val;
-@@ -795,40 +793,10 @@ static int bcm_enet_open(struct net_devi
+@@ -881,40 +879,10 @@ static int bcm_enet_open(struct net_devi
kdev = &priv->pdev->dev;
if (priv->has_phy) {
}
/* mask all interrupts and request them */
-@@ -838,7 +806,7 @@ static int bcm_enet_open(struct net_devi
+@@ -924,7 +892,7 @@ static int bcm_enet_open(struct net_devi
ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
if (ret)
ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, IRQF_DISABLED,
dev->name, dev);
-@@ -1023,9 +991,6 @@ out_freeirq_rx:
+@@ -1131,9 +1099,6 @@ out_freeirq_rx:
out_freeirq:
free_irq(dev->irq, dev);
return ret;
}
-@@ -1130,12 +1095,6 @@ static int bcm_enet_stop(struct net_devi
+@@ -1238,12 +1203,6 @@ static int bcm_enet_stop(struct net_devi
free_irq(priv->irq_rx, dev);
free_irq(dev->irq, dev);
return 0;
}
-@@ -1707,6 +1666,8 @@ static int bcm_enet_probe(struct platfor
+@@ -1838,6 +1797,8 @@ static int bcm_enet_probe(struct platfor
/* MII bus registration */
if (priv->has_phy) {
priv->mii_bus = mdiobus_alloc();
if (!priv->mii_bus) {
-@@ -1744,6 +1705,38 @@ static int bcm_enet_probe(struct platfor
+@@ -1875,6 +1836,38 @@ static int bcm_enet_probe(struct platfor
dev_err(&pdev->dev, "unable to register mdio bus\n");
goto out_free_mdio;
}
} else {
/* run platform code to initialize PHY device */
-@@ -1789,6 +1782,9 @@ static int bcm_enet_probe(struct platfor
+@@ -1920,6 +1913,9 @@ static int bcm_enet_probe(struct platfor
return 0;
out_unregister_mdio:
if (priv->mii_bus)
mdiobus_unregister(priv->mii_bus);
-@@ -1830,6 +1826,8 @@ static int bcm_enet_remove(struct platfo
+@@ -1961,6 +1957,8 @@ static int bcm_enet_remove(struct platfo
enet_writel(priv, 0, ENET_MIISC_REG);
if (priv->has_phy) {
+++ /dev/null
-From accc558f334662c8b16c121b4819931c028e8eb0 Mon Sep 17 00:00:00 2001
-From: Maxime Bizon <mbizon@freebox.fr>
-Date: Mon, 8 Jun 2009 16:12:10 +0200
-Subject: [PATCH 27/63] bcm63xx_enet: implement reset_autoneg ethtool.
-
----
- drivers/net/ethernet/broadcom/bcm63xx_enet.c | 15 +++++++++++++++
- 1 files changed, 15 insertions(+), 0 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -1289,6 +1289,20 @@ static void bcm_enet_get_ethtool_stats(s
- mutex_unlock(&priv->mib_update_lock);
- }
-
-+static int bcm_enet_nway_reset(struct net_device *dev)
-+{
-+ struct bcm_enet_priv *priv;
-+
-+ priv = netdev_priv(dev);
-+ if (priv->has_phy) {
-+ if (!priv->phydev)
-+ return -ENODEV;
-+ return genphy_restart_aneg(priv->phydev);
-+ }
-+
-+ return -EOPNOTSUPP;
-+}
-+
- static int bcm_enet_get_settings(struct net_device *dev,
- struct ethtool_cmd *cmd)
- {
-@@ -1431,6 +1445,7 @@ static const struct ethtool_ops bcm_enet
- .get_strings = bcm_enet_get_strings,
- .get_sset_count = bcm_enet_get_sset_count,
- .get_ethtool_stats = bcm_enet_get_ethtool_stats,
-+ .nway_reset = bcm_enet_nway_reset,
- .get_settings = bcm_enet_get_settings,
- .set_settings = bcm_enet_set_settings,
- .get_drvinfo = bcm_enet_get_drvinfo,
+++ /dev/null
-From 2e5b0197443fcb454ca88619e36bb33d7a79e3ea Mon Sep 17 00:00:00 2001
-From: Maxime Bizon <mbizon@freebox.fr>
-Date: Thu, 21 Jan 2010 17:50:54 +0100
-Subject: [PATCH] bcm63xx_enet: split dma registers access.
-
----
- arch/mips/bcm63xx/dev-enet.c | 23 +++-
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 +-
- drivers/net/ethernet/broadcom/bcm63xx_enet.c | 144 +++++++++++++---------
- 3 files changed, 111 insertions(+), 62 deletions(-)
-
---- a/arch/mips/bcm63xx/dev-enet.c
-+++ b/arch/mips/bcm63xx/dev-enet.c
-@@ -19,6 +19,16 @@ static struct resource shared_res[] = {
- .end = -1, /* filled at runtime */
- .flags = IORESOURCE_MEM,
- },
-+ {
-+ .start = -1, /* filled at runtime */
-+ .end = -1, /* filled at runtime */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .start = -1, /* filled at runtime */
-+ .end = -1, /* filled at runtime */
-+ .flags = IORESOURCE_MEM,
-+ },
- };
-
- static struct platform_device bcm63xx_enet_shared_device = {
-@@ -110,10 +120,15 @@ int __init bcm63xx_enet_register(int uni
- if (!shared_device_registered) {
- shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
- shared_res[0].end = shared_res[0].start;
-- if (BCMCPU_IS_6338())
-- shared_res[0].end += (RSET_ENETDMA_SIZE / 2) - 1;
-- else
-- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
-+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
-+
-+ shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
-+ shared_res[1].end = shared_res[1].start;
-+ shared_res[1].end += RSET_ENETDMAC_SIZE(16) - 1;
-+
-+ shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
-+ shared_res[2].end = shared_res[2].start;
-+ shared_res[2].end += RSET_ENETDMAS_SIZE(16) - 1;
-
- ret = platform_device_register(&bcm63xx_enet_shared_device);
- if (ret)
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -174,7 +174,9 @@ enum bcm63xx_regs_set {
- #define BCM_6358_RSET_SPI_SIZE 1804
- #define BCM_6368_RSET_SPI_SIZE 1804
- #define RSET_ENET_SIZE 2048
--#define RSET_ENETDMA_SIZE 2048
-+#define RSET_ENETDMA_SIZE 256
-+#define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
-+#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
- #define RSET_ENETSW_SIZE 65536
- #define RSET_UART_SIZE 24
- #define RSET_HSSPI_SIZE 1536
---- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -41,8 +41,8 @@ static int copybreak __read_mostly = 128
- module_param(copybreak, int, 0);
- MODULE_PARM_DESC(copybreak, "Receive copy threshold");
-
--/* io memory shared between all devices */
--static void __iomem *bcm_enet_shared_base;
-+/* io registers memory shared between all devices */
-+static void __iomem *bcm_enet_shared_base[3];
-
- /*
- * io helpers to access mac registers
-@@ -63,13 +63,35 @@ static inline void enet_writel(struct bc
- */
- static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
- {
-- return bcm_readl(bcm_enet_shared_base + off);
-+ return bcm_readl(bcm_enet_shared_base[0] + off);
- }
-
- static inline void enet_dma_writel(struct bcm_enet_priv *priv,
- u32 val, u32 off)
- {
-- bcm_writel(val, bcm_enet_shared_base + off);
-+ bcm_writel(val, bcm_enet_shared_base[0] + off);
-+}
-+
-+static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
-+{
-+ return bcm_readl(bcm_enet_shared_base[1] + off);
-+}
-+
-+static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
-+ u32 val, u32 off)
-+{
-+ bcm_writel(val, bcm_enet_shared_base[1] + off);
-+}
-+
-+static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
-+{
-+ return bcm_readl(bcm_enet_shared_base[2] + off);
-+}
-+
-+static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
-+ u32 val, u32 off)
-+{
-+ bcm_writel(val, bcm_enet_shared_base[2] + off);
- }
-
- /*
-@@ -353,8 +375,8 @@ static int bcm_enet_receive_queue(struct
- bcm_enet_refill_rx(dev);
-
- /* kick rx dma */
-- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
-- ENETDMA_CHANCFG_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
- }
-
- return processed;
-@@ -429,10 +451,10 @@ static int bcm_enet_poll(struct napi_str
- dev = priv->net_dev;
-
- /* ack interrupts */
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IR_REG(priv->rx_chan));
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IR_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IR_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IR_REG(priv->tx_chan));
-
- /* reclaim sent skb */
- tx_work_done = bcm_enet_tx_reclaim(dev, 0);
-@@ -451,10 +473,10 @@ static int bcm_enet_poll(struct napi_str
- napi_complete(napi);
-
- /* restore rx/tx interrupt */
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IRMASK_REG(priv->rx_chan));
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IRMASK_REG(priv->tx_chan));
-
- return rx_work_done;
- }
-@@ -497,8 +519,8 @@ static irqreturn_t bcm_enet_isr_dma(int
- priv = netdev_priv(dev);
-
- /* mask rx/tx interrupts */
-- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-
- napi_schedule(&priv->napi);
-
-@@ -557,8 +579,8 @@ static int bcm_enet_start_xmit(struct sk
- wmb();
-
- /* kick tx dma */
-- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
-- ENETDMA_CHANCFG_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-+ ENETDMAC_CHANCFG_REG(priv->tx_chan));
-
- /* stop queue if no more desc available */
- if (!priv->tx_desc_count)
-@@ -801,8 +823,8 @@ static int bcm_enet_open(struct net_devi
-
- /* mask all interrupts and request them */
- enet_writel(priv, 0, ENET_IRMASK_REG);
-- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-
- ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
- if (ret)
-@@ -889,28 +911,28 @@ static int bcm_enet_open(struct net_devi
- }
-
- /* write rx & tx ring addresses */
-- enet_dma_writel(priv, priv->rx_desc_dma,
-- ENETDMA_RSTART_REG(priv->rx_chan));
-- enet_dma_writel(priv, priv->tx_desc_dma,
-- ENETDMA_RSTART_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, priv->rx_desc_dma,
-+ ENETDMAS_RSTART_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, priv->tx_desc_dma,
-+ ENETDMAS_RSTART_REG(priv->tx_chan));
-
- /* clear remaining state ram for rx & tx channel */
-- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
-
- /* set max rx/tx length */
- enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
- enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
-
- /* set dma maximum burst len */
-- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
-- ENETDMA_MAXBURST_REG(priv->rx_chan));
-- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
-- ENETDMA_MAXBURST_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
-+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
-+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
-
- /* set correct transmit fifo watermark */
- enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
-@@ -928,26 +950,26 @@ static int bcm_enet_open(struct net_devi
- val |= ENET_CTL_ENABLE_MASK;
- enet_writel(priv, val, ENET_CTL_REG);
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
-- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
-- ENETDMA_CHANCFG_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
-
- /* watch "mib counters about to overflow" interrupt */
- enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
- enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
-
- /* watch "packet transferred" interrupt in rx and tx */
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IR_REG(priv->rx_chan));
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IR_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IR_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IR_REG(priv->tx_chan));
-
- /* make sure we enable napi before rx interrupt */
- napi_enable(&priv->napi);
-
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IRMASK_REG(priv->rx_chan));
-- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
-- ENETDMA_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IRMASK_REG(priv->tx_chan));
-
- if (priv->has_phy)
- phy_start(priv->phydev);
-@@ -1024,14 +1046,14 @@ static void bcm_enet_disable_dma(struct
- {
- int limit;
-
-- enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
-
- limit = 1000;
- do {
- u32 val;
-
-- val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
-- if (!(val & ENETDMA_CHANCFG_EN_MASK))
-+ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
-+ if (!(val & ENETDMAC_CHANCFG_EN_MASK))
- break;
- udelay(1);
- } while (limit--);
-@@ -1057,8 +1079,8 @@ static int bcm_enet_stop(struct net_devi
-
- /* mask all interrupts */
- enet_writel(priv, 0, ENET_IRMASK_REG);
-- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
-- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-
- /* make sure no mib update is scheduled */
- cancel_work_sync(&priv->mib_update_task);
-@@ -1597,7 +1619,7 @@ static int bcm_enet_probe(struct platfor
-
- /* stop if shared driver failed, assume driver->probe will be
- * called in the same order we register devices (correct ?) */
-- if (!bcm_enet_shared_base)
-+ if (!bcm_enet_shared_base[0])
- return -ENODEV;
-
- res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -1882,14 +1904,24 @@ struct platform_driver bcm63xx_enet_driv
- static int bcm_enet_shared_probe(struct platform_device *pdev)
- {
- struct resource *res;
-+ void __iomem *p[3];
-+ unsigned int i;
-
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (!res)
-- return -ENODEV;
-+ memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
-
-- bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res);
-- if (!bcm_enet_shared_base)
-- return -ENOMEM;
-+ for (i = 0; i < 3; i++) {
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-+ if (!res)
-+ return -EINVAL;
-+
-+ p[i] = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!p[i])
-+ return -ENOMEM;
-+
-+ bcm_enet_shared_base[i] = p;
-+ }
-+
-+ memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
-
- return 0;
- }
+++ /dev/null
-From d16c1a1410f6c35a835baaa445774b4421db6c96 Mon Sep 17 00:00:00 2001
-From: Maxime Bizon <mbizon@freebox.fr>
-Date: Sat, 23 Jan 2010 03:01:02 +0100
-Subject: [PATCH 8/8] bcm63xx_enet: add support for bcm6368 internal ethernet
- switch.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 +
- arch/mips/bcm63xx/dev-enet.c | 113 ++-
- .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 28 +
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 50 +
- .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 +
- drivers/net/ethernet/broadcom/bcm63xx_enet.c | 1018 +++++++++++++++++++-
- drivers/net/ethernet/broadcom/bcm63xx_enet.h | 75 ++
- 8 files changed, 1239 insertions(+), 66 deletions(-)
-
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -924,6 +924,10 @@ int __init board_register_devices(void)
- !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
- bcm63xx_enet_register(1, &board.enet1);
-
-+ if (board.has_enetsw &&
-+ !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
-+ bcm63xx_enetsw_register(&board.enetsw);
-+
- if (board.has_usbd)
- bcm63xx_usbd_register(&board.usbd);
-
---- a/arch/mips/bcm63xx/dev-enet.c
-+++ b/arch/mips/bcm63xx/dev-enet.c
-@@ -104,6 +104,64 @@ static struct platform_device bcm63xx_en
- },
- };
-
-+static struct resource enetsw_res[] = {
-+ {
-+ /* start & end filled at runtime */
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ /* start filled at runtime */
-+ .flags = IORESOURCE_IRQ,
-+ },
-+ {
-+ /* start filled at runtime */
-+ .flags = IORESOURCE_IRQ,
-+ },
-+};
-+
-+static struct bcm63xx_enetsw_platform_data enetsw_pd;
-+
-+static struct platform_device bcm63xx_enetsw_device = {
-+ .name = "bcm63xx_enetsw",
-+ .num_resources = ARRAY_SIZE(enetsw_res),
-+ .resource = enetsw_res,
-+ .dev = {
-+ .platform_data = &enetsw_pd,
-+ },
-+};
-+
-+static int __init register_shared(void)
-+{
-+ int ret, chan_count;
-+
-+ if (shared_device_registered)
-+ return 0;
-+
-+ shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
-+ shared_res[0].end = shared_res[0].start;
-+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
-+
-+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
-+ chan_count = 32;
-+ else
-+ chan_count = 8;
-+
-+ shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
-+ shared_res[1].end = shared_res[1].start;
-+ shared_res[1].end += RSET_ENETDMAC_SIZE(chan_count) - 1;
-+
-+ shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
-+ shared_res[2].end = shared_res[2].start;
-+ shared_res[2].end += RSET_ENETDMAS_SIZE(chan_count) - 1;
-+
-+ ret = platform_device_register(&bcm63xx_enet_shared_device);
-+ if (ret)
-+ return ret;
-+ shared_device_registered = 1;
-+
-+ return 0;
-+}
-+
- int __init bcm63xx_enet_register(int unit,
- const struct bcm63xx_enet_platform_data *pd)
- {
-@@ -117,24 +175,9 @@ int __init bcm63xx_enet_register(int uni
- if (unit == 1 && BCMCPU_IS_6338())
- return -ENODEV;
-
-- if (!shared_device_registered) {
-- shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
-- shared_res[0].end = shared_res[0].start;
-- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
--
-- shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
-- shared_res[1].end = shared_res[1].start;
-- shared_res[1].end += RSET_ENETDMAC_SIZE(16) - 1;
--
-- shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
-- shared_res[2].end = shared_res[2].start;
-- shared_res[2].end += RSET_ENETDMAS_SIZE(16) - 1;
--
-- ret = platform_device_register(&bcm63xx_enet_shared_device);
-- if (ret)
-- return ret;
-- shared_device_registered = 1;
-- }
-+ ret = register_shared();
-+ if (ret)
-+ return ret;
-
- if (unit == 0) {
- enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
-@@ -175,3 +218,37 @@ int __init bcm63xx_enet_register(int uni
- return ret;
- return 0;
- }
-+
-+int __init
-+bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd)
-+{
-+ int ret;
-+
-+ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
-+ return -ENODEV;
-+
-+ ret = register_shared();
-+ if (ret)
-+ return ret;
-+
-+ enetsw_res[0].start = bcm63xx_regset_address(RSET_ENETSW);
-+ enetsw_res[0].end = enetsw_res[0].start;
-+ enetsw_res[0].end += RSET_ENETSW_SIZE - 1;
-+ enetsw_res[1].start = bcm63xx_get_irq_number(IRQ_ENETSW_RXDMA0);
-+ enetsw_res[2].start = bcm63xx_get_irq_number(IRQ_ENETSW_TXDMA0);
-+ if (!enetsw_res[2].start)
-+ enetsw_res[2].start = -1;
-+
-+ memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
-+
-+ if (BCMCPU_IS_6328())
-+ enetsw_pd.num_ports = ENETSW_PORTS_6328;
-+ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
-+ enetsw_pd.num_ports = ENETSW_PORTS_6368;
-+
-+ ret = platform_device_register(&bcm63xx_enetsw_device);
-+ if (ret)
-+ return ret;
-+
-+ return 0;
-+}
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
-@@ -39,7 +39,35 @@ struct bcm63xx_enet_platform_data {
- int phy_id, int reg, int val));
- };
-
-+/*
-+ * on board ethernet switch platform data
-+ */
-+#define ENETSW_MAX_PORT 8
-+#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
-+#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
-+
-+#define ENETSW_RGMII_PORT0 4
-+
-+struct bcm63xx_enetsw_port {
-+ int used;
-+ int phy_id;
-+
-+ int bypass_link;
-+ int force_speed;
-+ int force_duplex_full;
-+
-+ const char *name;
-+};
-+
-+struct bcm63xx_enetsw_platform_data {
-+ char mac_addr[ETH_ALEN];
-+ int num_ports;
-+ struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
-+};
-+
- int __init bcm63xx_enet_register(int unit,
- const struct bcm63xx_enet_platform_data *pd);
-
-+int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
-+
- #endif /* ! BCM63XX_DEV_ENET_H_ */
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -832,10 +832,60 @@
- * _REG relative to RSET_ENETSW
- *************************************************************************/
-
-+/* Port traffic control */
-+#define ENETSW_PTCTRL_REG(x) (0x0 + (x))
-+#define ENETSW_PTCTRL_RXDIS_MASK (1 << 0)
-+#define ENETSW_PTCTRL_TXDIS_MASK (1 << 1)
-+
-+/* Switch mode register */
-+#define ENETSW_SWMODE_REG (0xb)
-+#define ENETSW_SWMODE_FWD_EN_MASK (1 << 1)
-+
-+/* IMP override Register */
-+#define ENETSW_IMPOV_REG (0xe)
-+#define ENETSW_IMPOV_FORCE_MASK (1 << 7)
-+#define ENETSW_IMPOV_TXFLOW_MASK (1 << 5)
-+#define ENETSW_IMPOV_RXFLOW_MASK (1 << 4)
-+#define ENETSW_IMPOV_1000_MASK (1 << 3)
-+#define ENETSW_IMPOV_100_MASK (1 << 2)
-+#define ENETSW_IMPOV_FDX_MASK (1 << 1)
-+#define ENETSW_IMPOV_LINKUP_MASK (1 << 0)
-+
-+/* Port override Register */
-+#define ENETSW_PORTOV_REG(x) (0x58 + (x))
-+#define ENETSW_PORTOV_ENABLE_MASK (1 << 6)
-+#define ENETSW_PORTOV_TXFLOW_MASK (1 << 5)
-+#define ENETSW_PORTOV_RXFLOW_MASK (1 << 4)
-+#define ENETSW_PORTOV_1000_MASK (1 << 3)
-+#define ENETSW_PORTOV_100_MASK (1 << 2)
-+#define ENETSW_PORTOV_FDX_MASK (1 << 1)
-+#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
-+
-+/* MDIO control register */
-+#define ENETSW_MDIOC_REG (0xb0)
-+#define ENETSW_MDIOC_EXT_MASK (1 << 16)
-+#define ENETSW_MDIOC_REG_SHIFT 20
-+#define ENETSW_MDIOC_PHYID_SHIFT 25
-+#define ENETSW_MDIOC_RD_MASK (1 << 30)
-+#define ENETSW_MDIOC_WR_MASK (1 << 31)
-+
-+/* MDIO data register */
-+#define ENETSW_MDIOD_REG (0xb4)
-+
-+/* Global Management Configuration Register */
-+#define ENETSW_GMCR_REG (0x200)
-+#define ENETSW_GMCR_RST_MIB_MASK (1 << 0)
-+
- /* MIB register */
- #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
- #define ENETSW_MIB_REG_COUNT 47
-
-+/* Jumbo control register port mask register */
-+#define ENETSW_JMBCTL_PORT_REG (0x4004)
-+
-+/* Jumbo control mib good frame register */
-+#define ENETSW_JMBCTL_MAXSIZE_REG (0x4008)
-+
-
- /*************************************************************************
- * _REG relative to RSET_OHCI_PRIV
---- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
-@@ -25,6 +25,7 @@ struct board_info {
- /* enabled feature/device */
- unsigned int has_enet0:1;
- unsigned int has_enet1:1;
-+ unsigned int has_enetsw:1;
- unsigned int has_pci:1;
- unsigned int has_pccard:1;
- unsigned int has_ohci0:1;
-@@ -37,6 +38,7 @@ struct board_info {
- /* ethernet config */
- struct bcm63xx_enet_platform_data enet0;
- struct bcm63xx_enet_platform_data enet1;
-+ struct bcm63xx_enetsw_platform_data enetsw;
-
- /* USB config */
- struct bcm63xx_usbd_platform_data usbd;
---- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -59,6 +59,49 @@ static inline void enet_writel(struct bc
- }
-
- /*
-+ * io helpers to access switch registers
-+ */
-+static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
-+{
-+ /* printk("enetsw_readl at %p\n", priv->base + off); */
-+ return bcm_readl(priv->base + off);
-+}
-+
-+static inline void enetsw_writel(struct bcm_enet_priv *priv,
-+ u32 val, u32 off)
-+{
-+ /* printk("enetsw_writel %08x at %p\n", val, priv->base + off); */
-+ bcm_writel(val, priv->base + off);
-+}
-+
-+static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
-+{
-+ /* printk("enetsw_readw at %p\n", priv->base + off); */
-+ return bcm_readw(priv->base + off);
-+}
-+
-+static inline void enetsw_writew(struct bcm_enet_priv *priv,
-+ u16 val, u32 off)
-+{
-+ /* printk("enetsw_writew %04x at %p\n", val, priv->base + off); */
-+ bcm_writew(val, priv->base + off);
-+}
-+
-+static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
-+{
-+ /* printk("enetsw_readb at %p\n", priv->base + off); */
-+ return bcm_readb(priv->base + off);
-+}
-+
-+static inline void enetsw_writeb(struct bcm_enet_priv *priv,
-+ u8 val, u32 off)
-+{
-+ /* printk("enetsw_writeb %02x at %p\n", val, priv->base + off); */
-+ bcm_writeb(val, priv->base + off);
-+}
-+
-+
-+/*
- * io helpers to access shared registers
- */
- static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
-@@ -218,7 +261,6 @@ static int bcm_enet_refill_rx(struct net
- if (!skb)
- break;
- priv->rx_skb[desc_idx] = skb;
--
- p = dma_map_single(&priv->pdev->dev, skb->data,
- priv->rx_skb_size,
- DMA_FROM_DEVICE);
-@@ -321,7 +363,8 @@ static int bcm_enet_receive_queue(struct
- }
-
- /* recycle packet if it's marked as bad */
-- if (unlikely(len_stat & DMADESC_ERR_MASK)) {
-+ if (!priv->enet_is_sw &&
-+ unlikely(len_stat & DMADESC_ERR_MASK)) {
- dev->stats.rx_errors++;
-
- if (len_stat & DMADESC_OVSIZE_MASK)
-@@ -552,6 +595,26 @@ static int bcm_enet_start_xmit(struct sk
- goto out_unlock;
- }
-
-+ /* pad small packets sent on a switch device */
-+ if (priv->enet_is_sw && skb->len < 64) {
-+ int needed = 64 - skb->len;
-+ char *data;
-+
-+ if (unlikely(skb_tailroom(skb) < needed)) {
-+ struct sk_buff *nskb;
-+
-+ nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
-+ if (!nskb) {
-+ ret = NETDEV_TX_BUSY;
-+ goto out_unlock;
-+ }
-+ dev_kfree_skb(skb);
-+ skb = nskb;
-+ }
-+ data = skb_put(skb, needed);
-+ memset(data, 0, needed);
-+ }
-+
- /* point to the next available desc */
- desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
- priv->tx_skb[priv->tx_curr_desc] = skb;
-@@ -929,9 +992,9 @@ static int bcm_enet_open(struct net_devi
- enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
-
- /* set dma maximum burst len */
-- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
-+ enet_dmac_writel(priv, priv->dma_maxburst,
- ENETDMAC_MAXBURST_REG(priv->rx_chan));
-- enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
-+ enet_dmac_writel(priv, priv->dma_maxburst,
- ENETDMAC_MAXBURST_REG(priv->tx_chan));
-
- /* set correct transmit fifo watermark */
-@@ -1528,7 +1591,7 @@ static int compute_hw_mtu(struct bcm_ene
- * it's appended
- */
- priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
-- BCMENET_DMA_MAXBURST * 4);
-+ priv->dma_maxburst * 4);
- return 0;
- }
-
-@@ -1635,6 +1698,9 @@ static int bcm_enet_probe(struct platfor
- return -ENOMEM;
- priv = netdev_priv(dev);
-
-+ priv->enet_is_sw = false;
-+ priv->dma_maxburst = BCMENET_DMA_MAXBURST;
-+
- ret = compute_hw_mtu(priv, dev->mtu);
- if (ret)
- goto out;
-@@ -1899,65 +1965,928 @@ struct platform_driver bcm63xx_enet_driv
- };
-
- /*
-- * reserve & remap memory space shared between all macs
-+ * switch mii access callbacks
- */
--static int bcm_enet_shared_probe(struct platform_device *pdev)
-+static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
-+ int ext, int phy_id, int location)
- {
-- struct resource *res;
-- void __iomem *p[3];
-- unsigned int i;
-+ u32 reg;
-+ int ret;
-
-- memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
-+ spin_lock_bh(&priv->enetsw_mdio_lock);
-+ enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
-
-- for (i = 0; i < 3; i++) {
-- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-- if (!res)
-- return -EINVAL;
-+ reg = ENETSW_MDIOC_RD_MASK |
-+ (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
-+ (location << ENETSW_MDIOC_REG_SHIFT);
-+
-+ if (ext)
-+ reg |= ENETSW_MDIOC_EXT_MASK;
-+
-+ enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
-+ udelay(50);
-+ ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
-+ spin_unlock_bh(&priv->enetsw_mdio_lock);
-+ return ret;
-+}
-
-- p[i] = devm_request_and_ioremap(&pdev->dev, res);
-- if (!p[i])
-- return -ENOMEM;
-+static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
-+ int ext, int phy_id, int location,
-+ uint16_t data)
-+{
-+ u32 reg;
-
-- bcm_enet_shared_base[i] = p;
-- }
-+ spin_lock_bh(&priv->enetsw_mdio_lock);
-+ enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
-
-- memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
-+ reg = ENETSW_MDIOC_WR_MASK |
-+ (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
-+ (location << ENETSW_MDIOC_REG_SHIFT);
-
-- return 0;
--}
-+ if (ext)
-+ reg |= ENETSW_MDIOC_EXT_MASK;
-
--static int bcm_enet_shared_remove(struct platform_device *pdev)
--{
-- return 0;
-+ reg |= data;
-+
-+ enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
-+ udelay(50);
-+ spin_unlock_bh(&priv->enetsw_mdio_lock);
- }
-
- /*
-- * this "shared" driver is needed because both macs share a single
-- * address space
-+ * enet sw PHY polling
- */
--struct platform_driver bcm63xx_enet_shared_driver = {
-- .probe = bcm_enet_shared_probe,
-- .remove = bcm_enet_shared_remove,
-- .driver = {
-- .name = "bcm63xx_enet_shared",
-- .owner = THIS_MODULE,
-- },
--};
-+static void swphy_poll_timer(unsigned long data)
-+{
-+ struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
-+ unsigned int i;
-+
-+ for (i = 0; i < priv->num_ports; i++) {
-+ struct bcm63xx_enetsw_port *port;
-+ int val, j, up, advertise, lpa, lpa2, speed, duplex, media;
-+ int external_phy = bcm_enet_port_is_rgmii(i);
-+ u8 override;
-+
-+ port = &priv->used_ports[i];
-+ if (!port->used)
-+ continue;
-+
-+ if (port->bypass_link)
-+ continue;
-+
-+ /* dummy read to clear */
-+ for (j = 0; j < 2; j++)
-+ val = bcmenet_sw_mdio_read(priv, external_phy,
-+ port->phy_id, MII_BMSR);
-+
-+ if (val == 0xffff)
-+ continue;
-+
-+ up = (val & BMSR_LSTATUS) ? 1 : 0;
-+ if (!(up ^ priv->sw_port_link[i]))
-+ continue;
-+
-+ priv->sw_port_link[i] = up;
-+
-+ /* link changed */
-+ if (!up) {
-+ dev_info(&priv->pdev->dev, "link DOWN on %s\n",
-+ port->name);
-+ enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
-+ ENETSW_PORTOV_REG(i));
-+ enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
-+ ENETSW_PTCTRL_TXDIS_MASK,
-+ ENETSW_PTCTRL_REG(i));
-+ continue;
-+ }
-+
-+ advertise = bcmenet_sw_mdio_read(priv, external_phy,
-+ port->phy_id, MII_ADVERTISE);
-+
-+ lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
-+ MII_LPA);
-+
-+ lpa2 = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
-+ MII_STAT1000);
-+
-+ /* figure out media and duplex from advertise and LPA values */
-+ media = mii_nway_result(lpa & advertise);
-+ duplex = (media & ADVERTISE_FULL) ? 1 : 0;
-+ if (lpa2 & LPA_1000FULL)
-+ duplex = 1;
-+
-+ if (lpa2 & (LPA_1000FULL | LPA_1000HALF))
-+ speed = 1000;
-+ else {
-+ if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
-+ speed = 100;
-+ else
-+ speed = 10;
-+ }
-+
-+ dev_info(&priv->pdev->dev,
-+ "link UP on %s, %dMbps, %s-duplex\n",
-+ port->name, speed, duplex ? "full" : "half");
-+
-+ override = ENETSW_PORTOV_ENABLE_MASK |
-+ ENETSW_PORTOV_LINKUP_MASK;
-+
-+ if (speed == 1000)
-+ override |= ENETSW_IMPOV_1000_MASK;
-+ else if (speed == 100)
-+ override |= ENETSW_IMPOV_100_MASK;
-+ if (duplex)
-+ override |= ENETSW_IMPOV_FDX_MASK;
-+
-+ enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
-+ enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
-+ }
-+
-+ priv->swphy_poll.expires = jiffies + HZ;
-+ add_timer(&priv->swphy_poll);
-+}
-
- /*
-- * entry point
-+ * open callback, allocate dma rings & buffers and start rx operation
- */
--static int __init bcm_enet_init(void)
-+static int bcm_enetsw_open(struct net_device *dev)
- {
-- int ret;
-+ struct bcm_enet_priv *priv;
-+ struct device *kdev;
-+ int i, ret;
-+ unsigned int size;
-+ void *p;
-+ u32 val;
-
-- ret = platform_driver_register(&bcm63xx_enet_shared_driver);
-- if (ret)
-- return ret;
-+ priv = netdev_priv(dev);
-+ kdev = &priv->pdev->dev;
-
-- ret = platform_driver_register(&bcm63xx_enet_driver);
-+ /* mask all interrupts and request them */
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+
-+ ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
-+ IRQF_DISABLED, dev->name, dev);
- if (ret)
-- platform_driver_unregister(&bcm63xx_enet_shared_driver);
-+ goto out_freeirq;
-+
-+ if (priv->irq_tx != -1) {
-+ ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
-+ IRQF_DISABLED, dev->name, dev);
-+ if (ret)
-+ goto out_freeirq_rx;
-+ }
-+
-+ /* allocate rx dma ring */
-+ size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
-+ p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
-+ if (!p) {
-+ dev_err(kdev, "cannot allocate rx ring %u\n", size);
-+ ret = -ENOMEM;
-+ goto out_freeirq_tx;
-+ }
-+
-+ memset(p, 0, size);
-+ priv->rx_desc_alloc_size = size;
-+ priv->rx_desc_cpu = p;
-+
-+ /* allocate tx dma ring */
-+ size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
-+ p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
-+ if (!p) {
-+ dev_err(kdev, "cannot allocate tx ring\n");
-+ ret = -ENOMEM;
-+ goto out_free_rx_ring;
-+ }
-+
-+ memset(p, 0, size);
-+ priv->tx_desc_alloc_size = size;
-+ priv->tx_desc_cpu = p;
-+
-+ priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
-+ GFP_KERNEL);
-+ if (!priv->tx_skb) {
-+ dev_err(kdev, "cannot allocate rx skb queue\n");
-+ ret = -ENOMEM;
-+ goto out_free_tx_ring;
-+ }
-+
-+ priv->tx_desc_count = priv->tx_ring_size;
-+ priv->tx_dirty_desc = 0;
-+ priv->tx_curr_desc = 0;
-+ spin_lock_init(&priv->tx_lock);
-+
-+ /* init & fill rx ring with skbs */
-+ priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
-+ GFP_KERNEL);
-+ if (!priv->rx_skb) {
-+ dev_err(kdev, "cannot allocate rx skb queue\n");
-+ ret = -ENOMEM;
-+ goto out_free_tx_skb;
-+ }
-+
-+ priv->rx_desc_count = 0;
-+ priv->rx_dirty_desc = 0;
-+ priv->rx_curr_desc = 0;
-+
-+ /* disable all ports */
-+ for (i = 0; i < priv->num_ports; i++) {
-+ enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
-+ ENETSW_PORTOV_REG(i));
-+ enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
-+ ENETSW_PTCTRL_TXDIS_MASK,
-+ ENETSW_PTCTRL_REG(i));
-+
-+ priv->sw_port_link[i] = 0;
-+ }
-+
-+ /* reset mib */
-+ val = enetsw_readb(priv, ENETSW_GMCR_REG);
-+ val |= ENETSW_GMCR_RST_MIB_MASK;
-+ enetsw_writeb(priv, val, ENETSW_GMCR_REG);
-+ mdelay(1);
-+ val &= ~ENETSW_GMCR_RST_MIB_MASK;
-+ enetsw_writeb(priv, val, ENETSW_GMCR_REG);
-+ mdelay(1);
-+
-+ /* force CPU port state */
-+ val = enetsw_readb(priv, ENETSW_IMPOV_REG);
-+ val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
-+ enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
-+
-+ /* enable switch forward engine */
-+ val = enetsw_readb(priv, ENETSW_SWMODE_REG);
-+ val |= ENETSW_SWMODE_FWD_EN_MASK;
-+ enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
-+
-+ /* enable jumbo on all ports */
-+ enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
-+ enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
-+
-+ /* initialize flow control buffer allocation */
-+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
-+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
-+
-+ if (bcm_enet_refill_rx(dev)) {
-+ dev_err(kdev, "cannot allocate rx skb queue\n");
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ /* write rx & tx ring addresses */
-+ enet_dmas_writel(priv, priv->rx_desc_dma,
-+ ENETDMAS_RSTART_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, priv->tx_desc_dma,
-+ ENETDMAS_RSTART_REG(priv->tx_chan));
-+
-+ /* clear remaining state ram for rx & tx channel */
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
-+
-+ /* set dma maximum burst len */
-+ enet_dmac_writel(priv, priv->dma_maxburst,
-+ ENETDMAC_MAXBURST_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, priv->dma_maxburst,
-+ ENETDMAC_MAXBURST_REG(priv->tx_chan));
-+
-+ /* set flow control low/high threshold to 1/3 / 2/3 */
-+ val = priv->rx_ring_size / 3;
-+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
-+ val = (priv->rx_ring_size * 2) / 3;
-+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
-+
-+ /* all set, enable mac and interrupts, start dma engine and
-+ * kick rx dma channel */
-+ wmb();
-+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
-+ enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-+ ENETDMAC_CHANCFG_REG(priv->rx_chan));
-+
-+ /* watch "packet transferred" interrupt in rx and tx */
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IR_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IR_REG(priv->tx_chan));
-+
-+ /* make sure we enable napi before rx interrupt */
-+ napi_enable(&priv->napi);
-+
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-+ ENETDMAC_IRMASK_REG(priv->tx_chan));
-+
-+ netif_carrier_on(dev);
-+ netif_start_queue(dev);
-+
-+ /*
-+ * apply override config for bypass_link ports here.
-+ */
-+ for (i = 0; i < priv->num_ports; i++) {
-+ struct bcm63xx_enetsw_port *port;
-+ u8 override;
-+ port = &priv->used_ports[i];
-+ if (!port->used)
-+ continue;
-+
-+ if (!port->bypass_link)
-+ continue;
-+
-+ override = ENETSW_PORTOV_ENABLE_MASK |
-+ ENETSW_PORTOV_LINKUP_MASK;
-+
-+ switch (port->force_speed) {
-+ case 1000:
-+ override |= ENETSW_IMPOV_1000_MASK;
-+ break;
-+ case 100:
-+ override |= ENETSW_IMPOV_100_MASK;
-+ break;
-+ case 10:
-+ break;
-+ default:
-+ printk(KERN_WARNING "invalid forced speed on port %s: assume 10\n",
-+ port->name);
-+ break;
-+ }
-+
-+ if (port->force_duplex_full)
-+ override |= ENETSW_IMPOV_FDX_MASK;
-+
-+
-+ enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
-+ enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
-+ }
-+
-+ /* start phy polling timer */
-+ init_timer(&priv->swphy_poll);
-+ priv->swphy_poll.function = swphy_poll_timer;
-+ priv->swphy_poll.data = (unsigned long)priv;
-+ priv->swphy_poll.expires = jiffies;
-+ add_timer(&priv->swphy_poll);
-+ return 0;
-+
-+out:
-+ for (i = 0; i < priv->rx_ring_size; i++) {
-+ struct bcm_enet_desc *desc;
-+
-+ if (!priv->rx_skb[i])
-+ continue;
-+
-+ desc = &priv->rx_desc_cpu[i];
-+ dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
-+ DMA_FROM_DEVICE);
-+ kfree_skb(priv->rx_skb[i]);
-+ }
-+ kfree(priv->rx_skb);
-+
-+out_free_tx_skb:
-+ kfree(priv->tx_skb);
-+
-+out_free_tx_ring:
-+ dma_free_coherent(kdev, priv->tx_desc_alloc_size,
-+ priv->tx_desc_cpu, priv->tx_desc_dma);
-+
-+out_free_rx_ring:
-+ dma_free_coherent(kdev, priv->rx_desc_alloc_size,
-+ priv->rx_desc_cpu, priv->rx_desc_dma);
-+
-+out_freeirq_tx:
-+ if (priv->irq_tx != -1)
-+ free_irq(priv->irq_tx, dev);
-+
-+out_freeirq_rx:
-+ free_irq(priv->irq_rx, dev);
-+
-+out_freeirq:
-+ return ret;
-+}
-+
-+/*
-+ * stop callback
-+ */
-+static int bcm_enetsw_stop(struct net_device *dev)
-+{
-+ struct bcm_enet_priv *priv;
-+ struct device *kdev;
-+ int i;
-+
-+ priv = netdev_priv(dev);
-+ kdev = &priv->pdev->dev;
-+
-+ del_timer_sync(&priv->swphy_poll);
-+ netif_stop_queue(dev);
-+ napi_disable(&priv->napi);
-+ del_timer_sync(&priv->rx_timeout);
-+
-+ /* mask all interrupts */
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+
-+ /* disable dma & mac */
-+ bcm_enet_disable_dma(priv, priv->tx_chan);
-+ bcm_enet_disable_dma(priv, priv->rx_chan);
-+
-+ /* force reclaim of all tx buffers */
-+ bcm_enet_tx_reclaim(dev, 1);
-+
-+ /* free the rx skb ring */
-+ for (i = 0; i < priv->rx_ring_size; i++) {
-+ struct bcm_enet_desc *desc;
-+
-+ if (!priv->rx_skb[i])
-+ continue;
-+
-+ desc = &priv->rx_desc_cpu[i];
-+ dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
-+ DMA_FROM_DEVICE);
-+ kfree_skb(priv->rx_skb[i]);
-+ }
-+
-+ /* free remaining allocated memory */
-+ kfree(priv->rx_skb);
-+ kfree(priv->tx_skb);
-+ dma_free_coherent(kdev, priv->rx_desc_alloc_size,
-+ priv->rx_desc_cpu, priv->rx_desc_dma);
-+ dma_free_coherent(kdev, priv->tx_desc_alloc_size,
-+ priv->tx_desc_cpu, priv->tx_desc_dma);
-+ if (priv->irq_tx != -1)
-+ free_irq(priv->irq_tx, dev);
-+ free_irq(priv->irq_rx, dev);
-+
-+ return 0;
-+}
-+
-+/*
-+ * try to sort out phy external status by walking the used_port field
-+ * in the bcm_enet_priv structure. in case the phy address is not
-+ * assigned to any physical port on the switch, assume it is external
-+ * (and yell at the user).
-+ */
-+static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
-+{
-+ int i;
-+
-+ for (i = 0; i < priv->num_ports; ++i) {
-+ if (!priv->used_ports[i].used)
-+ continue;
-+ if (priv->used_ports[i].phy_id == phy_id)
-+ return bcm_enet_port_is_rgmii(i);
-+ }
-+
-+ printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
-+ phy_id);
-+ return 1;
-+}
-+
-+/*
-+ * can't use bcmenet_sw_mdio_read directly as we need to sort out
-+ * external/internal status of the given phy_id first.
-+ */
-+static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
-+ int location)
-+{
-+ struct bcm_enet_priv *priv;
-+
-+ priv = netdev_priv(dev);
-+ return bcmenet_sw_mdio_read(priv,
-+ bcm_enetsw_phy_is_external(priv, phy_id),
-+ phy_id, location);
-+}
-+
-+/*
-+ * can't use bcmenet_sw_mdio_write directly as we need to sort out
-+ * external/internal status of the given phy_id first.
-+ */
-+static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
-+ int location,
-+ int val)
-+{
-+ struct bcm_enet_priv *priv;
-+
-+ priv = netdev_priv(dev);
-+ bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
-+ phy_id, location, val);
-+}
-+
-+static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+ struct mii_if_info mii;
-+
-+ mii.dev = dev;
-+ mii.mdio_read = bcm_enetsw_mii_mdio_read;
-+ mii.mdio_write = bcm_enetsw_mii_mdio_write;
-+ mii.phy_id = 0;
-+ mii.phy_id_mask = 0x3f;
-+ mii.reg_num_mask = 0x1f;
-+ return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
-+
-+}
-+
-+static const struct net_device_ops bcm_enetsw_ops = {
-+ .ndo_open = bcm_enetsw_open,
-+ .ndo_stop = bcm_enetsw_stop,
-+ .ndo_start_xmit = bcm_enet_start_xmit,
-+ .ndo_change_mtu = bcm_enet_change_mtu,
-+ .ndo_do_ioctl = bcm_enetsw_ioctl,
-+};
-+
-+
-+static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
-+ { "rx_packets", DEV_STAT(rx_packets), -1 },
-+ { "tx_packets", DEV_STAT(tx_packets), -1 },
-+ { "rx_bytes", DEV_STAT(rx_bytes), -1 },
-+ { "tx_bytes", DEV_STAT(tx_bytes), -1 },
-+ { "rx_errors", DEV_STAT(rx_errors), -1 },
-+ { "tx_errors", DEV_STAT(tx_errors), -1 },
-+ { "rx_dropped", DEV_STAT(rx_dropped), -1 },
-+ { "tx_dropped", DEV_STAT(tx_dropped), -1 },
-+
-+ { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
-+ { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
-+ { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
-+ { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
-+ { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
-+ { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
-+ { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
-+ { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
-+ { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
-+ { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
-+ ETHSW_MIB_RX_1024_1522 },
-+ { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
-+ ETHSW_MIB_RX_1523_2047 },
-+ { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
-+ ETHSW_MIB_RX_2048_4095 },
-+ { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
-+ ETHSW_MIB_RX_4096_8191 },
-+ { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
-+ ETHSW_MIB_RX_8192_9728 },
-+ { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
-+ { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
-+ { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
-+ { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
-+ { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
-+
-+ { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
-+ { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
-+ { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
-+ { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
-+ { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
-+ { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
-+
-+};
-+
-+#define BCM_ENETSW_STATS_LEN \
-+ (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
-+
-+static void bcm_enetsw_get_strings(struct net_device *netdev,
-+ u32 stringset, u8 *data)
-+{
-+ int i;
-+
-+ switch (stringset) {
-+ case ETH_SS_STATS:
-+ for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
-+ memcpy(data + i * ETH_GSTRING_LEN,
-+ bcm_enetsw_gstrings_stats[i].stat_string,
-+ ETH_GSTRING_LEN);
-+ }
-+ break;
-+ }
-+}
-+
-+static int bcm_enetsw_get_sset_count(struct net_device *netdev,
-+ int string_set)
-+{
-+ switch (string_set) {
-+ case ETH_SS_STATS:
-+ return BCM_ENETSW_STATS_LEN;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
-+ struct ethtool_drvinfo *drvinfo)
-+{
-+ strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
-+ strncpy(drvinfo->version, bcm_enet_driver_version, 32);
-+ strncpy(drvinfo->fw_version, "N/A", 32);
-+ strncpy(drvinfo->bus_info, "bcm63xx", 32);
-+ drvinfo->n_stats = BCM_ENETSW_STATS_LEN;
-+}
-+
-+static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
-+ struct ethtool_stats *stats,
-+ u64 *data)
-+{
-+ struct bcm_enet_priv *priv;
-+ int i;
-+
-+ priv = netdev_priv(netdev);
-+
-+ for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
-+ const struct bcm_enet_stats *s;
-+ u32 lo, hi;
-+ char *p;
-+ int reg;
-+
-+ s = &bcm_enetsw_gstrings_stats[i];
-+
-+ reg = s->mib_reg;
-+ if (reg == -1)
-+ continue;
-+
-+ lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
-+ p = (char *)priv + s->stat_offset;
-+
-+ if (s->sizeof_stat == sizeof(u64)) {
-+ hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
-+ *(u64 *)p = ((u64)hi << 32 | lo);
-+ } else {
-+ *(u32 *)p = lo;
-+ }
-+ }
-+
-+ for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
-+ const struct bcm_enet_stats *s;
-+ char *p;
-+
-+ s = &bcm_enetsw_gstrings_stats[i];
-+
-+ if (s->mib_reg == -1)
-+ p = (char *)&netdev->stats + s->stat_offset;
-+ else
-+ p = (char *)priv + s->stat_offset;
-+
-+ data[i] = (s->sizeof_stat == sizeof(u64)) ?
-+ *(u64 *)p : *(u32 *)p;
-+ }
-+}
-+
-+static void bcm_enetsw_get_ringparam(struct net_device *dev,
-+ struct ethtool_ringparam *ering)
-+{
-+ struct bcm_enet_priv *priv;
-+
-+ priv = netdev_priv(dev);
-+
-+ /* rx/tx ring is actually only limited by memory */
-+ ering->rx_max_pending = 8192;
-+ ering->tx_max_pending = 8192;
-+ ering->rx_mini_max_pending = 0;
-+ ering->rx_jumbo_max_pending = 0;
-+ ering->rx_pending = priv->rx_ring_size;
-+ ering->tx_pending = priv->tx_ring_size;
-+}
-+
-+static int bcm_enetsw_set_ringparam(struct net_device *dev,
-+ struct ethtool_ringparam *ering)
-+{
-+ struct bcm_enet_priv *priv;
-+ int was_running;
-+
-+ priv = netdev_priv(dev);
-+
-+ was_running = 0;
-+ if (netif_running(dev)) {
-+ bcm_enetsw_stop(dev);
-+ was_running = 1;
-+ }
-+
-+ priv->rx_ring_size = ering->rx_pending;
-+ priv->tx_ring_size = ering->tx_pending;
-+
-+ if (was_running) {
-+ int err;
-+
-+ err = bcm_enetsw_open(dev);
-+ if (err)
-+ dev_close(dev);
-+ }
-+ return 0;
-+}
-+
-+static struct ethtool_ops bcm_enetsw_ethtool_ops = {
-+ .get_strings = bcm_enetsw_get_strings,
-+ .get_sset_count = bcm_enetsw_get_sset_count,
-+ .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
-+ .get_drvinfo = bcm_enetsw_get_drvinfo,
-+ .get_ringparam = bcm_enetsw_get_ringparam,
-+ .set_ringparam = bcm_enetsw_set_ringparam,
-+};
-+
-+/*
-+ * allocate netdevice, request register memory and register device.
-+ */
-+static int bcm_enetsw_probe(struct platform_device *pdev)
-+{
-+ struct bcm_enet_priv *priv;
-+ struct net_device *dev;
-+ struct bcm63xx_enetsw_platform_data *pd;
-+ struct resource *res_mem;
-+ int ret, irq_rx, irq_tx;
-+
-+ /* stop if shared driver failed, assume driver->probe will be
-+ * called in the same order we register devices (correct ?) */
-+ if (!bcm_enet_shared_base[0])
-+ return -ENODEV;
-+
-+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ irq_rx = platform_get_irq(pdev, 0);
-+ irq_tx = platform_get_irq(pdev, 1);
-+ if (!res_mem || irq_rx < 0)
-+ return -ENODEV;
-+
-+ ret = 0;
-+ dev = alloc_etherdev(sizeof(*priv));
-+ if (!dev)
-+ return -ENOMEM;
-+ priv = netdev_priv(dev);
-+ memset(priv, 0, sizeof(*priv));
-+
-+ /* initialize default and fetch platform data */
-+ priv->enet_is_sw = true;
-+ priv->irq_rx = irq_rx;
-+ priv->irq_tx = irq_tx;
-+ priv->rx_ring_size = BCMENET_DEF_RX_DESC;
-+ priv->tx_ring_size = BCMENET_DEF_TX_DESC;
-+ priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
-+
-+ pd = pdev->dev.platform_data;
-+ if (pd) {
-+ memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
-+ memcpy(priv->used_ports, pd->used_ports,
-+ sizeof (pd->used_ports));
-+ priv->num_ports = pd->num_ports;
-+ }
-+
-+ ret = compute_hw_mtu(priv, dev->mtu);
-+ if (ret)
-+ goto out;
-+
-+ if (!request_mem_region(res_mem->start, resource_size(res_mem),
-+ "bcm63xx_enetsw")) {
-+ ret = -EBUSY;
-+ goto out;
-+ }
-+
-+ priv->base = ioremap(res_mem->start, resource_size(res_mem));
-+ if (priv->base == NULL) {
-+ ret = -ENOMEM;
-+ goto out_release_mem;
-+ }
-+
-+ priv->mac_clk = clk_get(&pdev->dev, "enetsw");
-+ if (IS_ERR(priv->mac_clk)) {
-+ ret = PTR_ERR(priv->mac_clk);
-+ goto out_unmap;
-+ }
-+ clk_enable(priv->mac_clk);
-+
-+ priv->rx_chan = 0;
-+ priv->tx_chan = 1;
-+ spin_lock_init(&priv->rx_lock);
-+
-+ /* init rx timeout (used for oom) */
-+ init_timer(&priv->rx_timeout);
-+ priv->rx_timeout.function = bcm_enet_refill_rx_timer;
-+ priv->rx_timeout.data = (unsigned long)dev;
-+
-+ /* register netdevice */
-+ dev->netdev_ops = &bcm_enetsw_ops;
-+ netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
-+ SET_ETHTOOL_OPS(dev, &bcm_enetsw_ethtool_ops);
-+ SET_NETDEV_DEV(dev, &pdev->dev);
-+
-+ spin_lock_init(&priv->enetsw_mdio_lock);
-+
-+ ret = register_netdev(dev);
-+ if (ret)
-+ goto out_put_clk;
-+
-+ netif_carrier_off(dev);
-+ platform_set_drvdata(pdev, dev);
-+ priv->pdev = pdev;
-+ priv->net_dev = dev;
-+
-+ return 0;
-+
-+out_put_clk:
-+ clk_put(priv->mac_clk);
-+
-+out_unmap:
-+ iounmap(priv->base);
-+
-+out_release_mem:
-+ release_mem_region(res_mem->start, resource_size(res_mem));
-+out:
-+ free_netdev(dev);
-+ return ret;
-+}
-+
-+
-+/*
-+ * exit func, stops hardware and unregisters netdevice
-+ */
-+static int bcm_enetsw_remove(struct platform_device *pdev)
-+{
-+ struct bcm_enet_priv *priv;
-+ struct net_device *dev;
-+ struct resource *res;
-+
-+ /* stop netdevice */
-+ dev = platform_get_drvdata(pdev);
-+ priv = netdev_priv(dev);
-+ unregister_netdev(dev);
-+
-+ /* release device resources */
-+ iounmap(priv->base);
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ release_mem_region(res->start, resource_size(res));
-+
-+ platform_set_drvdata(pdev, NULL);
-+ free_netdev(dev);
-+ return 0;
-+}
-+
-+struct platform_driver bcm63xx_enetsw_driver = {
-+ .probe = bcm_enetsw_probe,
-+ .remove = bcm_enetsw_remove,
-+ .driver = {
-+ .name = "bcm63xx_enetsw",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+/*
-+ * reserve & remap memory space shared between all macs
-+ */
-+static int bcm_enet_shared_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ void __iomem *p[3];
-+ unsigned int i;
-+
-+ memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
-+
-+ for (i = 0; i < 3; i++) {
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-+ if (!res)
-+ return -EINVAL;
-+
-+ p[i] = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!p[i])
-+ return -ENOMEM;
-+ }
-+
-+ memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
-+
-+ return 0;
-+}
-+
-+static int bcm_enet_shared_remove(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+
-+/*
-+ * this "shared" driver is needed because both macs share a single
-+ * address space
-+ */
-+struct platform_driver bcm63xx_enet_shared_driver = {
-+ .probe = bcm_enet_shared_probe,
-+ .remove = bcm_enet_shared_remove,
-+ .driver = {
-+ .name = "bcm63xx_enet_shared",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+/*
-+ * entry point
-+ */
-+static int __init bcm_enet_init(void)
-+{
-+ int ret;
-+
-+ ret = platform_driver_register(&bcm63xx_enet_shared_driver);
-+ if (ret)
-+ return ret;
-+
-+ ret = platform_driver_register(&bcm63xx_enet_driver);
-+ if (ret)
-+ platform_driver_unregister(&bcm63xx_enet_shared_driver);
-+
-+ ret = platform_driver_register(&bcm63xx_enetsw_driver);
-+ if (ret) {
-+ platform_driver_unregister(&bcm63xx_enet_driver);
-+ platform_driver_unregister(&bcm63xx_enet_shared_driver);
-+ }
-
- return ret;
- }
-@@ -1965,6 +2894,7 @@ static int __init bcm_enet_init(void)
- static void __exit bcm_enet_exit(void)
- {
- platform_driver_unregister(&bcm63xx_enet_driver);
-+ platform_driver_unregister(&bcm63xx_enetsw_driver);
- platform_driver_unregister(&bcm63xx_enet_shared_driver);
- }
-
---- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
-+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
-@@ -18,6 +18,7 @@
-
- /* maximum burst len for dma (4 bytes unit) */
- #define BCMENET_DMA_MAXBURST 16
-+#define BCMENETSW_DMA_MAXBURST 8
-
- /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
- * must be low enough so that a DMA transfer of above burst length can
-@@ -84,11 +85,60 @@
- #define ETH_MIB_RX_CNTRL 54
-
-
-+/*
-+ * SW MIB Counters register definitions
-+*/
-+#define ETHSW_MIB_TX_ALL_OCT 0
-+#define ETHSW_MIB_TX_DROP_PKTS 2
-+#define ETHSW_MIB_TX_QOS_PKTS 3
-+#define ETHSW_MIB_TX_BRDCAST 4
-+#define ETHSW_MIB_TX_MULT 5
-+#define ETHSW_MIB_TX_UNI 6
-+#define ETHSW_MIB_TX_COL 7
-+#define ETHSW_MIB_TX_1_COL 8
-+#define ETHSW_MIB_TX_M_COL 9
-+#define ETHSW_MIB_TX_DEF 10
-+#define ETHSW_MIB_TX_LATE 11
-+#define ETHSW_MIB_TX_EX_COL 12
-+#define ETHSW_MIB_TX_PAUSE 14
-+#define ETHSW_MIB_TX_QOS_OCT 15
-+
-+#define ETHSW_MIB_RX_ALL_OCT 17
-+#define ETHSW_MIB_RX_UND 19
-+#define ETHSW_MIB_RX_PAUSE 20
-+#define ETHSW_MIB_RX_64 21
-+#define ETHSW_MIB_RX_65_127 22
-+#define ETHSW_MIB_RX_128_255 23
-+#define ETHSW_MIB_RX_256_511 24
-+#define ETHSW_MIB_RX_512_1023 25
-+#define ETHSW_MIB_RX_1024_1522 26
-+#define ETHSW_MIB_RX_OVR 27
-+#define ETHSW_MIB_RX_JAB 28
-+#define ETHSW_MIB_RX_ALIGN 29
-+#define ETHSW_MIB_RX_CRC 30
-+#define ETHSW_MIB_RX_GD_OCT 31
-+#define ETHSW_MIB_RX_DROP 33
-+#define ETHSW_MIB_RX_UNI 34
-+#define ETHSW_MIB_RX_MULT 35
-+#define ETHSW_MIB_RX_BRDCAST 36
-+#define ETHSW_MIB_RX_SA_CHANGE 37
-+#define ETHSW_MIB_RX_FRAG 38
-+#define ETHSW_MIB_RX_OVR_DISC 39
-+#define ETHSW_MIB_RX_SYM 40
-+#define ETHSW_MIB_RX_QOS_PKTS 41
-+#define ETHSW_MIB_RX_QOS_OCT 42
-+#define ETHSW_MIB_RX_1523_2047 44
-+#define ETHSW_MIB_RX_2048_4095 45
-+#define ETHSW_MIB_RX_4096_8191 46
-+#define ETHSW_MIB_RX_8192_9728 47
-+
-+
- struct bcm_enet_mib_counters {
- u64 tx_gd_octets;
- u32 tx_gd_pkts;
- u32 tx_all_octets;
- u32 tx_all_pkts;
-+ u32 tx_unicast;
- u32 tx_brdcast;
- u32 tx_mult;
- u32 tx_64;
-@@ -97,7 +147,12 @@ struct bcm_enet_mib_counters {
- u32 tx_256_511;
- u32 tx_512_1023;
- u32 tx_1024_max;
-+ u32 tx_1523_2047;
-+ u32 tx_2048_4095;
-+ u32 tx_4096_8191;
-+ u32 tx_8192_9728;
- u32 tx_jab;
-+ u32 tx_drop;
- u32 tx_ovr;
- u32 tx_frag;
- u32 tx_underrun;
-@@ -114,6 +169,7 @@ struct bcm_enet_mib_counters {
- u32 rx_all_octets;
- u32 rx_all_pkts;
- u32 rx_brdcast;
-+ u32 rx_unicast;
- u32 rx_mult;
- u32 rx_64;
- u32 rx_65_127;
-@@ -197,6 +253,9 @@ struct bcm_enet_priv {
- /* number of dma desc in tx ring */
- int tx_ring_size;
-
-+ /* maximum dma burst size */
-+ int dma_maxburst;
-+
- /* cpu view of rx dma ring */
- struct bcm_enet_desc *tx_desc_cpu;
-
-@@ -269,6 +328,22 @@ struct bcm_enet_priv {
-
- /* maximum hardware transmit/receive size */
- unsigned int hw_mtu;
-+
-+ bool enet_is_sw;
-+
-+ /* port mapping for switch devices */
-+ int num_ports;
-+ struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
-+ int sw_port_link[ENETSW_MAX_PORT];
-+
-+ /* used to poll switch port state */
-+ struct timer_list swphy_poll;
-+ spinlock_t enetsw_mdio_lock;
- };
-
-+static inline int bcm_enet_port_is_rgmii(int portid)
-+{
-+ return portid >= ENETSW_RGMII_PORT0;
-+}
-+
- #endif /* ! BCM63XX_ENET_H_ */
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -861,6 +861,19 @@
+@@ -931,6 +931,19 @@
#define ENETSW_PORTOV_FDX_MASK (1 << 1)
#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
#define ENETSW_MDIOC_EXT_MASK (1 << 16)
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -2200,6 +2200,18 @@ static int bcm_enetsw_open(struct net_de
+@@ -2233,6 +2233,18 @@ static int bcm_enetsw_open(struct net_de
priv->sw_port_link[i] = 0;
}
#include <bcm63xx_dev_pcmcia.h>
#include <bcm63xx_dev_spi.h>
#include <bcm63xx_dev_usb_ehci.h>
-@@ -952,6 +953,7 @@ int __init board_register_devices(void)
+@@ -995,6 +996,7 @@ int __init board_register_devices(void)
pr_err(PFX "failed to register fallback SPROM\n");
}
#endif
if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
return BCM63XX_FLASH_TYPE_SERIAL;
else
-@@ -85,6 +108,9 @@ static int __init bcm63xx_detect_flash_t
+@@ -86,6 +109,9 @@ static int __init bcm63xx_detect_flash_t
return BCM63XX_FLASH_TYPE_NAND;
case BCM6368_CPU_ID:
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
case STRAPBUS_6368_BOOT_SEL_NAND:
return BCM63XX_FLASH_TYPE_NAND;
-@@ -116,8 +142,13 @@ int __init bcm63xx_flash_register(void)
+@@ -117,8 +143,13 @@ int __init bcm63xx_flash_register(void)
return platform_device_register(&mtd_dev);
case BCM63XX_FLASH_TYPE_SERIAL:
return -ENODEV;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -629,6 +629,7 @@
+@@ -672,6 +672,7 @@
#define GPIO_STRAPBUS_REG 0x40
#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
#define STRAPBUS_6368_BOOT_SEL_NAND 0
#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
-@@ -1443,6 +1444,7 @@
+@@ -1513,6 +1514,7 @@
#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
#define MISC_STRAPBUS_6328_REG 0x240
#include <board_bcm963xx.h>
+#include <pci_ath9k_fixup.h>
+ #include <uapi/linux/bcm933xx_hcs.h>
#include <uapi/linux/bcm963xx_tag.h>
-
-@@ -907,6 +908,7 @@ int __init board_register_devices(void)
+@@ -950,6 +951,7 @@ int __init board_register_devices(void)
{
int button_count = 0;
int led_count = 0;
if (board.has_uart0)
bcm63xx_uart_register(0);
-@@ -945,7 +947,8 @@ int __init board_register_devices(void)
+@@ -988,7 +990,8 @@ int __init board_register_devices(void)
* do this after registering enet devices
*/
#ifdef CONFIG_SSB_PCIHOST
memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
if (ssb_arch_register_fallback_sprom(
-@@ -987,5 +990,9 @@ int __init board_register_devices(void)
+@@ -1034,5 +1037,9 @@ int __init board_register_devices(void)
platform_device_register(&bcm63xx_gpio_keys_device);
}
static struct mtd_partition mtd_partitions[] = {
{
.name = "cfe",
-@@ -86,26 +88,30 @@ static int __init bcm63xx_detect_flash_t
+@@ -86,27 +88,31 @@ static int __init bcm63xx_detect_flash_t
bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
- return BCM63XX_FLASH_TYPE_PARALLEL;
+ bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_PARALLEL;
+ break;
+ case BCM3368_CPU_ID:
case BCM6358_CPU_ID:
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
case BCM6368_CPU_ID:
val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
if (val & STRAPBUS_6368_SPI_CLK_FAST)
-@@ -113,25 +119,32 @@ static int __init bcm63xx_detect_flash_t
+@@ -114,25 +120,32 @@ static int __init bcm63xx_detect_flash_t
switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
case STRAPBUS_6368_BOOT_SEL_NAND:
case BCM63XX_FLASH_TYPE_PARALLEL:
/* read base address of boot chip select (0) */
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-@@ -154,7 +167,7 @@ int __init bcm63xx_flash_register(void)
+@@ -155,7 +168,7 @@ int __init bcm63xx_flash_register(void)
return -ENODEV;
default:
pr_err("flash detection failed for BCM%x: %d\n",
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -966,7 +966,7 @@ int __init board_register_devices(void)
+@@ -1009,7 +1009,7 @@ int __init board_register_devices(void)
if (board.num_spis)
spi_register_board_info(board.spis, board.num_spis);
};
static struct spi_board_info bcm63xx_spi_flash_info[] = {
-@@ -137,10 +141,13 @@ static int __init bcm63xx_detect_flash_t
+@@ -138,10 +142,13 @@ static int __init bcm63xx_detect_flash_t
return 0;
}
+++ /dev/null
-From 1b0b5d325d0cc50cade62afd6a9416fb3cd1e658 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Mon, 7 Jan 2013 17:42:45 +0100
-Subject: [PATCH 69/72] 443-MIPS-BCM63XX-enable-enet-for-BCM6345.patch
-
----
- arch/mips/bcm63xx/dev-enet.c | 63 ++++++-
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +-
- .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 88 +++++++++
- arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 43 ++++-
- drivers/net/ethernet/broadcom/bcm63xx_enet.c | 199 ++++++++++++--------
- drivers/net/ethernet/broadcom/bcm63xx_enet.h | 15 ++
- 6 files changed, 320 insertions(+), 91 deletions(-)
-
---- a/arch/mips/bcm63xx/dev-enet.c
-+++ b/arch/mips/bcm63xx/dev-enet.c
-@@ -9,10 +9,44 @@
- #include <linux/init.h>
- #include <linux/kernel.h>
- #include <linux/platform_device.h>
-+#include <linux/export.h>
- #include <bcm63xx_dev_enet.h>
- #include <bcm63xx_io.h>
- #include <bcm63xx_regs.h>
-
-+#ifdef BCMCPU_RUNTIME_DETECT
-+static const unsigned long bcm6xxx_regs_enetdmac[] = {
-+ [ENETDMAC_CHANCFG] = ENETDMAC_CHANCFG_REG,
-+ [ENETDMAC_IR] = ENETDMAC_IR_REG,
-+ [ENETDMAC_IRMASK] = ENETDMAC_IRMASK_REG,
-+ [ENETDMAC_MAXBURST] = ENETDMAC_MAXBURST_REG,
-+};
-+
-+static const unsigned long bcm6345_regs_enetdmac[] = {
-+ [ENETDMAC_CHANCFG] = ENETDMA_6345_CHANCFG_REG,
-+ [ENETDMAC_IR] = ENETDMA_6345_IR_REG,
-+ [ENETDMAC_IRMASK] = ENETDMA_6345_IRMASK_REG,
-+ [ENETDMAC_MAXBURST] = ENETDMA_6345_MAXBURST_REG,
-+ [ENETDMAC_BUFALLOC] = ENETDMA_6345_BUFALLOC_REG,
-+ [ENETDMAC_RSTART] = ENETDMA_6345_RSTART_REG,
-+ [ENETDMAC_FC] = ENETDMA_6345_FC_REG,
-+ [ENETDMAC_LEN] = ENETDMA_6345_LEN_REG,
-+};
-+
-+const unsigned long *bcm63xx_regs_enetdmac;
-+EXPORT_SYMBOL(bcm63xx_regs_enetdmac);
-+
-+static __init void bcm63xx_enetdmac_regs_init(void)
-+{
-+ if (BCMCPU_IS_6345())
-+ bcm63xx_regs_enetdmac = bcm6345_regs_enetdmac;
-+ else
-+ bcm63xx_regs_enetdmac = bcm6xxx_regs_enetdmac;
-+}
-+#else
-+static __init void bcm63xx_enetdmac_regs_init(void) { }
-+#endif
-+
- static struct resource shared_res[] = {
- {
- .start = -1, /* filled at runtime */
-@@ -137,9 +171,14 @@ static int __init register_shared(void)
- if (shared_device_registered)
- return 0;
-
-+ bcm63xx_enetdmac_regs_init();
-+
- shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
- shared_res[0].end = shared_res[0].start;
-- shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
-+ if (BCMCPU_IS_6345())
-+ shared_res[0].end += (RSET_6345_ENETDMA_SIZE) - 1;
-+ else
-+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
-
- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
- chan_count = 32;
-@@ -172,7 +211,7 @@ int __init bcm63xx_enet_register(int uni
- if (unit > 1)
- return -ENODEV;
-
-- if (unit == 1 && BCMCPU_IS_6338())
-+ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
- return -ENODEV;
-
- ret = register_shared();
-@@ -213,6 +252,20 @@ int __init bcm63xx_enet_register(int uni
- dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
- }
-
-+ dpd->dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
-+ dpd->dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
-+ if (BCMCPU_IS_6345()) {
-+ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_CHAINING_MASK;
-+ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_WRAP_EN_MASK;
-+ dpd->dma_chan_en_mask |= ENETDMAC_CHANCFG_FLOWC_EN_MASK;
-+ dpd->dma_chan_int_mask |= ENETDMA_IR_BUFDONE_MASK;
-+ dpd->dma_chan_int_mask |= ENETDMA_IR_NOTOWNER_MASK;
-+ dpd->dma_chan_width = ENETDMA_6345_CHAN_WIDTH;
-+ dpd->dma_no_sram = 1;
-+ dpd->dma_desc_shift = ENETDMA_6345_DESC_SHIFT;
-+ } else
-+ dpd->dma_chan_width = ENETDMA_CHAN_WIDTH;
-+
- ret = platform_device_register(pdev);
- if (ret)
- return ret;
-@@ -246,6 +299,10 @@ bcm63xx_enetsw_register(const struct bcm
- else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
- enetsw_pd.num_ports = ENETSW_PORTS_6368;
-
-+ enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
-+ enetsw_pd.dma_chan_en_mask = ENETDMAC_CHANCFG_EN_MASK;
-+ enetsw_pd.dma_chan_int_mask = ENETDMAC_IR_PKTDONE_MASK;
-+
- ret = platform_device_register(&bcm63xx_enetsw_device);
- if (ret)
- return ret;
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -175,6 +175,7 @@ enum bcm63xx_regs_set {
- #define BCM_6368_RSET_SPI_SIZE 1804
- #define RSET_ENET_SIZE 2048
- #define RSET_ENETDMA_SIZE 256
-+#define RSET_6345_ENETDMA_SIZE 64
- #define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
- #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
- #define RSET_ENETSW_SIZE 65536
-@@ -305,7 +306,7 @@ enum bcm63xx_regs_set {
- #define BCM_6345_USBDMA_BASE (0xfffe2800)
- #define BCM_6345_ENET0_BASE (0xfffe1800)
- #define BCM_6345_ENETDMA_BASE (0xfffe2800)
--#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
-+#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
- #define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
- #define BCM_6345_ENETSW_BASE (0xdeadbeef)
- #define BCM_6345_PCMCIA_BASE (0xfffe2028)
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
-@@ -4,6 +4,8 @@
- #include <linux/if_ether.h>
- #include <linux/init.h>
-
-+#include <bcm63xx_regs.h>
-+
- /*
- * on board ethernet platform data
- */
-@@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
- int phy_id, int reg),
- void (*mii_write)(struct net_device *dev,
- int phy_id, int reg, int val));
-+
-+ /* DMA channel enable mask */
-+ u32 dma_chan_en_mask;
-+
-+ /* DMA channel interrupt mask */
-+ u32 dma_chan_int_mask;
-+
-+ /* Set to one if DMA engine has *no* SRAM */
-+ unsigned int dma_no_sram;
-+
-+ /* DMA channel register width */
-+ unsigned int dma_chan_width;
-+
-+ /* DMA descriptor shift */
-+ unsigned int dma_desc_shift;
- };
-
- /*
-@@ -63,6 +80,15 @@ struct bcm63xx_enetsw_platform_data {
- char mac_addr[ETH_ALEN];
- int num_ports;
- struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
-+
-+ /* DMA channel enable mask */
-+ u32 dma_chan_en_mask;
-+
-+ /* DMA channel interrupt mask */
-+ u32 dma_chan_int_mask;
-+
-+ /* DMA channel register width */
-+ unsigned int dma_chan_width;
- };
-
- int __init bcm63xx_enet_register(int unit,
-@@ -70,4 +96,69 @@ int __init bcm63xx_enet_register(int uni
-
- int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
-
-+enum bcm63xx_regs_enetdmac {
-+ ENETDMAC_CHANCFG,
-+ ENETDMAC_IR,
-+ ENETDMAC_IRMASK,
-+ ENETDMAC_MAXBURST,
-+ ENETDMAC_BUFALLOC,
-+ ENETDMAC_RSTART,
-+ ENETDMAC_FC,
-+ ENETDMAC_LEN,
-+};
-+
-+static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
-+{
-+#ifdef BCMCPU_RUNTIME_DETECT
-+ extern const unsigned long *bcm63xx_regs_enetdmac;
-+
-+ return bcm63xx_regs_enetdmac[reg];
-+#else
-+#ifdef CONFIG_BCM63XX_CPU_6345
-+ switch (reg) {
-+ case ENETDMAC_CHANCFG:
-+ return ENETDMA_6345_CHANCFG_REG;
-+ case ENETDMAC_IR:
-+ return ENETDMA_6345_IR_REG;
-+ case ENETDMAC_IRMASK:
-+ return ENETDMA_6345_IRMASK_REG;
-+ case ENETDMAC_MAXBURST:
-+ return ENETDMA_6345_MAXBURST_REG;
-+ case ENETDMAC_BUFALLOC:
-+ return ENETDMA_6345_BUFALLOC_REG;
-+ case ENETDMAC_RSTART:
-+ return ENETDMA_6345_RSTART_REG;
-+ case ENETDMAC_FC:
-+ return ENETDMA_6345_FC_REG;
-+ case ENETDMAC_LEN:
-+ return ENETDMA_6345_LEN_REG;
-+ }
-+#endif
-+#if defined(CONFIG_BCM63XX_CPU_6328) || \
-+ defined(CONFIG_BCM63XX_CPU_6338) || \
-+ defined(CONFIG_BCM63XX_CPU_6348) || \
-+ defined(CONFIG_BCM63XX_CPU_6358) || \
-+ defined(CONFIG_BCM63XX_CPU_6362) || \
-+ defined(CONFIG_BCM63XX_CPU_6368)
-+ switch (reg) {
-+ case ENETDMAC_CHANCFG:
-+ return ENETDMAC_CHANCFG_REG;
-+ case ENETDMAC_IR:
-+ return ENETDMAC_IR_REG;
-+ case ENETDMAC_IRMASK:
-+ return ENETDMAC_IRMASK_REG;
-+ case ENETDMAC_MAXBURST:
-+ return ENETDMAC_MAXBURST_REG;
-+ case ENETDMAC_BUFALLOC:
-+ case ENETDMAC_RSTART:
-+ case ENETDMAC_FC:
-+ case ENETDMAC_LEN:
-+ return 0;
-+ }
-+#endif
-+#endif
-+ return 0;
-+}
-+
-+
- #endif /* ! BCM63XX_DEV_ENET_H_ */
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -730,6 +730,8 @@
- /*************************************************************************
- * _REG relative to RSET_ENETDMA
- *************************************************************************/
-+#define ENETDMA_CHAN_WIDTH 0x10
-+#define ENETDMA_6345_CHAN_WIDTH 0x40
-
- /* Controller Configuration Register */
- #define ENETDMA_CFG_REG (0x0)
-@@ -785,31 +787,56 @@
- /* State Ram Word 4 */
- #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
-
-+/* Broadcom 6345 ENET DMA definitions */
-+#define ENETDMA_6345_CHANCFG_REG (0x00)
-+
-+#define ENETDMA_6345_MAXBURST_REG (0x40)
-+
-+#define ENETDMA_6345_RSTART_REG (0x08)
-+
-+#define ENETDMA_6345_LEN_REG (0x0C)
-+
-+#define ENETDMA_6345_IR_REG (0x14)
-+
-+#define ENETDMA_6345_IRMASK_REG (0x18)
-+
-+#define ENETDMA_6345_FC_REG (0x1C)
-+
-+#define ENETDMA_6345_BUFALLOC_REG (0x20)
-+
-+/* Shift down for EOP, SOP and WRAP bits */
-+#define ENETDMA_6345_DESC_SHIFT (3)
-
- /*************************************************************************
- * _REG relative to RSET_ENETDMAC
- *************************************************************************/
-
- /* Channel Configuration register */
--#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
-+#define ENETDMAC_CHANCFG_REG (0x0)
- #define ENETDMAC_CHANCFG_EN_SHIFT 0
- #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
- #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
- #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
- #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
- #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
-+#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
-+#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
-+#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
-+#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
-+#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
-+#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
-
- /* Interrupt Control/Status register */
--#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
-+#define ENETDMAC_IR_REG (0x4)
- #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
- #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
- #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
-
- /* Interrupt Mask register */
--#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
-+#define ENETDMAC_IRMASK_REG (0x8)
-
- /* Maximum Burst Length */
--#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
-+#define ENETDMAC_MAXBURST_REG (0xc)
-
-
- /*************************************************************************
-@@ -817,16 +844,16 @@
- *************************************************************************/
-
- /* Ring Start Address register */
--#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
-+#define ENETDMAS_RSTART_REG (0x0)
-
- /* State Ram Word 2 */
--#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
-+#define ENETDMAS_SRAM2_REG (0x4)
-
- /* State Ram Word 3 */
--#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
-+#define ENETDMAS_SRAM3_REG (0x8)
-
- /* State Ram Word 4 */
--#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
-+#define ENETDMAS_SRAM4_REG (0xc)
-
-
- /*************************************************************************
---- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
-@@ -115,26 +115,28 @@ static inline void enet_dma_writel(struc
- bcm_writel(val, bcm_enet_shared_base[0] + off);
- }
-
--static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
-+static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
- {
-- return bcm_readl(bcm_enet_shared_base[1] + off);
-+ return bcm_readl(bcm_enet_shared_base[1] +
-+ (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
- }
-
- static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
-- u32 val, u32 off)
-+ u32 val, u32 off, int chan)
- {
-- bcm_writel(val, bcm_enet_shared_base[1] + off);
-+ bcm_writel(val, bcm_enet_shared_base[1] +
-+ (bcm63xx_enetdmacreg(off) + (chan * priv->dma_chan_width)));
- }
-
--static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
-+static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
- {
-- return bcm_readl(bcm_enet_shared_base[2] + off);
-+ return bcm_readl(bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
- }
-
- static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
-- u32 val, u32 off)
-+ u32 val, u32 off, int chan)
- {
-- bcm_writel(val, bcm_enet_shared_base[2] + off);
-+ bcm_writel(val, bcm_enet_shared_base[2] + (off + (chan * priv->dma_chan_width)));
- }
-
- /*
-@@ -270,7 +272,7 @@ static int bcm_enet_refill_rx(struct net
- len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
- len_stat |= DMADESC_OWNER_MASK;
- if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
-- len_stat |= DMADESC_WRAP_MASK;
-+ len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
- priv->rx_dirty_desc = 0;
- } else {
- priv->rx_dirty_desc++;
-@@ -281,7 +283,10 @@ static int bcm_enet_refill_rx(struct net
- priv->rx_desc_count++;
-
- /* tell dma engine we allocated one buffer */
-- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
-+ if (!priv->dma_no_sram)
-+ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
-+ else
-+ enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
- }
-
- /* If rx ring is still empty, set a timer to try allocating
-@@ -357,7 +362,8 @@ static int bcm_enet_receive_queue(struct
-
- /* if the packet does not have start of packet _and_
- * end of packet flag set, then just recycle it */
-- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
-+ if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
-+ (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
- dev->stats.rx_dropped++;
- continue;
- }
-@@ -418,8 +424,8 @@ static int bcm_enet_receive_queue(struct
- bcm_enet_refill_rx(dev);
-
- /* kick rx dma */
-- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-- ENETDMAC_CHANCFG_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_en_mask,
-+ ENETDMAC_CHANCFG, priv->rx_chan);
- }
-
- return processed;
-@@ -494,10 +500,10 @@ static int bcm_enet_poll(struct napi_str
- dev = priv->net_dev;
-
- /* ack interrupts */
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IR_REG(priv->rx_chan));
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IR_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IR, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IR, priv->tx_chan);
-
- /* reclaim sent skb */
- tx_work_done = bcm_enet_tx_reclaim(dev, 0);
-@@ -516,10 +522,10 @@ static int bcm_enet_poll(struct napi_str
- napi_complete(napi);
-
- /* restore rx/tx interrupt */
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IRMASK, priv->tx_chan);
-
- return rx_work_done;
- }
-@@ -562,8 +568,8 @@ static irqreturn_t bcm_enet_isr_dma(int
- priv = netdev_priv(dev);
-
- /* mask rx/tx interrupts */
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
-
- napi_schedule(&priv->napi);
-
-@@ -624,14 +630,14 @@ static int bcm_enet_start_xmit(struct sk
- DMA_TO_DEVICE);
-
- len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
-- len_stat |= DMADESC_ESOP_MASK |
-+ len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
- DMADESC_APPEND_CRC |
- DMADESC_OWNER_MASK;
-
- priv->tx_curr_desc++;
- if (priv->tx_curr_desc == priv->tx_ring_size) {
- priv->tx_curr_desc = 0;
-- len_stat |= DMADESC_WRAP_MASK;
-+ len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
- }
- priv->tx_desc_count--;
-
-@@ -642,8 +648,8 @@ static int bcm_enet_start_xmit(struct sk
- wmb();
-
- /* kick tx dma */
-- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-- ENETDMAC_CHANCFG_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_en_mask,
-+ ENETDMAC_CHANCFG, priv->tx_chan);
-
- /* stop queue if no more desc available */
- if (!priv->tx_desc_count)
-@@ -771,6 +777,9 @@ static void bcm_enet_set_flow(struct bcm
- val &= ~ENET_RXCFG_ENFLOW_MASK;
- enet_writel(priv, val, ENET_RXCFG_REG);
-
-+ if (priv->dma_no_sram)
-+ return;
-+
- /* tx flow control (pause frame generation) */
- val = enet_dma_readl(priv, ENETDMA_CFG_REG);
- if (tx_en)
-@@ -886,8 +895,8 @@ static int bcm_enet_open(struct net_devi
-
- /* mask all interrupts and request them */
- enet_writel(priv, 0, ENET_IRMASK_REG);
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
-
- ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
- if (ret)
-@@ -964,8 +973,12 @@ static int bcm_enet_open(struct net_devi
- priv->rx_curr_desc = 0;
-
- /* initialize flow control buffer allocation */
-- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
-- ENETDMA_BUFALLOC_REG(priv->rx_chan));
-+ if (!priv->dma_no_sram)
-+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
-+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
-+ else
-+ enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
-+ ENETDMAC_BUFALLOC, priv->rx_chan);
-
- if (bcm_enet_refill_rx(dev)) {
- dev_err(kdev, "cannot allocate rx skb queue\n");
-@@ -974,18 +987,30 @@ static int bcm_enet_open(struct net_devi
- }
-
- /* write rx & tx ring addresses */
-- enet_dmas_writel(priv, priv->rx_desc_dma,
-- ENETDMAS_RSTART_REG(priv->rx_chan));
-- enet_dmas_writel(priv, priv->tx_desc_dma,
-- ENETDMAS_RSTART_REG(priv->tx_chan));
-+ if (!priv->dma_no_sram) {
-+ enet_dmas_writel(priv, priv->rx_desc_dma,
-+ ENETDMAS_RSTART_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, priv->tx_desc_dma,
-+ ENETDMAS_RSTART_REG, priv->tx_chan);
-+ } else {
-+ enet_dmac_writel(priv, priv->rx_desc_dma,
-+ ENETDMAC_RSTART, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->tx_desc_dma,
-+ ENETDMAC_RSTART, priv->tx_chan);
-+ }
-
- /* clear remaining state ram for rx & tx channel */
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
-+ if (!priv->dma_no_sram) {
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
-+ } else {
-+ enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
-+ enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
-+ }
-
- /* set max rx/tx length */
- enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
-@@ -993,18 +1018,24 @@ static int bcm_enet_open(struct net_devi
-
- /* set dma maximum burst len */
- enet_dmac_writel(priv, priv->dma_maxburst,
-- ENETDMAC_MAXBURST_REG(priv->rx_chan));
-+ ENETDMAC_MAXBURST, priv->rx_chan);
- enet_dmac_writel(priv, priv->dma_maxburst,
-- ENETDMAC_MAXBURST_REG(priv->tx_chan));
-+ ENETDMAC_MAXBURST, priv->tx_chan);
-
- /* set correct transmit fifo watermark */
- enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
-
- /* set flow control low/high threshold to 1/3 / 2/3 */
-- val = priv->rx_ring_size / 3;
-- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
-- val = (priv->rx_ring_size * 2) / 3;
-- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
-+ if (!priv->dma_no_sram) {
-+ val = priv->rx_ring_size / 3;
-+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
-+ val = (priv->rx_ring_size * 2) / 3;
-+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
-+ } else {
-+ enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
-+ }
-
- /* all set, enable mac and interrupts, start dma engine and
- * kick rx dma channel */
-@@ -1013,26 +1044,26 @@ static int bcm_enet_open(struct net_devi
- val |= ENET_CTL_ENABLE_MASK;
- enet_writel(priv, val, ENET_CTL_REG);
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
-- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-- ENETDMAC_CHANCFG_REG(priv->rx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_en_mask,
-+ ENETDMAC_CHANCFG, priv->rx_chan);
-
- /* watch "mib counters about to overflow" interrupt */
- enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
- enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
-
- /* watch "packet transferred" interrupt in rx and tx */
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IR_REG(priv->rx_chan));
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IR_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IR, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IR, priv->tx_chan);
-
- /* make sure we enable napi before rx interrupt */
- napi_enable(&priv->napi);
-
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, priv->dma_chan_int_mask,
-+ ENETDMAC_IRMASK, priv->tx_chan);
-
- if (priv->has_phy)
- phy_start(priv->phydev);
-@@ -1109,13 +1140,13 @@ static void bcm_enet_disable_dma(struct
- {
- int limit;
-
-- enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
-
- limit = 1000;
- do {
- u32 val;
-
-- val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
-+ val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
- if (!(val & ENETDMAC_CHANCFG_EN_MASK))
- break;
- udelay(1);
-@@ -1142,8 +1173,8 @@ static int bcm_enet_stop(struct net_devi
-
- /* mask all interrupts */
- enet_writel(priv, 0, ENET_IRMASK_REG);
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
-
- /* make sure no mib update is scheduled */
- cancel_work_sync(&priv->mib_update_task);
-@@ -1751,6 +1782,11 @@ static int bcm_enet_probe(struct platfor
- priv->pause_tx = pd->pause_tx;
- priv->force_duplex_full = pd->force_duplex_full;
- priv->force_speed_100 = pd->force_speed_100;
-+ priv->dma_chan_en_mask = pd->dma_chan_en_mask;
-+ priv->dma_chan_int_mask = pd->dma_chan_int_mask;
-+ priv->dma_chan_width = pd->dma_chan_width;
-+ priv->dma_no_sram = pd->dma_no_sram;
-+ priv->dma_desc_shift = pd->dma_desc_shift;
- }
-
- if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
-@@ -2122,8 +2158,8 @@ static int bcm_enetsw_open(struct net_de
- kdev = &priv->pdev->dev;
-
- /* mask all interrupts and request them */
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
-
- ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
- IRQF_DISABLED, dev->name, dev);
-@@ -2247,23 +2283,23 @@ static int bcm_enetsw_open(struct net_de
-
- /* write rx & tx ring addresses */
- enet_dmas_writel(priv, priv->rx_desc_dma,
-- ENETDMAS_RSTART_REG(priv->rx_chan));
-+ ENETDMAS_RSTART_REG, priv->rx_chan);
- enet_dmas_writel(priv, priv->tx_desc_dma,
-- ENETDMAS_RSTART_REG(priv->tx_chan));
-+ ENETDMAS_RSTART_REG, priv->tx_chan);
-
- /* clear remaining state ram for rx & tx channel */
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
-- enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
-+ enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
-
- /* set dma maximum burst len */
- enet_dmac_writel(priv, priv->dma_maxburst,
-- ENETDMAC_MAXBURST_REG(priv->rx_chan));
-+ ENETDMAC_MAXBURST, priv->rx_chan);
- enet_dmac_writel(priv, priv->dma_maxburst,
-- ENETDMAC_MAXBURST_REG(priv->tx_chan));
-+ ENETDMAC_MAXBURST, priv->tx_chan);
-
- /* set flow control low/high threshold to 1/3 / 2/3 */
- val = priv->rx_ring_size / 3;
-@@ -2276,21 +2312,21 @@ static int bcm_enetsw_open(struct net_de
- wmb();
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
- enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
-- ENETDMAC_CHANCFG_REG(priv->rx_chan));
-+ ENETDMAC_CHANCFG, priv->rx_chan);
-
- /* watch "packet transferred" interrupt in rx and tx */
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IR_REG(priv->rx_chan));
-+ ENETDMAC_IR, priv->rx_chan);
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IR_REG(priv->tx_chan));
-+ ENETDMAC_IR, priv->tx_chan);
-
- /* make sure we enable napi before rx interrupt */
- napi_enable(&priv->napi);
-
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IRMASK_REG(priv->rx_chan));
-+ ENETDMAC_IRMASK, priv->rx_chan);
- enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
-- ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ ENETDMAC_IRMASK, priv->tx_chan);
-
- netif_carrier_on(dev);
- netif_start_queue(dev);
-@@ -2396,8 +2432,8 @@ static int bcm_enetsw_stop(struct net_de
- del_timer_sync(&priv->rx_timeout);
-
- /* mask all interrupts */
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
-- enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
-+ enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
-
- /* disable dma & mac */
- bcm_enet_disable_dma(priv, priv->tx_chan);
-@@ -2735,6 +2771,9 @@ static int bcm_enetsw_probe(struct platf
- memcpy(priv->used_ports, pd->used_ports,
- sizeof (pd->used_ports));
- priv->num_ports = pd->num_ports;
-+ priv->dma_chan_en_mask = pd->dma_chan_en_mask;
-+ priv->dma_chan_int_mask = pd->dma_chan_int_mask;
-+ priv->dma_chan_width = pd->dma_chan_width;
- }
-
- ret = compute_hw_mtu(priv, dev->mtu);
---- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
-+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
-@@ -339,6 +339,21 @@ struct bcm_enet_priv {
- /* used to poll switch port state */
- struct timer_list swphy_poll;
- spinlock_t enetsw_mdio_lock;
-+
-+ /* dma channel enable mask */
-+ u32 dma_chan_en_mask;
-+
-+ /* dma channel interrupt mask */
-+ u32 dma_chan_int_mask;
-+
-+ /* dma engine has *no* internal SRAM */
-+ unsigned int dma_no_sram;
-+
-+ /* dma channel width */
-+ unsigned int dma_chan_width;
-+
-+ /* dma descriptor shift value */
-+ unsigned int dma_desc_shift;
- };
-
- static inline int bcm_enet_port_is_rgmii(int portid)
return;
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -992,7 +992,8 @@ int __init board_register_devices(void)
+@@ -1039,7 +1039,8 @@ int __init board_register_devices(void)
/* register any fixups */
for (i = 0; i < board.has_caldata; i++)
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -993,7 +993,7 @@ int __init board_register_devices(void)
+@@ -1040,7 +1040,7 @@ int __init board_register_devices(void)
/* register any fixups */
for (i = 0; i < board.has_caldata; i++)
pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset,
#include <pci_ath9k_fixup.h>
+#include <pci_rt2x00_fixup.h>
+ #include <uapi/linux/bcm933xx_hcs.h>
#include <uapi/linux/bcm963xx_tag.h>
-
-@@ -991,9 +992,19 @@ int __init board_register_devices(void)
+@@ -1038,9 +1039,19 @@ int __init board_register_devices(void)
}
/* register any fixups */
}
--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -141,7 +141,7 @@ static int __init bcm63xx_detect_flash_t
+@@ -142,7 +142,7 @@ static int __init bcm63xx_detect_flash_t
return 0;
}
#include <bcm63xx_dev_enet.h>
#include "bcm63xx_enet.h"
-@@ -1991,7 +1992,8 @@ static int bcm_enet_remove(struct platfo
+@@ -1983,7 +1984,8 @@ static int bcm_enet_remove(struct platfo
return 0;
}
.probe = bcm_enet_probe,
.remove = bcm_enet_remove,
.driver = {
-@@ -2000,6 +2002,42 @@ struct platform_driver bcm63xx_enet_driv
+@@ -1992,6 +1994,42 @@ struct platform_driver bcm63xx_enet_driv
},
};
/*
* switch mii access callbacks
*/
-@@ -2248,29 +2286,6 @@ static int bcm_enetsw_open(struct net_de
+@@ -2245,29 +2283,6 @@ static int bcm_enetsw_open(struct net_de
enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i));
}
/* initialize flow control buffer allocation */
enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
ENETDMA_BUFALLOC_REG(priv->rx_chan));
-@@ -2738,6 +2753,9 @@ static int bcm_enetsw_probe(struct platf
+@@ -2727,6 +2742,9 @@ static int bcm_enetsw_probe(struct platf
struct bcm63xx_enetsw_platform_data *pd;
struct resource *res_mem;
int ret, irq_rx, irq_tx;
+ u8 val;
/* stop if shared driver failed, assume driver->probe will be
- * called in the same order we register devices (correct ?) */
-@@ -2825,6 +2843,43 @@ static int bcm_enetsw_probe(struct platf
+ * called in the same order we register devices (correct ?)
+@@ -2816,6 +2834,43 @@ static int bcm_enetsw_probe(struct platf
priv->pdev = pdev;
priv->net_dev = dev;
return 0;
out_put_clk:
-@@ -2855,6 +2910,9 @@ static int bcm_enetsw_remove(struct plat
+@@ -2844,6 +2899,9 @@ static int bcm_enetsw_remove(struct plat
priv = netdev_priv(dev);
unregister_netdev(dev);
+++ /dev/null
---- a/arch/mips/bcm63xx/Kconfig
-+++ b/arch/mips/bcm63xx/Kconfig
-@@ -13,6 +13,10 @@ config BCM63XX_EHCI
- select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
- select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
-
-+config BCM63XX_CPU_3368
-+ bool "support 3368 CPU"
-+ select HW_HAS_PCI
-+
- config BCM63XX_CPU_6328
- bool "support 6328 CPU"
- select HW_HAS_PCI
---- a/arch/mips/bcm63xx/cpu.c
-+++ b/arch/mips/bcm63xx/cpu.c
-@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
- static unsigned int bcm63xx_cpu_freq;
- static unsigned int bcm63xx_memory_size;
-
-+static const unsigned long bcm3368_regs_base[] = {
-+ __GEN_CPU_REGS_TABLE(3368)
-+};
-+
-+static const int bcm3368_irqs[] = {
-+ __GEN_CPU_IRQ_TABLE(3368)
-+};
-+
- static const unsigned long bcm6328_regs_base[] = {
- __GEN_CPU_REGS_TABLE(6328)
- };
-@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(voi
- static unsigned int detect_cpu_clock(void)
- {
- switch (bcm63xx_get_cpu_id()) {
-+ case BCM3368_CPU_ID:
-+ return 300000000;
-+
- case BCM6328_CPU_ID:
- {
- unsigned int tmp, mips_pll_fcvo;
-@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(v
- banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
- }
-
-- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
-+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
- val = bcm_memc_readl(MEMC_CFG_REG);
- rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
- cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
-@@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
- chipid_reg = BCM_6345_PERF_BASE;
- break;
- case CPU_BMIPS4350:
-- if ((read_c0_prid() & 0xf0) == 0x10)
-+ switch ((read_c0_prid() & 0xff)) {
-+ case 0x04:
-+ chipid_reg = BCM_3368_PERF_BASE;
-+ break;
-+ case 0x10:
- chipid_reg = BCM_6345_PERF_BASE;
-- else
-+ break;
-+ default:
- chipid_reg = BCM_6368_PERF_BASE;
-+ break;
-+ }
- break;
- }
-
-@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
- bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
-
- switch (bcm63xx_cpu_id) {
-+ case BCM3368_CPU_ID:
-+ bcm63xx_regs_base = bcm3368_regs_base;
-+ bcm63xx_irqs = bcm3368_irqs;
-+ break;
- case BCM6328_CPU_ID:
- bcm63xx_regs_base = bcm6328_regs_base;
- bcm63xx_irqs = bcm6328_irqs;
---- a/arch/mips/bcm63xx/dev-uart.c
-+++ b/arch/mips/bcm63xx/dev-uart.c
-@@ -54,8 +54,8 @@ int __init bcm63xx_uart_register(unsigne
- if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
- return -ENODEV;
-
-- if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
-- !BCMCPU_IS_6368())
-+ if (id == 1 && !BCMCPU_IS_3368() && !BCMCPU_IS_6328() &&
-+ !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
- return -ENODEV;
-
- if (id == 0) {
---- a/arch/mips/bcm63xx/prom.c
-+++ b/arch/mips/bcm63xx/prom.c
-@@ -30,7 +30,9 @@ void __init prom_init(void)
- bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
-
- /* disable all hardware blocks clock for now */
-- if (BCMCPU_IS_6328())
-+ if (BCMCPU_IS_3368())
-+ mask = CKCTL_3368_ALL_SAFE_EN;
-+ else if (BCMCPU_IS_6328())
- mask = CKCTL_6328_ALL_SAFE_EN;
- else if (BCMCPU_IS_6338())
- mask = CKCTL_6338_ALL_SAFE_EN;
---- a/arch/mips/bcm63xx/setup.c
-+++ b/arch/mips/bcm63xx/setup.c
-@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
-
- /* mask and clear all external irq */
- switch (bcm63xx_get_cpu_id()) {
-+ case BCM3368_CPU_ID:
-+ perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
-+ break;
- case BCM6328_CPU_ID:
- perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
- break;
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
-@@ -9,6 +9,7 @@
- * compile time if only one CPU support is enabled (idea stolen from
- * arm mach-types)
- */
-+#define BCM3368_CPU_ID 0x3368
- #define BCM6328_CPU_ID 0x6328
- #define BCM6338_CPU_ID 0x6338
- #define BCM6345_CPU_ID 0x6345
-@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
- u8 bcm63xx_get_cpu_rev(void);
- unsigned int bcm63xx_get_cpu_freq(void);
-
-+#ifdef CONFIG_BCM63XX_CPU_3368
-+# ifdef bcm63xx_get_cpu_id
-+# undef bcm63xx_get_cpu_id
-+# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
-+# define BCMCPU_RUNTIME_DETECT
-+# else
-+# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
-+# endif
-+# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
-+#else
-+# define BCMCPU_IS_3368() (0)
-+#endif
-+
- #ifdef CONFIG_BCM63XX_CPU_6328
- # ifdef bcm63xx_get_cpu_id
- # undef bcm63xx_get_cpu_id
-@@ -196,6 +210,53 @@ enum bcm63xx_regs_set {
- #define RSET_RNG_SIZE 20
-
- /*
-+ * 3368 register sets base address
-+ */
-+#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
-+#define BCM_3368_PERF_BASE (0xfff8c000)
-+#define BCM_3368_TIMER_BASE (0xfff8c040)
-+#define BCM_3368_WDT_BASE (0xfff8c080)
-+#define BCM_3368_UART0_BASE (0xfff8c100)
-+#define BCM_3368_UART1_BASE (0xfff8c120)
-+#define BCM_3368_GPIO_BASE (0xfff8c080)
-+#define BCM_3368_SPI_BASE (0xfff8c800)
-+#define BCM_3368_HSSPI_BASE (0xdeadbeef)
-+#define BCM_3368_UDC0_BASE (0xdeadbeef)
-+#define BCM_3368_USBDMA_BASE (0xdeadbeef)
-+#define BCM_3368_OHCI0_BASE (0xdeadbeef)
-+#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
-+#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
-+#define BCM_3368_USBD_BASE (0xdeadbeef)
-+#define BCM_3368_MPI_BASE (0xfff80000)
-+#define BCM_3368_PCMCIA_BASE (0xfff80054)
-+#define BCM_3368_PCIE_BASE (0xdeadbeef)
-+#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
-+#define BCM_3368_DSL_BASE (0xdeadbeef)
-+#define BCM_3368_UBUS_BASE (0xdeadbeef)
-+#define BCM_3368_ENET0_BASE (0xfff98000)
-+#define BCM_3368_ENET1_BASE (0xfff98800)
-+#define BCM_3368_ENETDMA_BASE (0xfff99800)
-+#define BCM_3368_ENETDMAC_BASE (0xfff99900)
-+#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
-+#define BCM_3368_ENETSW_BASE (0xdeadbeef)
-+#define BCM_3368_EHCI0_BASE (0xdeadbeef)
-+#define BCM_3368_SDRAM_BASE (0xdeadbeef)
-+#define BCM_3368_MEMC_BASE (0xfff84000)
-+#define BCM_3368_DDR_BASE (0xdeadbeef)
-+#define BCM_3368_M2M_BASE (0xdeadbeef)
-+#define BCM_3368_ATM_BASE (0xdeadbeef)
-+#define BCM_3368_XTM_BASE (0xdeadbeef)
-+#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
-+#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
-+#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
-+#define BCM_3368_PCM_BASE (0xfff9c200)
-+#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
-+#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
-+#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
-+#define BCM_3368_RNG_BASE (0xdeadbeef)
-+#define BCM_3368_MISC_BASE (0xdeadbeef)
-+
-+/*
- * 6328 register sets base address
- */
- #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
-@@ -633,6 +694,9 @@ static inline unsigned long bcm63xx_regs
- #ifdef BCMCPU_RUNTIME_DETECT
- return bcm63xx_regs_base[set];
- #else
-+#ifdef CONFIG_BCM63XX_CPU_3368
-+ __GEN_RSET(3368)
-+#endif
- #ifdef CONFIG_BCM63XX_CPU_6328
- __GEN_RSET(6328)
- #endif
-@@ -701,6 +765,52 @@ enum bcm63xx_irq {
- };
-
- /*
-+ * 3368 irqs
-+ */
-+#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
-+#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
-+#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
-+#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
-+#define BCM_3368_DSL_IRQ 0
-+#define BCM_3368_UDC0_IRQ 0
-+#define BCM_3368_OHCI0_IRQ 0
-+#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
-+#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
-+#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
-+#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
-+#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
-+#define BCM_3368_HSSPI_IRQ 0
-+#define BCM_3368_EHCI0_IRQ 0
-+#define BCM_3368_USBD_IRQ 0
-+#define BCM_3368_USBD_RXDMA0_IRQ 0
-+#define BCM_3368_USBD_TXDMA0_IRQ 0
-+#define BCM_3368_USBD_RXDMA1_IRQ 0
-+#define BCM_3368_USBD_TXDMA1_IRQ 0
-+#define BCM_3368_USBD_RXDMA2_IRQ 0
-+#define BCM_3368_USBD_TXDMA2_IRQ 0
-+#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
-+#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
-+#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
-+#define BCM_3368_PCMCIA_IRQ 0
-+#define BCM_3368_ATM_IRQ 0
-+#define BCM_3368_ENETSW_RXDMA0_IRQ 0
-+#define BCM_3368_ENETSW_RXDMA1_IRQ 0
-+#define BCM_3368_ENETSW_RXDMA2_IRQ 0
-+#define BCM_3368_ENETSW_RXDMA3_IRQ 0
-+#define BCM_3368_ENETSW_TXDMA0_IRQ 0
-+#define BCM_3368_ENETSW_TXDMA1_IRQ 0
-+#define BCM_3368_ENETSW_TXDMA2_IRQ 0
-+#define BCM_3368_ENETSW_TXDMA3_IRQ 0
-+#define BCM_3368_XTM_IRQ 0
-+#define BCM_3368_XTM_DMA0_IRQ 0
-+
-+#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
-+#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
-+#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
-+#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
-+
-+
-+/*
- * 6328 irqs
- */
- #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
-@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio
- switch (bcm63xx_get_cpu_id()) {
- case BCM6328_CPU_ID:
- return 32;
-+ case BCM3368_CPU_ID:
- case BCM6358_CPU_ID:
- return 40;
- case BCM6338_CPU_ID:
---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -15,6 +15,39 @@
- /* Clock Control register */
- #define PERF_CKCTL_REG 0x4
-
-+#define CKCTL_3368_MAC_EN (1 << 3)
-+#define CKCTL_3368_TC_EN (1 << 5)
-+#define CKCTL_3368_US_TOP_EN (1 << 6)
-+#define CKCTL_3368_DS_TOP_EN (1 << 7)
-+#define CKCTL_3368_APM_EN (1 << 8)
-+#define CKCTL_3368_SPI_EN (1 << 9)
-+#define CKCTL_3368_USBS_EN (1 << 10)
-+#define CKCTL_3368_BMU_EN (1 << 11)
-+#define CKCTL_3368_PCM_EN (1 << 12)
-+#define CKCTL_3368_NTP_EN (1 << 13)
-+#define CKCTL_3368_ACP_B_EN (1 << 14)
-+#define CKCTL_3368_ACP_A_EN (1 << 15)
-+#define CKCTL_3368_EMUSB_EN (1 << 17)
-+#define CKCTL_3368_ENET0_EN (1 << 18)
-+#define CKCTL_3368_ENET1_EN (1 << 19)
-+#define CKCTL_3368_USBU_EN (1 << 20)
-+#define CKCTL_3368_EPHY_EN (1 << 21)
-+
-+#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
-+ CKCTL_3368_TC_EN | \
-+ CKCTL_3368_US_TOP_EN | \
-+ CKCTL_3368_DS_TOP_EN | \
-+ CKCTL_3368_APM_EN | \
-+ CKCTL_3368_SPI_EN | \
-+ CKCTL_3368_USBS_EN | \
-+ CKCTL_3368_BMU_EN | \
-+ CKCTL_3368_PCM_EN | \
-+ CKCTL_3368_NTP_EN | \
-+ CKCTL_3368_ACP_B_EN | \
-+ CKCTL_3368_ACP_A_EN | \
-+ CKCTL_3368_EMUSB_EN | \
-+ CKCTL_3368_USBU_EN)
-+
- #define CKCTL_6328_PHYMIPS_EN (1 << 0)
- #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
- #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
-@@ -181,6 +214,7 @@
- #define SYS_PLL_SOFT_RESET 0x1
-
- /* Interrupt Mask register */
-+#define PERF_IRQMASK_3368_REG 0xc
- #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
- #define PERF_IRQMASK_6338_REG 0xc
- #define PERF_IRQMASK_6345_REG 0xc
-@@ -190,6 +224,7 @@
- #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
-
- /* Interrupt Status register */
-+#define PERF_IRQSTAT_3368_REG 0x10
- #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
- #define PERF_IRQSTAT_6338_REG 0x10
- #define PERF_IRQSTAT_6345_REG 0x10
-@@ -199,6 +234,7 @@
- #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
-
- /* External Interrupt Configuration register */
-+#define PERF_EXTIRQ_CFG_REG_3368 0x14
- #define PERF_EXTIRQ_CFG_REG_6328 0x18
- #define PERF_EXTIRQ_CFG_REG_6338 0x14
- #define PERF_EXTIRQ_CFG_REG_6345 0x14
-@@ -1386,7 +1422,7 @@
- #define SPI_6348_RX_DATA 0x80
- #define SPI_6348_RX_DATA_SIZE 0x3f
-
--/* BCM 6358/6262/6368 SPI core */
-+/* BCM 3368/6358/6262/6368 SPI core */
- #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
- #define SPI_6358_MSG_CTL_WIDTH 16
- #define SPI_6358_MSG_DATA 0x02
---- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
-+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
-@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(
- static inline int is_bcm63xx_internal_registers(phys_t offset)
- {
- switch (bcm63xx_get_cpu_id()) {
-+ case BCM3368_CPU_ID:
-+ if (offset >= 0xfff80000)
-+ return 1;
-+ break;
- case BCM6338_CPU_ID:
- case BCM6345_CPU_ID:
- case BCM6348_CPU_ID:
---- a/arch/mips/bcm63xx/irq.c
-+++ b/arch/mips/bcm63xx/irq.c
-@@ -33,6 +33,19 @@ static DEFINE_SPINLOCK(ipic_lock);
- static DEFINE_SPINLOCK(epic_lock);
-
- #ifndef BCMCPU_RUNTIME_DETECT
-+#ifdef CONFIG_BCM63XX_CPU_3368
-+#define irq_stat_reg0 PERF_IRQSTAT_3368_REG
-+#define irq_mask_reg0 PERF_IRQMASK_3368_REG
-+#define irq_stat_reg1 0
-+#define irq_mask_reg1 0
-+#define irq_bits 32
-+#define is_ext_irq_cascaded 0
-+#define ext_irq_start 0
-+#define ext_irq_end 0
-+#define ext_irq_count 4
-+#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
-+#define ext_irq_cfg_reg2 0
-+#endif
- #ifdef CONFIG_BCM63XX_CPU_6328
- #define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
- #define irq_mask_reg0 PERF_IRQMASK_6328_REG(0)
-@@ -165,6 +178,13 @@ static void bcm63xx_init_irq(void)
- irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
-
- switch (bcm63xx_get_cpu_id()) {
-+ case BCM3368_CPU_ID:
-+ irq_stat_addr0 += PERF_IRQSTAT_3368_REG;
-+ irq_mask_addr0 += PERF_IRQMASK_3368_REG;
-+ irq_bits = 32;
-+ ext_irq_count = 4;
-+ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
-+ break;
- case BCM6328_CPU_ID:
- irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
- irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
---- a/arch/mips/bcm63xx/dev-spi.c
-+++ b/arch/mips/bcm63xx/dev-spi.c
-@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
- {
- if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
- bcm63xx_regs_spi = bcm6348_regs_spi;
-- if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
-+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
- bcm63xx_regs_spi = bcm6358_regs_spi;
- }
- #else
-@@ -87,7 +87,8 @@ int __init bcm63xx_spi_register(void)
- spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
- }
-
-- if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
-+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
-+ BCMCPU_IS_6368()) {
- spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
- spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
- spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
---- a/arch/mips/bcm63xx/clk.c
-+++ b/arch/mips/bcm63xx/clk.c
-@@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, i
- else
- clk_disable_unlocked(&clk_enet_misc);
-
-- if (BCMCPU_IS_6358()) {
-+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
- u32 mask;
-
- if (clk->id == 0)
-@@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
- */
- static void ephy_set(struct clk *clk, int enable)
- {
-- if (!BCMCPU_IS_6358())
-- return;
-- bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
-+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
-+ bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
- }
-
-
-@@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
- */
- static void pcm_set(struct clk *clk, int enable)
- {
-- if (!BCMCPU_IS_6358())
-- return;
-- bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
-+ if (BCMCPU_IS_3368())
-+ bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
-+ if (BCMCPU_IS_6358())
-+ bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
- }
-
- static struct clk clk_pcm = {
-@@ -221,7 +221,7 @@ static void spi_set(struct clk *clk, int
- mask = CKCTL_6338_SPI_EN;
- else if (BCMCPU_IS_6348())
- mask = CKCTL_6348_SPI_EN;
-- else if (BCMCPU_IS_6358())
-+ else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
- mask = CKCTL_6358_SPI_EN;
- else if (BCMCPU_IS_6362())
- mask = CKCTL_6362_SPI_EN;
-@@ -370,7 +370,7 @@ struct clk *clk_get(struct device *dev,
- return &clk_xtm;
- if (!strcmp(id, "periph"))
- return &clk_periph;
-- if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
-+ if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
- return &clk_pcm;
- if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
- return &clk_ipsec;
---- a/arch/mips/bcm63xx/dev-flash.c
-+++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -102,6 +102,7 @@ static int __init bcm63xx_detect_flash_t
- /* no way to auto detect so assume parallel */
- bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_PARALLEL;
- break;
-+ case BCM3368_CPU_ID:
- case BCM6358_CPU_ID:
- val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
- if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
---- a/arch/mips/pci/pci-bcm63xx.c
-+++ b/arch/mips/pci/pci-bcm63xx.c
-@@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(v
- /* setup PCI to local bus access, used by PCI device to target
- * local RAM while bus mastering */
- bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
-- if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
-+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
- val = MPI_SP0_REMAP_ENABLE_MASK;
- else
- val = 0;
-@@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
- case BCM6328_CPU_ID:
- case BCM6362_CPU_ID:
- return bcm63xx_register_pcie();
-+ case BCM3368_CPU_ID:
- case BCM6348_CPU_ID:
- case BCM6358_CPU_ID:
- case BCM6368_CPU_ID:
+++ /dev/null
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -37,6 +37,7 @@
- #include <pci_rt2x00_fixup.h>
-
- #include <uapi/linux/bcm963xx_tag.h>
-+#include <uapi/linux/bcm933xx_hcs.h>
-
- #define PFX "board_bcm963xx: "
-
-@@ -45,6 +46,7 @@
-
- #define CFE_OFFSET_64K 0x10000
- #define CFE_OFFSET_128K 0x20000
-+#define HCS_OFFSET_128K 0x20000
-
- static struct board_info board;
-
-@@ -782,8 +784,9 @@ void __init board_prom_init(void)
- unsigned int i;
- u8 *boot_addr, *cfe;
- char cfe_version[32];
-- char *board_name;
-+ char *board_name = NULL;
- u32 val;
-+ struct bcm_hcs *hcs;
-
- /* read base address of boot chip select (0)
- * 6328/6362 do not have MPI but boot from a fixed address
-@@ -812,9 +815,13 @@ void __init board_prom_init(void)
- if (strcmp(cfe_version, "unknown") != 0) {
- /* cfe present */
- boardid_fixup(boot_addr);
-+
-+ board_name = bcm63xx_nvram_get_name();
-+ } else if (BCMCPU_IS_3368()) {
-+ hcs = (struct bcm_hcs *)KSEG1ADDR(0x1fc00000 + HCS_OFFSET_128K);
-+ board_name = hcs->filename;
- }
-
-- board_name = bcm63xx_nvram_get_name();
- /* find board by name */
- for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
- if (strncmp(board_name, bcm963xx_boards[i]->name, 16))
---- /dev/null
-+++ b/include/uapi/linux/bcm933xx_hcs.h
-@@ -0,0 +1,18 @@
-+#ifndef __BCM_HCS_H
-+#define __BCM_HCS_H
-+
-+struct bcm_hcs {
-+ uint16_t magic;
-+ uint16_t control;
-+ uint16_t rev_maj;
-+ uint16_t rev_min;
-+ uint32_t build_date;
-+ uint32_t filelen;
-+ uint32_t ldaddress;
-+ char filename[64];
-+ uint16_t hcs;
-+ uint16_t her_znaet_chto;
-+ uint32_t crc;
-+};
-+
-+#endif /* __BCM_HCS */
+++ /dev/null
---- a/arch/mips/bcm63xx/nvram.c
-+++ b/arch/mips/bcm63xx/nvram.c
-@@ -45,6 +45,7 @@ void __init bcm63xx_nvram_init(void *add
- {
- unsigned int check_len;
- u32 crc, expected_crc;
-+ u8 hcs_mac_addr[ETH_ALEN] = { 0x00, 0x10, 0x18, 0xff, 0xff, 0xff };
-
- /* extract nvram data */
- memcpy(&nvram, addr, sizeof(nvram));
-@@ -65,6 +66,15 @@ void __init bcm63xx_nvram_init(void *add
- if (crc != expected_crc)
- pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
- expected_crc, crc);
-+
-+ /* Cable modems have a different NVRAM which is embedded in the eCos
-+ * firmware and not easily extractible, give at least a MAC address
-+ * pool.
-+ */
-+ if (BCMCPU_IS_3368()) {
-+ memcpy(nvram.mac_addr_base, hcs_mac_addr, ETH_ALEN);
-+ nvram.mac_addr_count = 2;
-+ }
- }
-
- u8 *bcm63xx_nvram_get_name(void)
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -522,6 +522,56 @@ static struct board_info __initdata boar
+@@ -555,6 +555,56 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
};
#endif
/*
-@@ -696,6 +746,7 @@ static const struct board_info __initcon
+@@ -732,6 +782,7 @@ static const struct board_info __initcon
&board_DV201AMR,
&board_96348gw_a,
&board_rta1025w_16,
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
-@@ -48,6 +50,12 @@
+@@ -49,6 +51,12 @@
+ #define CFE_OFFSET_64K 0x10000
#define CFE_OFFSET_128K 0x20000
- #define HCS_OFFSET_128K 0x20000
+#define NB4_PID_OFFSET 0xff80
+#define NB4_74X164_GPIO_BASE 64
static struct board_info board;
/*
-@@ -721,6 +729,596 @@ static struct board_info __initdata boar
+@@ -754,6 +762,596 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
};
#endif
/*
-@@ -754,6 +1352,11 @@ static const struct board_info __initcon
+@@ -790,6 +1388,11 @@ static const struct board_info __initcon
&board_96358vw2,
&board_AGPFS0,
&board_DWVS0,
#endif
};
-@@ -808,6 +1411,16 @@ static void __init boardid_fixup(u8 *boo
+@@ -844,6 +1447,16 @@ static void __init boardid_fixup(u8 *boo
struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K);
char *board_name = (char *)bcm63xx_nvram_get_name();
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -193,6 +193,40 @@ static struct board_info __initdata boar
+@@ -226,6 +226,40 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -1331,6 +1365,7 @@ static const struct board_info __initcon
+@@ -1367,6 +1401,7 @@ static const struct board_info __initcon
#ifdef CONFIG_BCM63XX_CPU_6338
&board_96338gw,
&board_96338w,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -720,6 +720,98 @@ static struct board_info __initdata boar
+@@ -753,6 +753,98 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_AGPFS0 = {
.name = "AGPF-S0",
.expected_cpu_id = 0x6358,
-@@ -1386,6 +1478,7 @@ static const struct board_info __initcon
+@@ -1422,6 +1514,7 @@ static const struct board_info __initcon
&board_96358vw,
&board_96358vw2,
&board_AGPFS0,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -856,6 +856,61 @@ static struct board_info __initdata boar
+@@ -889,6 +889,61 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
};
struct spi_gpio_platform_data nb4_spi_gpio_data = {
.sck = NB4_SPI_GPIO_CLK,
.mosi = NB4_SPI_GPIO_MOSI,
-@@ -1480,6 +1535,7 @@ static const struct board_info __initcon
+@@ -1516,6 +1571,7 @@ static const struct board_info __initcon
&board_AGPFS0,
&board_CPVA642,
&board_DWVS0,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -614,6 +614,67 @@ static struct board_info __initdata boar
+@@ -647,6 +647,67 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -1527,6 +1588,7 @@ static const struct board_info __initcon
+@@ -1563,6 +1624,7 @@ static const struct board_info __initcon
&board_96348gw_a,
&board_rta1025w_16,
&board_96348_D4PW,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -481,6 +481,112 @@ static struct board_info __initdata boar
+@@ -514,6 +514,112 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_FAST2404 = {
.name = "F@ST2404",
.expected_cpu_id = 0x6348,
-@@ -1581,6 +1687,8 @@ static const struct board_info __initcon
+@@ -1617,6 +1723,8 @@ static const struct board_info __initcon
#ifdef CONFIG_BCM63XX_CPU_6348
&board_96348r,
&board_96348gw,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -781,6 +781,78 @@ static struct board_info __initdata boar
+@@ -814,6 +814,78 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -1697,6 +1769,7 @@ static const struct board_info __initcon
+@@ -1733,6 +1805,7 @@ static const struct board_info __initcon
&board_rta1025w_16,
&board_96348_D4PW,
&board_spw500v,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1739,6 +1739,82 @@ static struct board_info __initdata boar
+@@ -1772,6 +1772,82 @@ static struct board_info __initdata boar
.spis = nb4_spi_devices,
.num_spis = ARRAY_SIZE(nb4_spi_devices),
};
#endif
/*
-@@ -1784,6 +1860,7 @@ static const struct board_info __initcon
+@@ -1820,6 +1896,7 @@ static const struct board_info __initcon
&board_nb4_ser_r2,
&board_nb4_fxc_r1,
&board_nb4_fxc_r2,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -227,6 +227,45 @@ static struct board_info __initdata boar
+@@ -260,6 +260,45 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -1828,6 +1867,7 @@ static const struct board_info __initcon
+@@ -1864,6 +1903,7 @@ static const struct board_info __initcon
&board_96338gw,
&board_96338w,
&board_96338w2_e7t,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1854,6 +1854,72 @@ static struct board_info __initdata boar
+@@ -1887,6 +1887,72 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -1901,6 +1967,7 @@ static const struct board_info __initcon
+@@ -1937,6 +2003,7 @@ static const struct board_info __initcon
&board_nb4_fxc_r1,
&board_nb4_fxc_r2,
&board_HW553,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -892,6 +892,65 @@ static struct board_info __initdata boar
+@@ -925,6 +925,65 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -1952,6 +2011,7 @@ static const struct board_info __initcon
+@@ -1988,6 +2047,7 @@ static const struct board_info __initcon
&board_96348_D4PW,
&board_spw500v,
&board_96348sv,
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
-@@ -2073,6 +2133,22 @@ void __init board_prom_init(void)
+@@ -2109,6 +2169,22 @@ void __init board_prom_init(void)
val &= MPI_CSBASE_BASE_MASK;
}
boot_addr = (u8 *)KSEG1ADDR(val);
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -452,6 +452,64 @@ static struct board_info __initdata boar
+@@ -485,6 +485,64 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_96348gw = {
.name = "96348GW",
.expected_cpu_id = 0x6348,
-@@ -2012,6 +2070,7 @@ static const struct board_info __initcon
+@@ -2048,6 +2106,7 @@ static const struct board_info __initcon
&board_spw500v,
&board_96348sv,
&board_V2500V_BB,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -510,6 +510,51 @@ static struct board_info __initdata boar
+@@ -543,6 +543,51 @@ static struct board_info __initdata boar
};
static struct board_info __initdata board_96348gw = {
.name = "96348GW",
.expected_cpu_id = 0x6348,
-@@ -2071,6 +2116,7 @@ static const struct board_info __initcon
+@@ -2107,6 +2152,7 @@ static const struct board_info __initcon
&board_96348sv,
&board_V2500V_BB,
&board_V2110,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1279,6 +1279,8 @@ static struct board_info __initdata boar
+@@ -1312,6 +1312,8 @@ static struct board_info __initdata boar
.name = "DWV-S0",
.expected_cpu_id = 0x6358,
.has_enet0 = 1,
.has_enet1 = 1,
.has_pci = 1,
-@@ -1294,6 +1296,7 @@ static struct board_info __initdata boar
+@@ -1327,6 +1329,7 @@ static struct board_info __initdata boar
},
.has_ohci0 = 1,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -555,6 +555,69 @@ static struct board_info __initdata boar
+@@ -588,6 +588,69 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_96348gw = {
.name = "96348GW",
.expected_cpu_id = 0x6348,
-@@ -2120,6 +2183,7 @@ static const struct board_info __initcon
+@@ -2156,6 +2219,7 @@ static const struct board_info __initcon
&board_V2500V_BB,
&board_V2110,
&board_ct536_ct5621,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -820,6 +820,7 @@ static struct board_info __initdata boar
+@@ -853,6 +853,7 @@ static struct board_info __initdata boar
.name = "RTA1025W_16",
.expected_cpu_id = 0x6348,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1118,6 +1118,46 @@ static struct board_info __initdata boar
+@@ -1151,6 +1151,46 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -2185,6 +2225,7 @@ static const struct board_info __initcon
+@@ -2221,6 +2261,7 @@ static const struct board_info __initcon
&board_V2110,
&board_ct536_ct5621,
&board_96348A_122,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -2192,6 +2192,78 @@ static struct board_info __initdata boar
+@@ -2225,6 +2225,78 @@ static struct board_info __initdata boar
#endif
/*
* all boards
*/
static const struct board_info __initconst *bcm963xx_boards[] = {
-@@ -2243,6 +2315,10 @@ static const struct board_info __initcon
+@@ -2279,6 +2351,10 @@ static const struct board_info __initcon
&board_HW553,
&board_spw303v,
#endif
};
/*
-@@ -2416,12 +2492,25 @@ void __init board_prom_init(void)
+@@ -2452,12 +2528,25 @@ void __init board_prom_init(void)
bcm63xx_pci_enabled = 1;
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G2_PCI;
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -2261,6 +2261,72 @@ static struct board_info __initdata boar
+@@ -2294,6 +2294,72 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
.has_ehci0 = 1,
};
#endif
/*
-@@ -2318,6 +2384,7 @@ static const struct board_info __initcon
+@@ -2354,6 +2420,7 @@ static const struct board_info __initcon
#ifdef CONFIG_BCM63XX_CPU_6368
&board_96368mvwg,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -75,13 +75,45 @@ static struct board_info __initdata boar
+@@ -108,13 +108,45 @@ static struct board_info __initdata boar
.port_no = 0,
},
.name = "96328avng::power",
.gpio = 4,
.active_low = 1,
-@@ -98,7 +130,7 @@ static struct board_info __initdata boar
+@@ -131,7 +163,7 @@ static struct board_info __initdata boar
.active_low = 1,
},
{
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -136,6 +136,76 @@ static struct board_info __initdata boar
+@@ -169,6 +169,76 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -2367,6 +2437,7 @@ static struct board_info __initdata boar
- static const struct board_info __initconst *bcm963xx_boards[] = {
+@@ -2403,6 +2473,7 @@ static const struct board_info __initcon
+ #endif
#ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng,
+ &board_963281TAN,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -206,6 +206,111 @@ static struct board_info __initdata boar
+@@ -239,6 +239,111 @@ static struct board_info __initdata boar
},
};
#endif
/*
-@@ -2438,6 +2543,7 @@ static const struct board_info __initcon
+@@ -2474,6 +2579,7 @@ static const struct board_info __initcon
#ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng,
&board_963281TAN,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1365,6 +1365,59 @@ static struct board_info __initdata boar
+@@ -1398,6 +1398,59 @@ static struct board_info __initdata boar
},
};
#endif
/*
-@@ -2573,6 +2626,7 @@ static const struct board_info __initcon
+@@ -2609,6 +2662,7 @@ static const struct board_info __initcon
&board_ct536_ct5621,
&board_96348A_122,
&board_CPVA502plus,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -56,6 +56,13 @@
+@@ -57,6 +57,13 @@
#define NB4_SPI_GPIO_CLK 6
#define NB4_74HC64_GPIO(X) (NB4_74X164_GPIO_BASE + (X))
static struct board_info board;
/*
-@@ -2308,6 +2315,113 @@ static struct board_info __initdata boar
+@@ -2341,6 +2348,113 @@ static struct board_info __initdata boar
.num_spis = ARRAY_SIZE(nb4_spi_devices),
};
static struct board_info __initdata board_HW553 = {
.name = "HW553",
.expected_cpu_id = 0x6358,
-@@ -2641,6 +2755,7 @@ static const struct board_info __initcon
+@@ -2677,6 +2791,7 @@ static const struct board_info __initcon
&board_nb4_ser_r2,
&board_nb4_fxc_r1,
&board_nb4_fxc_r2,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -2563,6 +2563,73 @@ static struct board_info __initdata boar
+@@ -2596,6 +2596,73 @@ static struct board_info __initdata boar
},
}
};
#endif
/*
-@@ -2758,6 +2825,7 @@ static const struct board_info __initcon
+@@ -2794,6 +2861,7 @@ static const struct board_info __initcon
&board_ct6373_1,
&board_HW553,
&board_spw303v,
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
-@@ -55,6 +56,8 @@
+@@ -56,6 +57,8 @@
#define NB4_SPI_GPIO_MOSI 7
#define NB4_SPI_GPIO_CLK 6
#define NB4_74HC64_GPIO(X) (NB4_74X164_GPIO_BASE + (X))
#define CT6373_PID_OFFSET 0xff80
#define CT6373_74X164_GPIO_BASE 64
-@@ -2632,6 +2635,103 @@ static struct board_info __initdata boar
+@@ -2665,6 +2668,103 @@ static struct board_info __initdata boar
};
#endif
/*
* known 6368 boards
*/
-@@ -2828,6 +2928,10 @@ static const struct board_info __initcon
+@@ -2864,6 +2964,10 @@ static const struct board_info __initcon
&board_DVAG3810BN,
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
&board_96368mvwg,
&board_96368mvngr,
-@@ -2895,6 +2999,11 @@ static void __init boardid_fixup(u8 *boo
+@@ -2931,6 +3035,11 @@ static void __init boardid_fixup(u8 *boo
}
}
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1033,6 +1033,57 @@ static struct board_info __initdata boar
+@@ -1066,6 +1066,57 @@ static struct board_info __initdata boar
.has_ehci0 = 1,
};
static struct board_info __initdata board_rta1025w_16 = {
.name = "RTA1025W_16",
.expected_cpu_id = 0x6348,
-@@ -2896,6 +2947,7 @@ static const struct board_info __initcon
+@@ -2932,6 +2983,7 @@ static const struct board_info __initcon
&board_96348gw_10,
&board_96348gw_11,
&board_FAST2404,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -217,6 +217,125 @@ static struct board_info __initdata boar
+@@ -250,6 +250,125 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_dsl_274xb_f1 = {
.name = "AW4339U",
.expected_cpu_id = 0x6328,
-@@ -2928,6 +3047,7 @@ static const struct board_info __initcon
+@@ -2964,6 +3083,7 @@ static const struct board_info __initcon
#ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng,
&board_963281TAN,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -147,6 +147,78 @@ static struct board_info __initdata boar
+@@ -180,6 +180,78 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_963281TAN = {
.name = "963281TAN",
.expected_cpu_id = 0x6328,
-@@ -3046,6 +3118,7 @@ static struct board_info __initdata boar
- static const struct board_info __initconst *bcm963xx_boards[] = {
+@@ -3082,6 +3154,7 @@ static const struct board_info __initcon
+ #endif
#ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng,
+ &board_96328A_1441N1,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -147,6 +147,72 @@ static struct board_info __initdata boar
+@@ -180,6 +180,72 @@ static struct board_info __initdata boar
},
};
static struct board_info __initdata board_96328A_1441N1 = {
.name = "96328A-1441N1",
.expected_cpu_id = 0x6328,
-@@ -3118,6 +3184,7 @@ static struct board_info __initdata boar
- static const struct board_info __initconst *bcm963xx_boards[] = {
+@@ -3154,6 +3220,7 @@ static const struct board_info __initcon
+ #endif
#ifdef CONFIG_BCM63XX_CPU_6328
&board_96328avng,
+ &board_96328A_1241N,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -752,6 +752,55 @@ static struct board_info __initdata boar
+@@ -785,6 +785,55 @@ static struct board_info __initdata boar
.has_uart0 = 1,
};
#endif
/*
-@@ -3198,6 +3247,7 @@ static const struct board_info __initcon
+@@ -3234,6 +3283,7 @@ static const struct board_info __initcon
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
&board_96345gw2,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -2858,6 +2858,374 @@ static struct board_info __initdata boar
+@@ -2891,6 +2891,374 @@ static struct board_info __initdata boar
},
};
/* T-Home Speedport W 303V Typ B */
static struct board_info __initdata board_spw303v = {
.name = "96358-502V",
-@@ -3286,6 +3654,10 @@ static const struct board_info __initcon
+@@ -3322,6 +3690,10 @@ static const struct board_info __initcon
&board_nb4_fxc_r2,
&board_ct6373_1,
&board_HW553,
&board_spw303v,
&board_DVAG3810BN,
#endif
-@@ -3351,13 +3723,37 @@ static void __init boardid_fixup(u8 *boo
+@@ -3387,13 +3759,37 @@ static void __init boardid_fixup(u8 *boo
struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K);
char *board_name = (char *)bcm63xx_nvram_get_name();
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -801,6 +801,60 @@ static struct board_info __initdata boar
+@@ -773,6 +773,60 @@ static struct board_info __initdata boar
},
},
};
#endif
/*
-@@ -3616,6 +3670,7 @@ static const struct board_info __initcon
+@@ -3652,6 +3706,7 @@ static const struct board_info __initcon
#ifdef CONFIG_BCM63XX_CPU_6345
&board_96345gw2,
&board_rta770bw,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -2058,6 +2058,99 @@ static struct board_info __initdata boar
+@@ -2091,6 +2091,99 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
.has_ehci0 = 1,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -1503,6 +1503,19 @@ static struct board_info __initdata boar
+@@ -1536,6 +1536,19 @@ static struct board_info __initdata boar
},
.has_ohci0 = 1,
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -963,6 +963,17 @@ static struct board_info __initdata boar
+@@ -996,6 +996,17 @@ static struct board_info __initdata boar
.active_low = 1,
},
},
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -591,6 +591,8 @@ static struct board_info __initdata boar
+@@ -624,6 +624,8 @@ static struct board_info __initdata boar
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -634,6 +636,8 @@ static struct board_info __initdata boar
+@@ -667,6 +669,8 @@ static struct board_info __initdata boar
.has_uart0 = 1,
.has_enet0 = 1,
.enet0 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -919,6 +923,8 @@ static struct board_info __initdata boar
+@@ -952,6 +956,8 @@ static struct board_info __initdata boar
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -991,6 +997,8 @@ static struct board_info __initdata boar
+@@ -1024,6 +1030,8 @@ static struct board_info __initdata boar
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1220,6 +1228,8 @@ static struct board_info __initdata boar
+@@ -1253,6 +1261,8 @@ static struct board_info __initdata boar
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1395,6 +1405,8 @@ static struct board_info __initdata boar
+@@ -1428,6 +1438,8 @@ static struct board_info __initdata boar
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1469,6 +1481,8 @@ static struct board_info __initdata boar
+@@ -1502,6 +1514,8 @@ static struct board_info __initdata boar
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1490,6 +1504,8 @@ static struct board_info __initdata boar
+@@ -1523,6 +1537,8 @@ static struct board_info __initdata boar
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1509,6 +1525,8 @@ static struct board_info __initdata boar
+@@ -1542,6 +1558,8 @@ static struct board_info __initdata boar
.use_internal_phy = 1,
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1884,6 +1902,8 @@ static struct board_info __initdata boar
+@@ -1917,6 +1935,8 @@ static struct board_info __initdata boar
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -1936,6 +1956,8 @@ static struct board_info __initdata boar
+@@ -1969,6 +1989,8 @@ static struct board_info __initdata boar
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -2076,6 +2098,8 @@ static struct board_info __initdata boar
+@@ -2109,6 +2131,8 @@ static struct board_info __initdata boar
},
.enet1 = {
.force_speed_100 = 1,
.force_duplex_full = 1,
},
-@@ -2193,6 +2217,8 @@ static struct board_info __initdata boar
+@@ -2226,6 +2250,8 @@ static struct board_info __initdata boar
},
.enet1 = {
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -2225,6 +2225,94 @@ static struct board_info __initdata boar
+@@ -2258,6 +2258,94 @@ static struct board_info __initdata boar
.has_ohci0 = 1,
.has_ehci0 = 1,
+++ /dev/null
---- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
-+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -69,6 +69,41 @@
- static struct board_info board;
-
- /*
-+ * known 3368 boards
-+ */
-+#ifdef CONFIG_BCM63XX_CPU_3368
-+static struct board_info __initdata board_cvg834g = {
-+ .name = "CVG834G_E15R3921",
-+ .expected_cpu_id = 0x3368,
-+
-+ .has_uart0 = 1,
-+ .has_uart1 = 1,
-+
-+ .has_enet0 = 1,
-+ .has_pci = 1,
-+
-+ .enet0 = {
-+ .has_phy = 1,
-+ .use_internal_phy = 1,
-+ },
-+
-+ .leds = {
-+ {
-+ .name = "CVG834G::switch-reset",
-+ .gpio = 36,
-+ .default_trigger= "default-on",
-+ },
-+
-+ {
-+ .name = "CVG834G:green:power",
-+ .gpio = 37,
-+ .default_trigger= "default-on",
-+ },
-+ },
-+};
-+#endif
-+
-+/*
- * known 6328 boards
- */
- #ifdef CONFIG_BCM63XX_CPU_6328
-@@ -3884,6 +3919,9 @@ static struct board_info __initdata boar
- * all boards
- */
- static const struct board_info __initconst *bcm963xx_boards[] = {
-+#ifdef CONFIG_BCM63XX_CPU_3368
-+ &board_cvg834g,
-+#endif
- #ifdef CONFIG_BCM63XX_CPU_6328
- &board_96328avng,
- &board_96328A_1241N,
#include <linux/spi/spi.h>
#include <linux/spi/spi_gpio.h>
#include <linux/spi/74x164.h>
-@@ -4001,7 +4002,7 @@ static const struct board_info __initcon
+@@ -3999,7 +4000,7 @@ static const struct board_info __initcon
* bcm4318 WLAN work
*/
#ifdef CONFIG_SSB_PCIHOST
.revision = 0x02,
.board_rev = 0x17,
.country_code = 0x0,
-@@ -4021,6 +4022,7 @@ static struct ssb_sprom bcm63xx_sprom =
+@@ -4019,6 +4020,7 @@ static struct ssb_sprom bcm63xx_sprom =
.boardflags_lo = 0x2848,
.boardflags_hi = 0x0000,
};
projects / openwrt / staging / xback.git / commitdiff