SUBTARGETS:=generic
KERNEL_PATCHVER:=5.10
+KERNEL_TESTING_PATCHVER:=5.15
define Target/Description
Build firmware images for Broadcom BCM4908 SoC family routers.
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_BCM4908=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_B53=y
+CONFIG_BCM4908_ENET=y
+CONFIG_BCM7038_WDT=y
+CONFIG_BCM7XXX_PHY=y
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BCM_PMB=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_PM=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
+CONFIG_COMMON_CLK=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_BLAKE2S=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_REMAP=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GRO_CELLS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HOLES_IN_ZONE=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_BRCMSTB=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_BCM63138=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BCM_UNIMAC=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MTD_BRCM_U_BOOT=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_OF_PARTS_BCM4908=y
+# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_CFE_BOOTFS=y
+# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_BCM_SF2=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_PADATA=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_BRCM_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCM4908=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELOCATABLE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_SUPPORT=y
+CONFIG_VMAP_STACK=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+From d0ae9c944b9472c5691a482297df7a57d7fd1199 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 19 Aug 2021 14:11:08 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix NAND node name
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This matches nand-controller.yaml requirements.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -298,7 +298,7 @@
+ status = "okay";
+ };
+
+- nand@1800 {
++ nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
--- /dev/null
+From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 5 Nov 2021 11:14:12 +0100
+Subject: [PATCH] dt-bindings: arm: bcm: document Netgear RAXE500 binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+One more BCM4908 based device.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
++++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
+@@ -29,6 +29,7 @@ properties:
+ items:
+ - enum:
+ - asus,gt-ac5300
++ - netgear,raxe500
+ - const: brcm,bcm4908
+
+ - description: BCM49408 based boards
--- /dev/null
+From d0e68d354f345873e15876a7b35be1baaf5e3ec9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 5 Nov 2021 11:14:13 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add DT for Netgear RAXE500
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's a home router based on BCM4908 SoC. It has: 1 GiB of RAM, 512 MiB
+NAND flash, 6 Ethernet ports and 3 x BCM43684 (WiFi). One of Ethernet
+ports is "2.5 G Multi-Gig port" that isn't described yet (it isn't known
+how it's wired up).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 +
+ .../bcm4908/bcm4908-netgear-raxe500.dts | 50 +++++++++++++++++++
+ 2 files changed, 51 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
+@@ -2,3 +2,4 @@
+ dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb
+ dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb
+ dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
++dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts
+@@ -0,0 +1,50 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include "bcm4908.dtsi"
++
++/ {
++ compatible = "netgear,raxe500", "brcm,bcm4908";
++ model = "Netgear RAXE500";
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00 0x00 0x00 0x40000000>;
++ };
++};
++
++&ehci {
++ status = "okay";
++};
++
++&ohci {
++ status = "okay";
++};
++
++&xhci {
++ status = "okay";
++};
++
++&ports {
++ port@0 {
++ label = "lan4";
++ };
++
++ port@1 {
++ label = "lan3";
++ };
++
++ port@2 {
++ label = "lan2";
++ };
++
++ port@3 {
++ label = "lan1";
++ };
++
++ port@7 {
++ reg = <7>;
++ phy-mode = "internal";
++ phy-handle = <&phy12>;
++ label = "wan";
++ };
++};
--- /dev/null
+From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 30 Dec 2021 12:05:35 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add pinctrl binding
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Describe pinmux block with its maps.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 135 ++++++++++++++++++
+ 1 file changed, 135 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -289,6 +289,141 @@
+ gpio-controller;
+ };
+
++ pinctrl@560 {
++ compatible = "brcm,bcm4908-pinctrl";
++ reg = <0x560 0x10>;
++
++ pins_led_0_a: led_0-a-pins {
++ function = "led_0";
++ groups = "led_0_grp_a";
++ };
++
++ pins_led_1_a: led_1-a-pins {
++ function = "led_1";
++ groups = "led_1_grp_a";
++ };
++
++ pins_led_2_a: led_2-a-pins {
++ function = "led_2";
++ groups = "led_2_grp_a";
++ };
++
++ pins_led_3_a: led_3-a-pins {
++ function = "led_3";
++ groups = "led_3_grp_a";
++ };
++
++ pins_led_4_a: led_4-a-pins {
++ function = "led_4";
++ groups = "led_4_grp_a";
++ };
++
++ pins_led_5_a: led_5-a-pins {
++ function = "led_5";
++ groups = "led_5_grp_a";
++ };
++
++ pins_led_6_a: led_6-a-pins {
++ function = "led_6";
++ groups = "led_6_grp_a";
++ };
++
++ pins_led_7_a: led_7-a-pins {
++ function = "led_7";
++ groups = "led_7_grp_a";
++ };
++
++ pins_led_8_a: led_8-a-pins {
++ function = "led_8";
++ groups = "led_8_grp_a";
++ };
++
++ pins_led_9_a: led_9-a-pins {
++ function = "led_9";
++ groups = "led_9_grp_a";
++ };
++
++ pins_led_21_a: led_21-a-pins {
++ function = "led_21";
++ groups = "led_21_grp_a";
++ };
++
++ pins_led_22_a: led_22-a-pins {
++ function = "led_22";
++ groups = "led_22_grp_a";
++ };
++
++ pins_led_26_a: led_26-a-pins {
++ function = "led_26";
++ groups = "led_26_grp_a";
++ };
++
++ pins_led_27_a: led_27-a-pins {
++ function = "led_27";
++ groups = "led_27_grp_a";
++ };
++
++ pins_led_28_a: led_28-a-pins {
++ function = "led_28";
++ groups = "led_28_grp_a";
++ };
++
++ pins_led_29_a: led_29-a-pins {
++ function = "led_29";
++ groups = "led_29_grp_a";
++ };
++
++ pins_led_30_a: led_30-a-pins {
++ function = "led_30";
++ groups = "led_30_grp_a";
++ };
++
++ pins_hs_uart: hs_uart-pins {
++ function = "hs_uart";
++ groups = "hs_uart_grp";
++ };
++
++ pins_i2c_a: i2c-a-pins {
++ function = "i2c";
++ groups = "i2c_grp_a";
++ };
++
++ pins_i2c_b: i2c-b-pins {
++ function = "i2c";
++ groups = "i2c_grp_b";
++ };
++
++ pins_i2s: i2s-pins {
++ function = "i2s";
++ groups = "i2s_grp";
++ };
++
++ pins_nand_ctrl: nand_ctrl-pins {
++ function = "nand_ctrl";
++ groups = "nand_ctrl_grp";
++ };
++
++ pins_nand_data: nand_data-pins {
++ function = "nand_data";
++ groups = "nand_data_grp";
++ };
++
++ pins_emmc_ctrl: emmc_ctrl-pins {
++ function = "emmc_ctrl";
++ groups = "emmc_ctrl_grp";
++ };
++
++ pins_usb0_pwr: usb0_pwr-pins {
++ function = "usb0_pwr";
++ groups = "usb0_pwr_grp";
++ };
++
++ pins_usb1_pwr: usb1_pwr-pins {
++ function = "usb1_pwr";
++ groups = "usb1_pwr_grp";
++ };
++ };
++
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x18>;
--- /dev/null
+From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 9 Feb 2022 21:14:17 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add watchdog block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt"
+binding which matches the first SoC with that block.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -278,6 +278,15 @@
+ twd: timer-mfd@400 {
+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
+ reg = <0x400 0x4c>;
++ ranges = <0x0 0x400 0x4c>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ watchdog@28 {
++ compatible = "brcm,bcm6345-wdt";
++ reg = <0x28 0x8>;
++ };
+ };
+
+ gpio0: gpio-controller@500 {
--- /dev/null
+From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 15 Feb 2022 07:36:39 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add I2C block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -458,6 +458,15 @@
+ };
+ };
+
++ i2c@2100 {
++ compatible = "brcm,brcmper-i2c";
++ reg = <0x2100 0x58>;
++ clock-frequency = <97500>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pins_i2c_a>;
++ status = "disabled";
++ };
++
+ misc@2600 {
+ compatible = "brcm,misc", "simple-mfd";
+ reg = <0x2600 0xe4>;
--- /dev/null
+From 076dcedc6628c6bf92bd17bfcf8fb7b1af62bfb6 Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 1 Jun 2022 15:56:51 -0700
+Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63158
+
+Add DTS for ARMv8 based broadband SoC BCM63158. bcm63158.dtsi is the
+SoC description DTS header and bcm963158.dts is a simple DTS file for
+Broadcom BCM963158 Reference board that only enable the UART port.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/Makefile | 1 +
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 2 +
+ .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 128 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm963158.dts | 30 ++++
+ 4 files changed, 161 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+
+--- a/arch/arm64/boot/dts/broadcom/Makefile
++++ b/arch/arm64/boot/dts/broadcom/Makefile
+@@ -7,5 +7,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp
+ bcm2837-rpi-cm3-io3.dtb
+
+ subdir-y += bcm4908
++subdir-y += bcmbca
+ subdir-y += northstar2
+ subdir-y += stingray
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++ compatible = "brcm,bcm63158", "brcm,bcmbca";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ B53_0: cpu@0 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_1: cpu@1 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_2: cpu@2 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x2>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_3: cpu@3 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x3>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu: pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&B53_0>, <&B53_1>,
++ <&B53_2>, <&B53_3>;
++ };
++
++ clocks: clocks {
++ periph_clk: periph-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
++ uart_clk: uart-clk {
++ compatible = "fixed-factor-clock";
++ #clock-cells = <0>;
++ clocks = <&periph_clk>;
++ clock-div = <4>;
++ clock-mult = <1>;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0x81000000 0x8000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ reg = <0x1000 0x1000>,
++ <0x2000 0x2000>,
++ <0x4000 0x2000>,
++ <0x6000 0x2000>;
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0xff800000 0x800000>;
++
++ uart0: serial@12000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12000 0x1000>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&uart_clk>, <&uart_clk>;
++ clock-names = "uartclk", "apb_pclk";
++ status = "disabled";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm63158.dtsi"
++
++/ {
++ model = "Broadcom BCM963158 Reference Board";
++ compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 1 Jun 2022 13:17:34 -0700
+Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912
+
+Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the
+SoC description DTS header and bcm94912.dts is a simple DTS file for
+Broadcom BCM94912 Reference board that only enable the UART port.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
+ .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++
+ 3 files changed, 160 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
+-dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
++dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
++ bcm963158.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++ compatible = "brcm,bcm4912", "brcm,bcmbca";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ B53_0: cpu@0 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_1: cpu@1 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_2: cpu@2 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x2>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_3: cpu@3 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x3>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu: pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&B53_0>, <&B53_1>,
++ <&B53_2>, <&B53_3>;
++ };
++
++ clocks: clocks {
++ periph_clk: periph-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
++ uart_clk: uart-clk {
++ compatible = "fixed-factor-clock";
++ #clock-cells = <0>;
++ clocks = <&periph_clk>;
++ clock-div = <4>;
++ clock-mult = <1>;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0x81000000 0x8000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ reg = <0x1000 0x1000>,
++ <0x2000 0x2000>,
++ <0x4000 0x2000>,
++ <0x6000 0x2000>;
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0xff800000 0x800000>;
++
++ uart0: serial@12000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12000 0x1000>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&uart_clk>, <&uart_clk>;
++ clock-names = "uartclk", "apb_pclk";
++ status = "disabled";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm4912.dtsi"
++
++/ {
++ model = "Broadcom BCM94912 Reference Board";
++ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From e663e06bd3f21e64bc2163910f626af68add6308 Mon Sep 17 00:00:00 2001
+From: Anand Gore <anand.gore@broadcom.com>
+Date: Wed, 1 Jun 2022 13:19:56 -0700
+Subject: [PATCH] ARM64: dts: Add DTS files for bcmbca SoC BCM6858
+
+Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC
+description DTS header and bcm96858.dts is a simple DTS file for
+Broadcom BCM96858 Reference board that only enables the UART port.
+
+Signed-off-by: Anand Gore <anand.gore@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
+ .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 121 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm96858.dts | 30 +++++
+ 3 files changed, 153 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
+- bcm963158.dtb
++ bcm963158.dtb \
++ bcm96858.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+@@ -0,0 +1,121 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++ compatible = "brcm,bcm6858", "brcm,bcmbca";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ B53_0: cpu@0 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_1: cpu@1 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_2: cpu@2 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x2>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_3: cpu@3 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x3>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu: pmu {
++ compatible = "arm,armv8-pmuv3";
++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&B53_0>, <&B53_1>,
++ <&B53_2>, <&B53_3>;
++ };
++
++ clocks: clocks {
++ periph_clk:periph-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0x81000000 0x8000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>, /* GICD */
++ <0x2000 0x2000>, /* GICC */
++ <0x4000 0x2000>, /* GICH */
++ <0x6000 0x2000>; /* GICV */
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
++ IRQ_TYPE_LEVEL_HIGH)>;
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0xff800000 0x62000>;
++
++ uart0: serial@640 {
++ compatible = "brcm,bcm6345-uart";
++ reg = <0x640 0x18>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&periph_clk>;
++ clock-names = "refclk";
++ status = "disabled";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm6858.dtsi"
++
++/ {
++ model = "Broadcom BCM96858 Reference Board";
++ compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 8 Jun 2022 11:00:59 -0700
+Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
+
+Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
+SoC description DTS header and bcm963146.dts is a simple DTS file for
+Broadcom BCM963146 Reference board that only enable the UART port.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
+ .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++
+ 3 files changed, 142 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
+ bcm963158.dtb \
+- bcm96858.dtb
++ bcm96858.dtb \
++ bcm963146.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+@@ -0,0 +1,110 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++ compatible = "brcm,bcm63146", "brcm,bcmbca";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ B53_0: cpu@0 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_1: cpu@1 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu: pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&B53_0>, <&B53_1>;
++ };
++
++ clocks: clocks {
++ periph_clk: periph-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
++ uart_clk: uart-clk {
++ compatible = "fixed-factor-clock";
++ #clock-cells = <0>;
++ clocks = <&periph_clk>;
++ clock-div = <4>;
++ clock-mult = <1>;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0x81000000 0x8000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>,
++ <0x2000 0x2000>,
++ <0x4000 0x2000>,
++ <0x6000 0x2000>;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
++ IRQ_TYPE_LEVEL_HIGH)>;
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0xff800000 0x800000>;
++
++ uart0: serial@12000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12000 0x1000>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&uart_clk>, <&uart_clk>;
++ clock-names = "uartclk", "apb_pclk";
++ status = "disabled";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm63146.dtsi"
++
++/ {
++ model = "Broadcom BCM963146 Reference Board";
++ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 8 Jun 2022 11:04:36 -0700
+Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
+
+Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
+SoC description DTS header and bcm96856.dts is a simple DTS file for
+Broadcom BCM96956 Reference board that only enable the UART port.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
+ .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++
+ 3 files changed, 135 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -2,4 +2,5 @@
+ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
+ bcm963158.dtb \
+ bcm96858.dtb \
+- bcm963146.dtb
++ bcm963146.dtb \
++ bcm96856.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+@@ -0,0 +1,103 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++ compatible = "brcm,bcm6856", "brcm,bcmbca";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ B53_0: cpu@0 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_1: cpu@1 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu: pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&B53_0>, <&B53_1>;
++ };
++
++ clocks: clocks {
++ periph_clk:periph-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0x81000000 0x8000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x1000 0x1000>, /* GICD */
++ <0x2000 0x2000>, /* GICC */
++ <0x4000 0x2000>, /* GICH */
++ <0x6000 0x2000>; /* GICV */
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
++ IRQ_TYPE_LEVEL_HIGH)>;
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0xff800000 0x800000>;
++
++ uart0: serial@640 {
++ compatible = "brcm,bcm6345-uart";
++ reg = <0x640 0x18>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&periph_clk>;
++ clock-names = "refclk";
++ status = "disabled";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm6856.dtsi"
++
++/ {
++ model = "Broadcom BCM96856 Reference Board";
++ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Thu, 9 Jun 2022 17:15:33 -0700
+Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813
+
+Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the
+SoC description DTS header and bcm96813.dts is a simple DTS file for
+Broadcom BCM96813 Reference board that only enable the UART port.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
+ .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++
+ .../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++
+ 3 files changed, 160 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dt
+ bcm963158.dtb \
+ bcm96858.dtb \
+ bcm963146.dtb \
+- bcm96856.dtb
++ bcm96856.dtb \
++ bcm96813.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+@@ -0,0 +1,128 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++ compatible = "brcm,bcm6813", "brcm,bcmbca";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ interrupt-parent = <&gic>;
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ B53_0: cpu@0 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_1: cpu@1 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x1>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_2: cpu@2 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x2>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ B53_3: cpu@3 {
++ compatible = "brcm,brahma-b53";
++ device_type = "cpu";
++ reg = <0x0 0x3>;
++ next-level-cache = <&L2_0>;
++ enable-method = "psci";
++ };
++
++ L2_0: l2-cache0 {
++ compatible = "cache";
++ };
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ pmu: pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&B53_0>, <&B53_1>,
++ <&B53_2>, <&B53_3>;
++ };
++
++ clocks: clocks {
++ periph_clk: periph-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <200000000>;
++ };
++ uart_clk: uart-clk {
++ compatible = "fixed-factor-clock";
++ #clock-cells = <0>;
++ clocks = <&periph_clk>;
++ clock-div = <4>;
++ clock-mult = <1>;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-0.2";
++ method = "smc";
++ };
++
++ axi@81000000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0x81000000 0x8000>;
++
++ gic: interrupt-controller@1000 {
++ compatible = "arm,gic-400";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++ reg = <0x1000 0x1000>,
++ <0x2000 0x2000>,
++ <0x4000 0x2000>,
++ <0x6000 0x2000>;
++ };
++ };
++
++ bus@ff800000 {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x0 0x0 0xff800000 0x800000>;
++
++ uart0: serial@12000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x12000 0x1000>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&uart_clk>, <&uart_clk>;
++ clock-names = "uartclk", "apb_pclk";
++ status = "disabled";
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm6813.dtsi"
++
++/ {
++ model = "Broadcom BCM96813 Reference Board";
++ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From ea559c81b61603d4044df6f826f10a832c42c98c Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 15 Jun 2022 17:52:59 -0700
+Subject: [PATCH] arm64: dts: broadcom: align gpio-key node names with dtschema
+
+The node names should be generic and DT schema expects certain pattern
+(e.g. with key/button/switch).
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20220616005333.18491-6-krzysztof.kozlowski@linaro.org
+---
+ .../broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts | 8 ++++----
+ .../boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 8 ++++----
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
+@@ -83,25 +83,25 @@
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+- brightness {
++ key-brightness {
+ label = "LEDs";
+ linux,code = <KEY_BRIGHTNESS_ZERO>;
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+ };
+
+- wps {
++ key-wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+- wifi {
++ key-wifi {
+ label = "WiFi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ };
+
+- restart {
++ key-restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -18,25 +18,25 @@
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+- wifi {
++ key-wifi {
+ label = "WiFi";
+ linux,code = <KEY_RFKILL>;
+ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ };
+
+- wps {
++ key-wps {
+ label = "WPS";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ };
+
+- restart {
++ key-restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ };
+
+- brightness {
++ key-brightness {
+ label = "LEDs";
+ linux,code = <KEY_BRIGHTNESS_ZERO>;
+ gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
--- /dev/null
+From b4a544e415e9be33b37d9bfa9d9f9f4d13f553d6 Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Fri, 8 Jul 2022 11:25:06 -0700
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix timer node for BCM4906 SoC
+
+The cpu mask value in interrupt property inherits from bcm4908.dtsi
+which sets to four cpus. Correct the value to two cpus for dual core
+BCM4906 SoC.
+
+Fixes: c8b404fb05dc ("arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P DTS files")
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi
+@@ -17,6 +17,14 @@
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
--- /dev/null
+From f3f575c4bef95384e68de552c7b29938fd0d9201 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 13 Jul 2022 22:03:51 +0200
+Subject: [PATCH] arm64: dts: Add base DTS file for bcmbca device Asus
+ GT-AX6000
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's a home router with 1 GiB of RAM, 6 Ethernet ports, 2 USB ports.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: William Zhang <william.zhang@broadcom.com>
+Link: https://lore.kernel.org/r/20220713200351.28526-2-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 4 +++-
+ .../bcmbca/bcm4912-asus-gt-ax6000.dts | 19 +++++++++++++++++++
+ 2 files changed, 22 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -1,5 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+-dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
++dtb-$(CONFIG_ARCH_BCMBCA) += \
++ bcm4912-asus-gt-ax6000.dtb \
++ bcm94912.dtb \
+ bcm963158.dtb \
+ bcm96858.dtb \
+ bcm963146.dtb \
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++/dts-v1/;
++
++#include "bcm4912.dtsi"
++
++/ {
++ compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca";
++ model = "Asus GT-AX6000";
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00 0x00 0x00 0x40000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From fdcd652ce2b6b819f5c4dc3cead5215c84ee6933 Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 1 Jun 2022 15:56:50 -0700
+Subject: [PATCH] arm64: bcmbca: add arch bcmbca machine entry
+
+Add ARCH_BCMBCA config for Broadcom Broadband SoC chipsets
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/Kconfig.platforms | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/Kconfig.platforms
++++ b/arch/arm64/Kconfig.platforms
+@@ -65,6 +65,15 @@ config ARCH_BCM_IPROC
+ help
+ This enables support for Broadcom iProc based SoCs
+
++config ARCH_BCMBCA
++ bool "Broadcom Broadband SoC"
++ help
++ Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
++ BCA chipset.
++
++ This enables support for Broadcom BCA ARM-based broadband chipsets,
++ including the DSL, PON and Wireless family of chips.
++
+ config ARCH_BERLIN
+ bool "Marvell Berlin SoC Family"
+ select DW_APB_ICTL
--- /dev/null
+From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 18 Jul 2022 15:20:58 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Include all 32 pins.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 75 +++++++++++++++++++
+ 1 file changed, 75 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -352,6 +352,61 @@
+ groups = "led_9_grp_a";
+ };
+
++ pins_led_10_a: led_10-a-pins {
++ function = "led_10";
++ groups = "led_10_grp_a";
++ };
++
++ pins_led_11_a: led_11-a-pins {
++ function = "led_11";
++ groups = "led_11_grp_a";
++ };
++
++ pins_led_12_a: led_12-a-pins {
++ function = "led_12";
++ groups = "led_12_grp_a";
++ };
++
++ pins_led_13_a: led_13-a-pins {
++ function = "led_13";
++ groups = "led_13_grp_a";
++ };
++
++ pins_led_14_a: led_14-a-pins {
++ function = "led_14";
++ groups = "led_14_grp_a";
++ };
++
++ pins_led_15_a: led_15-a-pins {
++ function = "led_15";
++ groups = "led_15_grp_a";
++ };
++
++ pins_led_16_a: led_16-a-pins {
++ function = "led_16";
++ groups = "led_16_grp_a";
++ };
++
++ pins_led_17_a: led_17-a-pins {
++ function = "led_17";
++ groups = "led_17_grp_a";
++ };
++
++ pins_led_18_a: led_18-a-pins {
++ function = "led_18";
++ groups = "led_18_grp_a";
++ };
++
++ pins_led_19_a: led_19-a-pins {
++ function = "led_19";
++ groups = "led_19_grp_a";
++ };
++
++ pins_led_20_a: led_20-a-pins {
++ function = "led_20";
++ groups = "led_20_grp_a";
++ };
++
+ pins_led_21_a: led_21-a-pins {
+ function = "led_21";
+ groups = "led_21_grp_a";
+@@ -362,6 +417,21 @@
+ groups = "led_22_grp_a";
+ };
+
++ pins_led_23_a: led_23-a-pins {
++ function = "led_23";
++ groups = "led_23_grp_a";
++ };
++
++ pins_led_24_a: led_24-a-pins {
++ function = "led_24";
++ groups = "led_24_grp_a";
++ };
++
++ pins_led_25_a: led_25-a-pins {
++ function = "led_25";
++ groups = "led_25_grp_a";
++ };
++
+ pins_led_26_a: led_26-a-pins {
+ function = "led_26";
+ groups = "led_26_grp_a";
+@@ -387,6 +457,11 @@
+ groups = "led_30_grp_a";
+ };
+
++ pins_led_31_a: led_31-a-pins {
++ function = "led_31";
++ groups = "led_31_grp_a";
++ };
++
+ pins_hs_uart: hs_uart-pins {
+ function = "hs_uart";
+ groups = "hs_uart_grp";
--- /dev/null
+From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 18 Jul 2022 15:20:59 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 includes LEDs controller that supports multiple brightness
+levels & hardware blinking.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+@@ -517,6 +517,14 @@
+ status = "okay";
+ };
+
++ leds: leds@800 {
++ compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
++ reg = <0x800 0xdc>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
+ nand-controller@1800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
--- /dev/null
+From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 18 Jul 2022 15:21:00 +0200
+Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are 5 software-controllable LEDs on PCB.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../bcm4908/bcm4908-asus-gt-ac5300.dts | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -2,6 +2,7 @@
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+
+ #include "bcm4908.dtsi"
+
+@@ -118,6 +119,53 @@
+ };
+ };
+
++&leds {
++ led-power@11 {
++ reg = <0x11>;
++ function = LED_FUNCTION_POWER;
++ color = <LED_COLOR_ID_WHITE>;
++ default-state = "on";
++ active-low;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pins_led_17_a>;
++ };
++
++ led-wan-red@12 {
++ reg = <0x12>;
++ function = LED_FUNCTION_WAN;
++ color = <LED_COLOR_ID_RED>;
++ active-low;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pins_led_18_a>;
++ };
++
++ led-wps@14 {
++ reg = <0x14>;
++ function = LED_FUNCTION_WPS;
++ color = <LED_COLOR_ID_WHITE>;
++ active-low;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pins_led_20_a>;
++ };
++
++ led-wan-white@15 {
++ reg = <0x15>;
++ function = LED_FUNCTION_WAN;
++ color = <LED_COLOR_ID_WHITE>;
++ active-low;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pins_led_21_a>;
++ };
++
++ led-lan@19 {
++ reg = <0x19>;
++ function = LED_FUNCTION_LAN;
++ color = <LED_COLOR_ID_WHITE>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pins_led_25_a>;
++ };
++};
++
+ &nandcs {
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
--- /dev/null
+From 4fdcbde682291fba2c3f45a41decd656d92a314f Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 3 Aug 2022 10:54:49 -0700
+Subject: [PATCH] arm64: dts: bcmbca: update BCM4908 board dts files
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Append "brcm,bcmbca" to compatible strings based on the new bcmbca
+binding rule for BCM4908 family based boards.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Acked-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20220803175455.47638-4-william.zhang@broadcom.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts | 2 +-
+ .../dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts | 2 +-
+ arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 2 +-
+ .../arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+@@ -7,7 +7,7 @@
+ #include "bcm4906.dtsi"
+
+ / {
+- compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908";
++ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
+ model = "Netgear R8000P";
+
+ memory@0 {
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
+@@ -7,7 +7,7 @@
+ #include "bcm4906.dtsi"
+
+ / {
+- compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908";
++ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
+ model = "TP-Link Archer C2300 V1";
+
+ memory@0 {
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+@@ -7,7 +7,7 @@
+ #include "bcm4908.dtsi"
+
+ / {
+- compatible = "asus,gt-ac5300", "brcm,bcm4908";
++ compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
+ model = "Asus GT-AC5300";
+
+ memory@0 {
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts
+@@ -3,7 +3,7 @@
+ #include "bcm4908.dtsi"
+
+ / {
+- compatible = "netgear,raxe500", "brcm,bcm4908";
++ compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca";
+ model = "Netgear RAXE500";
+
+ memory@0 {
--- /dev/null
+From ded8f22945899f4e87dd6d952bbc4abce6e64b7e Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 3 Aug 2022 10:54:50 -0700
+Subject: [PATCH] arm64: dts: Move BCM4908 dts to bcmbca folder
+
+As part of ARCH_BCM4908 to ARCH_BCMBCA migration, move the BCM4908 dts
+files to bcmbca folder and use CONFIG_ARCH_BCMBCA to build all the
+BCM4908 board dts. Delete bcm4908 folder and its makefile as well.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Link: https://lore.kernel.org/r/20220803175455.47638-5-william.zhang@broadcom.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/Makefile | 1 -
+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 5 -----
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 4 ++++
+ .../broadcom/{bcm4908 => bcmbca}/bcm4906-netgear-r8000p.dts | 0
+ .../{bcm4908 => bcmbca}/bcm4906-tplink-archer-c2300-v1.dts | 0
+ .../arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906.dtsi | 0
+ .../broadcom/{bcm4908 => bcmbca}/bcm4908-asus-gt-ac5300.dts | 0
+ .../broadcom/{bcm4908 => bcmbca}/bcm4908-netgear-raxe500.dts | 0
+ .../arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908.dtsi | 0
+ 9 files changed, 4 insertions(+), 6 deletions(-)
+ delete mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile
+ rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906-netgear-r8000p.dts (100%)
+ rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906-tplink-archer-c2300-v1.dts (100%)
+ rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906.dtsi (100%)
+ rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908-asus-gt-ac5300.dts (100%)
+ rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908-netgear-raxe500.dts (100%)
+ rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908.dtsi (100%)
+
+--- a/arch/arm64/boot/dts/broadcom/Makefile
++++ b/arch/arm64/boot/dts/broadcom/Makefile
+@@ -6,7 +6,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp
+ bcm2837-rpi-3-b-plus.dtb \
+ bcm2837-rpi-cm3-io3.dtb
+
+-subdir-y += bcm4908
+ subdir-y += bcmbca
+ subdir-y += northstar2
+ subdir-y += stingray
+--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
++++ /dev/null
+@@ -1,5 +0,0 @@
+-# SPDX-License-Identifier: GPL-2.0
+-dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb
+-dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb
+-dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
+-dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -1,5 +1,9 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_BCMBCA) += \
++ bcm4906-netgear-r8000p.dtb \
++ bcm4906-tplink-archer-c2300-v1.dtb \
++ bcm4908-asus-gt-ac5300.dtb \
++ bcm4908-netgear-raxe500.dtb \
+ bcm4912-asus-gt-ax6000.dtb \
+ bcm94912.dtb \
+ bcm963158.dtb \
+diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
+similarity index 100%
+rename from arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts
+rename to arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
+diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
+similarity index 100%
+rename from arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts
+rename to arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
+diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
+similarity index 100%
+rename from arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi
+rename to arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
+diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
+similarity index 100%
+rename from arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
+rename to arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
+diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
+similarity index 100%
+rename from arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts
+rename to arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
+diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+similarity index 100%
+rename from arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
+rename to arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
--- /dev/null
+From 72e0bdb6d7edb1785d58f2e8e7c80e1d2f93a319 Mon Sep 17 00:00:00 2001
+From: William Zhang <william.zhang@broadcom.com>
+Date: Wed, 3 Aug 2022 10:54:51 -0700
+Subject: [PATCH] arm64: dts: Add BCM4908 generic board dts
+
+Add generic bare bone bcm94908.dts file to support any 4908 based
+design. It supports cpu subsystem, memory and an uart console. This can
+be useful for board bring-up and cpu subsystem and memory related kernel
+test as well.
+
+Signed-off-by: William Zhang <william.zhang@broadcom.com>
+Link: https://lore.kernel.org/r/20220803175455.47638-6-william.zhang@broadcom.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 1 +
+ .../boot/dts/broadcom/bcmbca/bcm94908.dts | 30 +++++++++++++++++++
+ 2 files changed, 31 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
+@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
+ bcm4906-tplink-archer-c2300-v1.dtb \
+ bcm4908-asus-gt-ac5300.dtb \
+ bcm4908-netgear-raxe500.dtb \
++ bcm94908.dtb \
+ bcm4912-asus-gt-ax6000.dtb \
+ bcm94912.dtb \
+ bcm963158.dtb \
+--- /dev/null
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
+@@ -0,0 +1,30 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2022 Broadcom Ltd.
++ */
++
++/dts-v1/;
++
++#include "bcm4908.dtsi"
++
++/ {
++ model = "Broadcom BCM94908 Reference Board";
++ compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x08000000>;
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From 68064196cffea33f090bd2e8d81cd5e20107ecf1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 3 Nov 2022 11:53:16 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 TWD contains block with 4 timers. Add binding for it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221103105316.21294-1-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -283,6 +283,11 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+
++ timer@0 {
++ compatible = "brcm,bcm63138-timer";
++ reg = <0x0 0x28>;
++ };
++
+ watchdog@28 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x28 0x8>;
--- /dev/null
+From 4f9fb09175e87a233787a2dee1e5dabb14deb022 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 3 Nov 2022 12:00:15 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM6858 contains TWD block with timers, watchdog, and reset subblocks.
+Describe it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221103110015.21761-1-zajec5@gmail.com
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+---
+ .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+@@ -109,6 +109,25 @@
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x62000>;
+
++ twd: timer-mfd@400 {
++ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
++ reg = <0x400 0x4c>;
++ ranges = <0x0 0x400 0x4c>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ timer@0 {
++ compatible = "brcm,bcm63138-timer";
++ reg = <0x0 0x28>;
++ };
++
++ watchdog@28 {
++ compatible = "brcm,bcm6345-wdt";
++ reg = <0x28 0x8>;
++ };
++ };
++
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x18>;
--- /dev/null
+From 002181f5b150e60c77f21de7ad4dd10e4614cd91 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 11 Jul 2022 17:30:41 +0200
+Subject: [PATCH] mtd: parsers: add Broadcom's U-Boot parser
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Broadcom stores environment variables blocks inside U-Boot partition
+itself. This driver finds & registers them.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/20220711153041.6036-2-zajec5@gmail.com
+---
+ drivers/mtd/parsers/Kconfig | 10 ++++
+ drivers/mtd/parsers/Makefile | 1 +
+ drivers/mtd/parsers/brcm_u-boot.c | 84 +++++++++++++++++++++++++++++++
+ 3 files changed, 95 insertions(+)
+ create mode 100644 drivers/mtd/parsers/brcm_u-boot.c
+
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -20,6 +20,16 @@ config MTD_BCM63XX_PARTS
+ This provides partition parsing for BCM63xx devices with CFE
+ bootloaders.
+
++config MTD_BRCM_U_BOOT
++ tristate "Broadcom's U-Boot partition parser"
++ depends on ARCH_BCM4908 || COMPILE_TEST
++ help
++ Broadcom uses a custom way of storing U-Boot environment variables.
++ They are placed inside U-Boot partition itself at unspecified offset.
++ It's possible to locate them by looking for a custom header with a
++ magic value. This driver does that and creates subpartitions for
++ each found environment variables block.
++
+ config MTD_CMDLINE_PARTS
+ tristate "Command line partition table parsing"
+ depends on MTD
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -2,6 +2,7 @@
+ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+ obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
+ obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
++obj-$(CONFIG_MTD_BRCM_U_BOOT) += brcm_u-boot.o
+ obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
+ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
+--- /dev/null
++++ b/drivers/mtd/parsers/brcm_u-boot.c
+@@ -0,0 +1,84 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright © 2022 Rafał Miłecki <rafal@milecki.pl>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#define BRCM_U_BOOT_MAX_OFFSET 0x200000
++#define BRCM_U_BOOT_STEP 0x1000
++
++#define BRCM_U_BOOT_MAX_PARTS 2
++
++#define BRCM_U_BOOT_MAGIC 0x75456e76 /* uEnv */
++
++struct brcm_u_boot_header {
++ __le32 magic;
++ __le32 length;
++} __packed;
++
++static const char *names[BRCM_U_BOOT_MAX_PARTS] = {
++ "u-boot-env",
++ "u-boot-env-backup",
++};
++
++static int brcm_u_boot_parse(struct mtd_info *mtd,
++ const struct mtd_partition **pparts,
++ struct mtd_part_parser_data *data)
++{
++ struct brcm_u_boot_header header;
++ struct mtd_partition *parts;
++ size_t bytes_read;
++ size_t offset;
++ int err;
++ int i = 0;
++
++ parts = kcalloc(BRCM_U_BOOT_MAX_PARTS, sizeof(*parts), GFP_KERNEL);
++ if (!parts)
++ return -ENOMEM;
++
++ for (offset = 0;
++ offset < min_t(size_t, mtd->size, BRCM_U_BOOT_MAX_OFFSET);
++ offset += BRCM_U_BOOT_STEP) {
++ err = mtd_read(mtd, offset, sizeof(header), &bytes_read, (uint8_t *)&header);
++ if (err && !mtd_is_bitflip(err)) {
++ pr_err("Failed to read from %s at 0x%zx: %d\n", mtd->name, offset, err);
++ continue;
++ }
++
++ if (le32_to_cpu(header.magic) != BRCM_U_BOOT_MAGIC)
++ continue;
++
++ parts[i].name = names[i];
++ parts[i].offset = offset;
++ parts[i].size = sizeof(header) + le32_to_cpu(header.length);
++ i++;
++ pr_info("offset:0x%zx magic:0x%08x BINGO\n", offset, header.magic);
++
++ if (i == BRCM_U_BOOT_MAX_PARTS)
++ break;
++ }
++
++ *pparts = parts;
++
++ return i;
++};
++
++static const struct of_device_id brcm_u_boot_of_match_table[] = {
++ { .compatible = "brcm,u-boot" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, brcm_u_boot_of_match_table);
++
++static struct mtd_part_parser brcm_u_boot_mtd_parser = {
++ .parse_fn = brcm_u_boot_parse,
++ .name = "brcm_u-boot",
++ .of_match_table = brcm_u_boot_of_match_table,
++};
++module_mtd_part_parser(brcm_u_boot_mtd_parser);
++
++MODULE_LICENSE("GPL");
--- /dev/null
+From af30f8eaa8fe4ff1987280f716309711997bd979 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 29 Dec 2021 18:16:42 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: refactor LED regs access
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs.
+2. Add helper for handling non-lineral port <-> reg mappings.
+3. Add support for 12 B LED reg blocks on BCM4908 (different layout)
+
+Complete support for LEDs setup will be implemented once Linux receives
+a proper design & implementation for "hardware" LEDs.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/bcm_sf2.c | 54 ++++++++++++++++++++++++----
+ drivers/net/dsa/bcm_sf2.h | 10 ++++++
+ drivers/net/dsa/bcm_sf2_regs.h | 65 +++++++++++++++++++++++++++++++---
+ 3 files changed, 119 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -62,6 +62,38 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc
+ return REG_SWITCH_STATUS;
+ }
+
++static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
++{
++ switch (port) {
++ case 0:
++ return REG_LED_0_CNTRL;
++ case 1:
++ return REG_LED_1_CNTRL;
++ case 2:
++ return REG_LED_2_CNTRL;
++ }
++
++ switch (priv->type) {
++ case BCM4908_DEVICE_ID:
++ switch (port) {
++ case 3:
++ return REG_LED_3_CNTRL;
++ case 7:
++ return REG_LED_4_CNTRL;
++ default:
++ break;
++ }
++ break;
++ default:
++ break;
++ }
++
++ WARN_ONCE(1, "Unsupported port %d\n", port);
++
++ /* RO fallback reg */
++ return REG_SWITCH_STATUS;
++}
++
+ /* Return the number of active ports, not counting the IMP (CPU) port */
+ static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
+ {
+@@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(stru
+
+ /* Use PHY-driven LED signaling */
+ if (!enable) {
+- reg = reg_readl(priv, REG_LED_CNTRL(0));
+- reg |= SPDLNK_SRC_SEL;
+- reg_writel(priv, reg, REG_LED_CNTRL(0));
++ u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
++
++ if (priv->type == BCM7278_DEVICE_ID ||
++ priv->type == BCM7445_DEVICE_ID) {
++ reg = reg_led_readl(priv, led_ctrl, 0);
++ reg |= LED_CNTRL_SPDLNK_SRC_SEL;
++ reg_led_writel(priv, reg, led_ctrl, 0);
++ }
+ }
+ }
+
+@@ -1241,9 +1278,14 @@ static const u16 bcm_sf2_4908_reg_offset
+ [REG_SPHY_CNTRL] = 0x24,
+ [REG_CROSSBAR] = 0xc8,
+ [REG_RGMII_11_CNTRL] = 0x014c,
+- [REG_LED_0_CNTRL] = 0x40,
+- [REG_LED_1_CNTRL] = 0x4c,
+- [REG_LED_2_CNTRL] = 0x58,
++ [REG_LED_0_CNTRL] = 0x40,
++ [REG_LED_1_CNTRL] = 0x4c,
++ [REG_LED_2_CNTRL] = 0x58,
++ [REG_LED_3_CNTRL] = 0x64,
++ [REG_LED_4_CNTRL] = 0x88,
++ [REG_LED_5_CNTRL] = 0xa0,
++ [REG_LED_AGGREGATE_CTRL] = 0xb8,
++
+ };
+
+ static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
+--- a/drivers/net/dsa/bcm_sf2.h
++++ b/drivers/net/dsa/bcm_sf2.h
+@@ -210,6 +210,16 @@ SF2_IO_MACRO(acb);
+ SWITCH_INTR_L2(0);
+ SWITCH_INTR_L2(1);
+
++static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
++{
++ return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
++}
++
++static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
++{
++ writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
++}
++
+ /* RXNFC */
+ int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
+ struct ethtool_rxnfc *nfc, u32 *rule_locs);
+--- a/drivers/net/dsa/bcm_sf2_regs.h
++++ b/drivers/net/dsa/bcm_sf2_regs.h
+@@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs {
+ REG_LED_0_CNTRL,
+ REG_LED_1_CNTRL,
+ REG_LED_2_CNTRL,
++ REG_LED_3_CNTRL,
++ REG_LED_4_CNTRL,
++ REG_LED_5_CNTRL,
++ REG_LED_AGGREGATE_CTRL,
+ REG_SWITCH_REG_MAX,
+ };
+
+@@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs {
+ #define CROSSBAR_BCM4908_EXT_GPHY4 1
+ #define CROSSBAR_BCM4908_EXT_RGMII 2
+
++/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
++#define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
++#define LED_CNTRL_M10_ENCODE_SHIFT 2
++#define LED_CNTRL_M100_ENCODE_SHIFT 4
++#define LED_CNTRL_M1000_ENCODE_SHIFT 6
++#define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8
++#define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10
++#define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12
++#define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14
++#define LED_CNTRL_RX_DV_EN (1 << 16)
++#define LED_CNTRL_TX_EN_EN (1 << 17)
++#define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18
++#define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20
++#define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22
++#define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24)
++#define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25)
++#define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26)
++#define LED_CNTRL_ACT_LED_POL_SEL (1 << 27)
++#define LED_CNTRL_MASK 0x3
++
++/* Register relative to REG_LED_*_CNTRL (BCM4908) */
++#define REG_LED_CTRL 0x0
++#define LED_CTRL_RX_ACT_EN 0x00000001
++#define LED_CTRL_TX_ACT_EN 0x00000002
++#define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004
++#define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008
++#define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010
++#define LED_CTRL_ACT_LED_ACT_SEL 0x00000020
++#define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040
++#define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080
++#define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100
++#define LED_CTRL_ACT_LED_POL_SEL 0x00000200
++#define LED_CTRL_LED_SPD_OVRD 0x00001c00
++#define LED_CTRL_LNK_STATUS_OVRD 0x00002000
++#define LED_CTRL_SPD_OVRD_EN 0x00004000
++#define LED_CTRL_LNK_OVRD_EN 0x00008000
++
++/* Register relative to REG_LED_*_CNTRL (BCM4908) */
++#define REG_LED_LINK_SPEED_ENC_SEL 0x4
++#define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0
++#define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3
++#define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6
++#define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9
++#define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12
++#define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15
++#define LED_LINK_SPEED_ENC_SEL_MASK 0x7
++
++/* Register relative to REG_LED_*_CNTRL (BCM4908) */
++#define REG_LED_LINK_SPEED_ENC 0x8
++#define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0
++#define LED_LINK_SPEED_ENC_M10_SHIFT 3
++#define LED_LINK_SPEED_ENC_M100_SHIFT 6
++#define LED_LINK_SPEED_ENC_M1000_SHIFT 9
++#define LED_LINK_SPEED_ENC_M2500_SHIFT 12
++#define LED_LINK_SPEED_ENC_M10G_SHIFT 15
++#define LED_LINK_SPEED_ENC_MASK 0x7
++
+ /* Relative to REG_RGMII_CNTRL */
+ #define RGMII_MODE_EN (1 << 0)
+ #define ID_MODE_DIS (1 << 1)
+@@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs {
+ #define LPI_COUNT_SHIFT 9
+ #define LPI_COUNT_MASK 0x3F
+
+-#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
+-
+-#define SPDLNK_SRC_SEL (1 << 24)
+-
+ /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
+ #define INTRL2_CPU_STATUS 0x00
+ #define INTRL2_CPU_SET 0x04
--- /dev/null
+From e93a766da57fff3273bcb618edf5dfca1fb86b89 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 15 Sep 2022 15:30:13 +0200
+Subject: [PATCH] net: broadcom: bcm4908_enet: handle -EPROBE_DEFER when
+ getting MAC
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Reading MAC from OF may return -EPROBE_DEFER if underlaying NVMEM device
+isn't ready yet. In such case pass that error code up and "wait" to be
+probed later.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20220915133013.2243-1-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -720,6 +720,8 @@ static int bcm4908_enet_probe(struct pla
+
+ SET_NETDEV_DEV(netdev, &pdev->dev);
+ err = of_get_mac_address(dev->of_node, netdev->dev_addr);
++ if (err == -EPROBE_DEFER)
++ goto err_dma_free;
+ if (err)
+ eth_hw_addr_random(netdev);
+ netdev->netdev_ops = &bcm4908_enet_netdev_ops;
+@@ -730,14 +732,17 @@ static int bcm4908_enet_probe(struct pla
+ netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);
+
+ err = register_netdev(netdev);
+- if (err) {
+- bcm4908_enet_dma_free(enet);
+- return err;
+- }
++ if (err)
++ goto err_dma_free;
+
+ platform_set_drvdata(pdev, enet);
+
+ return 0;
++
++err_dma_free:
++ bcm4908_enet_dma_free(enet);
++
++ return err;
+ }
+
+ static int bcm4908_enet_remove(struct platform_device *pdev)
--- /dev/null
+From 3a1cc23a75abcd9cea585eb84846507363d58397 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 25 Oct 2022 15:22:45 +0200
+Subject: [PATCH] net: broadcom: bcm4908_enet: use build_skb()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+RX code can be more efficient with the build_skb(). Allocating actual
+SKB around eth packet buffer - right before passing it up - results in
+a better cache usage.
+
+Without RPS (echo 0 > rps_cpus) BCM4908 NAT masq performance "jumps"
+between two speeds: ~900 Mbps and 940 Mbps (it's a 4 CPUs SoC). This
+change bumps the lower speed from 905 Mb/s to 918 Mb/s (tested using
+single stream iperf 2.0.5 traffic).
+
+There are more optimizations to consider. One obvious to try is GRO
+however as BCM4908 doesn't do hw csum is may actually lower performance.
+Sometimes. Some early testing:
+
+┌─────────────────────────────────┬─────────────────────┬────────────────────┐
+│ │ netif_receive_skb() │ napi_gro_receive() │
+├─────────────────────────────────┼─────────────────────┼────────────────────┤
+│ netdev_alloc_skb() │ 905 Mb/s │ 892 Mb/s │
+│ napi_alloc_frag() + build_skb() │ 918 Mb/s │ 917 Mb/s │
+└─────────────────────────────────┴─────────────────────┴────────────────────┘
+
+Another ideas:
+1. napi_build_skb()
+2. skb_copy_from_linear_data() for small packets
+
+Those need proper testing first though. That can be done later.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221025132245.22871-1-zajec5@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 53 +++++++++++++-------
+ 1 file changed, 36 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -36,13 +36,24 @@
+ #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
+ ETH_FCS_LEN + 4) /* 32 */
+
++#define ENET_RX_SKB_BUF_SIZE (NET_SKB_PAD + NET_IP_ALIGN + \
++ ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
++ ENET_MTU_MAX + ETH_FCS_LEN + 4)
++#define ENET_RX_SKB_BUF_ALLOC_SIZE (SKB_DATA_ALIGN(ENET_RX_SKB_BUF_SIZE) + \
++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
++#define ENET_RX_BUF_DMA_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
++#define ENET_RX_BUF_DMA_SIZE (ENET_RX_SKB_BUF_SIZE - ENET_RX_BUF_DMA_OFFSET)
++
+ struct bcm4908_enet_dma_ring_bd {
+ __le32 ctl;
+ __le32 addr;
+ } __packed;
+
+ struct bcm4908_enet_dma_ring_slot {
+- struct sk_buff *skb;
++ union {
++ void *buf; /* RX */
++ struct sk_buff *skb; /* TX */
++ };
+ unsigned int len;
+ dma_addr_t dma_addr;
+ };
+@@ -260,22 +271,21 @@ static int bcm4908_enet_dma_alloc_rx_buf
+ u32 tmp;
+ int err;
+
+- slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
+-
+- slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
+- if (!slot->skb)
++ slot->buf = napi_alloc_frag(ENET_RX_SKB_BUF_ALLOC_SIZE);
++ if (!slot->buf)
+ return -ENOMEM;
+
+- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
++ slot->dma_addr = dma_map_single(dev, slot->buf + ENET_RX_BUF_DMA_OFFSET,
++ ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
+ err = dma_mapping_error(dev, slot->dma_addr);
+ if (err) {
+ dev_err(dev, "Failed to map DMA buffer: %d\n", err);
+- kfree_skb(slot->skb);
+- slot->skb = NULL;
++ skb_free_frag(slot->buf);
++ slot->buf = NULL;
+ return err;
+ }
+
+- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
++ tmp = ENET_RX_BUF_DMA_SIZE << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
+ tmp |= DMA_CTL_STATUS_OWN;
+ if (idx == enet->rx_ring.length - 1)
+ tmp |= DMA_CTL_STATUS_WRAP;
+@@ -315,11 +325,11 @@ static void bcm4908_enet_dma_uninit(stru
+
+ for (i = rx_ring->length - 1; i >= 0; i--) {
+ slot = &rx_ring->slots[i];
+- if (!slot->skb)
++ if (!slot->buf)
+ continue;
+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
+- kfree_skb(slot->skb);
+- slot->skb = NULL;
++ skb_free_frag(slot->buf);
++ slot->buf = NULL;
+ }
+ }
+
+@@ -575,6 +585,7 @@ static int bcm4908_enet_poll_rx(struct n
+ while (handled < weight) {
+ struct bcm4908_enet_dma_ring_bd *buf_desc;
+ struct bcm4908_enet_dma_ring_slot slot;
++ struct sk_buff *skb;
+ u32 ctl;
+ int len;
+ int err;
+@@ -598,16 +609,24 @@ static int bcm4908_enet_poll_rx(struct n
+
+ if (len < ETH_ZLEN ||
+ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
+- kfree_skb(slot.skb);
++ skb_free_frag(slot.buf);
+ enet->netdev->stats.rx_dropped++;
+ break;
+ }
+
+- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
++ dma_unmap_single(dev, slot.dma_addr, ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
++
++ skb = build_skb(slot.buf, ENET_RX_SKB_BUF_ALLOC_SIZE);
++ if (unlikely(!skb)) {
++ skb_free_frag(slot.buf);
++ enet->netdev->stats.rx_dropped++;
++ break;
++ }
++ skb_reserve(skb, ENET_RX_BUF_DMA_OFFSET);
++ skb_put(skb, len - ETH_FCS_LEN);
++ skb->protocol = eth_type_trans(skb, enet->netdev);
+
+- skb_put(slot.skb, len - ETH_FCS_LEN);
+- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
+- netif_receive_skb(slot.skb);
++ netif_receive_skb(skb);
+
+ enet->netdev->stats.rx_packets++;
+ enet->netdev->stats.rx_bytes += len;
--- /dev/null
+From 471ef777ec79baadc5cd9773d08f95f49cf5e2b1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 31 Oct 2022 11:48:56 +0100
+Subject: [PATCH] net: broadcom: bcm4908_enet: report queued and transmitted
+ bytes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This allows BQL to operate avoiding buffer bloat and reducing latency.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Link: https://lore.kernel.org/r/20221031104856.32388-1-zajec5@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/broadcom/bcm4908_enet.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
+@@ -505,6 +505,7 @@ static int bcm4908_enet_stop(struct net_
+ netif_carrier_off(netdev);
+ napi_disable(&rx_ring->napi);
+ napi_disable(&tx_ring->napi);
++ netdev_reset_queue(netdev);
+
+ bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
+ bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
+@@ -564,6 +565,8 @@ static int bcm4908_enet_start_xmit(struc
+ if (ring->write_idx + 1 == ring->length - 1)
+ tmp |= DMA_CTL_STATUS_WRAP;
+
++ netdev_sent_queue(enet->netdev, skb->len);
++
+ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
+ buf_desc->ctl = cpu_to_le32(tmp);
+
+@@ -671,6 +674,7 @@ static int bcm4908_enet_poll_tx(struct n
+ tx_ring->read_idx = 0;
+ }
+
++ netdev_completed_queue(enet->netdev, handled, bytes);
+ enet->netdev->stats.tx_packets += handled;
+ enet->netdev->stats.tx_bytes += bytes;
+
--- /dev/null
+From 7b5730f0ff24b0d7d1cb660a482384a807618a46 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 24 Jan 2022 11:22:42 +0100
+Subject: [PATCH] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+It's hardware block that is part of every SoC from BCM4908 family.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20220124102243.14912-1-zajec5@gmail.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ .../pinctrl/brcm,bcm4908-pinctrl.yaml | 72 +++++++++++++++++++
+ MAINTAINERS | 7 ++
+ 2 files changed, 79 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
+@@ -0,0 +1,72 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom BCM4908 pin controller
++
++maintainers:
++ - Rafał Miłecki <rafal@milecki.pl>
++
++description:
++ Binding for pin controller present on BCM4908 family SoCs.
++
++properties:
++ compatible:
++ const: brcm,bcm4908-pinctrl
++
++ reg:
++ maxItems: 1
++
++patternProperties:
++ '-pins$':
++ type: object
++ $ref: pinmux-node.yaml#
++
++ properties:
++ function:
++ enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
++ led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
++ led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
++ led_25, led_26, led_27, led_28, led_29, led_30, led_31,
++ hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
++ usb1_pwr ]
++
++ groups:
++ minItems: 1
++ maxItems: 2
++ items:
++ enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
++ led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
++ led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
++ led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
++ led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
++ led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
++ led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
++ led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
++ led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
++ led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
++ nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
++ usb1_pwr_grp ]
++
++allOf:
++ - $ref: pinctrl.yaml#
++
++required:
++ - compatible
++ - reg
++
++unevaluatedProperties: false
++
++examples:
++ - |
++ pinctrl@ff800560 {
++ compatible = "brcm,bcm4908-pinctrl";
++ reg = <0xff800560 0x10>;
++
++ led_0-a-pins {
++ function = "led_0";
++ groups = "led_0_grp_a";
++ };
++ };
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3572,6 +3572,13 @@ F: Documentation/devicetree/bindings/net
+ F: drivers/net/ethernet/broadcom/bcm4908_enet.*
+ F: drivers/net/ethernet/broadcom/unimac.h
+
++BROADCOM BCM4908 PINMUX DRIVER
++M: Rafał Miłecki <rafal@milecki.pl>
++M: bcm-kernel-feedback-list@broadcom.com
++L: linux-gpio@vger.kernel.org
++S: Maintained
++F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
++
+ BROADCOM BCM5301X ARM ARCHITECTURE
+ M: Hauke Mehrtens <hauke@hauke-m.de>
+ M: Rafał Miłecki <zajec5@gmail.com>
--- /dev/null
+From f7e322d99f1180270fb4a3e1ae992b3116cfcf34 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 24 Jan 2022 11:22:43 +0100
+Subject: [PATCH] pinctrl: bcm: add driver for BCM4908 pinmux
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 has its own pins layout so it needs a custom binding and a Linux
+driver.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ MAINTAINERS | 1 +
+ drivers/pinctrl/bcm/Kconfig | 14 +
+ drivers/pinctrl/bcm/Makefile | 1 +
+ drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++
+ 4 files changed, 579 insertions(+)
+ create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3578,6 +3578,7 @@ M: bcm-kernel-feedback-list@broadcom.com
+ L: linux-gpio@vger.kernel.org
+ S: Maintained
+ F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
++F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
+
+ BROADCOM BCM5301X ARM ARCHITECTURE
+ M: Hauke Mehrtens <hauke@hauke-m.de>
+--- a/drivers/pinctrl/bcm/Kconfig
++++ b/drivers/pinctrl/bcm/Kconfig
+@@ -29,6 +29,20 @@ config PINCTRL_BCM2835
+ help
+ Say Y here to enable the Broadcom BCM2835 GPIO driver.
+
++config PINCTRL_BCM4908
++ tristate "Broadcom BCM4908 pinmux driver"
++ depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
++ select PINMUX
++ select PINCONF
++ select GENERIC_PINCONF
++ select GENERIC_PINCTRL_GROUPS
++ select GENERIC_PINMUX_FUNCTIONS
++ default ARCH_BCM4908
++ help
++ Driver for BCM4908 family SoCs with integrated pin controller.
++
++ If compiled as module it will be called pinctrl-bcm4908.
++
+ config PINCTRL_BCM63XX
+ bool
+ select PINMUX
+--- a/drivers/pinctrl/bcm/Makefile
++++ b/drivers/pinctrl/bcm/Makefile
+@@ -3,6 +3,7 @@
+
+ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
+ obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
++obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
+ obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
+ obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
+ obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
+--- /dev/null
++++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
+@@ -0,0 +1,560 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
++
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/string_helpers.h>
++
++#include "../core.h"
++#include "../pinmux.h"
++
++#define BCM4908_NUM_PINS 86
++
++#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
++#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
++#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
++#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
++#define BCM4908_TEST_PORT_COMMAND 0x0c
++#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
++
++struct bcm4908_pinctrl {
++ struct device *dev;
++ void __iomem *base;
++ struct mutex mutex;
++ struct pinctrl_dev *pctldev;
++ struct pinctrl_desc pctldesc;
++};
++
++/*
++ * Groups
++ */
++
++struct bcm4908_pinctrl_pin_setup {
++ unsigned int number;
++ unsigned int function;
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
++ { 0, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
++ { 1, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
++ { 2, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
++ { 3, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
++ { 4, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
++ { 5, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
++ { 6, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
++ { 7, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
++ { 8, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
++ { 9, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
++ { 10, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
++ { 11, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
++ { 12, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
++ { 13, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
++ { 14, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
++ { 15, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
++ { 16, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
++ { 17, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
++ { 18, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
++ { 19, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
++ { 20, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
++ { 21, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
++ { 22, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
++ { 23, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
++ { 24, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
++ { 25, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
++ { 26, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
++ { 27, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
++ { 28, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
++ { 29, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
++ { 30, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
++ { 31, 3 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
++ { 8, 2 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
++ { 9, 2 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
++ { 0, 2 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
++ { 1, 2 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
++ { 30, 2 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
++ { 10, 0 }, /* CTS */
++ { 11, 0 }, /* RTS */
++ { 12, 0 }, /* RXD */
++ { 13, 0 }, /* TXD */
++};
++
++static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
++ { 18, 0 }, /* SDA */
++ { 19, 0 }, /* SCL */
++};
++
++static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
++ { 22, 0 }, /* SDA */
++ { 23, 0 }, /* SCL */
++};
++
++static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
++ { 27, 0 }, /* MCLK */
++ { 28, 0 }, /* LRCK */
++ { 29, 0 }, /* SDATA */
++ { 30, 0 }, /* SCLK */
++};
++
++static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
++ { 32, 0 },
++ { 33, 0 },
++ { 34, 0 },
++ { 43, 0 },
++ { 44, 0 },
++ { 45, 0 },
++ { 56, 1 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
++ { 35, 0 },
++ { 36, 0 },
++ { 37, 0 },
++ { 38, 0 },
++ { 39, 0 },
++ { 40, 0 },
++ { 41, 0 },
++ { 42, 0 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
++ { 46, 0 },
++ { 47, 0 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
++ { 63, 0 },
++ { 64, 0 },
++};
++
++static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
++ { 66, 0 },
++ { 67, 0 },
++};
++
++struct bcm4908_pinctrl_grp {
++ const char *name;
++ const struct bcm4908_pinctrl_pin_setup *pins;
++ const unsigned int num_pins;
++};
++
++static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
++ { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
++ { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
++ { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
++ { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
++ { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
++ { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
++ { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
++ { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
++ { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
++ { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
++ { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
++ { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
++ { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
++ { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
++ { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
++ { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
++ { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
++ { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
++ { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
++ { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
++ { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
++ { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
++ { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
++ { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
++ { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
++ { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
++ { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
++ { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
++ { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
++ { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
++ { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
++ { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
++ { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
++ { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
++ { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
++ { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
++ { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
++ { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
++ { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
++ { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
++ { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
++ { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
++ { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
++ { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
++ { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
++ { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
++};
++
++/*
++ * Functions
++ */
++
++struct bcm4908_pinctrl_function {
++ const char *name;
++ const char * const *groups;
++ const unsigned int num_groups;
++};
++
++static const char * const led_0_groups[] = { "led_0_grp_a" };
++static const char * const led_1_groups[] = { "led_1_grp_a" };
++static const char * const led_2_groups[] = { "led_2_grp_a" };
++static const char * const led_3_groups[] = { "led_3_grp_a" };
++static const char * const led_4_groups[] = { "led_4_grp_a" };
++static const char * const led_5_groups[] = { "led_5_grp_a" };
++static const char * const led_6_groups[] = { "led_6_grp_a" };
++static const char * const led_7_groups[] = { "led_7_grp_a" };
++static const char * const led_8_groups[] = { "led_8_grp_a" };
++static const char * const led_9_groups[] = { "led_9_grp_a" };
++static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
++static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
++static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
++static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
++static const char * const led_14_groups[] = { "led_14_grp_a" };
++static const char * const led_15_groups[] = { "led_15_grp_a" };
++static const char * const led_16_groups[] = { "led_16_grp_a" };
++static const char * const led_17_groups[] = { "led_17_grp_a" };
++static const char * const led_18_groups[] = { "led_18_grp_a" };
++static const char * const led_19_groups[] = { "led_19_grp_a" };
++static const char * const led_20_groups[] = { "led_20_grp_a" };
++static const char * const led_21_groups[] = { "led_21_grp_a" };
++static const char * const led_22_groups[] = { "led_22_grp_a" };
++static const char * const led_23_groups[] = { "led_23_grp_a" };
++static const char * const led_24_groups[] = { "led_24_grp_a" };
++static const char * const led_25_groups[] = { "led_25_grp_a" };
++static const char * const led_26_groups[] = { "led_26_grp_a" };
++static const char * const led_27_groups[] = { "led_27_grp_a" };
++static const char * const led_28_groups[] = { "led_28_grp_a" };
++static const char * const led_29_groups[] = { "led_29_grp_a" };
++static const char * const led_30_groups[] = { "led_30_grp_a" };
++static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
++static const char * const hs_uart_groups[] = { "hs_uart_grp" };
++static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
++static const char * const i2s_groups[] = { "i2s_grp" };
++static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" };
++static const char * const nand_data_groups[] = { "nand_data_grp" };
++static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
++static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" };
++static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" };
++
++static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
++ { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
++ { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
++ { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
++ { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
++ { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
++ { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
++ { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
++ { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
++ { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
++ { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
++ { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
++ { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
++ { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
++ { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
++ { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
++ { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
++ { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
++ { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
++ { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
++ { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
++ { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
++ { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
++ { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
++ { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
++ { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
++ { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
++ { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
++ { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
++ { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
++ { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
++ { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
++ { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
++ { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
++ { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
++ { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
++ { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
++ { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
++ { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
++ { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
++ { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
++};
++
++/*
++ * Groups code
++ */
++
++static const struct pinctrl_ops bcm4908_pinctrl_ops = {
++ .get_groups_count = pinctrl_generic_get_group_count,
++ .get_group_name = pinctrl_generic_get_group_name,
++ .get_group_pins = pinctrl_generic_get_group_pins,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
++ .dt_free_map = pinconf_generic_dt_free_map,
++};
++
++/*
++ * Functions code
++ */
++
++static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
++ unsigned int func_selector,
++ unsigned int group_selector)
++{
++ struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
++ const struct bcm4908_pinctrl_grp *group;
++ struct group_desc *group_desc;
++ int i;
++
++ group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
++ if (!group_desc)
++ return -EINVAL;
++ group = group_desc->data;
++
++ mutex_lock(&bcm4908_pinctrl->mutex);
++ for (i = 0; i < group->num_pins; i++) {
++ u32 lsb = 0;
++
++ lsb |= group->pins[i].number;
++ lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
++
++ writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
++ writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
++ writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
++ bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
++ }
++ mutex_unlock(&bcm4908_pinctrl->mutex);
++
++ return 0;
++}
++
++static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
++ .get_functions_count = pinmux_generic_get_function_count,
++ .get_function_name = pinmux_generic_get_function_name,
++ .get_function_groups = pinmux_generic_get_function_groups,
++ .set_mux = bcm4908_pinctrl_set_mux,
++};
++
++/*
++ * Controller code
++ */
++
++static struct pinctrl_desc bcm4908_pinctrl_desc = {
++ .name = "bcm4908-pinctrl",
++ .pctlops = &bcm4908_pinctrl_ops,
++ .pmxops = &bcm4908_pinctrl_pmxops,
++};
++
++static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
++ { .compatible = "brcm,bcm4908-pinctrl", },
++ { }
++};
++
++static int bcm4908_pinctrl_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct bcm4908_pinctrl *bcm4908_pinctrl;
++ struct pinctrl_desc *pctldesc;
++ struct pinctrl_pin_desc *pins;
++ int i;
++
++ bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
++ if (!bcm4908_pinctrl)
++ return -ENOMEM;
++ pctldesc = &bcm4908_pinctrl->pctldesc;
++ platform_set_drvdata(pdev, bcm4908_pinctrl);
++
++ /* Set basic properties */
++
++ bcm4908_pinctrl->dev = dev;
++
++ bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(bcm4908_pinctrl->base))
++ return PTR_ERR(bcm4908_pinctrl->base);
++
++ mutex_init(&bcm4908_pinctrl->mutex);
++
++ memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
++
++ /* Set pinctrl properties */
++
++ pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
++ if (!pins)
++ return -ENOMEM;
++ for (i = 0; i < BCM4908_NUM_PINS; i++) {
++ pins[i].number = i;
++ pins[i].name = devm_kasprintf(dev, GFP_KERNEL, "pin-%d", i);
++ if (!pins[i].name)
++ return -ENOMEM;
++ }
++ pctldesc->pins = pins;
++ pctldesc->npins = BCM4908_NUM_PINS;
++
++ /* Register */
++
++ bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
++ if (IS_ERR(bcm4908_pinctrl->pctldev))
++ return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
++ "Failed to register pinctrl\n");
++
++ /* Groups */
++
++ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
++ const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
++ int *pins;
++ int j;
++
++ pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
++ if (!pins)
++ return -ENOMEM;
++ for (j = 0; j < group->num_pins; j++)
++ pins[j] = group->pins[j].number;
++
++ pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
++ pins, group->num_pins, (void *)group);
++ }
++
++ /* Functions */
++
++ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
++ const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
++
++ pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
++ function->name,
++ function->groups,
++ function->num_groups, NULL);
++ }
++
++ return 0;
++}
++
++static struct platform_driver bcm4908_pinctrl_driver = {
++ .probe = bcm4908_pinctrl_probe,
++ .driver = {
++ .name = "bcm4908-pinctrl",
++ .of_match_table = bcm4908_pinctrl_of_match_table,
++ },
++};
++
++module_platform_driver(bcm4908_pinctrl_driver);
++
++MODULE_AUTHOR("Rafał Miłecki");
++MODULE_LICENSE("GPL v2");
++MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
--- /dev/null
+From d0aee048d648ec2d9aa7af43b127ebf847d497d5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 11 Feb 2022 11:58:06 +0100
+Subject: [PATCH] i2c: brcmstb: allow compiling on BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 SoCs use the same I2C hardware block as STB and BCM63xx devices.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+---
+ drivers/i2c/busses/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -477,8 +477,8 @@ config I2C_BCM_KONA
+
+ config I2C_BRCMSTB
+ tristate "BRCM Settop/DSL I2C controller"
+- depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \
+- ARCH_BCM_63XX || COMPILE_TEST
++ depends on ARCH_BCM2835 || ARCH_BCM4908 || ARCH_BCM_63XX || \
++ ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
+ default y
+ help
+ If you say yes to this option, support will be included for the
--- /dev/null
+From cd91fb2776967b2b2dea27307a3f23ba3d9bbb32 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 9 Feb 2022 21:32:02 +0100
+Subject: [PATCH] watchdog: allow building BCM7038_WDT for BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 is a SoCs family that shares a lot of hardware with BCM63xx
+including the watchdog block. Allow building this driver for it.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/20220209203202.26395-1-zajec5@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1756,7 +1756,7 @@ config BCM7038_WDT
+ tristate "BCM7038 Watchdog"
+ select WATCHDOG_CORE
+ depends on HAS_IOMEM
+- depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
++ depends on ARCH_BCM4908 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
+ help
+ Watchdog driver for the built-in hardware in Broadcom 7038 and
+ later SoCs used in set-top boxes. BCM7038 was made public
--- /dev/null
+From 2dd441f16d6ad6104d85c4e5dfeb6dde4df26869 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 16 Feb 2022 07:34:08 +0100
+Subject: [PATCH] watchdog: bcm7038_wdt: Support BCM6345 compatible string
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+A new "compatible" value has been added in the commit 17fffe91ba36
+("dt-bindings: watchdog: Add BCM6345 compatible to BCM7038 binding").
+It's meant to be used for BCM63xx SoCs family but hardware block can be
+programmed just like the 7038 one.
+
+Cc: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/20220216063408.23168-1-zajec5@gmail.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/bcm7038_wdt.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/watchdog/bcm7038_wdt.c
++++ b/drivers/watchdog/bcm7038_wdt.c
+@@ -212,6 +212,7 @@ static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_
+ bcm7038_wdt_resume);
+
+ static const struct of_device_id bcm7038_wdt_match[] = {
++ { .compatible = "brcm,bcm6345-wdt" },
+ { .compatible = "brcm,bcm7038-wdt" },
+ {},
+ };
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Feb 2021 22:01:03 +0100
+Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Linux driver can't handle more than 64 GPIOs
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+@@ -297,7 +297,7 @@
+ gpio0: gpio-controller@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg-names = "dirout", "dat";
+- reg = <0x500 0x28>, <0x528 0x28>;
++ reg = <0x500 0x8>, <0x528 0x8>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Jan 2021 10:44:53 +0100
+Subject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BCM4908 contains NAND controller version 0x0701 (v7.1). It means that
+NAND_WP should be available.
+
+For some reason setting #WP on doesn't result in clearing NAND_STATUS_WP
+status bit:
+[ 1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0)
+[ 1.086832] bcm63138_nand ff801800.nand: nand #WP expected on
+
+For now try working without touching #WP.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
++++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+@@ -37,7 +37,11 @@
+ * 1: NAND_WP is set by default, cleared for erase/write operations
+ * 2: NAND_WP is always cleared
+ */
++#if IS_ENABLED(CONFIG_ARCH_BCM4908)
++static int wp_on = 0;
++#else
+ static int wp_on = 1;
++#endif
+ module_param(wp_on, int, 0444);
+
+ /***********************************************************************
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Mon, 15 Feb 2021 23:59:26 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+GPHY needs to be enabled to succesfully probe & setup switch port
+connected to it. Otherwise hardcoding PHY OUI would be required.
+
+Before:
+brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
+
+After:
+brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
+brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/dsa/bcm_sf2.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1538,10 +1538,14 @@ static int bcm_sf2_sw_probe(struct platf
+ rev = reg_readl(priv, REG_PHY_REVISION);
+ priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
+
++ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
++
+ ret = b53_switch_register(dev);
+ if (ret)
+ goto out_mdio;
+
++ bcm_sf2_gphy_enable_set(priv->dev->ds, false);
++
+ dev_info(&pdev->dev,
+ "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
+ priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 16 Feb 2021 00:06:35 +0100
+Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908
+
+Trying to access disabled PHY results in MDIO_READ_FAIL and:
+[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode
+[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan
+[ 11.980205] ------------[ cut here ]------------
+[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/dsa/bcm_sf2.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/dsa/bcm_sf2.c
++++ b/drivers/net/dsa/bcm_sf2.c
+@@ -1552,6 +1552,12 @@ static int bcm_sf2_sw_probe(struct platf
+ priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
+ priv->irq0, priv->irq1);
+
++ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable
++ * GPHY when needed. Leave it enabled here.
++ */
++ if (priv->type == BCM4908_DEVICE_ID)
++ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
++
+ return 0;
+
+ out_mdio:
projects / openwrt / staging / neocturne.git / commitdiff