The kernel 5.15 now defaults. Remove unnecessary files.
Reviewed-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Nick Hainke <vincent@systemli.org>
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IPQ40XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8960 is not set
-# CONFIG_ARCH_MSM8974 is not set
-# CONFIG_ARCH_MSM8X60 is not set
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPUIDLE=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
-# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BCH=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_CMDLINE_PARSER=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_BLAKE2S=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_QCE=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXTCON=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_74X164=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OPTEE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-# CONFIG_IPQ_APSS_PLL is not set
-CONFIG_IPQ_GCC_4019=y
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_KPSS_XCC is not set
-# CONFIG_KRAITCC is not set
-CONFIG_LEDS_LP5523=y
-CONFIG_LEDS_LP5562=y
-CONFIG_LEDS_LP55XX_COMMON=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ4019=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-# CONFIG_MFD_QCOM_RPM is not set
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MSM_GCC_8660 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K_IPQ4019=y
-CONFIG_NET_DSA_TAG_IPQ4019=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OPTEE=y
-CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-CONFIG_PHY_QCOM_IPQ4019_USB=y
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-CONFIG_PINCTRL_IPQ4019=y
-# CONFIG_PINCTRL_IPQ6018 is not set
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_IPQ8074 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_MSM8976 is not set
-# CONFIG_PINCTRL_MSM8994 is not set
-# CONFIG_PINCTRL_MSM8996 is not set
-# CONFIG_PINCTRL_MSM8998 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_QCS404 is not set
-# CONFIG_PINCTRL_SC7180 is not set
-# CONFIG_PINCTRL_SDM660 is not set
-# CONFIG_PINCTRL_SDM845 is not set
-# CONFIG_PINCTRL_SM8150 is not set
-# CONFIG_PINCTRL_SM8250 is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_QCA807X_PHY=y
-CONFIG_QCOM_A53PLL=y
-CONFIG_QCOM_BAM_DMA=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_QCOM_IOMMU is not set
-CONFIG_QCOM_IPQ4019_ESS_EDMA=y
-# CONFIG_QCOM_LLCC is not set
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_QFPROM=y
-# CONFIG_QCOM_RMTFS_MEM is not set
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-# CONFIG_QCOM_SOCINFO is not set
-CONFIG_QCOM_TCSR=y
-# CONFIG_QCOM_TSENS is not set
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_REGULATOR_VCTRL=y
-CONFIG_REGULATOR_VQMMC_IPQ4019=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TEE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Wed, 9 Sep 2020 18:38:31 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
-
-Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
-
-Signed-off-by: John Crispin <john@phrozen.org>
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Reviewed-by: Vinod Koul <vkoul@kernel.org>
-Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
- 1 file changed, 74 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -606,5 +606,79 @@
- reg = <4>;
- };
- };
-+
-+ usb3_ss_phy: ssphy@9a000 {
-+ compatible = "qcom,usb-ss-ipq4019-phy";
-+ #phy-cells = <0>;
-+ reg = <0x9a000 0x800>;
-+ reg-names = "phy_base";
-+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
-+ reset-names = "por_rst";
-+ status = "disabled";
-+ };
-+
-+ usb3_hs_phy: hsphy@a6000 {
-+ compatible = "qcom,usb-hs-ipq4019-phy";
-+ #phy-cells = <0>;
-+ reg = <0xa6000 0x40>;
-+ reg-names = "phy_base";
-+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
-+ reset-names = "por_rst", "srif_rst";
-+ status = "disabled";
-+ };
-+
-+ usb3: usb3@8af8800 {
-+ compatible = "qcom,dwc3";
-+ reg = <0x8af8800 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
-+ <&gcc GCC_USB3_SLEEP_CLK>,
-+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
-+ clock-names = "master", "sleep", "mock_utmi";
-+ ranges;
-+ status = "disabled";
-+
-+ dwc3@8a00000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x8a00000 0xf8000>;
-+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ dr_mode = "host";
-+ };
-+ };
-+
-+ usb2_hs_phy: hsphy@a8000 {
-+ compatible = "qcom,usb-hs-ipq4019-phy";
-+ #phy-cells = <0>;
-+ reg = <0xa8000 0x40>;
-+ reg-names = "phy_base";
-+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
-+ reset-names = "por_rst", "srif_rst";
-+ status = "disabled";
-+ };
-+
-+ usb2: usb2@60f8800 {
-+ compatible = "qcom,dwc3";
-+ reg = <0x60f8800 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
-+ <&gcc GCC_USB2_SLEEP_CLK>,
-+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
-+ clock-names = "master", "sleep", "mock_utmi";
-+ ranges;
-+ status = "disabled";
-+
-+ dwc3@6000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x6000000 0xf8000>;
-+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&usb2_hs_phy>;
-+ phy-names = "usb2-phy";
-+ dr_mode = "host";
-+ };
-+ };
- };
- };
+++ /dev/null
-From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Wed, 9 Sep 2020 21:56:37 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels
-
-Lets add labels to more commonly used nodes for easier modification in board DTS files.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -191,7 +191,7 @@
- reg = <0x1800000 0x60000>;
- };
-
-- rng@22000 {
-+ prng: rng@22000 {
- compatible = "qcom,prng";
- reg = <0x22000 0x140>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
-@@ -301,7 +301,7 @@
- status = "disabled";
- };
-
-- crypto@8e3a000 {
-+ crypto: crypto@8e3a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0x08e3a000 0x6000>;
- clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
-@@ -387,7 +387,7 @@
- dma-names = "rx", "tx";
- };
-
-- watchdog@b017000 {
-+ watchdog: watchdog@b017000 {
- compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
- reg = <0xb017000 0x40>;
- clocks = <&sleep_clk>;
+++ /dev/null
-From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 7 Sep 2020 12:19:37 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node
-
-Since we now have driver for the SDHCI VQMMC LDO needed
-for I/0 voltage levels lets introduce the necessary node for it.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -210,6 +210,16 @@
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-+ vqmmc: regulator@1948000 {
-+ compatible = "qcom,vqmmc-ipq4019-regulator";
-+ reg = <0x01948000 0x4>;
-+ regulator-name = "vqmmc";
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <3000000>;
-+ regulator-always-on;
-+ status = "disabled";
-+ };
-+
- sdhci: sdhci@7824900 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x7824900 0x11c>, <0x7824000 0x800>;
+++ /dev/null
-From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Sun, 11 Mar 2018 14:41:31 +0100
-Subject: [PATCH 2/2] clk: fix apss cpu overclocking
-
-There's an interaction issue between the clk changes:"
-clk: qcom: ipq4019: Add the apss cpu pll divider clock node
-clk: qcom: ipq4019: remove fixed clocks and add pll clocks
-" and the cpufreq-dt.
-
-cpufreq-dt is now spamming the kernel-log with the following:
-
-[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
-for freq 761142857 (-34)
-
-This only happens on certain devices like the Compex WPJ428
-and AVM FritzBox!4040. However, other devices like the Asus
-RT-AC58U and Meraki MR33 work just fine.
-
-The issue stem from the fact that all higher CPU-Clocks
-are achieved by switching the clock-parent to the P_DDRPLLAPSS
-(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
-as part of the DDR calibration.
-
-For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
-at round 533 MHz (ddrpllsdcc = 190285714 Hz).
-
-whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
-clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
-
-This patch attempts to fix the issue by modifying
-clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
-to use a new qcom_find_freq_close() function, which returns the closest
-matching frequency, instead of the next higher. This way, the SoC in
-the FB4040 (with its max clock speed of 710.4 MHz) will no longer
-try to overclock to 761 MHz.
-
-Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
- 1 file changed, 31 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
- .reg = 0x2f020,
- };
-
-+
-+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
-+ unsigned long rate)
-+{
-+ const struct freq_tbl *last = NULL;
-+
-+ for ( ; f->freq; f++) {
-+ if (rate == f->freq)
-+ return f;
-+
-+ if (f->freq > rate) {
-+ if (!last ||
-+ (f->freq - rate) < (rate - last->freq))
-+ return f;
-+ else
-+ return last;
-+ }
-+ last = f;
-+ }
-+
-+ return last;
-+}
-+
- /*
- * Round rate function for APSS CPU PLL Clock divider.
- * It looks up the frequency table and returns the next higher frequency
-@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
- struct clk_hw *p_hw;
- const struct freq_tbl *f;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
- u32 mask;
- int ret;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1305,6 +1328,7 @@ static unsigned long
- clk_cpu_div_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
- {
-+ const struct freq_tbl *f;
- struct clk_fepll *pll = to_clk_fepll(hw);
- u32 cdiv, pre_div;
- u64 rate;
-@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
- rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
- do_div(rate, pre_div);
-
-- return rate;
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
-+ if (!f)
-+ return rate;
-+
-+ return f->freq;
- };
-
- static const struct clk_ops clk_regmap_cpu_div_ops = {
+++ /dev/null
-From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Tue, 28 Mar 2017 22:35:33 +0530
-Subject: [PATCH] clk: qcom: ipq4019: add ess reset
-
-Added the ESS reset in IPQ4019 GCC.
-
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
- 2 files changed, 22 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
- [GCC_TCSR_BCR] = {0x22000, 0},
- [GCC_MPM_BCR] = {0x24000, 0},
- [GCC_SPDM_BCR] = {0x25000, 0},
-+ [ESS_MAC1_ARES] = {0x1200C, 0},
-+ [ESS_MAC2_ARES] = {0x1200C, 1},
-+ [ESS_MAC3_ARES] = {0x1200C, 2},
-+ [ESS_MAC4_ARES] = {0x1200C, 3},
-+ [ESS_MAC5_ARES] = {0x1200C, 4},
-+ [ESS_PSGMII_ARES] = {0x1200C, 5},
-+ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
-+ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
-+ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
-+ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
-+ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
- };
-
- static const struct regmap_config gcc_ipq4019_regmap_config = {
---- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-@@ -165,5 +165,16 @@
- #define GCC_QDSS_BCR 69
- #define GCC_MPM_BCR 70
- #define GCC_SPDM_BCR 71
-+#define ESS_MAC1_ARES 72
-+#define ESS_MAC2_ARES 73
-+#define ESS_MAC3_ARES 74
-+#define ESS_MAC4_ARES 75
-+#define ESS_MAC5_ARES 76
-+#define ESS_PSGMII_ARES 77
-+#define ESS_MAC1_CLK_DIS 78
-+#define ESS_MAC2_CLK_DIS 79
-+#define ESS_MAC3_CLK_DIS 80
-+#define ESS_MAC4_CLK_DIS 81
-+#define ESS_MAC5_CLK_DIS 82
-
- #endif
+++ /dev/null
-From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 30 Oct 2020 13:36:31 +0100
-Subject: [PATCH] arm: compressed: add appended DTB section
-
-This adds a appended_dtb section to the ARM decompressor
-linker script.
-
-This allows using the existing ARM zImage appended DTB support for
-appending a DTB to the raw ELF kernel.
-
-Its size is set to 1MB max to match the zImage appended DTB size limit.
-
-To use it to pass the DTB to the kernel, objcopy is used:
-
-objcopy --set-section-flags=.appended_dtb=alloc,contents \
- --update-section=.appended_dtb=<target>.dtb vmlinux
-
-This is based off the following patch:
-https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/compressed/vmlinux.lds.S
-+++ b/arch/arm/boot/compressed/vmlinux.lds.S
-@@ -101,6 +101,13 @@ SECTIONS
-
- _edata = .;
-
-+ .appended_dtb : {
-+ /* leave space for appended DTB */
-+ . += 0x100000;
-+ }
-+
-+ _edata_dtb = .;
-+
- /*
- * The image_end section appears after any additional loadable sections
- * that the linker may decide to insert in the binary image. Having
-@@ -138,4 +145,4 @@ SECTIONS
-
- ARM_ASSERTS
- }
--ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
-+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
+++ /dev/null
-From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
-From: John Thomson <git@johnthomson.fastmail.com.au>
-Date: Fri, 23 Oct 2020 19:42:36 +1000
-Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
-
-For IPQ40XX systems where the SoC watchdog is activated before linux,
-the watchdog timer may be too small for linux to finish uncompress,
-boot, and watchdog management start.
-If the watchdog is enabled, set the timeout for it to 30 seconds.
-The functionality and offsets were copied from:
-drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
-The watchdog memory address was taken from:
-arch/arm/boot/dts/qcom-ipq4019.dtsi
-
-This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
-RouterBoot bootloader.
-
-Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
----
- arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -602,6 +602,41 @@ not_relocated: mov r0, #0
- bic r4, r4, #1
- blne cache_on
-
-+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
-+ * if it is enabled, so that there is time for kernel
-+ * to decompress, boot, and take over the watchdog.
-+ * data and functionality from drivers/watchdog/qcom-wdt.c
-+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
-+ */
-+#ifdef CONFIG_ARCH_IPQ40XX
-+watchdog_set:
-+ /* offsets:
-+ * 0x04 reset (=1 resets countdown)
-+ * 0x08 enable (=0 disables)
-+ * 0x0c status (=1 when SoC was reset by watchdog)
-+ * 0x10 bark (=timeout warning in ticks)
-+ * 0x14 bite (=timeout reset in ticks)
-+ * clock rate is 1<<15 hertz
-+ */
-+ .equ watchdog, 0x0b017000 @Store watchdog base address
-+ movw r0, #:lower16:watchdog
-+ movt r0, #:upper16:watchdog
-+ ldr r1, [r0, #0x08] @Get enabled?
-+ cmp r1, #1 @If not enabled, do not change
-+ bne watchdog_finished
-+ mov r1, #0
-+ str r1, [r0, #0x08] @Disable the watchdog
-+ mov r1, #1
-+ str r1, [r0, #0x04] @Pet the watchdog
-+ mov r1, #30 @30 seconds timeout
-+ lsl r1, r1, #15 @converted to ticks
-+ str r1, [r0, #0x10] @Set the bark timeout
-+ str r1, [r0, #0x14] @Set the bite timeout
-+ mov r1, #1
-+ str r1, [r0, #0x08] @Enable the watchdog
-+watchdog_finished:
-+#endif /* CONFIG_ARCH_IPQ40XX */
-+
- /*
- * The C runtime environment should now be setup sufficiently.
- * Set up some pointers, and start decompressing.
+++ /dev/null
-From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Dec 2020 13:35:35 +0100
-Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
-
-When using sdhci_msm_set_clock clock setting will fail, so lets
-use the generic sdhci_set_clock.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mmc/host/sdhci-msm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -2193,7 +2193,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
-
- static const struct sdhci_ops sdhci_msm_ops = {
- .reset = sdhci_msm_reset,
-- .set_clock = sdhci_msm_set_clock,
-+ .set_clock = sdhci_set_clock,
- .get_min_clock = sdhci_msm_get_min_clock,
- .get_max_clock = sdhci_msm_get_max_clock,
- .set_bus_width = sdhci_set_bus_width,
+++ /dev/null
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -404,6 +404,20 @@ static int __qcom_scm_set_dload_mode(str
- return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
- }
-
-+static int __qcom_scm_disable_sdi(struct device *dev)
-+{
-+ struct qcom_scm_desc desc = {
-+ .svc = QCOM_SCM_SVC_BOOT,
-+ .cmd = QCOM_SCM_BOOT_CONFIG_SDI,
-+ .arginfo = QCOM_SCM_ARGS(2),
-+ .args[0] = 1 /* 1: disable watchdog debug */,
-+ .args[1] = 0 /* 0: disable SDI */,
-+ .owner = ARM_SMCCC_OWNER_SIP,
-+ };
-+
-+ return qcom_scm_call(__scm->dev, &desc, NULL);
-+}
-+
- static void qcom_scm_set_download_mode(bool enable)
- {
- bool avail;
-@@ -1250,6 +1264,13 @@ static int qcom_scm_probe(struct platfor
- if (download_mode)
- qcom_scm_set_download_mode(true);
-
-+ /*
-+ * Factory firmware leaves SDI (a debug interface), which prevents
-+ * clean reboot.
-+ */
-+ if (of_machine_is_compatible("google,wifi"))
-+ __qcom_scm_disable_sdi(__scm->dev);
-+
- return 0;
- }
-
---- a/drivers/firmware/qcom_scm.h
-+++ b/drivers/firmware/qcom_scm.h
-@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
- #define QCOM_SCM_SVC_BOOT 0x01
- #define QCOM_SCM_BOOT_SET_ADDR 0x01
- #define QCOM_SCM_BOOT_TERMINATE_PC 0x02
-+#define QCOM_SCM_BOOT_CONFIG_SDI 0x09
- #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
- #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
- #define QCOM_SCM_FLUSH_FLAG_MASK 0x3
+++ /dev/null
---- a/drivers/firmware/qcom_scm-legacy.c
-+++ b/drivers/firmware/qcom_scm-legacy.c
-@@ -13,6 +13,9 @@
- #include <linux/arm-smccc.h>
- #include <linux/dma-mapping.h>
-
-+#include <asm/cacheflush.h>
-+#include <asm/outercache.h>
-+
- #include "qcom_scm.h"
-
- static DEFINE_MUTEX(qcom_scm_lock);
-@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
- } while (res->a0 == QCOM_SCM_INTERRUPTED);
- }
-
-+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
-+{
-+ u32 cacheline_size, ctr;
-+
-+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
-+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
-+
-+ start = round_down(start, cacheline_size);
-+ end = round_up(end, cacheline_size);
-+ outer_inv_range(start, end);
-+ while (start < end) {
-+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
-+ : "memory");
-+ start += cacheline_size;
-+ }
-+ dsb();
-+ isb();
-+}
-+
- /**
- * qcom_scm_call() - Sends a command to the SCM and waits for the command to
- * finish processing.
-@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,
-
- rsp = scm_legacy_command_to_response(cmd);
-
-- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-- if (dma_mapping_error(dev, cmd_phys)) {
-- kfree(cmd);
-- return -ENOMEM;
-+ if (dev) {
-+ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-+ if (dma_mapping_error(dev, cmd_phys)) {
-+ kfree(cmd);
-+ return -ENOMEM;
-+ }
-+ } else {
-+ cmd_phys = virt_to_phys(cmd);
-+ __cpuc_flush_dcache_area(cmd, alloc_len);
-+ outer_flush_range(cmd_phys, cmd_phys + alloc_len);
- }
-
- smc.args[0] = 1;
-@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,
- goto out;
-
- do {
-- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
-- sizeof(*rsp), DMA_FROM_DEVICE);
-+ if (dev) {
-+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
-+ cmd_len, sizeof(*rsp),
-+ DMA_FROM_DEVICE);
-+ } else {
-+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
-+ cmd_len;
-+ qcom_scm_inv_range(start, start + sizeof(*rsp));
-+ }
- } while (!rsp->is_complete);
-
-- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-- le32_to_cpu(rsp->buf_offset),
-- resp_len, DMA_FROM_DEVICE);
-+ if (dev) {
-+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-+ le32_to_cpu(rsp->buf_offset),
-+ resp_len, DMA_FROM_DEVICE);
-+ } else {
-+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
-+ le32_to_cpu(rsp->buf_offset);
-+ qcom_scm_inv_range(start, start + resp_len);
-+ }
-
- if (res) {
- res_buf = scm_legacy_get_response_buffer(rsp);
-@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,
- res->result[i] = le32_to_cpu(res_buf[i]);
- }
- out:
-- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
-+ if (dev)
-+ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
- kfree(cmd);
- return ret;
- }
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en
- desc.args[0] = flags;
- desc.args[1] = virt_to_phys(entry);
-
-+ /*
-+ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
-+ * require ugly DMA invalidation support that was dropped upstream a
-+ * while ago. For more info, see:
-+ *
-+ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
-+ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
-+ */
-+ if (of_machine_is_compatible("google,wifi"))
-+ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
-+
- return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
- }
- EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
+++ /dev/null
-From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
-Date: Wed, 20 Apr 2022 12:08:38 +0200
-Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
- NAND flash
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
-has 128 bytes OOB. This adds a static NAND ID entry to correct this.
-
-Tested on FRITZ!Box 7530 flashed with OpenWrt.
-
-Signed-off-by: Andreas Böhler <dev@aboehler.at>
-(changed id_len to 8, added comment about possible counterfeits)
----
---- a/drivers/mtd/nand/raw/nand_ids.c
-+++ b/drivers/mtd/nand/raw/nand_ids.c
-@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
- {"TC58NVG0S3E 1G 3.3V 8-bit",
- { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
- SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
-+ {"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
-+ { .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
-+ SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
- {"TC58NVG2S0F 4G 3.3V 8-bit",
- { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
- SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
+++ /dev/null
-From da75807ac41175e9db8c95f7a172b4133763b744 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <j4g8y7@gmail.com>
-Date: Mon, 11 Jan 2021 17:49:36 +0100
-Subject: [PATCH] skbuff: add DSA specific data to struct skb_shared_info
-
-All of the already existing DSA tagging protocol drivers
-are storing the tagging data directly into the skb. In most
-cases that is the only way to send the required information
-to the underlying ethernet switch.
-
-However on certain platforms (like the Qualcomm IPQ40xx
-SoCs) the built-in ethernet switch is connected directly
-to an ethernet MAC, and the tagging information must be
-sent out-of-band which is done directly via the hardware
-TX descriptors of the ethernet MAC.
-
-In such cases, putting the information into the skb causes
-unneccesary overhead, because the ethernet driver must
-remove that before sending the ethernet frame towards to
-the hardware.
-
-This change adds two new DSA specific fields to struct
-skb_shared_info which makes it possible to send the
-tagging information via skb->shinfo. With this approach,
-the twofold modifications of the skb data can be avoided.
-
-Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
----
- include/linux/skbuff.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -522,6 +522,9 @@ struct skb_shared_info {
- unsigned int gso_type;
- u32 tskey;
-
-+ unsigned int dsa_tag_proto;
-+ unsigned char dsa_tag_data[8];
-+
- /*
- * Warning : all fields before dataref are cleared in __alloc_skb()
- */
+++ /dev/null
-From 29a0c2fae991cab142575c92276c0afdeb260ebe Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <j4g8y7@gmail.com>
-Date: Thu, 28 Oct 2021 21:44:52 +0200
-Subject: [PATCH] net: dsa: tag_ipq4019: add shinfo based tagging driver for
- IPQ40xx
-
-This change adds a tagging protocol driver for the built-in
-ethernet switch of the Qualcomm Atheros IPQ4019 SoCs.
-
-In comparison to the existing tagging protocols this hardware
-requires a slightly different approach because the switch does
-not use in-band tags.
-
-On the receive path, the source port information is embedded
-into the RX descriptors of the ethernet MAC hardware. Similarly,
-the destination port mask must be sent via the TX descriptors
-of the ethernet MAC when a packet is sent towards the switch.
-
-In order to support this special requirements, this patch
-adds a new tagging protocol driver.
-
-The driver extracts the source port information directly
-from the 'receive return descriptor' of the ethernet MAC.
-It is possible because that descriptor is part of the skb
-received from the ethernet driver.
-
-Unfortunatley, it is not possible to put the destination
-port information directly to the TX descriptors, because
-those are handled internally by the driver of the ethernet
-hardware.
-
-To overcome this limitation, this tagging driver uses the
-DSA specific fields in skb->shinfo to send the destination
-port information to the ethernet driver.
-
-A similar tagging driver is exist but that uses skb
-extensions which causes unnecessary overhead.
-
-Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
----
- include/linux/dsa/ipq4019.h | 11 ++++++
- include/net/dsa.h | 2 +
- net/dsa/Kconfig | 6 +++
- net/dsa/Makefile | 1 +
- net/dsa/tag_ipq4019.c | 79 +++++++++++++++++++++++++++++++++++++
- 5 files changed, 99 insertions(+)
- create mode 100644 include/linux/dsa/ipq4019.h
- create mode 100644 net/dsa/tag_ipq4019.c
-
---- /dev/null
-+++ b/include/linux/dsa/ipq4019.h
-@@ -0,0 +1,11 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#ifndef DSA_IPQ40XX_H
-+#define DSA_IPQ40XX_H
-+
-+struct ipq40xx_dsa_tag_data {
-+ u8 from_cpu;
-+ u8 dp;
-+};
-+
-+#endif /* DSA_IPQ40XX_H */
---- a/include/net/dsa.h
-+++ b/include/net/dsa.h
-@@ -46,6 +46,7 @@ struct phylink_link_state;
- #define DSA_TAG_PROTO_AR9331_VALUE 16
- #define DSA_TAG_PROTO_RTL4_A_VALUE 17
- #define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22
-+#define DSA_TAG_PROTO_IPQ4019_VALUE 24
-
- enum dsa_tag_protocol {
- DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
-@@ -67,6 +68,7 @@ enum dsa_tag_protocol {
- DSA_TAG_PROTO_OCELOT = DSA_TAG_PROTO_OCELOT_VALUE,
- DSA_TAG_PROTO_AR9331 = DSA_TAG_PROTO_AR9331_VALUE,
- DSA_TAG_PROTO_RTL4_A = DSA_TAG_PROTO_RTL4_A_VALUE,
-+ DSA_TAG_PROTO_IPQ4019 = DSA_TAG_PROTO_IPQ4019_VALUE,
- };
-
- struct packet_type;
---- a/net/dsa/Kconfig
-+++ b/net/dsa/Kconfig
-@@ -63,6 +63,12 @@ config NET_DSA_TAG_BRCM_PREPEND
- Broadcom switches which places the tag before the Ethernet header
- (prepended).
-
-+config NET_DSA_TAG_IPQ4019
-+ tristate "Tag driver for Qualcomm Atheros IPQ4019 SoC built-in switch"
-+ help
-+ Say Y or M if you want to enable support for tagging frames for
-+ the built-in switch of the Qualcomm Atheros IPQ4019 SoC-s.
-+
- config NET_DSA_TAG_GSWIP
- tristate "Tag driver for Lantiq / Intel GSWIP switches"
- help
---- a/net/dsa/Makefile
-+++ b/net/dsa/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_NET_DSA_TAG_BRCM_COMMON) +=
- obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
- obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
- obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o
-+obj-$(CONFIG_NET_DSA_TAG_IPQ4019) += tag_ipq4019.o
- obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
- obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
- obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
---- /dev/null
-+++ b/net/dsa/tag_ipq4019.c
-@@ -0,0 +1,79 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+/* Copyright (c) 2021, Gabor Juhos <j4g8y7@gmail.com> */
-+
-+#include <linux/bitfield.h>
-+#include <linux/dsa/ipq4019.h>
-+
-+#include "dsa_priv.h"
-+
-+/* Receive Return Descriptor */
-+struct edma_rrd {
-+ u16 rrd0;
-+ u16 rrd1;
-+ u16 rrd2;
-+ u16 rrd3;
-+ u16 rrd4;
-+ u16 rrd5;
-+ u16 rrd6;
-+ u16 rrd7;
-+} __packed;
-+
-+#define EDMA_RRD_SIZE sizeof(struct edma_rrd)
-+
-+#define EDMA_RRD1_PORT_ID_MASK GENMASK(14, 12)
-+
-+static struct sk_buff *ipq4019_sh_tag_xmit(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct dsa_port *dp = dsa_slave_to_port(dev);
-+ struct ipq40xx_dsa_tag_data *tag_data;
-+
-+ BUILD_BUG_ON(sizeof_field(struct skb_shared_info, dsa_tag_data) <
-+ sizeof(struct ipq40xx_dsa_tag_data));
-+
-+ skb_shinfo(skb)->dsa_tag_proto = DSA_TAG_PROTO_IPQ4019;
-+ tag_data = (struct ipq40xx_dsa_tag_data *)skb_shinfo(skb)->dsa_tag_data;
-+
-+ tag_data->from_cpu = 1;
-+ /* set the destination port information */
-+ tag_data->dp = BIT(dp->index);
-+
-+ return skb;
-+}
-+
-+static struct sk_buff *ipq4019_sh_tag_rcv(struct sk_buff *skb,
-+ struct net_device *dev,
-+ struct packet_type *pt)
-+{
-+ struct edma_rrd *rrd;
-+ int offset;
-+ int port;
-+
-+ offset = EDMA_RRD_SIZE + ETH_HLEN;
-+ if (unlikely(skb_headroom(skb) < offset))
-+ return NULL;
-+
-+ rrd = (struct edma_rrd *)(skb->data - offset);
-+ port = FIELD_GET(EDMA_RRD1_PORT_ID_MASK, rrd->rrd1);
-+
-+ skb->dev = dsa_master_find_slave(dev, 0, port);
-+ if (!skb->dev)
-+ return NULL;
-+
-+ return skb;
-+}
-+
-+const struct dsa_device_ops ipq4019_sh_tag_dsa_ops = {
-+ .name = "ipq4019-sh",
-+ .proto = DSA_TAG_PROTO_IPQ4019,
-+ .xmit = ipq4019_sh_tag_xmit,
-+ .rcv = ipq4019_sh_tag_rcv,
-+};
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("DSA tag driver for the IPQ4019 SoC built-in ethernet switch");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
-+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_IPQ4019);
-+
-+module_dsa_tag_driver(ipq4019_sh_tag_dsa_ops);
+++ /dev/null
-From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 12:36:51 +0100
-Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support
-
-Allow compiling the IPQESS driver that supports the
-Qualcomm IPQ40xx SoC built-in ethernet controller.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++
- drivers/net/ethernet/qualcomm/Makefile | 1 +
- 2 files changed, 12 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -60,6 +60,17 @@ config QCOM_EMAC
- low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- Precision Clock Synchronization Protocol.
-
-+config QCOM_IPQ4019_ESS_EDMA
-+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
-+ depends on OF
-+ select PHYLINK
-+ help
-+ This driver supports the Qualcomm Atheros IPQ40xx built-in
-+ ESS EDMA ethernet controller.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called ipqess.
-+
- source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
-
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
- qcauart-objs := qca_uart.o
-
- obj-y += emac/
-+obj-y += ipqess/
-
- obj-$(CONFIG_RMNET) += rmnet/
+++ /dev/null
-From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Wed, 20 Oct 2021 13:21:45 +0200
-Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node
-
-Since IPQ40xx SoC built-in ethernet controller now has a driver,
-add its DT node so it can be used.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -38,6 +38,7 @@
- spi1 = &blsp1_spi2;
- i2c0 = &blsp1_i2c3;
- i2c1 = &blsp1_i2c4;
-+ ethernet0 = &gmac;
- };
-
- cpus {
-@@ -589,6 +590,57 @@
- status = "disabled";
- };
-
-+ gmac: ethernet@c080000 {
-+ compatible = "qcom,ipq4019-ess-edma";
-+ reg = <0xc080000 0x8000>;
-+ resets = <&gcc ESS_RESET>;
-+ reset-names = "ess_rst";
-+ clocks = <&gcc GCC_ESS_CLK>;
-+ clock-names = "ess_clk";
-+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
-+
-+ status = "disabled";
-+
-+ phy-mode = "internal";
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ pause;
-+ asym-pause;
-+ };
-+ };
-+
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From 3e1825e00dafb68eec25df389b63f3ab3d905b59 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <j4g8y7@gmail.com>
-Date: Fri, 25 Dec 2020 08:02:47 +0100
-Subject: [PATCH] net: phy: define PSGMII PHY interface mode
-
-The PSGMII interface is similar to QSGMII. The main difference
-is that the PSGMII interface combines five SGMII lines into a
-single link while in QSGMII only four lines are combined.
-
-Similarly to the QSGMII, this interface mode might also needs
-special handling within the MAC driver.
-
-Add definitions for the PHY layer to allow to express this type
-of connection between the MAC and PHY.
-
-Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
----
- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
- drivers/net/phy/phylink.c | 1 +
- include/linux/phy.h | 3 +++
- 3 files changed, 5 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
-@@ -64,6 +64,7 @@ properties:
- - mii
- - gmii
- - sgmii
-+ - psgmii
- - qsgmii
- - tbi
- - rev-mii
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -289,6 +289,7 @@ static int phylink_parse_mode(struct phy
-
- switch (pl->link_config.interface) {
- case PHY_INTERFACE_MODE_SGMII:
-+ case PHY_INTERFACE_MODE_PSGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- phylink_set(pl->supported, 10baseT_Half);
- phylink_set(pl->supported, 10baseT_Full);
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -134,6 +134,7 @@ typedef enum {
- PHY_INTERFACE_MODE_XGMII,
- PHY_INTERFACE_MODE_XLGMII,
- PHY_INTERFACE_MODE_MOCA,
-+ PHY_INTERFACE_MODE_PSGMII,
- PHY_INTERFACE_MODE_QSGMII,
- PHY_INTERFACE_MODE_TRGMII,
- PHY_INTERFACE_MODE_100BASEX,
-@@ -201,6 +202,8 @@ static inline const char *phy_modes(phy_
- return "xlgmii";
- case PHY_INTERFACE_MODE_MOCA:
- return "moca";
-+ case PHY_INTERFACE_MODE_PSGMII:
-+ return "psgmii";
- case PHY_INTERFACE_MODE_QSGMII:
- return "qsgmii";
- case PHY_INTERFACE_MODE_TRGMII:
+++ /dev/null
-From b5f71652b85a85ea53162e9e2b760b84fd0d254f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 18:10:28 +0100
-Subject: [PATCH] net: dsa: add Qualcomm IPQ4019 built-in switch support
-
-Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
-
-It shares most of the stuff with its external counterpart, however it is
-modified for the SoC.
-Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
-instead of 7.
-It also has no built-in PHY-s but rather requires external PSGMII based
-companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
-out calibration before using them.
-PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
-unfortunately requires some magic values as the datasheet doesnt document
-the bits that are being set or the register at all.
-
-Since its built-in it is MMIO like other peripherals and doesn't have its
-own MDIO bus but depends on the SoC provided one.
-
-CPU connection is at Port 0 and it uses some kind of a internal connection
-and no traditional RGMII/SGMII.
-It also doesn't use in-band tagging like other qca8k switches so a shinfo
-based tagger is used.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/dsa/qca/Kconfig | 9 +++++++++
- drivers/net/dsa/qca/Makefile | 1 +
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/dsa/qca/Kconfig
-+++ b/drivers/net/dsa/qca/Kconfig
-@@ -7,3 +7,12 @@ config NET_DSA_AR9331
- help
- This enables support for the Qualcomm Atheros AR9331 built-in Ethernet
- switch.
-+
-+config NET_DSA_QCA8K_IPQ4019
-+ tristate "Qualcomm Atheros IPQ4019 built-in Ethernet switch support"
-+ depends on HAS_IOMEM && NET_DSA
-+ select NET_DSA_TAG_IPQ4019
-+ select REGMAP
-+ help
-+ This enables support for the Qualcomm Atheros IPQ4019 SoC built-in
-+ Ethernet switch.
---- a/drivers/net/dsa/qca/Makefile
-+++ b/drivers/net/dsa/qca/Makefile
-@@ -1,2 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0-only
- obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o
-+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o
+++ /dev/null
-From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 18:15:04 +0100
-Subject: [PATCH] arm: dts: ipq4019: add switch node
-
-Since the built-in IPQ40xx switch now has a driver, add the required node
-for it to work.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++
- 1 file changed, 78 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -590,6 +590,82 @@
- status = "disabled";
- };
-
-+ switch: switch@c000000 {
-+ compatible = "qca,ipq4019-qca8337n";
-+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
-+ reg-names = "base", "psgmii_phy";
-+ resets = <&gcc ESS_PSGMII_ARES>;
-+ reset-names = "psgmii_rst";
-+ mdio = <&mdio>;
-+ psgmii-ethphy = <&psgmiiphy>;
-+
-+ status = "disabled";
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 { /* MAC0 */
-+ reg = <0>;
-+ label = "cpu";
-+ ethernet = <&gmac>;
-+ phy-mode = "internal";
-+
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ pause;
-+ asym-pause;
-+ };
-+ };
-+
-+ swport1: port@1 { /* MAC1 */
-+ reg = <1>;
-+ label = "lan1";
-+ phy-handle = <ðphy0>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport2: port@2 { /* MAC2 */
-+ reg = <2>;
-+ label = "lan2";
-+ phy-handle = <ðphy1>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport3: port@3 { /* MAC3 */
-+ reg = <3>;
-+ label = "lan3";
-+ phy-handle = <ðphy2>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport4: port@4 { /* MAC4 */
-+ reg = <4>;
-+ label = "lan4";
-+ phy-handle = <ðphy3>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport5: port@5 { /* MAC5 */
-+ reg = <5>;
-+ label = "wan";
-+ phy-handle = <ðphy4>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
- gmac: ethernet@c080000 {
- compatible = "qcom,ipq4019-ess-edma";
- reg = <0xc080000 0x8000>;
+++ /dev/null
-From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Thu, 1 Oct 2020 15:05:35 +0200
-Subject: [PATCH] dt-bindings: net: add QCA807x PHY
-
-Add DT bindings for Qualcomm QCA807x PHY series.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
- 1 file changed, 45 insertions(+)
- create mode 100644 include/dt-bindings/net/qcom-qca807x.h
-
---- /dev/null
-+++ b/include/dt-bindings/net/qcom-qca807x.h
-@@ -0,0 +1,45 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+/*
-+ * Device Tree constants for the Qualcomm QCA807X PHYs
-+ */
-+
-+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
-+#define _DT_BINDINGS_QCOM_QCA807X_H
-+
-+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
-+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
-+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
-+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
-+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
-+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
-+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
-+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
-+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
-+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
-+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
-+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
-+/* Default value */
-+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
-+
-+/* Full amplitude, full bias current */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
-+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
-+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
-+/* Both amplitude and bias current follow DSP */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
-+/* Full amplitude, half bias current */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
-+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
-+ * otherwise half bias current
-+ */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
-+/* Full amplitude; same bias current setting with “010” and “011”,
-+ * but half more bias is reduced when cable <10m
-+ */
-+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
-+/* Amplitude follow DSP; same bias current setting with “110”, default value */
-+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
-+
-+#endif
+++ /dev/null
-From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Wed, 7 Oct 2020 17:38:48 +0200
-Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
-
-This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
-
-They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
-
-They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
-
-Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
-
-Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
-But some vendors used these to driver generic LED-s controlled by userspace,
-so lets enable registering each PHY as GPIO controller and add driver for it.
-
-These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/phy/Kconfig | 6 ++++++
- drivers/net/phy/Makefile | 1 +
- 2 files changed, 7 insertions(+)
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -320,6 +320,12 @@ config AT803X_PHY
- Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
- QCA8337(Internal qca8k PHY) model
-
-+config QCA807X_PHY
-+ tristate "Qualcomm QCA807X PHYs"
-+ depends on OF_MDIO
-+ help
-+ Currently supports the QCA8072 and QCA8075 models.
-+
- config QSEMI_PHY
- tristate "Quality Semiconductor PHYs"
- help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -88,6 +88,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/
- obj-$(CONFIG_NATIONAL_PHY) += national.o
- obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
- obj-$(CONFIG_QSEMI_PHY) += qsemi.o
-+obj-$(CONFIG_QCA807X_PHY) += qca807x.o
- obj-$(CONFIG_REALTEK_PHY) += realtek.o
- obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
+++ /dev/null
-From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 2 Oct 2020 10:43:26 +0200
-Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
-
-This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -8,6 +8,7 @@
- #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/net/qcom-qca807x.h>
-
- / {
- #address-cells = <1>;
-@@ -726,22 +727,38 @@
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
-+
-+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
-+
-+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
-+
-+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- };
-
- ethphy3: ethernet-phy@3 {
- reg = <3>;
-+
-+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
- };
-
- ethphy4: ethernet-phy@4 {
- reg = <4>;
-+
-+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
-+ };
-+
-+ psgmiiphy: psgmii-phy@5 {
-+ reg = <5>;
-+
-+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
- };
- };
-
+++ /dev/null
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
- obj-$(CONFIG_QCOM_SMSM) += smsm.o
- obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
- obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
-+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
- obj-$(CONFIG_QCOM_APR) += apr.o
- obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
- obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -190,6 +190,13 @@ config QCOM_SOCINFO
- Say yes here to support the Qualcomm socinfo driver, providing
- information about the SoC to user space.
-
-+config QCOM_TCSR
-+ tristate "QCOM Top Control and Status Registers"
-+ depends on ARCH_QCOM
-+ help
-+ Say y here to enable TCSR support. The TCSR provides control
-+ functions for various peripherals.
-+
- config QCOM_WCNSS_CTRL
- tristate "Qualcomm WCNSS control driver"
- depends on ARCH_QCOM || COMPILE_TEST
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL 0xb0
-+#define TCSR_USB_HSPHY_CONFIG 0xC
-+
-+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
-+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
-+
-+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
-+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
-+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ const struct device_node *node = pdev->dev.of_node;
-+ void __iomem *base;
-+ u32 val;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+ writel(val, base + TCSR_USB_PORT_SEL);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
-+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
-+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
-+ u32 tmp = 0;
-+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
-+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
-+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
-+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
-+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
-+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
-+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
-+ dev_info(&pdev->dev,
-+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
-+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+ { .compatible = "qcom,tcsr", },
-+ { },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+ .driver = {
-+ .name = "tcsr",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tcsr_dt_match,
-+ },
-+ .probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,48 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0 0x1
-+#define TCSR_USB_SELECT_USB3_P1 0x2
-+#define TCSR_USB_SELECT_USB3_DUAL 0x3
-+
-+/* IPQ40xx HS PHY Mode Select */
-+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
-+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
-+
-+/* IPQ40xx ess interface mode select */
-+#define TCSR_ESS_PSGMII 0
-+#define TCSR_ESS_PSGMII_RGMII5 1
-+#define TCSR_ESS_PSGMII_RMII0 2
-+#define TCSR_ESS_PSGMII_RMII1 4
-+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
-+#define TCSR_ESS_PSGMII_RGMII4 9
-+
-+/*
-+ * IPQ40xx WiFi Global Config
-+ * Bit 30:AXID_EN
-+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
-+ * Bit 24: Use locally generated socslv_wxi_bvalid
-+ * 1: use locally generate socslv_wxi_bvalid for performance.
-+ * 0: use SNOC socslv_wxi_bvalid.
-+ */
-+#define TCSR_WIFI_GLB_CFG 0x41000000
-+
-+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
-+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
-+
-+#endif
+++ /dev/null
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -15,6 +15,7 @@
- */
-
- #include "qcom-ipq4019.dtsi"
-+#include <dt-bindings/soc/qcom,tcsr.h>
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
-@@ -29,6 +30,32 @@
- };
-
- soc {
-+ tcsr@194b000 {
-+ /* select hostmode */
-+ compatible = "qcom,tcsr";
-+ reg = <0x194b000 0x100>;
-+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-+ status = "okay";
-+ };
-+
-+ ess_tcsr@1953000 {
-+ compatible = "qcom,tcsr";
-+ reg = <0x1953000 0x1000>;
-+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-+ };
-+
-+ tcsr@1949000 {
-+ compatible = "qcom,tcsr";
-+ reg = <0x1949000 0x100>;
-+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-+ };
-+
-+ tcsr@1957000 {
-+ compatible = "qcom,tcsr";
-+ reg = <0x1957000 0x100>;
-+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-+ };
-+
- rng@22000 {
- status = "ok";
- };
-@@ -74,14 +101,6 @@
- pinctrl-names = "default";
- status = "ok";
- cs-gpios = <&tlmm 54 0>;
--
-- mx25l25635e@0 {
-- #address-cells = <1>;
-- #size-cells = <1>;
-- reg = <0>;
-- compatible = "mx25l25635e";
-- spi-max-frequency = <24000000>;
-- };
- };
-
- serial@78af000 {
-@@ -109,5 +128,41 @@
- wifi@a800000 {
- status = "ok";
- };
-+
-+ mdio@90000 {
-+ status = "okay";
-+ };
-+
-+ ess-switch@c000000 {
-+ status = "okay";
-+ };
-+
-+ ess-psgmii@98000 {
-+ status = "okay";
-+ };
-+
-+ edma@c080000 {
-+ status = "okay";
-+ };
-+
-+ usb3_ss_phy: ssphy@9a000 {
-+ status = "okay";
-+ };
-+
-+ usb3_hs_phy: hsphy@a6000 {
-+ status = "okay";
-+ };
-+
-+ usb3: usb3@8af8800 {
-+ status = "okay";
-+ };
-+
-+ usb2_hs_phy: hsphy@a8000 {
-+ status = "okay";
-+ };
-+
-+ usb2: usb2@60f8800 {
-+ status = "okay";
-+ };
- };
- };
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-@@ -18,5 +18,73 @@
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
-+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
-
-+ memory {
-+ device_type = "memory";
-+ reg = <0x80000000 0x10000000>;
-+ };
-+};
-+
-+&blsp1_spi1 {
-+ mx25l25635f@0 {
-+ compatible = "mx25l25635f", "jedec,spi-nor";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ reg = <0>;
-+ spi-max-frequency = <24000000>;
-+
-+ SBL1@0 {
-+ label = "SBL1";
-+ reg = <0x0 0x40000>;
-+ read-only;
-+ };
-+ MIBIB@40000 {
-+ label = "MIBIB";
-+ reg = <0x40000 0x20000>;
-+ read-only;
-+ };
-+ QSEE@60000 {
-+ label = "QSEE";
-+ reg = <0x60000 0x60000>;
-+ read-only;
-+ };
-+ CDT@c0000 {
-+ label = "CDT";
-+ reg = <0xc0000 0x10000>;
-+ read-only;
-+ };
-+ DDRPARAMS@d0000 {
-+ label = "DDRPARAMS";
-+ reg = <0xd0000 0x10000>;
-+ read-only;
-+ };
-+ APPSBLENV@e0000 {
-+ label = "APPSBLENV";
-+ reg = <0xe0000 0x10000>;
-+ read-only;
-+ };
-+ APPSBL@f0000 {
-+ label = "APPSBL";
-+ reg = <0xf0000 0x80000>;
-+ read-only;
-+ };
-+ ART@170000 {
-+ label = "ART";
-+ reg = <0x170000 0x10000>;
-+ read-only;
-+ };
-+ kernel@180000 {
-+ label = "kernel";
-+ reg = <0x180000 0x400000>;
-+ };
-+ rootfs@580000 {
-+ label = "rootfs";
-+ reg = <0x580000 0x1600000>;
-+ };
-+ firmware@180000 {
-+ label = "firmware";
-+ reg = <0x180000 0x1a00000>;
-+ };
-+ };
- };
+++ /dev/null
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-@@ -17,53 +17,79 @@
- stdout-path = "serial0:115200n8";
- };
-
-- memory {
-- device_type = "memory";
-- reg = <0x80000000 0x10000000>; /* 256MB */
-- };
--
- soc {
-+ rng@22000 {
-+ status = "okay";
-+ };
-+
- pinctrl@1000000 {
- serial_0_pins: serial0-pinmux {
-- pins = "gpio16", "gpio17";
-- function = "blsp_uart0";
-- bias-disable;
-+ mux {
-+ pins = "gpio16", "gpio17";
-+ function = "blsp_uart0";
-+ bias-disable;
-+ };
- };
-
- serial_1_pins: serial1-pinmux {
-- pins = "gpio8", "gpio9",
-- "gpio10", "gpio11";
-- function = "blsp_uart1";
-- bias-disable;
-+ mux {
-+ pins = "gpio8", "gpio9";
-+ function = "blsp_uart1";
-+ bias-disable;
-+ };
- };
-
- spi_0_pins: spi-0-pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
-- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
-+ };
-+ pinconf {
-+ pins = "gpio13", "gpio14", "gpio15";
-+ drive-strength = <12>;
-+ bias-disable;
-+ };
-+ pinconf_cs {
-+ pins = "gpio12";
-+ drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c-0-pinmux {
-- pins = "gpio20", "gpio21";
-- function = "blsp_i2c0";
-- bias-disable;
-+ pinmux {
-+ function = "blsp_i2c0";
-+ pins = "gpio10", "gpio11";
-+ };
-+ pinconf {
-+ pins = "gpio10", "gpio11";
-+ drive-strength = <16>;
-+ bias-disable;
-+ };
- };
-
- nand_pins: nand-pins {
-- pins = "gpio53", "gpio55", "gpio56",
-- "gpio57", "gpio58", "gpio59",
-- "gpio60", "gpio62", "gpio63",
-- "gpio64", "gpio65", "gpio66",
-- "gpio67", "gpio68", "gpio69";
-- function = "qpic";
-+ pullups {
-+ pins = "gpio52", "gpio53", "gpio58",
-+ "gpio59";
-+ function = "qpic";
-+ bias-pull-up;
-+ };
-+
-+ pulldowns {
-+ pins = "gpio54", "gpio55", "gpio56",
-+ "gpio57", "gpio60", "gpio61",
-+ "gpio62", "gpio63", "gpio64",
-+ "gpio65", "gpio66", "gpio67",
-+ "gpio68", "gpio69";
-+ function = "qpic";
-+ bias-pull-down;
-+ };
- };
- };
-
-@@ -89,11 +115,11 @@
- status = "ok";
- cs-gpios = <&tlmm 12 0>;
-
-- m25p80@0 {
-+ mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
-- compatible = "n25q128a11";
-+ compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
- };
-@@ -103,9 +129,48 @@
- perst-gpio = <&tlmm 38 0x1>;
- };
-
-+ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
-+ pinctrl-0 = <&i2c_0_pins>;
-+ pinctrl-names = "default";
-+
-+ status = "okay";
-+ };
-+
- qpic-nand@79b0000 {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- };
-+
-+ usb3_ss_phy: ssphy@9a000 {
-+ status = "okay";
-+ };
-+
-+ usb3_hs_phy: hsphy@a6000 {
-+ status = "okay";
-+ };
-+
-+ usb3: usb3@8af8800 {
-+ status = "okay";
-+ };
-+
-+ usb2_hs_phy: hsphy@a8000 {
-+ status = "okay";
-+ };
-+
-+ usb2: usb2@60f8800 {
-+ status = "okay";
-+ };
-+
-+ cryptobam: dma@8e04000 {
-+ status = "okay";
-+ };
-+
-+ crypto@8e3a000 {
-+ status = "okay";
-+ };
-+
-+ watchdog@b017000 {
-+ status = "okay";
-+ };
- };
- };
projects / openwrt / openwrt.git / commitdiff