drm/i915: Fix 852GM/GMV cdclk

It seems 852GM/GMV uses a different HPLLCC encoding than the other
85x platforms. For 852GM/GMV cdclk is always 133MHz. Try to detect that
using the PCI revision (sinc the device ID seems useless for that). I'm
not at all sure this is a good idea, but according to the specs it
should work.

v2: Rebased to the latest
v3: Rebased to the latest

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0b1d8d68ad2bb5a2e277626141cc0b8b738af0d4..73a46149564ab731abe6abf09219aaad9c96e36f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6826,6 +6826,14 @@ static int i85x_get_display_clock_speed(struct drm_device *dev)
 {
        u16 hpllcc = 0;
 
+       /*
+        * 852GM/852GMV only supports 133 MHz and the HPLLCC
+        * encoding is different :(
+        * FIXME is this the right way to detect 852GM/852GMV?
+        */
+       if (dev->pdev->revision == 0x1)
+               return 133333;
+
        pci_bus_read_config_word(dev->pdev->bus,
                                 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);