+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- fragment@0 {
- target-path = "/soc/mmc@11230000";
- __overlay__ {
- bus-width = <8>;
- max-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- hs400-ds-delay = <0x14014>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
- };
- };
-};
-
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <daniel@makrotopia.org>
- * Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- fragment@0 {
- target-path = "/soc/spi@1100a000";
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- spi_nand: spi_nand@0 {
- compatible = "spi-nand";
- reg = <0>;
- spi-max-frequency = <10000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bl2";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "reserved";
- reg = <0x80000 0x300000>;
- };
-
- partition@380000 {
- label = "fip";
- reg = <0x380000 0x200000>;
- read-only;
- };
-
- partition@580000 {
- label = "ubi";
- reg = <0x580000 0x7a80000>;
- };
- };
- };
- };
- };
-};
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/*
- * Authors: Daniel Golle <daniel@makrotopia.org>
- * Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- fragment@0 {
- target-path = "/soc/spi@1100a000";
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bl2";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x40000>;
- };
-
- partition@80000 {
- label = "reserved2";
- reg = <0x80000 0x80000>;
- };
-
- partition@100000 {
- label = "fip";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "recovery";
- reg = <0x180000 0xa80000>;
- };
-
- partition@c00000 {
- label = "fit";
- reg = <0xc00000 0x1400000>;
- };
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- fragment@0 {
- target-path = "/soc/mmc@11230000";
- __overlay__ {
- bus-width = <4>;
- max-frequency = <52000000>;
- cap-sd-highspeed;
- status = "okay";
- };
- };
-};
-
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Authors: Sam.Shih <sam.shih@mediatek.com>
- * Frank Wunderlich <frank-w@public-files.de>
- * Daniel Golle <daniel@makrotopia.org>
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#include "mt7986a.dtsi"
-
-/ {
- model = "Bananapi BPI-R3";
- chassis-type = "embedded";
- compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- dcin: regulator-12vd {
- compatible = "regulator-fixed";
- regulator-name = "12vd";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- /* cooling level (0, 1, 2) - pwm inverted */
- cooling-levels = <255 96 0>;
- pwms = <&pwm 0 10000 0>;
- status = "okay";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- reset-key {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&pio 9 GPIO_ACTIVE_LOW>;
- };
-
- wps-key {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 10 GPIO_ACTIVE_LOW>;
- };
- };
-
- /* i2c of the left SFP cage (wan) */
- i2c_sfp1: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- /* i2c of the right SFP cage (lan) */
- i2c_sfp2: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- green_led: led-0 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- blue_led: led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "1.8vd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- vin-supply = <&dcin>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3.3vd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- vin-supply = <&dcin>;
- };
-
- /* left SFP cage (wan) */
- sfp1: sfp-1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
- tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
- };
-
- /* right SFP cage (lan) */
- sfp2: sfp-2 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp2>;
- los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
- tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&cpu_thermal {
- cooling-maps {
- cpu-active-high {
- /* active: set fan to cooling level 2 */
- cooling-device = <&fan 2 2>;
- trip = <&cpu_trip_active_high>;
- };
-
- cpu-active-low {
- /* active: set fan to cooling level 1 */
- cooling-device = <&fan 1 1>;
- trip = <&cpu_trip_active_low>;
- };
-
- cpu-passive {
- /* passive: set fan to cooling level 0 */
- cooling-device = <&fan 0 0>;
- trip = <&cpu_trip_passive>;
- };
- };
-};
-
-&crypto {
- status = "okay";
-};
-
-ð {
- status = "okay";
-
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "2500base-x";
- sfp = <&sfp1>;
- managed = "in-band-status";
- };
-
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&mdio {
- switch: switch@31 {
- compatible = "mediatek,mt7531";
- reg = <31>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&pio>;
- interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
- reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&mmc0 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_default>;
- pinctrl-1 = <&mmc0_pins_uhs>;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_pins>;
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pio {
- i2c_pins: i2c-pins {
- mux {
- function = "i2c";
- groups = "i2c";
- };
- };
-
- mmc0_pins_default: mmc0-pins {
- mux {
- function = "emmc";
- groups = "emmc_51";
- };
- conf-cmd-dat {
- pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
- "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
- "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
- input-enable;
- drive-strength = <4>;
- bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
- };
- conf-clk {
- pins = "EMMC_CK";
- drive-strength = <6>;
- bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
- };
- conf-ds {
- pins = "EMMC_DSL";
- bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
- };
- conf-rst {
- pins = "EMMC_RSTB";
- drive-strength = <4>;
- bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
- };
- };
-
- mmc0_pins_uhs: mmc0-uhs-pins {
- mux {
- function = "emmc";
- groups = "emmc_51";
- };
- conf-cmd-dat {
- pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
- "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
- "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
- input-enable;
- drive-strength = <4>;
- bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
- };
- conf-clk {
- pins = "EMMC_CK";
- drive-strength = <6>;
- bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
- };
- conf-ds {
- pins = "EMMC_DSL";
- bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
- };
- conf-rst {
- pins = "EMMC_RSTB";
- drive-strength = <4>;
- bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
- };
- };
-
- pcie_pins: pcie-pins {
- mux {
- function = "pcie";
- groups = "pcie_clk", "pcie_pereset";
- };
- };
-
- pwm_pins: pwm-pins {
- mux {
- function = "pwm";
- groups = "pwm0", "pwm1_0";
- };
- };
-
- spi_flash_pins: spi-flash-pins {
- mux {
- function = "spi";
- groups = "spi0", "spi0_wp_hold";
- };
- };
-
- spic_pins: spic-pins {
- mux {
- function = "spi";
- groups = "spi1_0";
- };
- };
-
- uart1_pins: uart1-pins {
- mux {
- function = "uart";
- groups = "uart1_rx_tx";
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2_0_rx_tx";
- };
- };
-
- wf_2g_5g_pins: wf-2g-5g-pins {
- mux {
- function = "wifi";
- groups = "wf_2g", "wf_5g";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-
- wf_dbdc_pins: wf-dbdc-pins {
- mux {
- function = "wifi";
- groups = "wf_dbdc";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-
- wf_led_pins: wf-led-pins {
- mux {
- function = "led";
- groups = "wifi_led";
- };
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm_pins>;
- status = "okay";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_flash_pins>;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic_pins>;
- status = "okay";
-};
-
-&ssusb {
- status = "okay";
-};
-
-&switch {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "wan";
- };
-
- port@1 {
- reg = <1>;
- label = "lan0";
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- };
-
- port5: port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "2500base-x";
- sfp = <&sfp2>;
- managed = "in-band-status";
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
- };
-};
-
-&trng {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
- pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-
- led {
- led-active-low;
- };
-};
-
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/phy/phy.h>
-
-/ {
- compatible = "mediatek,mt7986a";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- clk40m: oscillator-40m {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- clock-output-names = "clkxtal";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x0>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x1>;
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- enable-method = "psci";
- reg = <0x2>;
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- enable-method = "psci";
- compatible = "arm,cortex-a53";
- reg = <0x3>;
- #cooling-cells = <2>;
- };
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x30000>;
- no-map;
- };
-
- wmcpu_emi: wmcpu-reserved@4fc00000 {
- no-map;
- reg = <0 0x4fc00000 0 0x00100000>;
- };
-
- wo_emi0: wo-emi@4fd00000 {
- reg = <0 0x4fd00000 0 0x40000>;
- no-map;
- };
-
- wo_emi1: wo-emi@4fd40000 {
- reg = <0 0x4fd40000 0 0x40000>;
- no-map;
- };
-
- wo_ilm0: wo-ilm@151e0000 {
- reg = <0 0x151e0000 0 0x8000>;
- no-map;
- };
-
- wo_ilm1: wo-ilm@151f0000 {
- reg = <0 0x151f0000 0 0x8000>;
- no-map;
- };
-
- wo_data: wo-data@4fd80000 {
- reg = <0 0x4fd80000 0 0x240000>;
- no-map;
- };
-
- wo_dlm0: wo-dlm@151e8000 {
- reg = <0 0x151e8000 0 0x2000>;
- no-map;
- };
-
- wo_dlm1: wo-dlm@151f8000 {
- reg = <0 0x151f8000 0 0x2000>;
- no-map;
- };
-
- wo_boot: wo-boot@15194000 {
- reg = <0 0x15194000 0 0x1000>;
- no-map;
- };
-
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
-
- gic: interrupt-controller@c000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- interrupt-controller;
- reg = <0 0x0c000000 0 0x10000>, /* GICD */
- <0 0x0c080000 0 0x80000>, /* GICR */
- <0 0x0c400000 0 0x2000>, /* GICC */
- <0 0x0c410000 0 0x1000>, /* GICH */
- <0 0x0c420000 0 0x2000>; /* GICV */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- infracfg: infracfg@10001000 {
- compatible = "mediatek,mt7986-infracfg", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- wed_pcie: wed-pcie@10003000 {
- compatible = "mediatek,mt7986-wed-pcie",
- "syscon";
- reg = <0 0x10003000 0 0x10>;
- };
-
- topckgen: topckgen@1001b000 {
- compatible = "mediatek,mt7986-topckgen", "syscon";
- reg = <0 0x1001B000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- watchdog: watchdog@1001c000 {
- compatible = "mediatek,mt7986-wdt";
- reg = <0 0x1001c000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- #reset-cells = <1>;
- status = "disabled";
- };
-
- apmixedsys: apmixedsys@1001e000 {
- compatible = "mediatek,mt7986-apmixedsys";
- reg = <0 0x1001E000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- pio: pinctrl@1001f000 {
- compatible = "mediatek,mt7986a-pinctrl";
- reg = <0 0x1001f000 0 0x1000>,
- <0 0x11c30000 0 0x1000>,
- <0 0x11c40000 0 0x1000>,
- <0 0x11e20000 0 0x1000>,
- <0 0x11e30000 0 0x1000>,
- <0 0x11f00000 0 0x1000>,
- <0 0x11f10000 0 0x1000>,
- <0 0x1000b000 0 0x1000>;
- reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
- "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pio 0 0 100>;
- interrupt-controller;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- #interrupt-cells = <2>;
- };
-
- sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7986-sgmiisys_0",
- "syscon";
- reg = <0 0x10060000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7986-sgmiisys_1",
- "syscon";
- reg = <0 0x10070000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- trng: rng@1020f000 {
- compatible = "mediatek,mt7986-rng",
- "mediatek,mt7623-rng";
- reg = <0 0x1020f000 0 0x100>;
- clocks = <&infracfg CLK_INFRA_TRNG_CK>;
- clock-names = "rng";
- status = "disabled";
- };
-
- crypto: crypto@10320000 {
- compatible = "inside-secure,safexcel-eip97";
- reg = <0 0x10320000 0 0x40000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ring0", "ring1", "ring2", "ring3";
- clocks = <&infracfg CLK_INFRA_EIP97_CK>;
- clock-names = "infra_eip97_ck";
- assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
- assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
- status = "disabled";
- };
-
- pwm: pwm@10048000 {
- compatible = "mediatek,mt7986-pwm";
- reg = <0 0x10048000 0 0x1000>;
- #clock-cells = <1>;
- #pwm-cells = <2>;
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_PWM_SEL>,
- <&infracfg CLK_INFRA_PWM_STA>,
- <&infracfg CLK_INFRA_PWM1_CK>,
- <&infracfg CLK_INFRA_PWM2_CK>;
- clock-names = "top", "main", "pwm1", "pwm2";
- status = "disabled";
- };
-
- uart0: serial@11002000 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11002000 0 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_UART0_SEL>,
- <&infracfg CLK_INFRA_UART0_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
- <&topckgen CLK_TOP_UART_SEL>;
- status = "disabled";
- };
-
- uart1: serial@11003000 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11003000 0 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_UART1_SEL>,
- <&infracfg CLK_INFRA_UART1_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
- status = "disabled";
- };
-
- uart2: serial@11004000 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11004000 0 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_UART2_SEL>,
- <&infracfg CLK_INFRA_UART2_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
- status = "disabled";
- };
-
- i2c0: i2c@11008000 {
- compatible = "mediatek,mt7986-i2c";
- reg = <0 0x11008000 0 0x90>,
- <0 0x10217080 0 0x80>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clock-div = <5>;
- clocks = <&infracfg CLK_INFRA_I2C0_CK>,
- <&infracfg CLK_INFRA_AP_DMA_CK>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi0: spi@1100a000 {
- compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0x1100a000 0 0x100>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_MPLL_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&infracfg CLK_INFRA_SPI0_CK>,
- <&infracfg CLK_INFRA_SPI0_HCK_CK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
- status = "disabled";
- };
-
- spi1: spi@1100b000 {
- compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0x1100b000 0 0x100>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_MPLL_D2>,
- <&topckgen CLK_TOP_SPIM_MST_SEL>,
- <&infracfg CLK_INFRA_SPI1_CK>,
- <&infracfg CLK_INFRA_SPI1_HCK_CK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
- status = "disabled";
- };
-
- auxadc: adc@1100d000 {
- compatible = "mediatek,mt7986-auxadc";
- reg = <0 0x1100d000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
- clock-names = "main";
- #io-channel-cells = <1>;
- status = "disabled";
- };
-
- ssusb: usb@11200000 {
- compatible = "mediatek,mt7986-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x11200000 0 0x2e00>,
- <0 0x11203e00 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
- <&infracfg CLK_INFRA_IUSB_CK>,
- <&infracfg CLK_INFRA_IUSB_133_CK>,
- <&infracfg CLK_INFRA_IUSB_66M_CK>,
- <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
- clock-names = "sys_ck",
- "ref_ck",
- "mcu_ck",
- "dma_ck",
- "xhci_ck";
- phys = <&u2port0 PHY_TYPE_USB2>,
- <&u3port0 PHY_TYPE_USB3>,
- <&u2port1 PHY_TYPE_USB2>;
- status = "disabled";
- };
-
- mmc0: mmc@11230000 {
- compatible = "mediatek,mt7986-mmc";
- reg = <0 0x11230000 0 0x1000>,
- <0 0x11c20000 0 0x1000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
- <&infracfg CLK_INFRA_MSDC_HCK_CK>,
- <&infracfg CLK_INFRA_MSDC_CK>,
- <&infracfg CLK_INFRA_MSDC_133M_CK>,
- <&infracfg CLK_INFRA_MSDC_66M_CK>;
- clock-names = "source", "hclk", "source_cg", "bus_clk",
- "sys_cg";
- status = "disabled";
- };
-
- thermal: thermal@1100c800 {
- #thermal-sensor-cells = <1>;
- compatible = "mediatek,mt7986-thermal";
- reg = <0 0x1100c800 0 0x800>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_THERM_CK>,
- <&infracfg CLK_INFRA_ADC_26M_CK>,
- <&infracfg CLK_INFRA_ADC_FRC_CK>;
- clock-names = "therm", "auxadc", "adc_32k";
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- nvmem-cells = <&thermal_calibration>;
- nvmem-cell-names = "calibration-data";
- };
-
- pcie: pcie@11280000 {
- compatible = "mediatek,mt7986-pcie",
- "mediatek,mt8192-pcie";
- device_type = "pci";
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0x00 0x11280000 0x00 0x4000>;
- reg-names = "pcie-mac";
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x00 0xff>;
- ranges = <0x82000000 0x00 0x20000000 0x00
- 0x20000000 0x00 0x10000000>;
- clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
- <&infracfg CLK_INFRA_IPCIE_CK>,
- <&infracfg CLK_INFRA_IPCIER_CK>,
- <&infracfg CLK_INFRA_IPCIEB_CK>;
- clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
- status = "disabled";
-
- phys = <&pcie_port PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- pcie_intc: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- pcie_phy: t-phy@11c00000 {
- compatible = "mediatek,mt7986-tphy",
- "mediatek,generic-tphy-v2";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- pcie_port: pcie-phy@11c00000 {
- reg = <0 0x11c00000 0 0x20000>;
- clocks = <&clk40m>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
- };
-
- efuse: efuse@11d00000 {
- compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
- reg = <0 0x11d00000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- thermal_calibration: calib@274 {
- reg = <0x274 0xc>;
- };
- };
-
- usb_phy: t-phy@11e10000 {
- compatible = "mediatek,mt7986-tphy",
- "mediatek,generic-tphy-v2";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x11e10000 0x1700>;
- status = "disabled";
-
- u2port0: usb-phy@0 {
- reg = <0x0 0x700>;
- clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
- <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
- clock-names = "ref", "da_ref";
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@700 {
- reg = <0x700 0x900>;
- clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- u2port1: usb-phy@1000 {
- reg = <0x1000 0x700>;
- clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
- <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
- clock-names = "ref", "da_ref";
- #phy-cells = <1>;
- };
- };
-
- ethsys: syscon@15000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mediatek,mt7986-ethsys",
- "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- wed0: wed@15010000 {
- compatible = "mediatek,mt7986-wed",
- "syscon";
- reg = <0 0x15010000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
- <&wo_data>, <&wo_boot>;
- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
- "wo-data", "wo-boot";
- mediatek,wo-ccif = <&wo_ccif0>;
- };
-
- wed1: wed@15011000 {
- compatible = "mediatek,mt7986-wed",
- "syscon";
- reg = <0 0x15011000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
- <&wo_data>, <&wo_boot>;
- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
- "wo-data", "wo-boot";
- mediatek,wo-ccif = <&wo_ccif1>;
- };
-
- wo_ccif0: syscon@151a5000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151a5000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wo_ccif1: syscon@151ad000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151ad000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- eth: ethernet@15100000 {
- compatible = "mediatek,mt7986-eth";
- reg = <0 0x15100000 0 0x80000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <ðsys CLK_ETH_FE_EN>,
- <ðsys CLK_ETH_GP2_EN>,
- <ðsys CLK_ETH_GP1_EN>,
- <ðsys CLK_ETH_WOCPU1_EN>,
- <ðsys CLK_ETH_WOCPU0_EN>,
- <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
- <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
- <&sgmiisys0 CLK_SGMII0_CDR_REF>,
- <&sgmiisys0 CLK_SGMII0_CDR_FB>,
- <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
- <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
- <&sgmiisys1 CLK_SGMII1_CDR_REF>,
- <&sgmiisys1 CLK_SGMII1_CDR_FB>,
- <&topckgen CLK_TOP_NETSYS_SEL>,
- <&topckgen CLK_TOP_NETSYS_500M_SEL>;
- clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
- "sgmii_tx250m", "sgmii_rx250m",
- "sgmii_cdr_ref", "sgmii_cdr_fb",
- "sgmii2_tx250m", "sgmii2_rx250m",
- "sgmii2_cdr_ref", "sgmii2_cdr_fb",
- "netsys0", "netsys1";
- assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
- <&topckgen CLK_TOP_SGM_325M_SEL>;
- assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
- <&apmixedsys CLK_APMIXED_SGMPLL>;
- mediatek,ethsys = <ðsys>;
- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
- mediatek,wed-pcie = <&wed_pcie>;
- mediatek,wed = <&wed0>, <&wed1>;
- #reset-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- wifi: wifi@18000000 {
- compatible = "mediatek,mt7986-wmac";
- resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
- reset-names = "consys";
- clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
- <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
- clock-names = "mcu", "ap2conn";
- reg = <0 0x18000000 0 0x1000000>,
- <0 0x10003000 0 0x1000>,
- <0 0x11d10000 0 0x1000>;
- interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wmcpu_emi>;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
- thermal-sensors = <&thermal 0>;
-
- trips {
- cpu_trip_active_high: active-high {
- temperature = <115000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_low: active-low {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_passive: passive {
- temperature = <40000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986b.dtsi"
-
-/ {
- model = "MediaTek MT7986b RFB";
- compatible = "mediatek,mt7986b-rfb";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&ssusb {
- vusb33-supply = <®_3p3v>;
- vbus-supply = <®_5v>;
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
- pinctrl-0 = <&wf_2g_5g_pins>;
- pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-ð {
- status = "okay";
-
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
-
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy5: phy@5 {
- compatible = "ethernet-phy-id67c9.de0a";
- reg = <5>;
- reset-gpios = <&pio 6 1>;
- reset-deassert-us = <20000>;
- phy-mode = "2500base-x";
- };
-
- phy6: phy@6 {
- compatible = "ethernet-phy-id67c9.de0a";
- reg = <6>;
- phy-mode = "2500base-x";
- };
-
- switch@0 {
- compatible = "mediatek,mt7531";
- reg = <31>;
- reset-gpios = <&pio 5 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan0";
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- };
-
- port@6 {
- reg = <6>;
- ethernet = <&gmac0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
- };
- };
- };
-};
-
-&crypto {
- status = "okay";
-};
-
-&pio {
- wf_2g_5g_pins: wf_2g_5g-pins {
- mux {
- function = "wifi";
- groups = "wf_2g", "wf_5g";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-
- wf_dbdc_pins: wf_dbdc-pins {
- mux {
- function = "wifi";
- groups = "wf_dbdc";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include "mt7986a.dtsi"
-/ {
- compatible = "mediatek,mt7986b";
-};
-
-&pio {
- compatible = "mediatek,mt7986b-pinctrl";
- gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-#define MT7981_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7981_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
- _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
- _div_table, _parent_name) \
- { \
- .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
- .en_mask = _en_mask, .flags = _flags, \
- .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
- .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
- .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
- .pcw_shift = _pcw_shift, .div_table = _div_table, \
- .parent_name = _parent_name, \
- }
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
- _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
- PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
- _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
- "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
- 32, 0x0200, 4, 0, 0x0204, 0),
- PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
- 0x0210, 4, 0, 0x0214, 0),
- PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
- 0x0220, 4, 0, 0x0224, 0),
- PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
- 0x0230, 4, 0, 0x0234, 0),
- PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
- 0x0240, 4, 0, 0x0244, 0),
- PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
- 0x0250, 4, 0, 0x0254, 0),
- PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
- 0x0260, 4, 0, 0x0264, 0),
- PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
- 0x0278, 4, 0, 0x027C, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
- { .compatible = "mediatek,mt7981-apmixedsys", },
- {}
-};
-
-static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
- clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_apmixed_data;
- }
- return r;
-
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static struct platform_driver clk_mt7981_apmixed_drv = {
- .probe = clk_mt7981_apmixed_probe,
- .driver = {
- .name = "clk-mt7981-apmixed",
- .of_match_table = of_match_clk_mt7981_apmixed,
- },
-};
-builtin_platform_driver(clk_mt7981_apmixed_drv);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
- .set_ofs = 0xE4,
- .clr_ofs = 0xE4,
- .sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &sgmii0_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_no_setclr_inv, \
- }
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
- GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
- GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
- GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
- GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
- .set_ofs = 0xE4,
- .clr_ofs = 0xE4,
- .sta_ofs = 0xE4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &sgmii1_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_no_setclr_inv, \
- }
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
- GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
- GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
- GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
- GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
- .set_ofs = 0x30,
- .clr_ofs = 0x30,
- .sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = ð_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_no_setclr_inv, \
- }
-
-static const struct mtk_gate eth_clks[] __initconst = {
- GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
- GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
- GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
- GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
- struct clk_onecell_data *clk_data;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0",
- mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
- struct clk_onecell_data *clk_data;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1",
- mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
- struct clk_onecell_data *clk_data;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
- FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
- "uart_sel" };
-
-static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
- "spi_sel" };
-
-static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
- "spim_mst_sel" };
-
-static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
- "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
- "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
- /* MODULE_CLK_SEL_0 */
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
- infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
- infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
- infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
- infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
- infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
- infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
- infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
- infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
- infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
- infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
- 2, -1, -1, -1),
- /* MODULE_CLK_SEL_1 */
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
- infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
- -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
- .set_ofs = 0x40,
- .clr_ofs = 0x44,
- .sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
- .set_ofs = 0x50,
- .clr_ofs = 0x54,
- .sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
- .set_ofs = 0x60,
- .clr_ofs = 0x64,
- .sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &infra0_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
- }
-
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &infra1_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
- }
-
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &infra2_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
- }
-
-static const struct mtk_gate infra_clks[] = {
- /* INFRA0 */
- GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
- GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
- GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
- GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
- GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
- GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-
- GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
- GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
- GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
- GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
- GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
- GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
- 14),
- GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
- GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
- GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
- GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
- GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
- /* INFRA1 */
- GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
- GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
- GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
- GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
- GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
- GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
- GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
- GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
- GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
- GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
- GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
- GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
- GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
- 13),
- GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
- 14),
- GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
- GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
- GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
- GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
- GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
- GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
- GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
- GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
- GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
- GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
- /* INFRA2 */
- GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
- GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
- GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
- GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
- GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
- GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
- 13),
- GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
- GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-};
-
-static int clk_mt7981_infracfg_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
- ARRAY_SIZE(infra_clks);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
- &mt7981_clk_lock, clk_data);
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_infracfg_data;
- }
- return r;
-
-free_infracfg_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
- { .compatible = "mediatek,mt7981-infracfg", },
- {}
-};
-
-static struct platform_driver clk_mt7981_infracfg_drv = {
- .probe = clk_mt7981_infracfg_probe,
- .driver = {
- .name = "clk-mt7981-infracfg",
- .of_match_table = of_match_clk_mt7981_infracfg,
- },
-};
-builtin_platform_driver(clk_mt7981_infracfg_drv);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7981_clk_lock);
-
-static const struct mtk_fixed_factor top_divs[] = {
- FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
- FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
- FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
- FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
- FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
- FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
- FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
- FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
- FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
- FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
- FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
- FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
- FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
- FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
- FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
- FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
- FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
- FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
- FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
- FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
- FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
- FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
- FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
- FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
- FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
- FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
- FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
- FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
- FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
- FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
- FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
- FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
- FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
- FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
- FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
- FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
- FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
- FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
- FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
- FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
- FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
- FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
- FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
- FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
- FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
- FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
- FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
- FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
- FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
- FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
- FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
- FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
- FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
- FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
- FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
- FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
- FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
- FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
- FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
- FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
- FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
- FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
- FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
- FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
- FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
- FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
- FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
- FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
- FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
- FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
- FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
- FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
- FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
- FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
- FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
- FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-};
-
-static const char * const nfi1x_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_mm_d4",
- "net1_d8_d2",
- "cb_net2_d6",
- "cb_m_d4",
- "cb_mm_d8",
- "net1_d8_d4",
- "cb_m_d8"
-};
-
-static const char * const spinfi_parents[] __initconst = {
- "cksq_40m_d2",
- "cb_cksq_40m",
- "net1_d5_d4",
- "cb_m_d4",
- "cb_mm_d8",
- "net1_d8_d4",
- "mm_d6_d2",
- "cb_m_d8"
-};
-
-static const char * const spi_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_m_d2",
- "cb_mm_d4",
- "net1_d8_d2",
- "cb_net2_d6",
- "net1_d5_d4",
- "cb_m_d4",
- "net1_d8_d4"
-};
-
-static const char * const uart_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_m_d8",
- "m_d8_d2"
-};
-
-static const char * const pwm_parents[] __initconst = {
- "cb_cksq_40m",
- "net1_d8_d2",
- "net1_d5_d4",
- "cb_m_d4",
- "m_d8_d2",
- "cb_rtc_32k"
-};
-
-static const char * const i2c_parents[] __initconst = {
- "cb_cksq_40m",
- "net1_d5_d4",
- "cb_m_d4",
- "net1_d8_d4"
-};
-
-static const char * const pextp_tl_ck_parents[] __initconst = {
- "cb_cksq_40m",
- "net1_d5_d4",
- "cb_m_d4",
- "cb_rtc_32k"
-};
-
-static const char * const emmc_208m_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_m_d2",
- "cb_net2_d4",
- "cb_apll2_196m",
- "cb_mm_d4",
- "net1_d8_d2",
- "cb_mm_d6"
-};
-
-static const char * const emmc_400m_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_net2_d2",
- "cb_mm_d2",
- "cb_net2_d2"
-};
-
-static const char * const csw_f26m_parents[] __initconst = {
- "cksq_40m_d2",
- "m_d8_d2"
-};
-
-static const char * const dramc_md32_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_m_d2",
- "cb_wedmcu_208m"
-};
-
-static const char * const sysaxi_parents[] __initconst = {
- "cb_cksq_40m",
- "net1_d8_d2"
-};
-
-static const char * const sysapb_parents[] __initconst = {
- "cb_cksq_40m",
- "m_d3_d2"
-};
-
-static const char * const arm_db_main_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_net2_d6"
-};
-
-static const char * const ap2cnn_host_parents[] __initconst = {
- "cb_cksq_40m",
- "net1_d8_d4"
-};
-
-static const char * const netsys_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_mm_d2"
-};
-
-static const char * const netsys_500m_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_net1_d5"
-};
-
-static const char * const netsys_mcu_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_mm_720m",
- "cb_net1_d4",
- "cb_net1_d5",
- "cb_m_416m"
-};
-
-static const char * const netsys_2x_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_net2_800m",
- "cb_mm_720m"
-};
-
-static const char * const sgm_325m_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_sgm_325m"
-};
-
-static const char * const sgm_reg_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_net2_d4"
-};
-
-static const char * const eip97b_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_net1_d5",
- "cb_m_416m",
- "cb_mm_d2",
- "net1_d5_d2"
-};
-
-static const char * const aud_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_apll2_196m"
-};
-
-static const char * const a1sys_parents[] __initconst = {
- "cb_cksq_40m",
- "apll2_d4"
-};
-
-static const char * const aud_l_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_apll2_196m",
- "m_d8_d2"
-};
-
-static const char * const a_tuner_parents[] __initconst = {
- "cb_cksq_40m",
- "apll2_d4",
- "m_d8_d2"
-};
-
-static const char * const u2u3_parents[] __initconst = {
- "cb_cksq_40m",
- "m_d8_d2"
-};
-
-static const char * const u2u3_sys_parents[] __initconst = {
- "cb_cksq_40m",
- "net1_d5_d4"
-};
-
-static const char * const usb_frmcnt_parents[] __initconst = {
- "cb_cksq_40m",
- "cb_mm_d3_d5"
-};
-
-static const struct mtk_mux top_muxes[] = {
- /* CLK_CFG_0 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
- 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
- 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
- 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
- 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
- /* CLK_CFG_1 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
- 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
- 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
- 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
- pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
- 0x1C0, 7),
- /* CLK_CFG_2 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
- emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
- 0x1C0, 8),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
- emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
- 0x1C0, 9),
- MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
- csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
- 0x1C0, 10,
- CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
- csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
- 31, 0x1C0, 11,
- CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- /* CLK_CFG_3 */
- MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
- 7, 0x1C0, 12,
- CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
- sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
- 0x1C0, 13,
- CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
- sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
- 23, 0x1C0, 14,
- CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
- arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
- 0x1C0, 15),
- /* CLK_CFG_4 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
- ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
- 0x1C0, 16),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
- 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
- netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
- 0x1C0, 18),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
- netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
- 0x1C0, 19),
- /* CLK_CFG_5 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
- netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
- 0x1C0, 20),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
- sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
- 0x1C0, 21),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
- 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
- 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
- /* CLK_CFG_6 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
- csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
- 7, 0x1C0, 24),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
- 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
- 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
- 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
- /* CLK_CFG_7 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
- a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
- 0x1C0, 28),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
- 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
- u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
- 0x1C0, 30),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
- u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
- 0x1C4, 0),
- /* CLK_CFG_8 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
- usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
- 0x1C4, 1),
-};
-
-static struct mtk_composite top_aud_divs[] = {
- DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
- 0x0420, 0, 0x0420, 8, 8),
-};
-
-static int clk_mt7981_topckgen_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes) +
- ARRAY_SIZE(top_aud_divs);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
- &mt7981_clk_lock, clk_data);
- mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base,
- &mt7981_clk_lock, clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_topckgen_data;
- }
- return r;
-
-free_topckgen_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
- { .compatible = "mediatek,mt7981-topckgen", },
- {}
-};
-
-static struct platform_driver clk_mt7981_topckgen_drv = {
- .probe = clk_mt7981_topckgen_probe,
- .driver = {
- .name = "clk-mt7981-topckgen",
- .of_match_table = of_match_clk_mt7981_topckgen,
- },
-};
-builtin_platform_driver(clk_mt7981_topckgen_drv);
+++ /dev/null
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-#define MT7986_PLL_FMAX (2500UL * MHZ)
-#define CON0_MT7986_RST_BAR BIT(27)
-
-#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
- _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
- _div_table, _parent_name) \
- { \
- .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
- .en_mask = _en_mask, .flags = _flags, \
- .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
- .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
- .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
- .pcw_shift = _pcw_shift, .div_table = _div_table, \
- .parent_name = _parent_name, \
- }
-
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
- _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
- PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
- _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
- "clkxtal")
-
-static const struct mtk_pll_data plls[] = {
- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
- 0x0200, 4, 0, 0x0204, 0),
- PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
- 0x0210, 4, 0, 0x0214, 0),
- PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
- 0x0220, 4, 0, 0x0224, 0),
- PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
- 0x0230, 4, 0, 0x0234, 0),
- PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
- 32, 0x0240, 4, 0, 0x0244, 0),
- PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
- 0x0250, 4, 0, 0x0254, 0),
- PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
- 4, 0, 0x0264, 0),
- PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
- 0x0278, 4, 0, 0x027c, 0),
-};
-
-static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
- { .compatible = "mediatek,mt7986-apmixedsys", },
- {}
-};
-
-static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
- clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_apmixed_data;
- }
- return r;
-
-free_apmixed_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static struct platform_driver clk_mt7986_apmixed_drv = {
- .probe = clk_mt7986_apmixed_probe,
- .driver = {
- .name = "clk-mt7986-apmixed",
- .of_match_table = of_match_clk_mt7986_apmixed,
- },
-};
-builtin_platform_driver(clk_mt7986_apmixed_drv);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-
-#include "clk-mtk.h"
-#include "clk-gate.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-
-static const struct mtk_gate_regs sgmii0_cg_regs = {
- .set_ofs = 0xe4,
- .clr_ofs = 0xe4,
- .sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII0(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &sgmii0_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_no_setclr_inv, \
- }
-
-static const struct mtk_gate sgmii0_clks[] __initconst = {
- GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
- GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
- GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
- GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs sgmii1_cg_regs = {
- .set_ofs = 0xe4,
- .clr_ofs = 0xe4,
- .sta_ofs = 0xe4,
-};
-
-#define GATE_SGMII1(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &sgmii1_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_no_setclr_inv, \
- }
-
-static const struct mtk_gate sgmii1_clks[] __initconst = {
- GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
- GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
- GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
- GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
-};
-
-static const struct mtk_gate_regs eth_cg_regs = {
- .set_ofs = 0x30,
- .clr_ofs = 0x30,
- .sta_ofs = 0x30,
-};
-
-#define GATE_ETH(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = ð_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_no_setclr_inv, \
- }
-
-static const struct mtk_gate eth_clks[] __initconst = {
- GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
- GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
- GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
- GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
- GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
-};
-
-static void __init mtk_sgmiisys_0_init(struct device_node *node)
-{
- struct clk_onecell_data *clk_data;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
- mtk_sgmiisys_0_init);
-
-static void __init mtk_sgmiisys_1_init(struct device_node *node)
-{
- struct clk_onecell_data *clk_data;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
- mtk_sgmiisys_1_init);
-
-static void __init mtk_ethsys_init(struct device_node *node)
-{
- struct clk_onecell_data *clk_data;
- int r;
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r)
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
-}
-CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
+++ /dev/null
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_factor infra_divs[] = {
- FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
-};
-
-static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
- "uart_sel" };
-
-static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
- "spi_sel" };
-
-static const char *const infra_pwm_bsel_parents[] __initconst = {
- "top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
-};
-
-static const char *const infra_pcie_parents[] __initconst = {
- "top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
-};
-
-static const struct mtk_mux infra_muxes[] = {
- /* MODULE_CLK_SEL_0 */
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
- infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
- infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
- infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
- infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
- infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
- -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
- infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
- 2, -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
- infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
- 2, -1, -1, -1),
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
- infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
- 2, -1, -1, -1),
- /* MODULE_CLK_SEL_1 */
- MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
- infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
- -1, -1, -1),
-};
-
-static const struct mtk_gate_regs infra0_cg_regs = {
- .set_ofs = 0x40,
- .clr_ofs = 0x44,
- .sta_ofs = 0x48,
-};
-
-static const struct mtk_gate_regs infra1_cg_regs = {
- .set_ofs = 0x50,
- .clr_ofs = 0x54,
- .sta_ofs = 0x58,
-};
-
-static const struct mtk_gate_regs infra2_cg_regs = {
- .set_ofs = 0x60,
- .clr_ofs = 0x64,
- .sta_ofs = 0x68,
-};
-
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &infra0_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
- }
-
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &infra1_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
- }
-
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
- { \
- .id = _id, .name = _name, .parent_name = _parent, \
- .regs = &infra2_cg_regs, .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
- }
-
-static const struct mtk_gate infra_clks[] = {
- /* INFRA0 */
- GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
- GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
- GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
- GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
- GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
- GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
- GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
- GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
- GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
- GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
- GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
- GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
- GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
- 14),
- GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
- GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
- GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
- GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
- GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
- /* INFRA1 */
- GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
- GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
- GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
- GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
- GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
- GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
- GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
- GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
- 10),
- GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
- GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
- GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
- 13),
- GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
- 14),
- GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
- GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
- GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
- 17),
- GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
- 18),
- GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
- 19),
- GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
- GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
- GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
- /* INFRA2 */
- GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
- GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
- 1),
- GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
- GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
- GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
- GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
- 13),
- GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
- GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
-};
-
-static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
- ARRAY_SIZE(infra_clks);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
- &mt7986_clk_lock, clk_data);
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_infracfg_data;
- }
- return r;
-
-free_infracfg_data:
- mtk_free_clk_data(clk_data);
- return r;
-
-}
-
-static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
- { .compatible = "mediatek,mt7986-infracfg", },
- {}
-};
-
-static struct platform_driver clk_mt7986_infracfg_drv = {
- .probe = clk_mt7986_infracfg_probe,
- .driver = {
- .name = "clk-mt7986-infracfg",
- .of_match_table = of_match_clk_mt7986_infracfg,
- },
-};
-builtin_platform_driver(clk_mt7986_infracfg_drv);
+++ /dev/null
-// SPDX-License-Identifier: GPL-1.0
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include "clk-mtk.h"
-#include "clk-gate.h"
-#include "clk-mux.h"
-
-#include <dt-bindings/clock/mt7986-clk.h>
-#include <linux/clk.h>
-
-static DEFINE_SPINLOCK(mt7986_clk_lock);
-
-static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
- FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
-};
-
-static const struct mtk_fixed_factor top_divs[] = {
- /* XTAL */
- FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
- FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
- FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
- /* MPLL */
- FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
- FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
- FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
- FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
- FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
- /* MMPLL */
- FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
- FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
- FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
- FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
- FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
- FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
- /* APLL2 */
- FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
- /* NET1PLL */
- FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
- FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
- FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
- FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
- FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
- FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
- /* NET2PLL */
- FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
- FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
- FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
- /* WEDMCUPLL */
- FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
- 10),
-};
-
-static const char *const nfi1x_parents[] __initconst = { "top_xtal",
- "top_mmpll_d8",
- "top_net1pll_d8_d2",
- "top_net2pll_d3_d2",
- "top_mpll_d4",
- "top_mmpll_d8_d2",
- "top_wedmcupll_d5_d2",
- "top_mpll_d8" };
-
-static const char *const spinfi_parents[] __initconst = {
- "top_xtal_d2", "top_xtal", "top_net1pll_d5_d4",
- "top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
- "top_mmpll_d3_d8", "top_mpll_d8"
-};
-
-static const char *const spi_parents[] __initconst = {
- "top_xtal", "top_mpll_d2", "top_mmpll_d8",
- "top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4",
- "top_mpll_d4", "top_wedmcupll_d5_d2"
-};
-
-static const char *const uart_parents[] __initconst = { "top_xtal",
- "top_mpll_d8",
- "top_mpll_d8_d2" };
-
-static const char *const pwm_parents[] __initconst = {
- "top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
-};
-
-static const char *const i2c_parents[] __initconst = {
- "top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
-};
-
-static const char *const pextp_tl_ck_parents[] __initconst = {
- "top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
-};
-
-static const char *const emmc_250m_parents[] __initconst = {
- "top_xtal", "top_net1pll_d5_d2"
-};
-
-static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
- "mpll" };
-
-static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
- "top_mpll_d8_d2" };
-
-static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
- "top_mpll_d2" };
-
-static const char *const sysaxi_parents[] __initconst = { "top_xtal",
- "top_net1pll_d8_d2",
- "top_net2pll_d4" };
-
-static const char *const sysapb_parents[] __initconst = { "top_xtal",
- "top_mpll_d3_d2",
- "top_net2pll_d4_d2" };
-
-static const char *const arm_db_main_parents[] __initconst = {
- "top_xtal", "top_net2pll_d3_d2"
-};
-
-static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
- "top_xtal" };
-
-static const char *const netsys_parents[] __initconst = { "top_xtal",
- "top_mmpll_d4" };
-
-static const char *const netsys_500m_parents[] __initconst = {
- "top_xtal", "top_net1pll_d5"
-};
-
-static const char *const netsys_mcu_parents[] __initconst = {
- "top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
- "top_net1pll_d5"
-};
-
-static const char *const netsys_2x_parents[] __initconst = {
- "top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
-};
-
-static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
- "sgmpll" };
-
-static const char *const sgm_reg_parents[] __initconst = {
- "top_xtal", "top_net1pll_d8_d4"
-};
-
-static const char *const a1sys_parents[] __initconst = { "top_xtal",
- "top_apll2_d4" };
-
-static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
- "top_mmpll_d2" };
-
-static const char *const eip_b_parents[] __initconst = { "top_xtal",
- "net2pll" };
-
-static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
- "top_mpll_d8_d2" };
-
-static const char *const a_tuner_parents[] __initconst = { "top_xtal",
- "top_apll2_d4",
- "top_mpll_d8_d2" };
-
-static const char *const u2u3_sys_parents[] __initconst = {
- "top_xtal", "top_net1pll_d5_d4"
-};
-
-static const char *const da_u2_refsel_parents[] __initconst = {
- "top_xtal", "top_mmpll_u2phy"
-};
-
-static const struct mtk_mux top_muxes[] = {
- /* CLK_CFG_0 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
- 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
- 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
- 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
- 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
- /* CLK_CFG_1 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
- 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
- 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
- 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
- pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
- 31, 0x1C0, 7),
- /* CLK_CFG_2 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
- emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
- 0x1C0, 8),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
- emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
- 0x1C0, 9),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
- f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
- 0x1C0, 10),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
- /* CLK_CFG_3 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
- 0x1C0, 12),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
- arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
- 31, 0x1C0, 15),
- /* CLK_CFG_4 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
- arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
- 0x1C0, 16),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
- 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
- netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
- 23, 0x1C0, 18),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
- netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
- 0x1C0, 19),
- /* CLK_CFG_5 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
- netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
- 0x1C0, 20),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
- sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
- 0x1C0, 21),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
- 0x1C0, 22),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
- 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
- /* CLK_CFG_6 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
- conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
- 0x1C0, 24),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
- 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
- f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
- 0x1C0, 26),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
- f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
- 0x1C0, 27),
- /* CLK_CFG_7 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
- 0x1C0, 28),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
- 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
- a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
- 0x1C0, 30),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
- 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
- /* CLK_CFG_8 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
- u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
- 0x1C4, 1),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
- u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
- 0x1C4, 2),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
- da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
- 23, 0x1C4, 3),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
- da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
- 31, 0x1C4, 4),
- /* CLK_CFG_9 */
- MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
- sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
- 0x1C4, 5),
-};
-
-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
- ARRAY_SIZE(top_muxes);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- clk_data);
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
- &mt7986_clk_lock, clk_data);
-
- clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
- clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
- clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
- clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
- clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
- clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_topckgen_data;
- }
- return r;
-
-free_topckgen_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
- { .compatible = "mediatek,mt7986-topckgen", },
- {}
-};
-
-static struct platform_driver clk_mt7986_topckgen_drv = {
- .probe = clk_mt7986_topckgen_probe,
- .driver = {
- .name = "clk-mt7986-topckgen",
- .of_match_table = of_match_clk_mt7986_topckgen,
- },
-};
-builtin_platform_driver(clk_mt7986_topckgen_drv);
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-mux.h"
+#include "clk-pll.h"
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#define MT7988_PLL_FMAX (2500UL * MHZ)
};
static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
- {
- .compatible = "mediatek,mt7988-apmixedsys",
- },
- {}
+ { .compatible = "mediatek,mt7988-apmixedsys", },
+ { /* sentinel */ }
};
static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
{
- struct clk_onecell_data *clk_data;
+ struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
},
};
builtin_platform_driver(clk_mt7988_apmixed_drv);
+MODULE_LICENSE("GPL");
29),
};
-static int clk_mt7988_ethsys_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks));
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_data;
- }
- return r;
-
-free_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc ethdma_desc = {
+ .clks = ethdma_clks,
+ .num_clks = ARRAY_SIZE(ethdma_clks),
+};
static const struct mtk_gate_regs sgmii0_cg_regs = {
.set_ofs = 0xe4,
GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
};
-static int clk_mt7988_sgmii0_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_data;
- }
- return r;
-
-free_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc sgmii0_desc = {
+ .clks = sgmii0_clks,
+ .num_clks = ARRAY_SIZE(sgmii0_clks),
+};
static const struct mtk_gate_regs sgmii1_cg_regs = {
.set_ofs = 0xe4,
GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
};
-static int clk_mt7988_sgmii1_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_data;
- }
- return r;
-
-free_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc sgmii1_desc = {
+ .clks = sgmii1_clks,
+ .num_clks = ARRAY_SIZE(sgmii1_clks),
+};
static const struct mtk_gate_regs ethwarp_cg_regs = {
.set_ofs = 0x14,
"netsys_mcu_sel", 15),
};
-static int clk_mt7988_ethwarp_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks));
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_data;
- }
- return r;
-
-free_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
-
-static const struct of_device_id of_match_clk_mt7988_ethsys[] = {
- {
- .compatible = "mediatek,mt7988-ethsys",
- },
- {}
+static const struct mtk_clk_desc ethwarp_desc = {
+ .clks = ethwarp_clks,
+ .num_clks = ARRAY_SIZE(ethwarp_clks),
};
-static struct platform_driver clk_mt7988_ethsys_drv = {
- .probe = clk_mt7988_ethsys_probe,
- .driver = {
- .name = "clk-mt7988-ethsys",
- .of_match_table = of_match_clk_mt7988_ethsys,
- },
-};
-builtin_platform_driver(clk_mt7988_ethsys_drv);
-
-static const struct of_device_id of_match_clk_mt7988_sgmii0[] = {
- {
- .compatible = "mediatek,mt7988-sgmiisys_0",
- },
- {}
+static const struct of_device_id of_match_clk_mt7986_eth[] = {
+ { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc },
+ { .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
+ { .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
+ { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc },
+ { /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
-static struct platform_driver clk_mt7988_sgmii0_drv = {
- .probe = clk_mt7988_sgmii0_probe,
+static struct platform_driver clk_mt7988_eth_drv = {
.driver = {
- .name = "clk-mt7988-sgmiisys_0",
- .of_match_table = of_match_clk_mt7988_sgmii0,
+ .name = "clk-mt7988-eth",
+ .of_match_table = of_match_clk_mt7986_eth,
},
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
-builtin_platform_driver(clk_mt7988_sgmii0_drv);
+module_platform_driver(clk_mt7988_eth_drv);
-static const struct of_device_id of_match_clk_mt7988_sgmii1[] = {
- {
- .compatible = "mediatek,mt7988-sgmiisys_1",
- },
- {}
-};
-
-static struct platform_driver clk_mt7988_sgmii1_drv = {
- .probe = clk_mt7988_sgmii1_probe,
- .driver = {
- .name = "clk-mt7988-sgmiisys_1",
- .of_match_table = of_match_clk_mt7988_sgmii1,
- },
-};
-builtin_platform_driver(clk_mt7988_sgmii1_drv);
-
-static const struct of_device_id of_match_clk_mt7988_ethwarp[] = {
- {
- .compatible = "mediatek,mt7988-ethwarp",
- },
- {}
-};
-
-static struct platform_driver clk_mt7988_ethwarp_drv = {
- .probe = clk_mt7988_ethwarp_probe,
- .driver = {
- .name = "clk-mt7988-ethwarp",
- .of_match_table = of_match_clk_mt7988_ethwarp,
- },
-};
-builtin_platform_driver(clk_mt7988_ethwarp_drv);
\ No newline at end of file
+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
+MODULE_LICENSE("GPL");
"sysaxi_sel", 31),
};
-static int clk_mt7988_infracfg_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
-
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
- &mt7988_clk_lock, clk_data);
-
- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
- clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_infracfg_data;
- }
- return r;
-
-free_infracfg_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc infra_desc = {
+ .clks = infra_clks,
+ .num_clks = ARRAY_SIZE(infra_clks),
+ .mux_clks = infra_muxes,
+ .num_mux_clks = ARRAY_SIZE(infra_muxes),
+ .clk_lock = &mt7988_clk_lock,
+};
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
- {
- .compatible = "mediatek,mt7988-infracfg",
- },
- {}
+ { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
+ { /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
static struct platform_driver clk_mt7988_infracfg_drv = {
- .probe = clk_mt7988_infracfg_probe,
.driver = {
.name = "clk-mt7988-infracfg",
.of_match_table = of_match_clk_mt7988_infracfg,
},
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
};
-builtin_platform_driver(clk_mt7988_infracfg_drv);
+module_platform_driver(clk_mt7988_infracfg_drv);
8, 8),
};
-static int clk_mt7988_topckgen_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
- ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- clk_data);
-
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-
- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
- &mt7988_clk_lock, clk_data);
-
- mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
- base, &mt7988_clk_lock, clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_topckgen_data;
- }
- return r;
-
-free_topckgen_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc topck_desc = {
+ .fixed_clks = top_fixed_clks,
+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+ .factor_clks = top_divs,
+ .num_factor_clks = ARRAY_SIZE(top_divs),
+ .mux_clks = top_muxes,
+ .num_mux_clks = ARRAY_SIZE(top_muxes),
+ .composite_clks = top_aud_divs,
+ .num_composite_clks = ARRAY_SIZE(top_aud_divs),
+ .clk_lock = &mt7988_clk_lock,
+};
static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
"net1pll_d4" };
mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
};
-static int clk_mt7988_mcusys_probe(struct platform_device *pdev)
-{
- struct clk_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
- int r;
- void __iomem *base;
- int nr = ARRAY_SIZE(mcu_muxes);
-
- base = of_iomap(node, 0);
- if (!base) {
- pr_err("%s(): ioremap failed\n", __func__);
- return -ENOMEM;
- }
-
- clk_data = mtk_alloc_clk_data(nr);
- if (!clk_data)
- return -ENOMEM;
-
- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
- &mt7988_clk_lock, clk_data);
-
- r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
- __func__, r);
- goto free_mcusys_data;
- }
- return r;
-
-free_mcusys_data:
- mtk_free_clk_data(clk_data);
- return r;
-}
+static const struct mtk_clk_desc mcusys_desc = {
+ .composite_clks = mcu_muxes,
+ .num_composite_clks = ARRAY_SIZE(mcu_muxes),
+};
static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
- {
- .compatible = "mediatek,mt7988-topckgen",
- },
- {}
+ { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
+ { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
+ { /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
static struct platform_driver clk_mt7988_topckgen_drv = {
- .probe = clk_mt7988_topckgen_probe,
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7988-topckgen",
.of_match_table = of_match_clk_mt7988_topckgen,
},
};
-builtin_platform_driver(clk_mt7988_topckgen_drv);
-
-static const struct of_device_id of_match_clk_mt7988_mcusys[] = {
- {
- .compatible = "mediatek,mt7988-mcusys",
- },
- {}
-};
-
-static struct platform_driver clk_mt7988_mcusys_drv = {
- .probe = clk_mt7988_mcusys_probe,
- .driver = {
- .name = "clk-mt7988-mcusys",
- .of_match_table = of_match_clk_mt7988_mcusys,
- },
-};
-builtin_platform_driver(clk_mt7988_mcusys_drv);
\ No newline at end of file
+module_platform_driver(clk_mt7988_topckgen_drv);
+MODULE_LICENSE("GPL");
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-
-#define MTK_GPHY_ID_MT7981 0x03a29461
-#define MTK_GPHY_ID_MT7988 0x03a29481
-
-#define MTK_EXT_PAGE_ACCESS 0x1f
-#define MTK_PHY_PAGE_STANDARD 0x0000
-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
-
-#define MTK_PHY_LPI_REG_14 0x14
-#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
-
-#define MTK_PHY_LPI_REG_1c 0x1c
-#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
-
-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
-
-#define ANALOG_INTERNAL_OPERATION_MAX_US 20
-#define TXRESERVE_MIN 0
-#define TXRESERVE_MAX 7
-
-#define MTK_PHY_ANARG_RG 0x10
-#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_TXVLD_DA_RG 0x12
-#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
-#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
-#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
-#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
-#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
-#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
-#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
-#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
-#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
-
-#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
-#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
-#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
-
-#define MTK_PHY_RXADC_CTRL_RG7 0xc6
-#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
-
-#define MTK_PHY_RXADC_CTRL_RG9 0xc8
-#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
-#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
-#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
-#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
-
-#define MTK_PHY_LDO_OUTPUT_V 0xd7
-
-#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
-#define MTK_PHY_RG_CAL_CKINV BIT(12)
-#define MTK_PHY_RG_ANA_CALEN BIT(8)
-#define MTK_PHY_RG_ZCALEN_A BIT(0)
-
-#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
-#define MTK_PHY_RG_ZCALEN_B BIT(12)
-#define MTK_PHY_RG_ZCALEN_C BIT(8)
-#define MTK_PHY_RG_ZCALEN_D BIT(4)
-#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
-
-#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
-#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
-
-#define MTK_PHY_RG_TX_FILTER 0xfe
-
-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
-#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
-#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
-
-#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
-#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
-
-#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
-#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
-
-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
-#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
-#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
-
-#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
-#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
-#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
-
-#define MTK_PHY_RG_AD_CAL_COMP 0x17a
-#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
-
-#define MTK_PHY_RG_AD_CAL_CLK 0x17b
-#define MTK_PHY_DA_CAL_CLK BIT(0)
-
-#define MTK_PHY_RG_AD_CALIN 0x17c
-#define MTK_PHY_DA_CALIN_FLAG BIT(0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
-#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
-#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
-#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
-#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
-#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
-#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
-#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
-#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
-
-#define MTK_PHY_RG_DEV1E_REG19b 0x19b
-#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
-
-#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
-#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
-#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
-#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
-#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
-#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
-#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
-#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
-#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
-#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
-
-#define MTK_PHY_RG_DEV1E_REG234 0x234
-#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
-#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
-#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
-
-#define MTK_PHY_RG_LPF_CNT_VAL 0x235
-
-#define MTK_PHY_RG_DEV1E_REG238 0x238
-#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
-#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
-
-#define MTK_PHY_RG_DEV1E_REG239 0x239
-#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
-#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
-
-#define MTK_PHY_RG_DEV1E_REG27C 0x27c
-#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
-#define MTK_PHY_RG_DEV1E_REG27D 0x27d
-#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
-
-#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
-#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
-#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
-
-#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
-#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
-#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
-#define MTK_PHY_LPI_TR_READY BIT(9)
-#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
-
-#define MTK_PHY_RG_DEV1E_REG323 0x323
-#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
-#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
-
-#define MTK_PHY_RG_DEV1E_REG324 0x324
-#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
-#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
-
-#define MTK_PHY_RG_DEV1E_REG326 0x326
-#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
-#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
-#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
-#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
-#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
-
-#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
-#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
-
-#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
-#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
-#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
-#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL 0x24
-#define MTK_PHY_LED0_ON_MASK GENMASK(6, 0)
-#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
-#define MTK_PHY_LED0_ON_LINK100 BIT(1)
-#define MTK_PHY_LED0_ON_LINK10 BIT(2)
-#define MTK_PHY_LED0_ON_LINKDOWN BIT(3)
-#define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */
-#define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */
-#define MTK_PHY_LED0_FORCE_ON BIT(6)
-#define MTK_PHY_LED0_POLARITY BIT(14)
-#define MTK_PHY_LED0_ENABLE BIT(15)
-
-#define MTK_PHY_LED0_BLINK_CTRL 0x25
-#define MTK_PHY_LED0_1000TX BIT(0)
-#define MTK_PHY_LED0_1000RX BIT(1)
-#define MTK_PHY_LED0_100TX BIT(2)
-#define MTK_PHY_LED0_100RX BIT(3)
-#define MTK_PHY_LED0_10TX BIT(4)
-#define MTK_PHY_LED0_10RX BIT(5)
-#define MTK_PHY_LED0_COLLISION BIT(6)
-#define MTK_PHY_LED0_RX_CRC_ERR BIT(7)
-#define MTK_PHY_LED0_RX_IDLE_ERR BIT(8)
-#define MTK_PHY_LED0_FORCE_BLINK BIT(9)
-
-#define MTK_PHY_LED1_ON_CTRL 0x26
-#define MTK_PHY_LED1_ON_MASK GENMASK(6, 0)
-#define MTK_PHY_LED1_ON_LINK1000 BIT(0)
-#define MTK_PHY_LED1_ON_LINK100 BIT(1)
-#define MTK_PHY_LED1_ON_LINK10 BIT(2)
-#define MTK_PHY_LED1_ON_LINKDOWN BIT(3)
-#define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */
-#define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */
-#define MTK_PHY_LED1_FORCE_ON BIT(6)
-#define MTK_PHY_LED1_POLARITY BIT(14)
-#define MTK_PHY_LED1_ENABLE BIT(15)
-
-#define MTK_PHY_LED1_BLINK_CTRL 0x27
-#define MTK_PHY_LED1_1000TX BIT(0)
-#define MTK_PHY_LED1_1000RX BIT(1)
-#define MTK_PHY_LED1_100TX BIT(2)
-#define MTK_PHY_LED1_100RX BIT(3)
-#define MTK_PHY_LED1_10TX BIT(4)
-#define MTK_PHY_LED1_10RX BIT(5)
-#define MTK_PHY_LED1_COLLISION BIT(6)
-#define MTK_PHY_LED1_RX_CRC_ERR BIT(7)
-#define MTK_PHY_LED1_RX_IDLE_ERR BIT(8)
-#define MTK_PHY_LED1_FORCE_BLINK BIT(9)
-
-#define MTK_PHY_RG_BG_RASEL 0x115
-#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
-
-/* These macro privides efuse parsing for internal phy. */
-#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
-
-#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
-#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
-
-#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
-#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
-
-#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
-#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
-
-enum {
- NO_PAIR,
- PAIR_A,
- PAIR_B,
- PAIR_C,
- PAIR_D,
-};
-
-enum {
- GPHY_PORT0,
- GPHY_PORT1,
- GPHY_PORT2,
- GPHY_PORT3,
-};
-
-enum calibration_mode {
- EFUSE_K,
- SW_K
-};
-
-enum CAL_ITEM {
- REXT,
- TX_OFFSET,
- TX_AMP,
- TX_R50,
- TX_VCM
-};
-
-enum CAL_MODE {
- EFUSE_M,
- SW_M
-};
-
-struct mtk_socphy_shared_priv {
- u32 boottrap;
-};
-
-static int mtk_socphy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-}
-
-static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-}
-
-/* One calibration cycle consists of:
- * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
- * until AD_CAL_COMP is ready to output calibration result.
- * 2.Wait until DA_CAL_CLK is available.
- * 3.Fetch AD_CAL_COMP_OUT.
- */
-static int cal_cycle(struct phy_device *phydev, int devad,
- u32 regnum, u16 mask, u16 cal_val)
-{
- int reg_val;
- int ret;
-
- phy_modify_mmd(phydev, devad, regnum,
- mask, cal_val);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
- MTK_PHY_DA_CALIN_FLAG);
-
- ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_AD_CAL_CLK, reg_val,
- reg_val & MTK_PHY_DA_CAL_CLK, 500,
- ANALOG_INTERNAL_OPERATION_MAX_US, false);
- if (ret) {
- phydev_err(phydev, "Calibration cycle timeout\n");
- return ret;
- }
-
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
- MTK_PHY_DA_CALIN_FLAG);
- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
- MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
- phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
-
- return ret;
-}
-
-static int rext_fill_result(struct phy_device *phydev, u16 *buf)
-{
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
- MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
- MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
-
- return 0;
-}
-
-static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
-{
- u16 rext_cal_val[2];
-
- rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
- rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
- rext_fill_result(phydev, rext_cal_val);
-
- return 0;
-}
-
-static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
-{
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
- MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
- MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
- MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
- MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
-
- return 0;
-}
-
-static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
-{
- u16 tx_offset_cal_val[4];
-
- tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
- tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
- tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
- tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
-
- tx_offset_fill_result(phydev, tx_offset_cal_val);
-
- return 0;
-}
-
-static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
-{
- int i;
- int bias[16] = {};
- const int vals_9461[16] = { 7, 1, 4, 7,
- 7, 1, 4, 7,
- 7, 1, 4, 7,
- 7, 1, 4, 7 };
- const int vals_9481[16] = { 10, 6, 6, 10,
- 10, 6, 6, 10,
- 10, 6, 6, 10,
- 10, 6, 6, 10 };
- switch (phydev->drv->phy_id) {
- case MTK_GPHY_ID_MT7981:
- /* We add some calibration to efuse values
- * due to board level influence.
- * GBE: +7, TBT: +1, HBT: +4, TST: +7
- */
- memcpy(bias, (const void *)vals_9461, sizeof(bias));
- break;
- case MTK_GPHY_ID_MT7988:
- memcpy(bias, (const void *)vals_9481, sizeof(bias));
- break;
- }
-
- /* Prevent overflow */
- for (i = 0; i < 12; i++) {
- if (buf[i >> 2] + bias[i] > 63) {
- buf[i >> 2] = 63;
- bias[i] = 0;
- }
- }
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
- MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
- MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
- MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
- MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
- MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
- MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
- MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
- MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
-
- return 0;
-}
-
-static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
-{
- u16 tx_amp_cal_val[4];
-
- tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
- tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
- tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
- tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
- tx_amp_fill_result(phydev, tx_amp_cal_val);
-
- return 0;
-}
-
-static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
- u8 txg_calen_x)
-{
- int bias = 0;
- u16 reg, val;
-
- if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
- bias = -2;
-
- val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-
- switch (txg_calen_x) {
- case PAIR_A:
- reg = MTK_PHY_DA_TX_R50_PAIR_A;
- break;
- case PAIR_B:
- reg = MTK_PHY_DA_TX_R50_PAIR_B;
- break;
- case PAIR_C:
- reg = MTK_PHY_DA_TX_R50_PAIR_C;
- break;
- case PAIR_D:
- reg = MTK_PHY_DA_TX_R50_PAIR_D;
- break;
- default:
- return -EINVAL;
- }
-
- phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
-
- return 0;
-}
-
-static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
- u8 txg_calen_x)
-{
- u16 tx_r50_cal_val;
-
- switch (txg_calen_x) {
- case PAIR_A:
- tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
- break;
- case PAIR_B:
- tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
- break;
- case PAIR_C:
- tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
- break;
- case PAIR_D:
- tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
- break;
- default:
- return -EINVAL;
- }
- tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
-
- return 0;
-}
-
-static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
-{
- u8 lower_idx, upper_idx, txreserve_val;
- u8 lower_ret, upper_ret;
- int ret;
-
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ANA_CALEN);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_CAL_CKINV);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_TXVOS_CALEN);
-
- switch (rg_txreserve_x) {
- case PAIR_A:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN0_A,
- MTK_PHY_DASN_DAC_IN0_A_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN1_A,
- MTK_PHY_DASN_DAC_IN1_A_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ZCALEN_A);
- break;
- case PAIR_B:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN0_B,
- MTK_PHY_DASN_DAC_IN0_B_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN1_B,
- MTK_PHY_DASN_DAC_IN1_B_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_B);
- break;
- case PAIR_C:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN0_C,
- MTK_PHY_DASN_DAC_IN0_C_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN1_C,
- MTK_PHY_DASN_DAC_IN1_C_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_C);
- break;
- case PAIR_D:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN0_D,
- MTK_PHY_DASN_DAC_IN0_D_MASK);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DASN_DAC_IN1_D,
- MTK_PHY_DASN_DAC_IN1_D_MASK);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_D);
- break;
- default:
- ret = -EINVAL;
- goto restore;
- }
-
- lower_idx = TXRESERVE_MIN;
- upper_idx = TXRESERVE_MAX;
-
- phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
- while ((upper_idx - lower_idx) > 1) {
- txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
- ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK |
- MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK |
- MTK_PHY_DA_RX_PSBN_LP_MASK,
- txreserve_val << 12 | txreserve_val << 8 |
- txreserve_val << 4 | txreserve_val);
- if (ret == 1) {
- upper_idx = txreserve_val;
- upper_ret = ret;
- } else if (ret == 0) {
- lower_idx = txreserve_val;
- lower_ret = ret;
- } else {
- goto restore;
- }
- }
-
- if (lower_idx == TXRESERVE_MIN) {
- lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK |
- MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK |
- MTK_PHY_DA_RX_PSBN_LP_MASK,
- lower_idx << 12 | lower_idx << 8 |
- lower_idx << 4 | lower_idx);
- ret = lower_ret;
- } else if (upper_idx == TXRESERVE_MAX) {
- upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK |
- MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK |
- MTK_PHY_DA_RX_PSBN_LP_MASK,
- upper_idx << 12 | upper_idx << 8 |
- upper_idx << 4 | upper_idx);
- ret = upper_ret;
- }
- if (ret < 0)
- goto restore;
-
- /* We calibrate TX-VCM in different logic. Check upper index and then
- * lower index. If this calibration is valid, apply lower index's result.
- */
- ret = upper_ret - lower_ret;
- if (ret == 1) {
- ret = 0;
- /* Make sure we use upper_idx in our calibration system */
- cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK |
- MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK |
- MTK_PHY_DA_RX_PSBN_LP_MASK,
- upper_idx << 12 | upper_idx << 8 |
- upper_idx << 4 | upper_idx);
- phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
- } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
- lower_ret == 1) {
- ret = 0;
- cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
- MTK_PHY_DA_RX_PSBN_TBT_MASK |
- MTK_PHY_DA_RX_PSBN_HBT_MASK |
- MTK_PHY_DA_RX_PSBN_GBE_MASK |
- MTK_PHY_DA_RX_PSBN_LP_MASK,
- lower_idx << 12 | lower_idx << 8 |
- lower_idx << 4 | lower_idx);
- phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
- lower_idx);
- } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
- lower_ret == 0) {
- ret = 0;
- phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
- upper_idx);
- } else {
- ret = -EINVAL;
- }
-
-restore:
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ANA_CALEN);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_TXVOS_CALEN);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
- MTK_PHY_RG_ZCALEN_A);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
- MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
- MTK_PHY_RG_ZCALEN_D);
-
- return ret;
-}
-
-static void mt798x_phy_common_finetune(struct phy_device *phydev)
-{
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* EnabRandUpdTrig = 1 */
- __phy_write(phydev, 0x11, 0x2f00);
- __phy_write(phydev, 0x12, 0xe);
- __phy_write(phydev, 0x10, 0x8fb0);
-
- /* NormMseLoThresh = 85 */
- __phy_write(phydev, 0x11, 0x55a0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x83aa);
-
- /* TrFreeze = 0 */
- __phy_write(phydev, 0x11, 0x0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9686);
-
- /* SSTrKp1000Slv = 5 */
- __phy_write(phydev, 0x11, 0xbaef);
- __phy_write(phydev, 0x12, 0x2e);
- __phy_write(phydev, 0x10, 0x968c);
-
- /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
- * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
- */
- __phy_write(phydev, 0x11, 0xd10a);
- __phy_write(phydev, 0x12, 0x34);
- __phy_write(phydev, 0x10, 0x8f82);
-
- /* VcoSlicerThreshBitsHigh */
- __phy_write(phydev, 0x11, 0x5555);
- __phy_write(phydev, 0x12, 0x55);
- __phy_write(phydev, 0x10, 0x8ec0);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-
- /* rg_tr_lpf_cnt_val = 512 */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-
- /* IIR2 related */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-
- /* FFE peaking */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
- MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
- MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
-
- /* Disable LDO pump */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
- /* Adjust LDO output voltage */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-}
-
-static void mt7981_phy_finetune(struct phy_device *phydev)
-{
- u16 val[8] = { 0x01ce, 0x01c1,
- 0x020f, 0x0202,
- 0x03d0, 0x03c0,
- 0x0013, 0x0005 };
- int i, k;
-
- /* 100M eye finetune:
- * Keep middle level of TX MLT3 shapper as default.
- * Only change TX MLT3 overshoot level here.
- */
- for (k = 0, i = 1; i < 12; i++) {
- if (i % 3 == 0)
- continue;
- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
- }
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
- __phy_write(phydev, 0x11, 0xc71);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
-
- /* FfeUpdGainForce = 4 */
- __phy_write(phydev, 0x11, 0x240);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9680);
-
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
-static void mt7988_phy_finetune(struct phy_device *phydev)
-{
- u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
- 0x020d, 0x0206, 0x0384, 0x03d0,
- 0x03c6, 0x030a, 0x0011, 0x0005 };
- int i;
-
- /* Set default MLT3 shaper first */
- for (i = 0; i < 12; i++)
- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
-
- /* TCT finetune */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-
- /* Disable TX power saving */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
- __phy_write(phydev, 0x11, 0x671);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* ResetSyncOffset = 5 */
- __phy_write(phydev, 0x11, 0x500);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate is 1 at default on mt7988 */
-
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
- /* TxClkOffset = 2 */
- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
-static void mt798x_phy_eee(struct phy_device *phydev)
-{
- phy_modify_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
- MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
- MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
- FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- 0xff));
-
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_TESTMUX_ADC_CTRL,
- MTK_PHY_RG_TXEN_DIG_MASK);
-
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
-
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
- MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
- MTK_PHY_LPI_SLV_SEND_TX_EN,
- FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
- MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
- MTK_PHY_LPI_TXPCS_LOC_RCV,
- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
- MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
- FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
- FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
- MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
- FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
- 0x33) |
- MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
- MTK_PHY_LPI_VCO_EEE_STG0_EN);
-
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
- MTK_PHY_EEE_WAKE_MAS_INT_DC |
- MTK_PHY_EEE_WAKE_SLV_INT_DC);
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
- MTK_PHY_SMI_DETCNT_MAX_MASK,
- FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
- MTK_PHY_SMI_DET_MAX_EN);
-
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
- MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
- MTK_PHY_TREC_UPDATE_ENAB_CLR |
- MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
- MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* Regsigdet_sel_1000 = 0 */
- __phy_write(phydev, 0x11, 0xb);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9690);
-
- /* REG_EEE_st2TrKf1000 = 3 */
- __phy_write(phydev, 0x11, 0x114f);
- __phy_write(phydev, 0x12, 0x2);
- __phy_write(phydev, 0x10, 0x969a);
-
- /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
- __phy_write(phydev, 0x11, 0x3028);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x969e);
-
- /* RegEEE_slv_wake_int_timer_tar = 8 */
- __phy_write(phydev, 0x11, 0x5010);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96a0);
-
- /* RegEEE_trfreeze_timer2 = 586 */
- __phy_write(phydev, 0x11, 0x24a);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96a8);
-
- /* RegEEE100Stg1_tar = 16 */
- __phy_write(phydev, 0x11, 0x3210);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96b8);
-
- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
- __phy_write(phydev, 0x11, 0x1463);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96ca);
-
- /* DfeTailEnableVgaThresh1000 = 27 */
- __phy_write(phydev, 0x11, 0x36);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8f80);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
-
- __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
- FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1,
- MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
- MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
-}
-
-static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
- u8 start_pair, u8 end_pair)
-{
- u8 pair_n;
- int ret;
-
- for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
- /* TX_OFFSET & TX_AMP have no SW calibration. */
- switch (cal_item) {
- case TX_VCM:
- ret = tx_vcm_cal_sw(phydev, pair_n);
- break;
- default:
- return -EINVAL;
- }
- if (ret)
- return ret;
- }
- return 0;
-}
-
-static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
- u8 start_pair, u8 end_pair, u32 *buf)
-{
- u8 pair_n;
- int ret;
-
- for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
- /* TX_VCM has no efuse calibration. */
- switch (cal_item) {
- case REXT:
- ret = rext_cal_efuse(phydev, buf);
- break;
- case TX_OFFSET:
- ret = tx_offset_cal_efuse(phydev, buf);
- break;
- case TX_AMP:
- ret = tx_amp_cal_efuse(phydev, buf);
- break;
- case TX_R50:
- ret = tx_r50_cal_efuse(phydev, buf, pair_n);
- break;
- default:
- return -EINVAL;
- }
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
- enum CAL_MODE cal_mode, u8 start_pair,
- u8 end_pair, u32 *buf)
-{
- int ret;
-
- switch (cal_mode) {
- case EFUSE_M:
- ret = cal_efuse(phydev, cal_item, start_pair,
- end_pair, buf);
- break;
- case SW_M:
- ret = cal_sw(phydev, cal_item, start_pair, end_pair);
- break;
- default:
- return -EINVAL;
- }
-
- if (ret) {
- phydev_err(phydev, "cal %d failed\n", cal_item);
- return -EIO;
- }
-
- return 0;
-}
-
-static int mt798x_phy_calibration(struct phy_device *phydev)
-{
- int ret = 0;
- u32 *buf;
- size_t len;
- struct nvmem_cell *cell;
-
- cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
- if (IS_ERR(cell)) {
- if (PTR_ERR(cell) == -EPROBE_DEFER)
- return PTR_ERR(cell);
- return 0;
- }
-
- buf = (u32 *)nvmem_cell_read(cell, &len);
- if (IS_ERR(buf))
- return PTR_ERR(buf);
- nvmem_cell_put(cell);
-
- if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
- phydev_err(phydev, "invalid efuse data\n");
- ret = -EINVAL;
- goto out;
- }
-
- ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
- if (ret)
- goto out;
- ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
- if (ret)
- goto out;
- ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
- if (ret)
- goto out;
- ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
- if (ret)
- goto out;
- ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
- if (ret)
- goto out;
-
-out:
- kfree(buf);
- return ret;
-}
-
-static int mt798x_phy_config_init(struct phy_device *phydev)
-{
- switch (phydev->drv->phy_id) {
- case MTK_GPHY_ID_MT7981:
- mt7981_phy_finetune(phydev);
- break;
- case MTK_GPHY_ID_MT7988:
- mt7988_phy_finetune(phydev);
- break;
- }
-
- mt798x_phy_common_finetune(phydev);
- mt798x_phy_eee(phydev);
-
- return mt798x_phy_calibration(phydev);
-}
-
-static int mt7988_phy_setup_led(struct phy_device *phydev)
-{
- struct mtk_socphy_shared_priv *priv = phydev->shared->priv;
- int port = phydev->mdio.addr;
- u32 reg = priv->boottrap;
- struct pinctrl *pinctrl;
-
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY |
- MTK_PHY_LED0_ON_LINK10 |
- MTK_PHY_LED0_ON_LINK100 |
- MTK_PHY_LED0_ON_LINK1000);
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
- MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY |
- MTK_PHY_LED1_ON_LINK10 |
- MTK_PHY_LED1_ON_LINK100 |
- MTK_PHY_LED1_ON_LINK1000);
-
- if ((port == GPHY_PORT0 && reg & BIT(8)) ||
- (port == GPHY_PORT1 && reg & BIT(9)) ||
- (port == GPHY_PORT2 && reg & BIT(10)) ||
- (port == GPHY_PORT3 && reg & BIT(11))) {
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED0_POLARITY);
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
- MTK_PHY_LED1_POLARITY);
- }
-
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
- MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX |
- MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX |
- MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX);
- phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
- MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX |
- MTK_PHY_LED1_100TX | MTK_PHY_LED1_100RX |
- MTK_PHY_LED1_10TX | MTK_PHY_LED1_10RX);
-
- pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
- if (IS_ERR(pinctrl)) {
- dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n");
- return PTR_ERR(pinctrl);
- }
-
- return 0;
-}
-
-static int mt7988_phy_probe_shared(struct phy_device *phydev)
-{
- struct mtk_socphy_shared_priv *priv = phydev->shared->priv;
- void __iomem *boottrap;
- struct device_node *np;
- u32 reg;
-
- np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap");
- if (!np)
- return -ENOENT;
-
- boottrap = of_iomap(np, 0);
- if (!boottrap)
- return -ENOMEM;
-
- reg = readl(boottrap);
- iounmap(boottrap);
-
- priv->boottrap = reg;
-
- return 0;
-}
-
-static int mt7981_phy_probe(struct phy_device *phydev)
-{
- return mt798x_phy_calibration(phydev);
-}
-
-static int mt7988_phy_probe(struct phy_device *phydev)
-{
- int err;
-
- err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
- sizeof(struct mtk_socphy_shared_priv));
- if (err)
- return err;
-
- if (phy_package_probe_once(phydev)) {
- err = mt7988_phy_probe_shared(phydev);
- if (err)
- return err;
- }
-
- mt7988_phy_setup_led(phydev);
-
- return mt798x_phy_calibration(phydev);
-}
-
-static struct phy_driver mtk_socphy_driver[] = {
- {
- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
- .name = "MediaTek MT7981 PHY",
- .config_init = mt798x_phy_config_init,
- .config_intr = genphy_no_config_intr,
- .handle_interrupt = genphy_handle_interrupt_no_ack,
- .probe = mt7981_phy_probe,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
- .read_page = mtk_socphy_read_page,
- .write_page = mtk_socphy_write_page,
- },
- {
- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
- .name = "MediaTek MT7988 PHY",
- .config_init = mt798x_phy_config_init,
- .config_intr = genphy_no_config_intr,
- .handle_interrupt = genphy_handle_interrupt_no_ack,
- .probe = mt7988_phy_probe,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
- .read_page = mtk_socphy_read_page,
- .write_page = mtk_socphy_write_page,
- },
-};
-
-module_phy_driver(mtk_socphy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
- { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
- { }
-};
-
-MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
-MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7981 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7981_PIN(_number, _name) \
- MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
- PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
- PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
- PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
- PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
- PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
- PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
- PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
- PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
- PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
- PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
- PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-
- PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
- PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
- PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
- PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
- PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-
- PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-
- PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
- PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
- PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
- PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
- PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
- PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
- PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
- PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
- PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-
- PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
- PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
- PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
- PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-
- PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
- PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-
- PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
- PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-
- PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-
- PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
- PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
- PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
- PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-
- PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
- PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
- PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
- PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
- PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
- PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
- PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
- PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
- PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
- PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
- PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
- PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
- PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-
- PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
- PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
- PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
- PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
- PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-
- PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-
- PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
- PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
- PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
- PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
- PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
- PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
- PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
- PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
- PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
- PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-
- PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
- PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
- PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
- PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
- PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
- PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-
- PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
- PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-
- PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
- PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-
- PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-
- PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
- PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
- PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
- PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
- PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
- PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
- PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
- PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
- PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-
- PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
- PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
- PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
- PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-
- PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
- PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
- PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
- PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
- PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-
- PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
- PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
- PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
- PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
- PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
- PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-
- PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-
- PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
- PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-
- PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-
- PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-
- PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-
- PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-
- PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-
- PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-
- PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-
- PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-
- PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
- PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
- PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
- PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-
- PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
- PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
- PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
- PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-
- PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-
- PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
- PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
- PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
- PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-
- PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
- PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-
- PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-
- PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-
- PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
- PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-
- PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
- PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
- PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
- PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
- PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-
- PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-
- PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
- PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
- PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
- PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-
- PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-
- PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-
- PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-
- PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-};
-
-static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
- PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-
- PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
- PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
- PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
- PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
- PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-
- PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-
- PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
- PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
- PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
- PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-
- PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-
- PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-
- PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-
- PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-};
-
-static const unsigned int mt7981_pull_type[] = {
- MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
- MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
- MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
- MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
- MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
- MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
- MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
- MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
- MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
- MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
- MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
- MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
- MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
- MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
- MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
- MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
- MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
- MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
- MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
- MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
- MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
- MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
- MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
- MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
- MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
- MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
- MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
- MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
- MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
- MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
- MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
- MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
- MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
- MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
- MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
- MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
- [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
- [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
- [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
- [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
- [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
- [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
- [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
- [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
- [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
- [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
- [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
- [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7981_pins[] = {
- MT7981_PIN(0, "GPIO_WPS"),
- MT7981_PIN(1, "GPIO_RESET"),
- MT7981_PIN(2, "SYS_WATCHDOG"),
- MT7981_PIN(3, "PCIE_PERESET_N"),
- MT7981_PIN(4, "JTAG_JTDO"),
- MT7981_PIN(5, "JTAG_JTDI"),
- MT7981_PIN(6, "JTAG_JTMS"),
- MT7981_PIN(7, "JTAG_JTCLK"),
- MT7981_PIN(8, "JTAG_JTRST_N"),
- MT7981_PIN(9, "WO_JTAG_JTDO"),
- MT7981_PIN(10, "WO_JTAG_JTDI"),
- MT7981_PIN(11, "WO_JTAG_JTMS"),
- MT7981_PIN(12, "WO_JTAG_JTCLK"),
- MT7981_PIN(13, "WO_JTAG_JTRST_N"),
- MT7981_PIN(14, "USB_VBUS"),
- MT7981_PIN(15, "PWM0"),
- MT7981_PIN(16, "SPI0_CLK"),
- MT7981_PIN(17, "SPI0_MOSI"),
- MT7981_PIN(18, "SPI0_MISO"),
- MT7981_PIN(19, "SPI0_CS"),
- MT7981_PIN(20, "SPI0_HOLD"),
- MT7981_PIN(21, "SPI0_WP"),
- MT7981_PIN(22, "SPI1_CLK"),
- MT7981_PIN(23, "SPI1_MOSI"),
- MT7981_PIN(24, "SPI1_MISO"),
- MT7981_PIN(25, "SPI1_CS"),
- MT7981_PIN(26, "SPI2_CLK"),
- MT7981_PIN(27, "SPI2_MOSI"),
- MT7981_PIN(28, "SPI2_MISO"),
- MT7981_PIN(29, "SPI2_CS"),
- MT7981_PIN(30, "SPI2_HOLD"),
- MT7981_PIN(31, "SPI2_WP"),
- MT7981_PIN(32, "UART0_RXD"),
- MT7981_PIN(33, "UART0_TXD"),
- MT7981_PIN(34, "PCIE_CLK_REQ"),
- MT7981_PIN(35, "PCIE_WAKE_N"),
- MT7981_PIN(36, "SMI_MDC"),
- MT7981_PIN(37, "SMI_MDIO"),
- MT7981_PIN(38, "GBE_INT"),
- MT7981_PIN(39, "GBE_RESET"),
- MT7981_PIN(40, "WF_DIG_RESETB"),
- MT7981_PIN(41, "WF_CBA_RESETB"),
- MT7981_PIN(42, "WF_XO_REQ"),
- MT7981_PIN(43, "WF_TOP_CLK"),
- MT7981_PIN(44, "WF_TOP_DATA"),
- MT7981_PIN(45, "WF_HB1"),
- MT7981_PIN(46, "WF_HB2"),
- MT7981_PIN(47, "WF_HB3"),
- MT7981_PIN(48, "WF_HB4"),
- MT7981_PIN(49, "WF_HB0"),
- MT7981_PIN(50, "WF_HB0_B"),
- MT7981_PIN(51, "WF_HB5"),
- MT7981_PIN(52, "WF_HB6"),
- MT7981_PIN(53, "WF_HB7"),
- MT7981_PIN(54, "WF_HB8"),
- MT7981_PIN(55, "WF_HB9"),
- MT7981_PIN(56, "WF_HB10"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-/* WA_AICE */
-static int mt7981_wa_aice1_pins[] = { 0, 1, };
-static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wa_aice2_pins[] = { 0, 1, };
-static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-
-static int mt7981_wa_aice3_pins[] = { 28, 29, };
-static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-
-static int mt7981_wm_aice1_pins[] = { 9, 10, };
-static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-
-static int mt7981_wm_aice2_pins[] = { 30, 31, };
-static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-
-/* WM_UART */
-static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-
-static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-
-static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-
-/* DFD */
-static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-
-/* SYS_WATCHDOG */
-static int mt7981_watchdog_pins[] = { 2, };
-static int mt7981_watchdog_funcs[] = { 1, };
-
-static int mt7981_watchdog1_pins[] = { 13, };
-static int mt7981_watchdog1_funcs[] = { 5, };
-
-/* PCIE_PERESET_N */
-static int mt7981_pcie_pereset_pins[] = { 3, };
-static int mt7981_pcie_pereset_funcs[] = { 1, };
-
-/* JTAG */
-static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-
-/* WM_JTAG */
-static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-
-static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* WO0_JTAG */
-static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-
-static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-
-/* UART2 */
-static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-
-/* GBE_LED0 */
-static int mt7981_gbe_led0_pins[] = { 8, };
-static int mt7981_gbe_led0_funcs[] = { 3, };
-
-/* PTA_EXT */
-static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-
-static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-
-/* PWM2 */
-static int mt7981_pwm2_pins[] = { 7, };
-static int mt7981_pwm2_funcs[] = { 4, };
-
-/* NET_WO0_UART_TXD */
-static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-
-static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-
-static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-
-/* SPI1 */
-static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-
-/* I2C */
-static int mt7981_i2c0_0_pins[] = { 6, 7, };
-static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-
-static int mt7981_i2c0_1_pins[] = { 30, 31, };
-static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-
-static int mt7981_i2c0_2_pins[] = { 36, 37, };
-static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-
-static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-
-static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-
-static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-
-static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-
-/* DFD_NTRST */
-static int mt7981_dfd_ntrst_pins[] = { 8, };
-static int mt7981_dfd_ntrst_funcs[] = { 6, };
-
-/* PWM0 */
-static int mt7981_pwm0_0_pins[] = { 13, };
-static int mt7981_pwm0_0_funcs[] = { 2, };
-
-static int mt7981_pwm0_1_pins[] = { 15, };
-static int mt7981_pwm0_1_funcs[] = { 1, };
-
-/* PWM1 */
-static int mt7981_pwm1_0_pins[] = { 14, };
-static int mt7981_pwm1_0_funcs[] = { 2, };
-
-static int mt7981_pwm1_1_pins[] = { 15, };
-static int mt7981_pwm1_1_funcs[] = { 3, };
-
-/* GBE_LED1 */
-static int mt7981_gbe_led1_pins[] = { 13, };
-static int mt7981_gbe_led1_funcs[] = { 3, };
-
-/* PCM */
-static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-
-/* UDI */
-static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-
-/* DRV_VBUS */
-static int mt7981_drv_vbus_pins[] = { 14, };
-static int mt7981_drv_vbus_funcs[] = { 1, };
-
-/* EMMC */
-static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-/* SNFI */
-static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-
-/* SPI0 */
-static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI0 */
-static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-
-/* SPI1 */
-static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-
-/* SPI2 */
-static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-
-/* UART1 */
-static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-
-/* UART2 */
-static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-/* UART0 */
-static int mt7981_uart0_pins[] = { 32, 33, };
-static int mt7981_uart0_funcs[] = { 1, 1, };
-
-/* PCIE_CLK_REQ */
-static int mt7981_pcie_clk_pins[] = { 34, };
-static int mt7981_pcie_clk_funcs[] = { 2, };
-
-/* PCIE_WAKE_N */
-static int mt7981_pcie_wake_pins[] = { 35, };
-static int mt7981_pcie_wake_funcs[] = { 2, };
-
-/* MDC_MDIO */
-static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-
-/* WF0_MODE1 */
-static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* WF0_MODE3 */
-static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-/* WF2G_LED */
-static int mt7981_wf2g_led0_pins[] = { 30, };
-static int mt7981_wf2g_led0_funcs[] = { 2, };
-
-static int mt7981_wf2g_led1_pins[] = { 34, };
-static int mt7981_wf2g_led1_funcs[] = { 1, };
-
-/* WF5G_LED */
-static int mt7981_wf5g_led0_pins[] = { 31, };
-static int mt7981_wf5g_led0_funcs[] = { 2, };
-
-static int mt7981_wf5g_led1_pins[] = { 35, };
-static int mt7981_wf5g_led1_funcs[] = { 1, };
-
-/* MT7531_INT */
-static int mt7981_mt7531_int_pins[] = { 38, };
-static int mt7981_mt7531_int_funcs[] = { 1, };
-
-/* ANT_SEL */
-static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-
-static const struct group_desc mt7981_groups[] = {
- /* @GPIO(0,1): WA_AICE(2) */
- PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
- /* @GPIO(0,1): WA_AICE(3) */
- PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
- /* @GPIO(0,1): WM_UART(5) */
- PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
- /* @GPIO(0,1,4,5): DFD(6) */
- PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
- /* @GPIO(2): SYS_WATCHDOG(1) */
- PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
- /* @GPIO(3): PCIE_PERESET_N(1) */
- PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
- /* @GPIO(4,8) JTAG(1) */
- PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
- /* @GPIO(4,8) WM_JTAG(2) */
- PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
- /* @GPIO(9,13) WO0_JTAG(1) */
- PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
- /* @GPIO(4,7) WM_JTAG(3) */
- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
- /* @GPIO(8) GBE_LED0(3) */
- PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
- /* @GPIO(4,6) PTA_EXT(4) */
- PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
- /* @GPIO(7) PWM2(4) */
- PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
- /* @GPIO(8) NET_WO0_UART_TXD(4) */
- PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
- /* @GPIO(4,7) SPI1(5) */
- PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
- /* @GPIO(6,7) I2C(5) */
- PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
- /* @GPIO(0,1,4,5): DFD_NTRST(6) */
- PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
- /* @GPIO(9,10): WM_AICE(2) */
- PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
- /* @GPIO(13): PWM0(2) */
- PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
- /* @GPIO(15): PWM0(1) */
- PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
- /* @GPIO(14): PWM1(2) */
- PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
- /* @GPIO(15): PWM1(3) */
- PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
- /* @GPIO(14) NET_WO0_UART_TXD(3) */
- PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
- /* @GPIO(15) NET_WO0_UART_TXD(4) */
- PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
- /* @GPIO(13) GBE_LED0(3) */
- PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
- /* @GPIO(9,13) PCM(4) */
- PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
- /* @GPIO(13): SYS_WATCHDOG1(5) */
- PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
- /* @GPIO(9,13) UDI(4) */
- PINCTRL_PIN_GROUP("udi", mt7981_udi),
- /* @GPIO(14) DRV_VBUS(1) */
- PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
- /* @GPIO(15,25): EMMC(2) */
- PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
- /* @GPIO(16,21): SNFI(3) */
- PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
- /* @GPIO(16,19): SPI0(1) */
- PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
- /* @GPIO(20,21): SPI0(1) */
- PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
- /* @GPIO(22,25) SPI1(1) */
- PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
- /* @GPIO(26,29): SPI2(1) */
- PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
- /* @GPIO(30,31): SPI0(1) */
- PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
- /* @GPIO(16,19): UART1(4) */
- PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
- /* @GPIO(26,29): UART1(2) */
- PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
- /* @GPIO(22,25): UART1(3) */
- PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
- /* @GPIO(22,24) PTA_EXT(4) */
- PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
- /* @GPIO(20,21): WM_UART(4) */
- PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
- /* @GPIO(30,31): WM_UART(3) */
- PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
- /* @GPIO(20,24) WM_JTAG(5) */
- PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
- /* @GPIO(25,29) WO0_JTAG(5) */
- PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
- /* @GPIO(28,29): WA_AICE(3) */
- PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
- /* @GPIO(30,31): WM_AICE(5) */
- PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
- /* @GPIO(30,31): I2C(4) */
- PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
- /* @GPIO(30,31): I2C(6) */
- PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
- /* @GPIO(32,33): I2C(1) */
- PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
- /* @GPIO(32,33): I2C(2) */
- PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
- /* @GPIO(32,33): I2C(3) */
- PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
- /* @GPIO(32,33): I2C(5) */
- PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
- /* @GPIO(34): PCIE_CLK_REQ(2) */
- PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
- /* @GPIO(35): PCIE_WAKE_N(2) */
- PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
- /* @GPIO(36,37): I2C(2) */
- PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
- /* @GPIO(36,37): MDC_MDIO(1) */
- PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
- /* @GPIO(36,37): MDC_MDIO(3) */
- PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
- /* @GPIO(69,85): WF0_MODE1(1) */
- PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
- /* @GPIO(74,80): WF0_MODE3(3) */
- PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
- /* @GPIO(30): WF2G_LED(2) */
- PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
- /* @GPIO(34): WF2G_LED(1) */
- PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
- /* @GPIO(31): WF5G_LED(2) */
- PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
- /* @GPIO(35): WF5G_LED(1) */
- PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
- /* @GPIO(38): MT7531_INT(1) */
- PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
- /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
- PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
- "wa_aice3", "wm_aice1_2", };
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
- "wo0_jtag_1", "wm_jtag_1", };
-static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
- "wf2g_led1", "wf5g_led0", "wf5g_led1", };
-static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
- "pwm1_0", "pwm1_1", };
-static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
- "spi2_wp_hold", };
-static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
- "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-static const char *mt7981_pcm_groups[] = { "pcm", };
-static const char *mt7981_udi_groups[] = { "udi", };
-static const char *mt7981_usb_groups[] = { "drv_vbus", };
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
- "wf0_mode1", "wf0_mode3", "mt7531_int", };
-static const char *mt7981_ant_groups[] = { "ant_sel", };
-
-static const struct function_desc mt7981_functions[] = {
- {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
- {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
- {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
- {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
- {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
- {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
- {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
- {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
- {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
- {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
- {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
- {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
- {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
- {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
- {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
- {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
- {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-};
-
-static const struct mtk_eint_hw mt7981_eint_hw = {
- .port_mask = 7,
- .ports = 7,
- .ap_num = ARRAY_SIZE(mt7981_pins),
- .db_cnt = 16,
-};
-
-static const char * const mt7981_pinctrl_register_base_names[] = {
- "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
- "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-};
-
-static struct mtk_pin_soc mt7981_data = {
- .reg_cal = mt7981_reg_cals,
- .pins = mt7981_pins,
- .npins = ARRAY_SIZE(mt7981_pins),
- .grps = mt7981_groups,
- .ngrps = ARRAY_SIZE(mt7981_groups),
- .funcs = mt7981_functions,
- .nfuncs = ARRAY_SIZE(mt7981_functions),
- .eint_hw = &mt7981_eint_hw,
- .gpio_m = 0,
- .ies_present = false,
- .base_names = mt7981_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
- .pull_type = mt7981_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
- .drive_set = mtk_pinconf_drive_set_rev1,
- .drive_get = mtk_pinconf_drive_get_rev1,
- .adv_pull_get = mtk_pinconf_adv_pull_get,
- .adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7981_pinctrl_of_match[] = {
- { .compatible = "mediatek,mt7981-pinctrl", },
- {}
-};
-
-static int mt7981_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-}
-
-static struct platform_driver mt7981_pinctrl_driver = {
- .driver = {
- .name = "mt7981-pinctrl",
- .of_match_table = mt7981_pinctrl_of_match,
- },
- .probe = mt7981_pinctrl_probe,
-};
-
-static int __init mt7981_pinctrl_init(void)
-{
- return platform_driver_register(&mt7981_pinctrl_driver);
-}
-arch_initcall(mt7981_pinctrl_init);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7986 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits) \
- PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits, 32, 0)
-
-/**
- * enum - Locking variants of the iocfg bases
- *
- * MT7986 have multiple bases to program pin configuration listed as the below:
- * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
- * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
- * _i_based could be used to indicate what base the pin should be mapped into.
- *
- * Each iocfg register base control different group of pads on the SoC
- *
- *
- * chip carrier
- *
- * A B C D E F G H
- * +------------------------+
- * 8 | o o o o o o o o |
- * 7 | o o o o o o o o |
- * 6 | o o o o o o o o |
- * 5 | o o o o o o o o |
- * 4 | o o o o o o o o |
- * 3 | o o o o o o o o |
- * 2 | o o o o o o o o |
- * 1 | o o o o o o o o |
- * +------------------------+
- *
- * inside Chip carrier
- *
- * A B C D E F G H
- * +------------------------+
- * 8 | |
- * 7 | TL TR |
- * 6 | +---------+ |
- * 5 | LT | | RT |
- * 4 | | | |
- * 3 | LB | | RB |
- * 2 | +---------+ |
- * 1 | |
- * +------------------------+
- *
- */
-
-enum {
- GPIO_BASE,
- IOCFG_RT_BASE,
- IOCFG_RB_BASE,
- IOCFG_LT_BASE,
- IOCFG_LB_BASE,
- IOCFG_TR_BASE,
- IOCFG_TL_BASE,
-};
-
-static const char *const mt7986_pinctrl_register_base_names[] = {
- "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
- "iocfg_tl",
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
- PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
- PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
- PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
- PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
- PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
- PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
- PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
- PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
- PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
- PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
- PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
- PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
- PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
- PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
- PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
- PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
- PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
- PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
- PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
- PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
- PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
- PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
- PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
- PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
- PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
- PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
- PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
- PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
- PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
- PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
- PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
- PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
- PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
- PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
- PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
- PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
- PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
- PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
- PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
- PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
- PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
- PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
- PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
- PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
- PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
- PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
- PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
- PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
- PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
- PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
- PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
- PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
- PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
- PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
- PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
- PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
- PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
- PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
- PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
- PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
- PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
- PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
- PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
- PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
- PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
- PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
- PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
- PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
- PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
- PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
- PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
- PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
- PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
- PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
- PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
- PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
- PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
- PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
- PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
- PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
- PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
- PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
- PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
- PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
- PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
- PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
- PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
- PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
- PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
- PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
- PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
- PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
- PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
- PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
- PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
- PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
- PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
- PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
- PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
- PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
- PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
- PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
- PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
- PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
- PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
- PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
- PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
- PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
- PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
- PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
- PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
- PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
- PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
- PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
- PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
- PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
- PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
- PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
- PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
- PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
- PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
- PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
- PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
- PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
- PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
- PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
- PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
- PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
- PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
- PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
- PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
- PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
- PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
- PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
- PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
- PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
- PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
- PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
- PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
- PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
- PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
- PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
- PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
- PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
- PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
- PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
- PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
- PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
- PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
- PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
- PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
- PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
- PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
- PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
- PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
- PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
- PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
- PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
- PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
- PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
- PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
- PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
- PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
- PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
- PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
- PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
- PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
- PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
- PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
- PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
- PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
- PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
- PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
- PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
- PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
- PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
-};
-
-static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
- PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
- PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
- PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
- PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
- PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
- PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
- PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
- PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
- PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
- PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
- PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
- PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
- PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
- PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
- PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
- PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
- PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
- PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
- PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
- PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
- PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
- PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
- PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
- PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
- PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
- PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
- PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
- PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
- PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
-};
-
-static const unsigned int mt7986_pull_type[] = {
- MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
- MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
- MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
- MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
- MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
- MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
- MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
- MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
- MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
- MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
- MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
- MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
- MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
- MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
- MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
- MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
- MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
- MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
- MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
- MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
- MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
- MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
- MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
- MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
- MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
- MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
- MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
- MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
- MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
- MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
- MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
- MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
- MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
- MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
- MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
- MTK_PULL_PU_PD_TYPE,/*100*/
-};
-
-static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
- [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
- [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
- [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
- [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
- [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
- [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
- [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
- [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
- [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
- [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
- [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
- [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7986a_pins[] = {
- MT7986_PIN(0, "SYS_WATCHDOG"),
- MT7986_PIN(1, "WF2G_LED"),
- MT7986_PIN(2, "WF5G_LED"),
- MT7986_PIN(3, "I2C_SCL"),
- MT7986_PIN(4, "I2C_SDA"),
- MT7986_PIN(5, "GPIO_0"),
- MT7986_PIN(6, "GPIO_1"),
- MT7986_PIN(7, "GPIO_2"),
- MT7986_PIN(8, "GPIO_3"),
- MT7986_PIN(9, "GPIO_4"),
- MT7986_PIN(10, "GPIO_5"),
- MT7986_PIN(11, "GPIO_6"),
- MT7986_PIN(12, "GPIO_7"),
- MT7986_PIN(13, "GPIO_8"),
- MT7986_PIN(14, "GPIO_9"),
- MT7986_PIN(15, "GPIO_10"),
- MT7986_PIN(16, "GPIO_11"),
- MT7986_PIN(17, "GPIO_12"),
- MT7986_PIN(18, "GPIO_13"),
- MT7986_PIN(19, "GPIO_14"),
- MT7986_PIN(20, "GPIO_15"),
- MT7986_PIN(21, "PWM0"),
- MT7986_PIN(22, "PWM1"),
- MT7986_PIN(23, "SPI0_CLK"),
- MT7986_PIN(24, "SPI0_MOSI"),
- MT7986_PIN(25, "SPI0_MISO"),
- MT7986_PIN(26, "SPI0_CS"),
- MT7986_PIN(27, "SPI0_HOLD"),
- MT7986_PIN(28, "SPI0_WP"),
- MT7986_PIN(29, "SPI1_CLK"),
- MT7986_PIN(30, "SPI1_MOSI"),
- MT7986_PIN(31, "SPI1_MISO"),
- MT7986_PIN(32, "SPI1_CS"),
- MT7986_PIN(33, "SPI2_CLK"),
- MT7986_PIN(34, "SPI2_MOSI"),
- MT7986_PIN(35, "SPI2_MISO"),
- MT7986_PIN(36, "SPI2_CS"),
- MT7986_PIN(37, "SPI2_HOLD"),
- MT7986_PIN(38, "SPI2_WP"),
- MT7986_PIN(39, "UART0_RXD"),
- MT7986_PIN(40, "UART0_TXD"),
- MT7986_PIN(41, "PCIE_PERESET_N"),
- MT7986_PIN(42, "UART1_RXD"),
- MT7986_PIN(43, "UART1_TXD"),
- MT7986_PIN(44, "UART1_CTS"),
- MT7986_PIN(45, "UART1_RTS"),
- MT7986_PIN(46, "UART2_RXD"),
- MT7986_PIN(47, "UART2_TXD"),
- MT7986_PIN(48, "UART2_CTS"),
- MT7986_PIN(49, "UART2_RTS"),
- MT7986_PIN(50, "EMMC_DATA_0"),
- MT7986_PIN(51, "EMMC_DATA_1"),
- MT7986_PIN(52, "EMMC_DATA_2"),
- MT7986_PIN(53, "EMMC_DATA_3"),
- MT7986_PIN(54, "EMMC_DATA_4"),
- MT7986_PIN(55, "EMMC_DATA_5"),
- MT7986_PIN(56, "EMMC_DATA_6"),
- MT7986_PIN(57, "EMMC_DATA_7"),
- MT7986_PIN(58, "EMMC_CMD"),
- MT7986_PIN(59, "EMMC_CK"),
- MT7986_PIN(60, "EMMC_DSL"),
- MT7986_PIN(61, "EMMC_RSTB"),
- MT7986_PIN(62, "PCM_DTX"),
- MT7986_PIN(63, "PCM_DRX"),
- MT7986_PIN(64, "PCM_CLK"),
- MT7986_PIN(65, "PCM_FS"),
- MT7986_PIN(66, "MT7531_INT"),
- MT7986_PIN(67, "SMI_MDC"),
- MT7986_PIN(68, "SMI_MDIO"),
- MT7986_PIN(69, "WF0_DIG_RESETB"),
- MT7986_PIN(70, "WF0_CBA_RESETB"),
- MT7986_PIN(71, "WF0_XO_REQ"),
- MT7986_PIN(72, "WF0_TOP_CLK"),
- MT7986_PIN(73, "WF0_TOP_DATA"),
- MT7986_PIN(74, "WF0_HB1"),
- MT7986_PIN(75, "WF0_HB2"),
- MT7986_PIN(76, "WF0_HB3"),
- MT7986_PIN(77, "WF0_HB4"),
- MT7986_PIN(78, "WF0_HB0"),
- MT7986_PIN(79, "WF0_HB0_B"),
- MT7986_PIN(80, "WF0_HB5"),
- MT7986_PIN(81, "WF0_HB6"),
- MT7986_PIN(82, "WF0_HB7"),
- MT7986_PIN(83, "WF0_HB8"),
- MT7986_PIN(84, "WF0_HB9"),
- MT7986_PIN(85, "WF0_HB10"),
- MT7986_PIN(86, "WF1_DIG_RESETB"),
- MT7986_PIN(87, "WF1_CBA_RESETB"),
- MT7986_PIN(88, "WF1_XO_REQ"),
- MT7986_PIN(89, "WF1_TOP_CLK"),
- MT7986_PIN(90, "WF1_TOP_DATA"),
- MT7986_PIN(91, "WF1_HB1"),
- MT7986_PIN(92, "WF1_HB2"),
- MT7986_PIN(93, "WF1_HB3"),
- MT7986_PIN(94, "WF1_HB4"),
- MT7986_PIN(95, "WF1_HB0"),
- MT7986_PIN(96, "WF1_HB0_B"),
- MT7986_PIN(97, "WF1_HB5"),
- MT7986_PIN(98, "WF1_HB6"),
- MT7986_PIN(99, "WF1_HB7"),
- MT7986_PIN(100, "WF1_HB8"),
-};
-
-static const struct mtk_pin_desc mt7986b_pins[] = {
- MT7986_PIN(0, "SYS_WATCHDOG"),
- MT7986_PIN(1, "WF2G_LED"),
- MT7986_PIN(2, "WF5G_LED"),
- MT7986_PIN(3, "I2C_SCL"),
- MT7986_PIN(4, "I2C_SDA"),
- MT7986_PIN(5, "GPIO_0"),
- MT7986_PIN(6, "GPIO_1"),
- MT7986_PIN(7, "GPIO_2"),
- MT7986_PIN(8, "GPIO_3"),
- MT7986_PIN(9, "GPIO_4"),
- MT7986_PIN(10, "GPIO_5"),
- MT7986_PIN(11, "GPIO_6"),
- MT7986_PIN(12, "GPIO_7"),
- MT7986_PIN(13, "GPIO_8"),
- MT7986_PIN(14, "GPIO_9"),
- MT7986_PIN(15, "GPIO_10"),
- MT7986_PIN(16, "GPIO_11"),
- MT7986_PIN(17, "GPIO_12"),
- MT7986_PIN(18, "GPIO_13"),
- MT7986_PIN(19, "GPIO_14"),
- MT7986_PIN(20, "GPIO_15"),
- MT7986_PIN(21, "PWM0"),
- MT7986_PIN(22, "PWM1"),
- MT7986_PIN(23, "SPI0_CLK"),
- MT7986_PIN(24, "SPI0_MOSI"),
- MT7986_PIN(25, "SPI0_MISO"),
- MT7986_PIN(26, "SPI0_CS"),
- MT7986_PIN(27, "SPI0_HOLD"),
- MT7986_PIN(28, "SPI0_WP"),
- MT7986_PIN(29, "SPI1_CLK"),
- MT7986_PIN(30, "SPI1_MOSI"),
- MT7986_PIN(31, "SPI1_MISO"),
- MT7986_PIN(32, "SPI1_CS"),
- MT7986_PIN(33, "SPI2_CLK"),
- MT7986_PIN(34, "SPI2_MOSI"),
- MT7986_PIN(35, "SPI2_MISO"),
- MT7986_PIN(36, "SPI2_CS"),
- MT7986_PIN(37, "SPI2_HOLD"),
- MT7986_PIN(38, "SPI2_WP"),
- MT7986_PIN(39, "UART0_RXD"),
- MT7986_PIN(40, "UART0_TXD"),
- MT7986_NOT_BALLOUT_PIN(41),
- MT7986_NOT_BALLOUT_PIN(42),
- MT7986_NOT_BALLOUT_PIN(43),
- MT7986_NOT_BALLOUT_PIN(44),
- MT7986_NOT_BALLOUT_PIN(45),
- MT7986_NOT_BALLOUT_PIN(46),
- MT7986_NOT_BALLOUT_PIN(47),
- MT7986_NOT_BALLOUT_PIN(48),
- MT7986_NOT_BALLOUT_PIN(49),
- MT7986_NOT_BALLOUT_PIN(50),
- MT7986_NOT_BALLOUT_PIN(51),
- MT7986_NOT_BALLOUT_PIN(52),
- MT7986_NOT_BALLOUT_PIN(53),
- MT7986_NOT_BALLOUT_PIN(54),
- MT7986_NOT_BALLOUT_PIN(55),
- MT7986_NOT_BALLOUT_PIN(56),
- MT7986_NOT_BALLOUT_PIN(57),
- MT7986_NOT_BALLOUT_PIN(58),
- MT7986_NOT_BALLOUT_PIN(59),
- MT7986_NOT_BALLOUT_PIN(60),
- MT7986_NOT_BALLOUT_PIN(61),
- MT7986_NOT_BALLOUT_PIN(62),
- MT7986_NOT_BALLOUT_PIN(63),
- MT7986_NOT_BALLOUT_PIN(64),
- MT7986_NOT_BALLOUT_PIN(65),
- MT7986_PIN(66, "MT7531_INT"),
- MT7986_PIN(67, "SMI_MDC"),
- MT7986_PIN(68, "SMI_MDIO"),
- MT7986_PIN(69, "WF0_DIG_RESETB"),
- MT7986_PIN(70, "WF0_CBA_RESETB"),
- MT7986_PIN(71, "WF0_XO_REQ"),
- MT7986_PIN(72, "WF0_TOP_CLK"),
- MT7986_PIN(73, "WF0_TOP_DATA"),
- MT7986_PIN(74, "WF0_HB1"),
- MT7986_PIN(75, "WF0_HB2"),
- MT7986_PIN(76, "WF0_HB3"),
- MT7986_PIN(77, "WF0_HB4"),
- MT7986_PIN(78, "WF0_HB0"),
- MT7986_PIN(79, "WF0_HB0_B"),
- MT7986_PIN(80, "WF0_HB5"),
- MT7986_PIN(81, "WF0_HB6"),
- MT7986_PIN(82, "WF0_HB7"),
- MT7986_PIN(83, "WF0_HB8"),
- MT7986_PIN(84, "WF0_HB9"),
- MT7986_PIN(85, "WF0_HB10"),
- MT7986_PIN(86, "WF1_DIG_RESETB"),
- MT7986_PIN(87, "WF1_CBA_RESETB"),
- MT7986_PIN(88, "WF1_XO_REQ"),
- MT7986_PIN(89, "WF1_TOP_CLK"),
- MT7986_PIN(90, "WF1_TOP_DATA"),
- MT7986_PIN(91, "WF1_HB1"),
- MT7986_PIN(92, "WF1_HB2"),
- MT7986_PIN(93, "WF1_HB3"),
- MT7986_PIN(94, "WF1_HB4"),
- MT7986_PIN(95, "WF1_HB0"),
- MT7986_PIN(96, "WF1_HB0_B"),
- MT7986_PIN(97, "WF1_HB5"),
- MT7986_PIN(98, "WF1_HB6"),
- MT7986_PIN(99, "WF1_HB7"),
- MT7986_PIN(100, "WF1_HB8"),
-};
-
-/* List all groups consisting of these pins dedicated to the enablement of
- * certain hardware block and the corresponding mode for all of the pins.
- * The hardware probably has multiple combinations of these pinouts.
- */
-
-static int mt7986_watchdog_pins[] = { 0, };
-static int mt7986_watchdog_funcs[] = { 1, };
-
-static int mt7986_wifi_led_pins[] = { 1, 2, };
-static int mt7986_wifi_led_funcs[] = { 1, 1, };
-
-static int mt7986_i2c_pins[] = { 3, 4, };
-static int mt7986_i2c_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
-static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
-static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_pwm1_1_pins[] = { 20, };
-static int mt7986_pwm1_1_funcs[] = { 2, };
-
-static int mt7986_pwm0_pins[] = { 21, };
-static int mt7986_pwm0_funcs[] = { 1, };
-
-static int mt7986_pwm1_0_pins[] = { 22, };
-static int mt7986_pwm1_0_funcs[] = { 1, };
-
-static int mt7986_emmc_45_pins[] = {
- 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
-static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
-static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
-static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
-static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-
-static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-
-static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-
-static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
-
-static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
-static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
-static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
-
-static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
-static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
-
-static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
-static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
-
-static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
-static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
-
-static int mt7986_uart0_pins[] = { 39, 40, };
-static int mt7986_uart0_funcs[] = { 1, 1, };
-
-static int mt7986_pcie_reset_pins[] = { 41, };
-static int mt7986_pcie_reset_funcs[] = { 1, };
-
-static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
-static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-
-static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-
-static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
-static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_emmc_51_pins[] = {
- 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
-static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
-static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
-static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
-
-static int mt7986_switch_int_pins[] = { 66, };
-static int mt7986_switch_int_funcs[] = { 1, };
-
-static int mt7986_mdc_mdio_pins[] = { 67, 68, };
-static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
-
-static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
-static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
-static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
-
-static int mt7986_wf_dbdc_pins[] = {
- 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
-static int mt7986_wf_dbdc_funcs[] = {
- 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-static int mt7986_pcie_clk_pins[] = { 9, };
-static int mt7986_pcie_clk_funcs[] = { 1, };
-
-static int mt7986_pcie_wake_pins[] = { 10, };
-static int mt7986_pcie_wake_funcs[] = { 1, };
-
-static const struct group_desc mt7986_groups[] = {
- PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
- PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
- PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
- PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
- PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
- PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
- PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
- PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
- PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
- PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
- PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
- PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
- PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
- PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
- PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
- PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
- PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
- PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
- PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
- PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
- PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
- PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
- PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
- PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
- PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
- PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
- PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
- PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
- PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
- PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
- PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
- PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
- PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
- PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
- PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
- PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
- PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
- PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
- PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-
-static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
-static const char *mt7986_emmc_groups[] = {
- "emmc_45", "emmc_51", };
-static const char *mt7986_ethernet_groups[] = {
- "switch_int", "mdc_mdio", };
-static const char *mt7986_i2c_groups[] = { "i2c", };
-static const char *mt7986_led_groups[] = { "wifi_led", };
-static const char *mt7986_flash_groups[] = { "snfi", };
-static const char *mt7986_pcie_groups[] = {
- "pcie_clk", "pcie_wake", "pcie_pereset" };
-static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
-static const char *mt7986_spi_groups[] = {
- "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
-static const char *mt7986_uart_groups[] = {
- "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
- "uart1_2_rx_tx", "uart1_2_cts_rts",
- "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
- "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
-};
-static const char *mt7986_wdt_groups[] = { "watchdog", };
-static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
-
-static const struct function_desc mt7986_functions[] = {
- {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
- {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
- {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
- {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
- {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
- {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
- {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
- {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
- {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
- {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
- {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
- {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
-};
-
-static const struct mtk_eint_hw mt7986a_eint_hw = {
- .port_mask = 7,
- .ports = 7,
- .ap_num = ARRAY_SIZE(mt7986a_pins),
- .db_cnt = 16,
- .db_time = debounce_time_mt6765,
-};
-
-static const struct mtk_eint_hw mt7986b_eint_hw = {
- .port_mask = 7,
- .ports = 7,
- .ap_num = ARRAY_SIZE(mt7986b_pins),
- .db_cnt = 16,
- .db_time = debounce_time_mt6765,
-};
-
-static struct mtk_pin_soc mt7986a_data = {
- .reg_cal = mt7986_reg_cals,
- .pins = mt7986a_pins,
- .npins = ARRAY_SIZE(mt7986a_pins),
- .grps = mt7986_groups,
- .ngrps = ARRAY_SIZE(mt7986_groups),
- .funcs = mt7986_functions,
- .nfuncs = ARRAY_SIZE(mt7986_functions),
- .eint_hw = &mt7986a_eint_hw,
- .gpio_m = 0,
- .ies_present = false,
- .base_names = mt7986_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
- .pull_type = mt7986_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
- .drive_set = mtk_pinconf_drive_set_rev1,
- .drive_get = mtk_pinconf_drive_get_rev1,
- .adv_pull_get = mtk_pinconf_adv_pull_get,
- .adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static struct mtk_pin_soc mt7986b_data = {
- .reg_cal = mt7986_reg_cals,
- .pins = mt7986b_pins,
- .npins = ARRAY_SIZE(mt7986b_pins),
- .grps = mt7986_groups,
- .ngrps = ARRAY_SIZE(mt7986_groups),
- .funcs = mt7986_functions,
- .nfuncs = ARRAY_SIZE(mt7986_functions),
- .eint_hw = &mt7986b_eint_hw,
- .gpio_m = 0,
- .ies_present = false,
- .base_names = mt7986_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
- .pull_type = mt7986_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
- .drive_set = mtk_pinconf_drive_set_rev1,
- .drive_get = mtk_pinconf_drive_get_rev1,
- .adv_pull_get = mtk_pinconf_adv_pull_get,
- .adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7986a_pinctrl_of_match[] = {
- {.compatible = "mediatek,mt7986a-pinctrl",},
- {}
-};
-
-static const struct of_device_id mt7986b_pinctrl_of_match[] = {
- {.compatible = "mediatek,mt7986b-pinctrl",},
- {}
-};
-
-static int mt7986a_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
-}
-
-static int mt7986b_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
-}
-
-static struct platform_driver mt7986a_pinctrl_driver = {
- .driver = {
- .name = "mt7986a-pinctrl",
- .of_match_table = mt7986a_pinctrl_of_match,
- },
- .probe = mt7986a_pinctrl_probe,
-};
-
-static struct platform_driver mt7986b_pinctrl_driver = {
- .driver = {
- .name = "mt7986b-pinctrl",
- .of_match_table = mt7986b_pinctrl_of_match,
- },
- .probe = mt7986b_pinctrl_probe,
-};
-
-static int __init mt7986a_pinctrl_init(void)
-{
- return platform_driver_register(&mt7986a_pinctrl_driver);
-}
-
-static int __init mt7986b_pinctrl_init(void)
-{
- return platform_driver_register(&mt7986b_pinctrl_driver);
-}
-
-arch_initcall(mt7986a_pinctrl_init);
-arch_initcall(mt7986b_pinctrl_init);
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
-static const char *mt7988_jtag_groups[] = {
+static const char * const mt7988_jtag_groups[] = {
"tops_jtag0_0", "wo0_jtag", "wo1_jtag",
"wo2_jtag", "jtag", "tops_jtag0_1",
};
-static const char *mt7988_int_usxgmii_groups[] = {
+static const char * const mt7988_int_usxgmii_groups[] = {
"int_usxgmii",
};
-static const char *mt7988_pwm_groups[] = {
+static const char * const mt7988_pwm_groups[] = {
"pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7"
};
-static const char *mt7988_dfd_groups[] = {
+static const char * const mt7988_dfd_groups[] = {
"dfd",
};
-static const char *mt7988_i2c_groups[] = {
+static const char * const mt7988_i2c_groups[] = {
"xfi_phy0_i2c0",
"xfi_phy1_i2c0",
"xfi_phy_pll_i2c0",
"i2c2_0",
"i2c2_1",
};
-static const char *mt7988_ethernet_groups[] = {
+static const char * const mt7988_ethernet_groups[] = {
"mdc_mdio0",
"2p5g_ext_mdio",
"gbe_ext_mdio",
"mdc_mdio1",
};
-static const char *mt7988_pcie_groups[] = {
+static const char * const mt7988_pcie_groups[] = {
"pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0",
"pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c",
"pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c",
"pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1",
"pcie_clk_req_n0_1"
};
-static const char *mt7988_pmic_groups[] = {
+static const char * const mt7988_pmic_groups[] = {
"pmic",
};
-static const char *mt7988_wdt_groups[] = {
+static const char * const mt7988_wdt_groups[] = {
"watchdog",
};
-static const char *mt7988_spi_groups[] = {
+static const char * const mt7988_spi_groups[] = {
"spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
};
-static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
+static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
"emmc_51" };
-static const char *mt7988_uart_groups[] = {
+static const char * const mt7988_uart_groups[] = {
"uart2",
"tops_uart0_0",
"uart2_0",
"net_wo1_uart_txd_1",
"net_wo2_uart_txd_1",
};
-static const char *mt7988_udi_groups[] = {
+static const char * const mt7988_udi_groups[] = {
"udi",
};
-static const char *mt7988_audio_groups[] = {
+static const char * const mt7988_audio_groups[] = {
"i2s", "pcm",
};
-static const char *mt7988_led_groups[] = {
+static const char * const mt7988_led_groups[] = {
"gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
"gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
"wf5g_led0", "wf5g_led1",
};
-static const char *mt7988_usb_groups[] = {
+static const char * const mt7988_usb_groups[] = {
"drv_vbus",
"drv_vbus_p1",
};
.db_cnt = 16,
};
-static const char *mt7988_pinctrl_register_base_names[] = {
+static const char * const mt7988_pinctrl_register_base_names[] = {
"gpio_base", "iocfg_tr_base", "iocfg_br_base",
"iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
};
return platform_driver_register(&mt7988_pinctrl_driver);
}
arch_initcall(mt7988_pinctrl_init);
+
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7981_H
-#define _DT_BINDINGS_CLK_MT7981_H
-
-/* TOPCKGEN */
-#define CLK_TOP_CB_CKSQ_40M 0
-#define CLK_TOP_CB_M_416M 1
-#define CLK_TOP_CB_M_D2 2
-#define CLK_TOP_CB_M_D3 3
-#define CLK_TOP_M_D3_D2 4
-#define CLK_TOP_CB_M_D4 5
-#define CLK_TOP_CB_M_D8 6
-#define CLK_TOP_M_D8_D2 7
-#define CLK_TOP_CB_MM_720M 8
-#define CLK_TOP_CB_MM_D2 9
-#define CLK_TOP_CB_MM_D3 10
-#define CLK_TOP_CB_MM_D3_D5 11
-#define CLK_TOP_CB_MM_D4 12
-#define CLK_TOP_CB_MM_D6 13
-#define CLK_TOP_MM_D6_D2 14
-#define CLK_TOP_CB_MM_D8 15
-#define CLK_TOP_CB_APLL2_196M 16
-#define CLK_TOP_APLL2_D2 17
-#define CLK_TOP_APLL2_D4 18
-#define CLK_TOP_NET1_2500M 19
-#define CLK_TOP_CB_NET1_D4 20
-#define CLK_TOP_CB_NET1_D5 21
-#define CLK_TOP_NET1_D5_D2 22
-#define CLK_TOP_NET1_D5_D4 23
-#define CLK_TOP_CB_NET1_D8 24
-#define CLK_TOP_NET1_D8_D2 25
-#define CLK_TOP_NET1_D8_D4 26
-#define CLK_TOP_CB_NET2_800M 27
-#define CLK_TOP_CB_NET2_D2 28
-#define CLK_TOP_CB_NET2_D4 29
-#define CLK_TOP_NET2_D4_D2 30
-#define CLK_TOP_NET2_D4_D4 31
-#define CLK_TOP_CB_NET2_D6 32
-#define CLK_TOP_CB_WEDMCU_208M 33
-#define CLK_TOP_CB_SGM_325M 34
-#define CLK_TOP_CKSQ_40M_D2 35
-#define CLK_TOP_CB_RTC_32K 36
-#define CLK_TOP_CB_RTC_32P7K 37
-#define CLK_TOP_USB_TX250M 38
-#define CLK_TOP_FAUD 39
-#define CLK_TOP_NFI1X 40
-#define CLK_TOP_USB_EQ_RX250M 41
-#define CLK_TOP_USB_CDR_CK 42
-#define CLK_TOP_USB_LN0_CK 43
-#define CLK_TOP_SPINFI_BCK 44
-#define CLK_TOP_SPI 45
-#define CLK_TOP_SPIM_MST 46
-#define CLK_TOP_UART_BCK 47
-#define CLK_TOP_PWM_BCK 48
-#define CLK_TOP_I2C_BCK 49
-#define CLK_TOP_PEXTP_TL 50
-#define CLK_TOP_EMMC_208M 51
-#define CLK_TOP_EMMC_400M 52
-#define CLK_TOP_DRAMC_REF 53
-#define CLK_TOP_DRAMC_MD32 54
-#define CLK_TOP_SYSAXI 55
-#define CLK_TOP_SYSAPB 56
-#define CLK_TOP_ARM_DB_MAIN 57
-#define CLK_TOP_AP2CNN_HOST 58
-#define CLK_TOP_NETSYS 59
-#define CLK_TOP_NETSYS_500M 60
-#define CLK_TOP_NETSYS_WED_MCU 61
-#define CLK_TOP_NETSYS_2X 62
-#define CLK_TOP_SGM_325M 63
-#define CLK_TOP_SGM_REG 64
-#define CLK_TOP_F26M 65
-#define CLK_TOP_EIP97B 66
-#define CLK_TOP_USB3_PHY 67
-#define CLK_TOP_AUD 68
-#define CLK_TOP_A1SYS 69
-#define CLK_TOP_AUD_L 70
-#define CLK_TOP_A_TUNER 71
-#define CLK_TOP_U2U3_REF 72
-#define CLK_TOP_U2U3_SYS 73
-#define CLK_TOP_U2U3_XHCI 74
-#define CLK_TOP_USB_FRMCNT 75
-#define CLK_TOP_NFI1X_SEL 76
-#define CLK_TOP_SPINFI_SEL 77
-#define CLK_TOP_SPI_SEL 78
-#define CLK_TOP_SPIM_MST_SEL 79
-#define CLK_TOP_UART_SEL 80
-#define CLK_TOP_PWM_SEL 81
-#define CLK_TOP_I2C_SEL 82
-#define CLK_TOP_PEXTP_TL_SEL 83
-#define CLK_TOP_EMMC_208M_SEL 84
-#define CLK_TOP_EMMC_400M_SEL 85
-#define CLK_TOP_F26M_SEL 86
-#define CLK_TOP_DRAMC_SEL 87
-#define CLK_TOP_DRAMC_MD32_SEL 88
-#define CLK_TOP_SYSAXI_SEL 89
-#define CLK_TOP_SYSAPB_SEL 90
-#define CLK_TOP_ARM_DB_MAIN_SEL 91
-#define CLK_TOP_AP2CNN_HOST_SEL 92
-#define CLK_TOP_NETSYS_SEL 93
-#define CLK_TOP_NETSYS_500M_SEL 94
-#define CLK_TOP_NETSYS_MCU_SEL 95
-#define CLK_TOP_NETSYS_2X_SEL 96
-#define CLK_TOP_SGM_325M_SEL 97
-#define CLK_TOP_SGM_REG_SEL 98
-#define CLK_TOP_EIP97B_SEL 99
-#define CLK_TOP_USB3_PHY_SEL 100
-#define CLK_TOP_AUD_SEL 101
-#define CLK_TOP_A1SYS_SEL 102
-#define CLK_TOP_AUD_L_SEL 103
-#define CLK_TOP_A_TUNER_SEL 104
-#define CLK_TOP_U2U3_SEL 105
-#define CLK_TOP_U2U3_SYS_SEL 106
-#define CLK_TOP_U2U3_XHCI_SEL 107
-#define CLK_TOP_USB_FRMCNT_SEL 108
-#define CLK_TOP_AUD_I2S_M 109
-
-/* INFRACFG */
-#define CLK_INFRA_66M_MCK 0
-#define CLK_INFRA_UART0_SEL 1
-#define CLK_INFRA_UART1_SEL 2
-#define CLK_INFRA_UART2_SEL 3
-#define CLK_INFRA_SPI0_SEL 4
-#define CLK_INFRA_SPI1_SEL 5
-#define CLK_INFRA_SPI2_SEL 6
-#define CLK_INFRA_PWM1_SEL 7
-#define CLK_INFRA_PWM2_SEL 8
-#define CLK_INFRA_PWM3_SEL 9
-#define CLK_INFRA_PWM_BSEL 10
-#define CLK_INFRA_PCIE_SEL 11
-#define CLK_INFRA_GPT_STA 12
-#define CLK_INFRA_PWM_HCK 13
-#define CLK_INFRA_PWM_STA 14
-#define CLK_INFRA_PWM1_CK 15
-#define CLK_INFRA_PWM2_CK 16
-#define CLK_INFRA_PWM3_CK 17
-#define CLK_INFRA_CQ_DMA_CK 18
-#define CLK_INFRA_AUD_BUS_CK 19
-#define CLK_INFRA_AUD_26M_CK 20
-#define CLK_INFRA_AUD_L_CK 21
-#define CLK_INFRA_AUD_AUD_CK 22
-#define CLK_INFRA_AUD_EG2_CK 23
-#define CLK_INFRA_DRAMC_26M_CK 24
-#define CLK_INFRA_DBG_CK 25
-#define CLK_INFRA_AP_DMA_CK 26
-#define CLK_INFRA_SEJ_CK 27
-#define CLK_INFRA_SEJ_13M_CK 28
-#define CLK_INFRA_THERM_CK 29
-#define CLK_INFRA_I2C0_CK 30
-#define CLK_INFRA_UART0_CK 31
-#define CLK_INFRA_UART1_CK 32
-#define CLK_INFRA_UART2_CK 33
-#define CLK_INFRA_SPI2_CK 34
-#define CLK_INFRA_SPI2_HCK_CK 35
-#define CLK_INFRA_NFI1_CK 36
-#define CLK_INFRA_SPINFI1_CK 37
-#define CLK_INFRA_NFI_HCK_CK 38
-#define CLK_INFRA_SPI0_CK 39
-#define CLK_INFRA_SPI1_CK 40
-#define CLK_INFRA_SPI0_HCK_CK 41
-#define CLK_INFRA_SPI1_HCK_CK 42
-#define CLK_INFRA_FRTC_CK 43
-#define CLK_INFRA_MSDC_CK 44
-#define CLK_INFRA_MSDC_HCK_CK 45
-#define CLK_INFRA_MSDC_133M_CK 46
-#define CLK_INFRA_MSDC_66M_CK 47
-#define CLK_INFRA_ADC_26M_CK 48
-#define CLK_INFRA_ADC_FRC_CK 49
-#define CLK_INFRA_FBIST2FPC_CK 50
-#define CLK_INFRA_I2C_MCK_CK 51
-#define CLK_INFRA_I2C_PCK_CK 52
-#define CLK_INFRA_IUSB_133_CK 53
-#define CLK_INFRA_IUSB_66M_CK 54
-#define CLK_INFRA_IUSB_SYS_CK 55
-#define CLK_INFRA_IUSB_CK 56
-#define CLK_INFRA_IPCIE_CK 57
-#define CLK_INFRA_IPCIE_PIPE_CK 58
-#define CLK_INFRA_IPCIER_CK 59
-#define CLK_INFRA_IPCIEB_CK 60
-
-/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_NET2PLL 1
-#define CLK_APMIXED_MMPLL 2
-#define CLK_APMIXED_SGMPLL 3
-#define CLK_APMIXED_WEDMCUPLL 4
-#define CLK_APMIXED_NET1PLL 5
-#define CLK_APMIXED_MPLL 6
-#define CLK_APMIXED_APLL2 7
-
-/* SGMIISYS_0 */
-#define CLK_SGM0_TX_EN 0
-#define CLK_SGM0_RX_EN 1
-#define CLK_SGM0_CK0_EN 2
-#define CLK_SGM0_CDR_CK0_EN 3
-
-/* SGMIISYS_1 */
-#define CLK_SGM1_TX_EN 0
-#define CLK_SGM1_RX_EN 1
-#define CLK_SGM1_CK1_EN 2
-#define CLK_SGM1_CDR_CK1_EN 3
-
-/* ETHSYS */
-#define CLK_ETH_FE_EN 0
-#define CLK_ETH_GP2_EN 1
-#define CLK_ETH_GP1_EN 2
-#define CLK_ETH_WOCPU0_EN 3
-
-#endif /* _DT_BINDINGS_CLK_MT7981_H */
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-/*
- * Copyright (c) 2021 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_MT7986_H
-#define _DT_BINDINGS_CLK_MT7986_H
-
-/* APMIXEDSYS */
-
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_NET2PLL 1
-#define CLK_APMIXED_MMPLL 2
-#define CLK_APMIXED_SGMPLL 3
-#define CLK_APMIXED_WEDMCUPLL 4
-#define CLK_APMIXED_NET1PLL 5
-#define CLK_APMIXED_MPLL 6
-#define CLK_APMIXED_APLL2 7
-
-/* TOPCKGEN */
-
-#define CLK_TOP_XTAL 0
-#define CLK_TOP_XTAL_D2 1
-#define CLK_TOP_RTC_32K 2
-#define CLK_TOP_RTC_32P7K 3
-#define CLK_TOP_MPLL_D2 4
-#define CLK_TOP_MPLL_D4 5
-#define CLK_TOP_MPLL_D8 6
-#define CLK_TOP_MPLL_D8_D2 7
-#define CLK_TOP_MPLL_D3_D2 8
-#define CLK_TOP_MMPLL_D2 9
-#define CLK_TOP_MMPLL_D4 10
-#define CLK_TOP_MMPLL_D8 11
-#define CLK_TOP_MMPLL_D8_D2 12
-#define CLK_TOP_MMPLL_D3_D8 13
-#define CLK_TOP_MMPLL_U2PHY 14
-#define CLK_TOP_APLL2_D4 15
-#define CLK_TOP_NET1PLL_D4 16
-#define CLK_TOP_NET1PLL_D5 17
-#define CLK_TOP_NET1PLL_D5_D2 18
-#define CLK_TOP_NET1PLL_D5_D4 19
-#define CLK_TOP_NET1PLL_D8_D2 20
-#define CLK_TOP_NET1PLL_D8_D4 21
-#define CLK_TOP_NET2PLL_D4 22
-#define CLK_TOP_NET2PLL_D4_D2 23
-#define CLK_TOP_NET2PLL_D3_D2 24
-#define CLK_TOP_WEDMCUPLL_D5_D2 25
-#define CLK_TOP_NFI1X_SEL 26
-#define CLK_TOP_SPINFI_SEL 27
-#define CLK_TOP_SPI_SEL 28
-#define CLK_TOP_SPIM_MST_SEL 29
-#define CLK_TOP_UART_SEL 30
-#define CLK_TOP_PWM_SEL 31
-#define CLK_TOP_I2C_SEL 32
-#define CLK_TOP_PEXTP_TL_SEL 33
-#define CLK_TOP_EMMC_250M_SEL 34
-#define CLK_TOP_EMMC_416M_SEL 35
-#define CLK_TOP_F_26M_ADC_SEL 36
-#define CLK_TOP_DRAMC_SEL 37
-#define CLK_TOP_DRAMC_MD32_SEL 38
-#define CLK_TOP_SYSAXI_SEL 39
-#define CLK_TOP_SYSAPB_SEL 40
-#define CLK_TOP_ARM_DB_MAIN_SEL 41
-#define CLK_TOP_ARM_DB_JTSEL 42
-#define CLK_TOP_NETSYS_SEL 43
-#define CLK_TOP_NETSYS_500M_SEL 44
-#define CLK_TOP_NETSYS_MCU_SEL 45
-#define CLK_TOP_NETSYS_2X_SEL 46
-#define CLK_TOP_SGM_325M_SEL 47
-#define CLK_TOP_SGM_REG_SEL 48
-#define CLK_TOP_A1SYS_SEL 49
-#define CLK_TOP_CONN_MCUSYS_SEL 50
-#define CLK_TOP_EIP_B_SEL 51
-#define CLK_TOP_PCIE_PHY_SEL 52
-#define CLK_TOP_USB3_PHY_SEL 53
-#define CLK_TOP_F26M_SEL 54
-#define CLK_TOP_AUD_L_SEL 55
-#define CLK_TOP_A_TUNER_SEL 56
-#define CLK_TOP_U2U3_SEL 57
-#define CLK_TOP_U2U3_SYS_SEL 58
-#define CLK_TOP_U2U3_XHCI_SEL 59
-#define CLK_TOP_DA_U2_REFSEL 60
-#define CLK_TOP_DA_U2_CK_1P_SEL 61
-#define CLK_TOP_AP2CNN_HOST_SEL 62
-#define CLK_TOP_JTAG 63
-
-/* INFRACFG */
-
-#define CLK_INFRA_SYSAXI_D2 0
-#define CLK_INFRA_UART0_SEL 1
-#define CLK_INFRA_UART1_SEL 2
-#define CLK_INFRA_UART2_SEL 3
-#define CLK_INFRA_SPI0_SEL 4
-#define CLK_INFRA_SPI1_SEL 5
-#define CLK_INFRA_PWM1_SEL 6
-#define CLK_INFRA_PWM2_SEL 7
-#define CLK_INFRA_PWM_BSEL 8
-#define CLK_INFRA_PCIE_SEL 9
-#define CLK_INFRA_GPT_STA 10
-#define CLK_INFRA_PWM_HCK 11
-#define CLK_INFRA_PWM_STA 12
-#define CLK_INFRA_PWM1_CK 13
-#define CLK_INFRA_PWM2_CK 14
-#define CLK_INFRA_CQ_DMA_CK 15
-#define CLK_INFRA_EIP97_CK 16
-#define CLK_INFRA_AUD_BUS_CK 17
-#define CLK_INFRA_AUD_26M_CK 18
-#define CLK_INFRA_AUD_L_CK 19
-#define CLK_INFRA_AUD_AUD_CK 20
-#define CLK_INFRA_AUD_EG2_CK 21
-#define CLK_INFRA_DRAMC_26M_CK 22
-#define CLK_INFRA_DBG_CK 23
-#define CLK_INFRA_AP_DMA_CK 24
-#define CLK_INFRA_SEJ_CK 25
-#define CLK_INFRA_SEJ_13M_CK 26
-#define CLK_INFRA_THERM_CK 27
-#define CLK_INFRA_I2C0_CK 28
-#define CLK_INFRA_UART0_CK 29
-#define CLK_INFRA_UART1_CK 30
-#define CLK_INFRA_UART2_CK 31
-#define CLK_INFRA_NFI1_CK 32
-#define CLK_INFRA_SPINFI1_CK 33
-#define CLK_INFRA_NFI_HCK_CK 34
-#define CLK_INFRA_SPI0_CK 35
-#define CLK_INFRA_SPI1_CK 36
-#define CLK_INFRA_SPI0_HCK_CK 37
-#define CLK_INFRA_SPI1_HCK_CK 38
-#define CLK_INFRA_FRTC_CK 39
-#define CLK_INFRA_MSDC_CK 40
-#define CLK_INFRA_MSDC_HCK_CK 41
-#define CLK_INFRA_MSDC_133M_CK 42
-#define CLK_INFRA_MSDC_66M_CK 43
-#define CLK_INFRA_ADC_26M_CK 44
-#define CLK_INFRA_ADC_FRC_CK 45
-#define CLK_INFRA_FBIST2FPC_CK 46
-#define CLK_INFRA_IUSB_133_CK 47
-#define CLK_INFRA_IUSB_66M_CK 48
-#define CLK_INFRA_IUSB_SYS_CK 49
-#define CLK_INFRA_IUSB_CK 50
-#define CLK_INFRA_IPCIE_CK 51
-#define CLK_INFRA_IPCIE_PIPE_CK 52
-#define CLK_INFRA_IPCIER_CK 53
-#define CLK_INFRA_IPCIEB_CK 54
-#define CLK_INFRA_TRNG_CK 55
-
-/* SGMIISYS_0 */
-
-#define CLK_SGMII0_TX250M_EN 0
-#define CLK_SGMII0_RX250M_EN 1
-#define CLK_SGMII0_CDR_REF 2
-#define CLK_SGMII0_CDR_FB 3
-
-/* SGMIISYS_1 */
-
-#define CLK_SGMII1_TX250M_EN 0
-#define CLK_SGMII1_RX250M_EN 1
-#define CLK_SGMII1_CDR_REF 2
-#define CLK_SGMII1_CDR_FB 3
-
-/* ETHSYS */
-
-#define CLK_ETH_FE_EN 0
-#define CLK_ETH_GP2_EN 1
-#define CLK_ETH_GP1_EN 2
-#define CLK_ETH_WOCPU1_EN 3
-#define CLK_ETH_WOCPU0_EN 4
-
-#endif /* _DT_BINDINGS_CLK_MT7986_H */
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-/*
- * Copyright (c) 2022 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
-#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
-
-/* INFRACFG resets */
-#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6
-#define MT7986_INFRACFG_SSUSB_SW_RST 7
-#define MT7986_INFRACFG_EIP97_SW_RST 8
-#define MT7986_INFRACFG_AUDIO_SW_RST 13
-#define MT7986_INFRACFG_CQ_DMA_SW_RST 14
-
-#define MT7986_INFRACFG_TRNG_SW_RST 17
-#define MT7986_INFRACFG_AP_DMA_SW_RST 32
-#define MT7986_INFRACFG_I2C_SW_RST 33
-#define MT7986_INFRACFG_NFI_SW_RST 34
-#define MT7986_INFRACFG_SPI0_SW_RST 35
-#define MT7986_INFRACFG_SPI1_SW_RST 36
-#define MT7986_INFRACFG_UART0_SW_RST 37
-#define MT7986_INFRACFG_UART1_SW_RST 38
-#define MT7986_INFRACFG_UART2_SW_RST 39
-#define MT7986_INFRACFG_AUXADC_SW_RST 43
-
-#define MT7986_INFRACFG_APXGPT_SW_RST 66
-#define MT7986_INFRACFG_PWM_SW_RST 68
-
-#define MT7986_INFRACFG_SW_RST_NUM 69
-
-/* TOPRGU resets */
-#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0
-#define MT7986_TOPRGU_SGMII0_SW_RST 1
-#define MT7986_TOPRGU_SGMII1_SW_RST 2
-#define MT7986_TOPRGU_INFRA_SW_RST 3
-#define MT7986_TOPRGU_U2PHY_SW_RST 5
-#define MT7986_TOPRGU_PCIE_SW_RST 6
-#define MT7986_TOPRGU_SSUSB_SW_RST 7
-#define MT7986_TOPRGU_ETHDMA_SW_RST 20
-#define MT7986_TOPRGU_CONSYS_SW_RST 23
-
-#define MT7986_TOPRGU_SW_RST_NUM 24
-
-/* ETHSYS Subsystem resets */
-#define MT7986_ETHSYS_FE_SW_RST 6
-#define MT7986_ETHSYS_PMTR_SW_RST 8
-#define MT7986_ETHSYS_GMAC_SW_RST 23
-#define MT7986_ETHSYS_PPE0_SW_RST 30
-#define MT7986_ETHSYS_PPE1_SW_RST 31
-
-#define MT7986_ETHSYS_SW_RST_NUM 32
-
-#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
--- /dev/null
+From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001
+From: Andrew Davis <afd@ti.com>
+Date: Mon, 24 Oct 2022 12:34:28 -0500
+Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source
+ files
+
+Currently DTB Overlays (.dtbo) are build from source files with the same
+extension (.dts) as the base DTs (.dtb). This may become confusing and
+even lead to wrong results. For example, a composite DTB (created from a
+base DTB and a set of overlays) might have the same name as one of the
+overlays that create it.
+
+Different files should be generated from differently named sources.
+ .dtb <-> .dts
+ .dtbo <-> .dtso
+
+We do not remove the ability to compile DTBO files from .dts files here,
+only add a new rule allowing the .dtso file name. The current .dts named
+overlays can be renamed with time. After all have been renamed we can
+remove the other rule.
+
+Signed-off-by: Andrew Davis <afd@ti.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Frank Rowand <frowand.list@gmail.com>
+Tested-by: Frank Rowand <frowand.list@gmail.com>
+Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com
+Signed-off-by: Rob Herring <robh@kernel.org>
+---
+ scripts/Makefile.lib | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T
+ $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
+ $(call if_changed_dep,dtc)
+
++$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
++ $(call if_changed_dep,dtc)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+
+ # Bzip2
--- /dev/null
+From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sat, 5 Nov 2022 23:36:16 +0100
+Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
+ Wireless Ethernet Dispatch
+
+Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
+Dispatch to offload traffic received by the wlan interface to lan/wan
+one.
+
+Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -76,6 +76,47 @@
+ no-map;
+ reg = <0 0x4fc00000 0 0x00100000>;
+ };
++
++ wo_emi0: wo-emi@4fd00000 {
++ reg = <0 0x4fd00000 0 0x40000>;
++ no-map;
++ };
++
++ wo_emi1: wo-emi@4fd40000 {
++ reg = <0 0x4fd40000 0 0x40000>;
++ no-map;
++ };
++
++ wo_ilm0: wo-ilm@151e0000 {
++ reg = <0 0x151e0000 0 0x8000>;
++ no-map;
++ };
++
++ wo_ilm1: wo-ilm@151f0000 {
++ reg = <0 0x151f0000 0 0x8000>;
++ no-map;
++ };
++
++ wo_data: wo-data@4fd80000 {
++ reg = <0 0x4fd80000 0 0x240000>;
++ no-map;
++ };
++
++ wo_dlm0: wo-dlm@151e8000 {
++ reg = <0 0x151e8000 0 0x2000>;
++ no-map;
++ };
++
++ wo_dlm1: wo-dlm@151f8000 {
++ reg = <0 0x151f8000 0 0x2000>;
++ no-map;
++ };
++
++ wo_boot: wo-boot@15194000 {
++ reg = <0 0x15194000 0 0x1000>;
++ no-map;
++ };
++
+ };
+
+ timer {
+@@ -239,6 +280,11 @@
+ reg = <0 0x15010000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
++ <&wo_data>, <&wo_boot>;
++ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
++ "wo-data", "wo-boot";
++ mediatek,wo-ccif = <&wo_ccif0>;
+ };
+
+ wed1: wed@15011000 {
+@@ -247,6 +293,25 @@
+ reg = <0 0x15011000 0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
++ <&wo_data>, <&wo_boot>;
++ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
++ "wo-data", "wo-boot";
++ mediatek,wo-ccif = <&wo_ccif1>;
++ };
++
++ wo_ccif0: syscon@151a5000 {
++ compatible = "mediatek,mt7986-wo-ccif", "syscon";
++ reg = <0 0x151a5000 0 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ wo_ccif1: syscon@151ad000 {
++ compatible = "mediatek,mt7986-wo-ccif", "syscon";
++ reg = <0 0x151ad000 0 0x1000>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ eth: ethernet@15100000 {
--- /dev/null
+From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 6 Nov 2022 09:50:24 +0100
+Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order
+
+This arrange device tree nodes in alphabetical order.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++----------
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++---
+ 2 files changed, 58 insertions(+), 58 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -54,6 +54,53 @@
+ };
+ };
+
++&pio {
++ uart1_pins: uart1-pins {
++ mux {
++ function = "uart";
++ groups = "uart1";
++ };
++ };
++
++ uart2_pins: uart2-pins {
++ mux {
++ function = "uart";
++ groups = "uart2";
++ };
++ };
++
++ wf_2g_5g_pins: wf-2g-5g-pins {
++ mux {
++ function = "wifi";
++ groups = "wf_2g", "wf_5g";
++ };
++ conf {
++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++ "WF1_TOP_CLK", "WF1_TOP_DATA";
++ drive-strength = <4>;
++ };
++ };
++
++ wf_dbdc_pins: wf-dbdc-pins {
++ mux {
++ function = "wifi";
++ groups = "wf_dbdc";
++ };
++ conf {
++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++ "WF0_TOP_CLK", "WF0_TOP_DATA";
++ drive-strength = <4>;
++ };
++ };
++};
++
+ &switch {
+ ports {
+ #address-cells = <1>;
+@@ -121,50 +168,3 @@
+ pinctrl-0 = <&wf_2g_5g_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>;
+ };
+-
+-&pio {
+- uart1_pins: uart1-pins {
+- mux {
+- function = "uart";
+- groups = "uart1";
+- };
+- };
+-
+- uart2_pins: uart2-pins {
+- mux {
+- function = "uart";
+- groups = "uart2";
+- };
+- };
+-
+- wf_2g_5g_pins: wf-2g-5g-pins {
+- mux {
+- function = "wifi";
+- groups = "wf_2g", "wf_5g";
+- };
+- conf {
+- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+- "WF1_TOP_CLK", "WF1_TOP_DATA";
+- drive-strength = <4>;
+- };
+- };
+-
+- wf_dbdc_pins: wf-dbdc-pins {
+- mux {
+- function = "wifi";
+- groups = "wf_dbdc";
+- };
+- conf {
+- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+- "WF0_TOP_CLK", "WF0_TOP_DATA";
+- drive-strength = <4>;
+- };
+- };
+-};
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -25,10 +25,6 @@
+ };
+ };
+
+-&uart0 {
+- status = "okay";
+-};
+-
+ ð {
+ status = "okay";
+
+@@ -99,13 +95,6 @@
+ };
+ };
+
+-&wifi {
+- status = "okay";
+- pinctrl-names = "default", "dbdc";
+- pinctrl-0 = <&wf_2g_5g_pins>;
+- pinctrl-1 = <&wf_dbdc_pins>;
+-};
+-
+ &pio {
+ wf_2g_5g_pins: wf-2g-5g-pins {
+ mux {
+@@ -138,3 +127,14 @@
+ };
+ };
+ };
++
++&uart0 {
++ status = "okay";
++};
++
++&wifi {
++ status = "okay";
++ pinctrl-names = "default", "dbdc";
++ pinctrl-0 = <&wf_2g_5g_pins>;
++ pinctrl-1 = <&wf_dbdc_pins>;
++};
--- /dev/null
+From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 6 Nov 2022 09:50:27 +0100
+Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes
+
+This patch adds crypto engine support for MT7986.
+
+Signed-off-by: Vic Wu <vic.wu@mediatek.com>
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++
+ 3 files changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -25,6 +25,10 @@
+ };
+ };
+
++&crypto {
++ status = "okay";
++};
++
+ ð {
+ status = "okay";
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -223,6 +223,21 @@
+ status = "disabled";
+ };
+
++ crypto: crypto@10320000 {
++ compatible = "inside-secure,safexcel-eip97";
++ reg = <0 0x10320000 0 0x40000>;
++ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "ring0", "ring1", "ring2", "ring3";
++ clocks = <&infracfg CLK_INFRA_EIP97_CK>;
++ clock-names = "infra_eip97_ck";
++ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
++ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
++ status = "disabled";
++ };
++
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -25,6 +25,10 @@
+ };
+ };
+
++&crypto {
++ status = "okay";
++};
++
+ ð {
+ status = "okay";
+
--- /dev/null
+From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 6 Nov 2022 09:50:29 +0100
+Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node
+
+Add i2c Node to mt7986 devicetree.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -279,6 +279,20 @@
+ status = "disabled";
+ };
+
++ i2c0: i2c@11008000 {
++ compatible = "mediatek,mt7986-i2c";
++ reg = <0 0x11008000 0 0x90>,
++ <0 0x10217080 0 0x80>;
++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++ clock-div = <5>;
++ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
++ <&infracfg CLK_INFRA_AP_DMA_CK>;
++ clock-names = "main", "dma";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ ethsys: syscon@15000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
--- /dev/null
+From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001
+From: Matthias Brugger <mbrugger@suse.com>
+Date: Mon, 14 Nov 2022 13:16:53 +0100
+Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible
+
+Missing SoC compatible in the board file causes dt bindings check.
+
+Signed-off-by: Matthias Brugger <mbrugger@suse.com>
+Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++
+ 4 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -9,7 +9,7 @@
+
+ / {
+ model = "MediaTek MT7986a RFB";
+- compatible = "mediatek,mt7986a-rfb";
++ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
+
+ aliases {
+ serial0 = &uart0;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/reset/mt7986-resets.h>
+
+ / {
++ compatible = "mediatek,mt7986a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -9,7 +9,7 @@
+
+ / {
+ model = "MediaTek MT7986b RFB";
+- compatible = "mediatek,mt7986b-rfb";
++ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
+
+ aliases {
+ serial0 = &uart0;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+@@ -5,6 +5,9 @@
+ */
+
+ #include "mt7986a.dtsi"
++/ {
++ compatible = "mediatek,mt7986b";
++};
+
+ &pio {
+ compatible = "mediatek,mt7986b-pinctrl";
--- /dev/null
+From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 18 Nov 2022 20:01:21 +0100
+Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
+
+This patch adds spi support for MT7986.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
+ 3 files changed, 98 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -59,6 +59,20 @@
+ };
+
+ &pio {
++ spi_flash_pins: spi-flash-pins {
++ mux {
++ function = "spi";
++ groups = "spi0", "spi0_wp_hold";
++ };
++ };
++
++ spic_pins: spic-pins {
++ mux {
++ function = "spi";
++ groups = "spi1_2";
++ };
++ };
++
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+@@ -105,6 +119,27 @@
+ };
+ };
+
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi_flash_pins>;
++ cs-gpios = <0>, <0>;
++ status = "okay";
++ spi_nand: spi_nand@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++ spi-tx-buswidth = <4>;
++ spi-rx-buswidth = <4>;
++ };
++};
++
++&spi1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spic_pins>;
++ cs-gpios = <0>, <0>;
++ status = "okay";
++};
++
+ &switch {
+ ports {
+ #address-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -294,6 +294,34 @@
+ status = "disabled";
+ };
+
++ spi0: spi@1100a000 {
++ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0 0x1100a000 0 0x100>;
++ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&topckgen CLK_TOP_MPLL_D2>,
++ <&topckgen CLK_TOP_SPI_SEL>,
++ <&infracfg CLK_INFRA_SPI0_CK>,
++ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
++ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
++ status = "disabled";
++ };
++
++ spi1: spi@1100b000 {
++ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0 0x1100b000 0 0x100>;
++ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&topckgen CLK_TOP_MPLL_D2>,
++ <&topckgen CLK_TOP_SPIM_MST_SEL>,
++ <&infracfg CLK_INFRA_SPI1_CK>,
++ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
++ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
++ status = "disabled";
++ };
++
+ ethsys: syscon@15000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -100,6 +100,20 @@
+ };
+
+ &pio {
++ spi_flash_pins: spi-flash-pins {
++ mux {
++ function = "spi";
++ groups = "spi0", "spi0_wp_hold";
++ };
++ };
++
++ spic_pins: spic-pins {
++ mux {
++ function = "spi";
++ groups = "spi1_2";
++ };
++ };
++
+ wf_2g_5g_pins: wf-2g-5g-pins {
+ mux {
+ function = "wifi";
+@@ -132,6 +146,27 @@
+ };
+ };
+
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi_flash_pins>;
++ cs-gpios = <0>, <0>;
++ status = "okay";
++ spi_nand: spi_nand@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++ spi-tx-buswidth = <4>;
++ spi-rx-buswidth = <4>;
++ };
++};
++
++&spi1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spic_pins>;
++ cs-gpios = <0>, <0>;
++ status = "okay";
++};
++
+ &uart0 {
+ status = "okay";
+ };
--- /dev/null
+From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 6 Jan 2023 16:28:42 +0100
+Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes
+
+This patch adds USB support for MT7986.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
+Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++
+ 3 files changed, 71 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -140,6 +140,10 @@
+ status = "okay";
+ };
+
++&ssusb {
++ status = "okay";
++};
++
+ &switch {
+ ports {
+ #address-cells = <1>;
+@@ -201,6 +205,10 @@
+ status = "okay";
+ };
+
++&usb_phy {
++ status = "okay";
++};
++
+ &wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -322,6 +322,61 @@
+ status = "disabled";
+ };
+
++ ssusb: usb@11200000 {
++ compatible = "mediatek,mt7986-xhci",
++ "mediatek,mtk-xhci";
++ reg = <0 0x11200000 0 0x2e00>,
++ <0 0x11203e00 0 0x0100>;
++ reg-names = "mac", "ippc";
++ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
++ <&infracfg CLK_INFRA_IUSB_CK>,
++ <&infracfg CLK_INFRA_IUSB_133_CK>,
++ <&infracfg CLK_INFRA_IUSB_66M_CK>,
++ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
++ clock-names = "sys_ck",
++ "ref_ck",
++ "mcu_ck",
++ "dma_ck",
++ "xhci_ck";
++ phys = <&u2port0 PHY_TYPE_USB2>,
++ <&u3port0 PHY_TYPE_USB3>,
++ <&u2port1 PHY_TYPE_USB2>;
++ status = "disabled";
++ };
++
++ usb_phy: t-phy@11e10000 {
++ compatible = "mediatek,mt7986-tphy",
++ "mediatek,generic-tphy-v2";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0 0x11e10000 0x1700>;
++ status = "disabled";
++
++ u2port0: usb-phy@0 {
++ reg = <0x0 0x700>;
++ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
++ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
++ clock-names = "ref", "da_ref";
++ #phy-cells = <1>;
++ };
++
++ u3port0: usb-phy@700 {
++ reg = <0x700 0x900>;
++ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
++ clock-names = "ref";
++ #phy-cells = <1>;
++ };
++
++ u2port1: usb-phy@1000 {
++ reg = <0x1000 0x700>;
++ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
++ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
++ clock-names = "ref", "da_ref";
++ #phy-cells = <1>;
++ };
++ };
++
+ ethsys: syscon@15000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -167,10 +167,18 @@
+ status = "okay";
+ };
+
++&ssusb {
++ status = "okay";
++};
++
+ &uart0 {
+ status = "okay";
+ };
+
++&usb_phy {
++ status = "okay";
++};
++
+ &wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
--- /dev/null
+From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 6 Jan 2023 16:28:43 +0100
+Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes
+
+This patch adds mmc support for MT7986.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++
+ 2 files changed, 111 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -5,6 +5,8 @@
+ */
+
+ /dts-v1/;
++#include <dt-bindings/pinctrl/mt65xx.h>
++
+ #include "mt7986a.dtsi"
+
+ / {
+@@ -23,6 +25,24 @@
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
++
++ reg_1p8v: regulator-1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed-1.8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed-3.3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
+ };
+
+ &crypto {
+@@ -58,7 +78,83 @@
+ };
+ };
+
++&mmc0 {
++ pinctrl-names = "default", "state_uhs";
++ pinctrl-0 = <&mmc0_pins_default>;
++ pinctrl-1 = <&mmc0_pins_uhs>;
++ bus-width = <8>;
++ max-frequency = <200000000>;
++ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ hs400-ds-delay = <0x14014>;
++ vmmc-supply = <®_3p3v>;
++ vqmmc-supply = <®_1p8v>;
++ non-removable;
++ no-sd;
++ no-sdio;
++ status = "okay";
++};
++
+ &pio {
++ mmc0_pins_default: mmc0-pins {
++ mux {
++ function = "emmc";
++ groups = "emmc_51";
++ };
++ conf-cmd-dat {
++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++ input-enable;
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ conf-clk {
++ pins = "EMMC_CK";
++ drive-strength = <6>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-ds {
++ pins = "EMMC_DSL";
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-rst {
++ pins = "EMMC_RSTB";
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ };
++
++ mmc0_pins_uhs: mmc0-uhs-pins {
++ mux {
++ function = "emmc";
++ groups = "emmc_51";
++ };
++ conf-cmd-dat {
++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++ input-enable;
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ conf-clk {
++ pins = "EMMC_CK";
++ drive-strength = <6>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-ds {
++ pins = "EMMC_DSL";
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-rst {
++ pins = "EMMC_RSTB";
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ };
++
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -345,6 +345,21 @@
+ status = "disabled";
+ };
+
++ mmc0: mmc@11230000 {
++ compatible = "mediatek,mt7986-mmc";
++ reg = <0 0x11230000 0 0x1000>,
++ <0 0x11c20000 0 0x1000>;
++ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
++ <&infracfg CLK_INFRA_MSDC_HCK_CK>,
++ <&infracfg CLK_INFRA_MSDC_CK>,
++ <&infracfg CLK_INFRA_MSDC_133M_CK>,
++ <&infracfg CLK_INFRA_MSDC_66M_CK>;
++ clock-names = "source", "hclk", "source_cg", "bus_clk",
++ "sys_cg";
++ status = "disabled";
++ };
++
+ usb_phy: t-phy@11e10000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
--- /dev/null
+From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 6 Jan 2023 16:28:44 +0100
+Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
+
+This patch adds PCIe support for MT7986.
+
+Signed-off-by: Jieyy Yang <jieyy.yang@mediatek.com>
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++
+ 2 files changed, 68 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -93,6 +93,15 @@
+ non-removable;
+ no-sd;
+ no-sdio;
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_pins>;
++ status = "okay";
++};
++
++&pcie_phy {
+ status = "okay";
+ };
+
+@@ -155,6 +164,13 @@
+ };
+ };
+
++ pcie_pins: pcie-pins {
++ mux {
++ function = "pcie";
++ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
++ };
++ };
++
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt7986-clk.h>
+ #include <dt-bindings/reset/mt7986-resets.h>
++#include <dt-bindings/phy/phy.h>
+
+ / {
+ compatible = "mediatek,mt7986a";
+@@ -360,6 +361,57 @@
+ status = "disabled";
+ };
+
++ pcie: pcie@11280000 {
++ compatible = "mediatek,mt7986-pcie",
++ "mediatek,mt8192-pcie";
++ device_type = "pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ reg = <0x00 0x11280000 0x00 0x4000>;
++ reg-names = "pcie-mac";
++ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++ bus-range = <0x00 0xff>;
++ ranges = <0x82000000 0x00 0x20000000 0x00
++ 0x20000000 0x00 0x10000000>;
++ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
++ <&infracfg CLK_INFRA_IPCIE_CK>,
++ <&infracfg CLK_INFRA_IPCIER_CK>,
++ <&infracfg CLK_INFRA_IPCIEB_CK>;
++ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
++ status = "disabled";
++
++ phys = <&pcie_port PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &pcie_intc 0>,
++ <0 0 0 2 &pcie_intc 1>,
++ <0 0 0 3 &pcie_intc 2>,
++ <0 0 0 4 &pcie_intc 3>;
++ pcie_intc: interrupt-controller {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ };
++ };
++
++ pcie_phy: t-phy@11c00000 {
++ compatible = "mediatek,mt7986-tphy",
++ "mediatek,generic-tphy-v2";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ status = "disabled";
++
++ pcie_port: pcie-phy@11c00000 {
++ reg = <0 0x11c00000 0 0x20000>;
++ clocks = <&clk40m>;
++ clock-names = "ref";
++ #phy-cells = <1>;
++ };
++ };
++
+ usb_phy: t-phy@11e10000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
--- /dev/null
+From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 6 Jan 2023 16:28:45 +0100
+Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
+
+Add support for Bananapi R3 SBC.
+
+- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
+- SPI-NAND/NOR support (switched CS by sw5/C)
+- all rj45 ports and both SFP working (eth1/lan4)
+- all USB-Ports + SIM-Slot tested
+- i2c and all uarts tested
+- wifi tested (with eeprom calibration data)
+
+The device can boot from all 4 storage options. Both, SPI and MMC, can
+be switched using hardware switches on the board, see
+https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/Makefile | 5 +
+ .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++
+ .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++
+ .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++
+ .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 +
+ .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++
+ 6 files changed, 630 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+
+--- a/arch/arm64/boot/dts/mediatek/Makefile
++++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Author: Sam.Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++ fragment@0 {
++ target-path = "/soc/mmc@11230000";
++ __overlay__ {
++ bus-width = <8>;
++ max-frequency = <200000000>;
++ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
++ mmc-hs400-1_8v;
++ hs400-ds-delay = <0x14014>;
++ non-removable;
++ no-sd;
++ no-sdio;
++ status = "okay";
++ };
++ };
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -0,0 +1,55 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Authors: Daniel Golle <daniel@makrotopia.org>
++ * Frank Wunderlich <frank-w@public-files.de>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++ fragment@0 {
++ target-path = "/soc/spi@1100a000";
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ spi_nand: spi_nand@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++ spi-tx-buswidth = <4>;
++ spi-rx-buswidth = <4>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "bl2";
++ reg = <0x0 0x80000>;
++ read-only;
++ };
++
++ partition@80000 {
++ label = "reserved";
++ reg = <0x80000 0x300000>;
++ };
++
++ partition@380000 {
++ label = "fip";
++ reg = <0x380000 0x200000>;
++ read-only;
++ };
++
++ partition@580000 {
++ label = "ubi";
++ reg = <0x580000 0x7a80000>;
++ };
++ };
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -0,0 +1,68 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Authors: Daniel Golle <daniel@makrotopia.org>
++ * Frank Wunderlich <frank-w@public-files.de>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++ fragment@0 {
++ target-path = "/soc/spi@1100a000";
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "bl2";
++ reg = <0x0 0x20000>;
++ read-only;
++ };
++
++ partition@20000 {
++ label = "reserved";
++ reg = <0x20000 0x20000>;
++ };
++
++ partition@40000 {
++ label = "u-boot-env";
++ reg = <0x40000 0x40000>;
++ };
++
++ partition@80000 {
++ label = "reserved2";
++ reg = <0x80000 0x80000>;
++ };
++
++ partition@100000 {
++ label = "fip";
++ reg = <0x100000 0x80000>;
++ read-only;
++ };
++
++ partition@180000 {
++ label = "recovery";
++ reg = <0x180000 0xa80000>;
++ };
++
++ partition@c00000 {
++ label = "fit";
++ reg = <0xc00000 0x1400000>;
++ };
++ };
++ };
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -0,0 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Author: Sam.Shih <sam.shih@mediatek.com>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++ fragment@0 {
++ target-path = "/soc/mmc@11230000";
++ __overlay__ {
++ bus-width = <4>;
++ max-frequency = <52000000>;
++ cap-sd-highspeed;
++ status = "okay";
++ };
++ };
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -0,0 +1,450 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Authors: Sam.Shih <sam.shih@mediatek.com>
++ * Frank Wunderlich <frank-w@public-files.de>
++ * Daniel Golle <daniel@makrotopia.org>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/mt65xx.h>
++
++#include "mt7986a.dtsi"
++
++/ {
++ model = "Bananapi BPI-R3";
++ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++ aliases {
++ serial0 = &uart0;
++ ethernet0 = &gmac0;
++ ethernet1 = &gmac1;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ dcin: regulator-12vd {
++ compatible = "regulator-fixed";
++ regulator-name = "12vd";
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++
++ reset-key {
++ label = "reset";
++ linux,code = <KEY_RESTART>;
++ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
++ };
++
++ wps-key {
++ label = "wps";
++ linux,code = <KEY_WPS_BUTTON>;
++ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ /* i2c of the left SFP cage (wan) */
++ i2c_sfp1: i2c-gpio-0 {
++ compatible = "i2c-gpio";
++ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++ i2c-gpio,delay-us = <2>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ /* i2c of the right SFP cage (lan) */
++ i2c_sfp2: i2c-gpio-1 {
++ compatible = "i2c-gpio";
++ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++ i2c-gpio,delay-us = <2>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ green_led: led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_POWER;
++ gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++
++ blue_led: led-1 {
++ color = <LED_COLOR_ID_BLUE>;
++ function = LED_FUNCTION_STATUS;
++ gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
++ default-state = "off";
++ };
++ };
++
++ reg_1p8v: regulator-1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "1.8vd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-boot-on;
++ regulator-always-on;
++ vin-supply = <&dcin>;
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3.3vd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ vin-supply = <&dcin>;
++ };
++
++ /* left SFP cage (wan) */
++ sfp1: sfp-1 {
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c_sfp1>;
++ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
++ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
++ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
++ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
++ };
++
++ /* right SFP cage (lan) */
++ sfp2: sfp-2 {
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c_sfp2>;
++ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
++ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
++ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
++ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&crypto {
++ status = "okay";
++};
++
++ð {
++ status = "okay";
++
++ gmac0: mac@0 {
++ compatible = "mediatek,eth-mac";
++ reg = <0>;
++ phy-mode = "2500base-x";
++
++ fixed-link {
++ speed = <2500>;
++ full-duplex;
++ pause;
++ };
++ };
++
++ gmac1: mac@1 {
++ compatible = "mediatek,eth-mac";
++ reg = <1>;
++ phy-mode = "2500base-x";
++ sfp = <&sfp1>;
++ managed = "in-band-status";
++ };
++
++ mdio: mdio-bus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++};
++
++&mdio {
++ switch: switch@31 {
++ compatible = "mediatek,mt7531";
++ reg = <31>;
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&pio>;
++ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
++ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&mmc0 {
++ pinctrl-names = "default", "state_uhs";
++ pinctrl-0 = <&mmc0_pins_default>;
++ pinctrl-1 = <&mmc0_pins_uhs>;
++ vmmc-supply = <®_3p3v>;
++ vqmmc-supply = <®_1p8v>;
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c_pins>;
++ status = "okay";
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_pins>;
++ status = "okay";
++};
++
++&pcie_phy {
++ status = "okay";
++};
++
++&pio {
++ i2c_pins: i2c-pins {
++ mux {
++ function = "i2c";
++ groups = "i2c";
++ };
++ };
++
++ mmc0_pins_default: mmc0-pins {
++ mux {
++ function = "emmc";
++ groups = "emmc_51";
++ };
++ conf-cmd-dat {
++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++ input-enable;
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ conf-clk {
++ pins = "EMMC_CK";
++ drive-strength = <6>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-ds {
++ pins = "EMMC_DSL";
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-rst {
++ pins = "EMMC_RSTB";
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ };
++
++ mmc0_pins_uhs: mmc0-uhs-pins {
++ mux {
++ function = "emmc";
++ groups = "emmc_51";
++ };
++ conf-cmd-dat {
++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++ input-enable;
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ conf-clk {
++ pins = "EMMC_CK";
++ drive-strength = <6>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-ds {
++ pins = "EMMC_DSL";
++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++ };
++ conf-rst {
++ pins = "EMMC_RSTB";
++ drive-strength = <4>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++ };
++ };
++
++ pcie_pins: pcie-pins {
++ mux {
++ function = "pcie";
++ groups = "pcie_clk", "pcie_pereset";
++ };
++ };
++
++ spi_flash_pins: spi-flash-pins {
++ mux {
++ function = "spi";
++ groups = "spi0", "spi0_wp_hold";
++ };
++ };
++
++ spic_pins: spic-pins {
++ mux {
++ function = "spi";
++ groups = "spi1_0";
++ };
++ };
++
++ uart1_pins: uart1-pins {
++ mux {
++ function = "uart";
++ groups = "uart1_rx_tx";
++ };
++ };
++
++ uart2_pins: uart2-pins {
++ mux {
++ function = "uart";
++ groups = "uart2_0_rx_tx";
++ };
++ };
++
++ wf_2g_5g_pins: wf-2g-5g-pins {
++ mux {
++ function = "wifi";
++ groups = "wf_2g", "wf_5g";
++ };
++ conf {
++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++ "WF1_TOP_CLK", "WF1_TOP_DATA";
++ drive-strength = <4>;
++ };
++ };
++
++ wf_dbdc_pins: wf-dbdc-pins {
++ mux {
++ function = "wifi";
++ groups = "wf_dbdc";
++ };
++ conf {
++ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++ "WF1_TOP_CLK", "WF1_TOP_DATA";
++ drive-strength = <4>;
++ };
++ };
++
++ wf_led_pins: wf-led-pins {
++ mux {
++ function = "led";
++ groups = "wifi_led";
++ };
++ };
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi_flash_pins>;
++ status = "okay";
++};
++
++&spi1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spic_pins>;
++ status = "okay";
++};
++
++&ssusb {
++ status = "okay";
++};
++
++&switch {
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "wan";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan0";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan1";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan2";
++ };
++
++ port@4 {
++ reg = <4>;
++ label = "lan3";
++ };
++
++ port5: port@5 {
++ reg = <5>;
++ label = "lan4";
++ phy-mode = "2500base-x";
++ sfp = <&sfp2>;
++ managed = "in-band-status";
++ };
++
++ port@6 {
++ reg = <6>;
++ label = "cpu";
++ ethernet = <&gmac0>;
++ phy-mode = "2500base-x";
++
++ fixed-link {
++ speed = <2500>;
++ full-duplex;
++ pause;
++ };
++ };
++ };
++};
++
++&trng {
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pins>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart2_pins>;
++ status = "okay";
++};
++
++&usb_phy {
++ status = "okay";
++};
++
++&watchdog {
++ status = "okay";
++};
++
++&wifi {
++ status = "okay";
++ pinctrl-names = "default", "dbdc";
++ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
++ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++};
++
--- /dev/null
+From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Wed, 17 May 2023 12:11:08 +0200
+Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible
+
+The chassis-type string identifies the form-factor of the system:
+add this property to all device trees of devices for which the form
+factor is known.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 +
+ .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 +
+ arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 +
+ 28 files changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+@@ -11,6 +11,7 @@
+
+ / {
+ model = "MediaTek MT2712 evaluation board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "MediaTek MT6755 EVB";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
+@@ -10,6 +10,7 @@
+
+ / {
+ model = "MediaTek MT6779 EVB";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "MediaTek MT6795 Evaluation Board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "MediaTek MT6797 Evaluation Board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
+@@ -12,6 +12,7 @@
+
+ / {
+ model = "Mediatek X20 Development Board";
++ chassis-type = "embedded";
+ compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -15,6 +15,7 @@
+
+ / {
+ model = "Bananapi BPI-R64";
++ chassis-type = "embedded";
+ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -15,6 +15,7 @@
+
+ / {
+ model = "MediaTek MT7622 RFB1 board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -16,6 +16,7 @@
+
+ / {
+ model = "Bananapi BPI-R3";
++ chassis-type = "embedded";
+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -11,6 +11,7 @@
+
+ / {
+ model = "MediaTek MT7986a RFB";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "MediaTek MT7986b RFB";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
+@@ -11,6 +11,7 @@
+
+ / {
+ model = "Pumpkin MT8167";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
+
+ memory@40000000 {
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
+@@ -8,6 +8,7 @@
+
+ / {
+ model = "Google Hanawl";
++ chassis-type = "laptop";
+ compatible = "google,hana-rev7", "mediatek,mt8173";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
+@@ -8,6 +8,7 @@
+
+ / {
+ model = "Google Hana";
++ chassis-type = "laptop";
+ compatible = "google,hana-rev6", "google,hana-rev5",
+ "google,hana-rev4", "google,hana-rev3",
+ "google,hana", "mediatek,mt8173";
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
+@@ -8,6 +8,7 @@
+
+ / {
+ model = "Google Elm";
++ chassis-type = "laptop";
+ compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
+ "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
+ "google,elm", "mediatek,mt8173";
+--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+@@ -10,6 +10,7 @@
+
+ / {
+ model = "MediaTek MT8173 evaluation board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+@@ -11,6 +11,7 @@
+
+ / {
+ model = "MediaTek MT8183 evaluation board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
+
+ aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "Google burnet board";
++ chassis-type = "convertible";
+ compatible = "google,burnet", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "Google damu board";
++ chassis-type = "convertible";
+ compatible = "google,damu", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "Google juniper sku16 board";
++ chassis-type = "convertible";
+ compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "MediaTek kakadu board sku22";
++ chassis-type = "tablet";
+ compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
+ "google,kakadu", "mediatek,mt8183";
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
+@@ -9,6 +9,7 @@
+
+ / {
+ model = "MediaTek kakadu board";
++ chassis-type = "tablet";
+ compatible = "google,kakadu-rev3", "google,kakadu-rev2",
+ "google,kakadu", "mediatek,mt8183";
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
+@@ -12,6 +12,7 @@
+
+ / {
+ model = "MediaTek kodama sku16 board";
++ chassis-type = "tablet";
+ compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
+@@ -12,6 +12,7 @@
+
+ / {
+ model = "MediaTek kodama sku272 board";
++ chassis-type = "tablet";
+ compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
+@@ -12,6 +12,7 @@
+
+ / {
+ model = "MediaTek kodama sku288 board";
++ chassis-type = "tablet";
+ compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
+@@ -14,6 +14,7 @@
+
+ / {
+ model = "MediaTek krane sku0 board";
++ chassis-type = "tablet";
+ compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
+@@ -14,6 +14,7 @@
+
+ / {
+ model = "MediaTek krane sku176 board";
++ chassis-type = "tablet";
+ compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
+ };
+
+--- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
+@@ -7,6 +7,7 @@
+
+ / {
+ model = "MediaTek MT8186 evaluation board";
++ chassis-type = "embedded";
+ compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+
+ aliases {
--- /dev/null
+From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Apr 2023 15:20:44 +0200
+Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM
+
+This adds pwm node to mt7986.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -240,6 +240,20 @@
+ status = "disabled";
+ };
+
++ pwm: pwm@10048000 {
++ compatible = "mediatek,mt7986-pwm";
++ reg = <0 0x10048000 0 0x1000>;
++ #clock-cells = <1>;
++ #pwm-cells = <2>;
++ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&topckgen CLK_TOP_PWM_SEL>,
++ <&infracfg CLK_INFRA_PWM_STA>,
++ <&infracfg CLK_INFRA_PWM1_CK>,
++ <&infracfg CLK_INFRA_PWM2_CK>;
++ clock-names = "top", "main", "pwm1", "pwm2";
++ status = "disabled";
++ };
++
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
--- /dev/null
+From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Fri, 21 Apr 2023 15:20:45 +0200
+Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3
+
+Add pwm node and pinctrl to BananaPi R3 devicetree.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -275,6 +275,13 @@
+ };
+ };
+
++ pwm_pins: pwm-pins {
++ mux {
++ function = "pwm";
++ groups = "pwm0", "pwm1_0";
++ };
++ };
++
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+@@ -345,6 +352,12 @@
+ };
+ };
+
++&pwm {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm_pins>;
++ status = "okay";
++};
++
+ &spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
--- /dev/null
+From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 5 Feb 2023 18:48:33 +0100
+Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3
+
+Leds for Wifi are low-active, so add property to devicetree.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -460,5 +460,9 @@
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++
++ led {
++ led-active-low;
++ };
+ };
+
--- /dev/null
+From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <frank-w@public-files.de>
+Date: Sun, 28 May 2023 13:33:42 +0200
+Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for
+ bl2
+
+To store uncompressed bl2 more space is required than partition is
+actually defined.
+
+There is currently no known usage of this reserved partition.
+Openwrt uses same partition layout.
+
+We added same change to u-boot with commit d7bb1099 [1].
+
+[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e
+
+Cc: stable@vger.kernel.org
+Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -27,15 +27,10 @@
+
+ partition@0 {
+ label = "bl2";
+- reg = <0x0 0x20000>;
++ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+- partition@20000 {
+- label = "reserved";
+- reg = <0x20000 0x20000>;
+- };
+-
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x40000>;
--- /dev/null
+From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 30 May 2023 22:12:33 +0200
+Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse
+
+Add thermal related nodes to mt7986 devicetree.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++-
+ 1 file changed, 35 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -337,6 +337,15 @@
+ status = "disabled";
+ };
+
++ auxadc: adc@1100d000 {
++ compatible = "mediatek,mt7986-auxadc";
++ reg = <0 0x1100d000 0 0x1000>;
++ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
++ clock-names = "main";
++ #io-channel-cells = <1>;
++ status = "disabled";
++ };
++
+ ssusb: usb@11200000 {
+ compatible = "mediatek,mt7986-xhci",
+ "mediatek,mtk-xhci";
+@@ -375,6 +384,21 @@
+ status = "disabled";
+ };
+
++ thermal: thermal@1100c800 {
++ #thermal-sensor-cells = <1>;
++ compatible = "mediatek,mt7986-thermal";
++ reg = <0 0x1100c800 0 0x800>;
++ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&infracfg CLK_INFRA_THERM_CK>,
++ <&infracfg CLK_INFRA_ADC_26M_CK>,
++ <&infracfg CLK_INFRA_ADC_FRC_CK>;
++ clock-names = "therm", "auxadc", "adc_32k";
++ mediatek,auxadc = <&auxadc>;
++ mediatek,apmixedsys = <&apmixedsys>;
++ nvmem-cells = <&thermal_calibration>;
++ nvmem-cell-names = "calibration-data";
++ };
++
+ pcie: pcie@11280000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+@@ -426,6 +450,17 @@
+ };
+ };
+
++ efuse: efuse@11d00000 {
++ compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
++ reg = <0 0x11d00000 0 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ thermal_calibration: calib@274 {
++ reg = <0x274 0xc>;
++ };
++ };
++
+ usb_phy: t-phy@11e10000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
+@@ -567,5 +602,4 @@
+ memory-region = <&wmcpu_emi>;
+ };
+ };
+-
+ };
--- /dev/null
+From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 30 May 2023 22:12:34 +0200
+Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones
+
+Add thermal-zones to mt7986 devicetree.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -602,4 +602,32 @@
+ memory-region = <&wmcpu_emi>;
+ };
+ };
++
++ thermal-zones {
++ cpu_thermal: cpu-thermal {
++ polling-delay-passive = <1000>;
++ polling-delay = <1000>;
++ thermal-sensors = <&thermal 0>;
++
++ trips {
++ cpu_trip_active_high: active-high {
++ temperature = <115000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++
++ cpu_trip_active_low: active-low {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++
++ cpu_trip_passive: passive {
++ temperature = <40000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ };
++ };
++ };
+ };
--- /dev/null
+From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 30 May 2023 22:12:35 +0200
+Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to
+ BPI-R3 dts
+
+Add pwm-fan and cooling-maps to BananaPi-R3 devicetree.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -38,6 +38,15 @@
+ regulator-always-on;
+ };
+
++ fan: pwm-fan {
++ compatible = "pwm-fan";
++ #cooling-cells = <2>;
++ /* cooling level (0, 1, 2) - pwm inverted */
++ cooling-levels = <255 96 0>;
++ pwms = <&pwm 0 10000 0>;
++ status = "okay";
++ };
++
+ gpio-keys {
+ compatible = "gpio-keys";
+
+@@ -133,6 +142,28 @@
+ };
+ };
+
++&cpu_thermal {
++ cooling-maps {
++ cpu-active-high {
++ /* active: set fan to cooling level 2 */
++ cooling-device = <&fan 2 2>;
++ trip = <&cpu_trip_active_high>;
++ };
++
++ cpu-active-low {
++ /* active: set fan to cooling level 1 */
++ cooling-device = <&fan 1 1>;
++ trip = <&cpu_trip_active_low>;
++ };
++
++ cpu-passive {
++ /* passive: set fan to cooling level 0 */
++ cooling-device = <&fan 0 0>;
++ trip = <&cpu_trip_passive>;
++ };
++ };
++};
++
+ &crypto {
+ status = "okay";
+ };
--- /dev/null
+From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 6 Jun 2023 16:43:20 +0100
+Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of
+ Bananapi R3
+
+The bootrom burned into the MT7986 SoC will try multiple locations on
+the SPI-NAND flash to load bl2 in case the bl2 image located at the the
+previously attempted offset is corrupt.
+
+Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND,
+allowing for up to four redundant copies of bl2 (typically sized a
+bit less than 0x40000).
+
+Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,13 +29,13 @@
+
+ partition@0 {
+ label = "bl2";
+- reg = <0x0 0x80000>;
++ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+- partition@80000 {
++ partition@100000 {
+ label = "reserved";
+- reg = <0x80000 0x300000>;
++ reg = <0x100000 0x280000>;
+ };
+
+ partition@380000 {
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
-@@ -23,7 +22,7 @@
+@@ -24,7 +23,7 @@
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
-@@ -40,23 +39,22 @@
-
- gpio-keys {
- compatible = "gpio-keys";
-- poll-interval = <100>;
-
- factory {
+@@ -45,18 +44,18 @@
+ key-factory {
label = "factory";
linux,code = <BTN_0>;
- gpios = <&pio 0 0>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
};
- wps {
+ key-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 0>;
};
reg_1p8v: regulator-1p8v {
-@@ -132,22 +130,22 @@
+@@ -132,22 +131,22 @@
port@0 {
reg = <0>;
};
port@4 {
-@@ -236,15 +234,28 @@
-
- &pcie {
- pinctrl-names = "default";
-- pinctrl-0 = <&pcie0_pins>;
-+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+@@ -240,7 +239,22 @@
status = "okay";
-
- pcie@0,0 {
- status = "okay";
- };
-+
-+ pcie@1,0 {
-+ status = "okay";
-+ };
};
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_pins>;
++ status = "okay";
++};
++
&pio {
+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
-@@ -521,11 +532,11 @@
+@@ -517,11 +531,11 @@
};
&sata {
};
};
};
-@@ -272,3 +281,17 @@
+@@ -273,3 +282,17 @@
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -559,6 +559,7 @@
+@@ -578,6 +578,7 @@
compatible = "mediatek,mt7622-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -111,7 +111,7 @@
- };
-
- psci {
-- compatible = "arm,psci-0.2";
-+ compatible = "arm,psci-1.0";
- method = "smc";
- };
-
-@@ -127,6 +127,13 @@
+@@ -134,6 +134,13 @@
#size-cells = <2>;
ranges;
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -22,7 +22,7 @@
+@@ -24,7 +24,7 @@
chosen {
stdout-path = "serial0:115200n8";
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -18,6 +18,7 @@
+@@ -20,6 +20,7 @@
aliases {
serial0 = &uart0;
};
chosen {
-@@ -160,22 +161,22 @@
+@@ -164,22 +165,22 @@
port@1 {
reg = <1>;
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -19,6 +19,10 @@
+@@ -21,6 +21,10 @@
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
};
chosen {
-@@ -42,8 +46,8 @@
+@@ -44,8 +48,8 @@
compatible = "gpio-keys";
- factory {
+ factory-key {
- label = "factory";
- linux,code = <BTN_0>;
+ label = "reset";
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
-@@ -57,17 +61,25 @@
+@@ -59,17 +63,17 @@
leds {
compatible = "gpio-leds";
-- green {
-- label = "bpi-r64:pio:green";
-- gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
-+ led_system_blue: blue {
-+ label = "bpi-r64:pio:blue";
-+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
+- led-0 {
++ led_system_green: led-0 {
+ label = "bpi-r64:pio:green";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
-- red {
+- led-1 {
- label = "bpi-r64:pio:red";
+- color = <LED_COLOR_ID_RED>;
- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ led_system_green: green {
-+ label = "bpi-r64:pio:green";
-+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
++ led_system_blue: led-1 {
++ label = "bpi-r64:pio:blue";
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
-+
-+/*
-+ * red {
-+ * label = "bpi-r64:pio:red";
-+ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ * default-state = "off";
-+ * };
-+ */
};
-
- memory {
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -564,12 +564,16 @@
+@@ -558,12 +558,16 @@
status = "okay";
};
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -259,14 +259,42 @@
+@@ -255,14 +255,42 @@
status = "disabled";
};
+++ /dev/null
-From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:38 +0100
-Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware
- engines
-
-Add the necessary helpers to register/unregister hardware ECC engines
-that will be called from ECC engine drivers.
-
-Also add helpers to get the right engine from the user
-perspective. Keep a reference of the in use ECC engine in order to
-prevent modules to be unloaded. Put the reference when the engine gets
-retired.
-
-A static list of hardware (only) ECC engines is setup to keep track of
-the registered engines.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com
-(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152)
----
- drivers/mtd/nand/core.c | 10 +++--
- drivers/mtd/nand/ecc.c | 88 ++++++++++++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h | 28 +++++++++++++
- 3 files changed, 123 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/nand/core.c
-+++ b/drivers/mtd/nand/core.c
-@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct
- nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
- break;
- case NAND_ECC_ENGINE_TYPE_ON_HOST:
-- pr_err("On-host hardware ECC engines not supported yet\n");
-+ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
-+ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
-+ return -EPROBE_DEFER;
- break;
- default:
- pr_err("Missing ECC engine type\n");
-@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct
- {
- switch (nand->ecc.ctx.conf.engine_type) {
- case NAND_ECC_ENGINE_TYPE_ON_HOST:
-- pr_err("On-host hardware ECC engines not supported yet\n");
-+ nand_ecc_put_on_host_hw_engine(nand);
- break;
- case NAND_ECC_ENGINE_TYPE_NONE:
- case NAND_ECC_ENGINE_TYPE_SOFT:
-@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_
- /* Look for the ECC engine to use */
- ret = nanddev_get_ecc_engine(nand);
- if (ret) {
-- pr_err("No ECC engine found\n");
-+ if (ret != -EPROBE_DEFER)
-+ pr_err("No ECC engine found\n");
-+
- return ret;
- }
-
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -96,6 +96,12 @@
- #include <linux/module.h>
- #include <linux/mtd/nand.h>
- #include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_platform.h>
-+
-+static LIST_HEAD(on_host_hw_engines);
-+static DEFINE_MUTEX(on_host_hw_engines_mutex);
-
- /**
- * nand_ecc_init_ctx - Init the ECC engine context
-@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_
- }
- EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
-
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+ struct nand_ecc_engine *item;
-+
-+ if (!engine)
-+ return -EINVAL;
-+
-+ /* Prevent multiple registrations of one engine */
-+ list_for_each_entry(item, &on_host_hw_engines, node)
-+ if (item == engine)
-+ return 0;
-+
-+ mutex_lock(&on_host_hw_engines_mutex);
-+ list_add_tail(&engine->node, &on_host_hw_engines);
-+ mutex_unlock(&on_host_hw_engines_mutex);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
-+
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
-+{
-+ if (!engine)
-+ return -EINVAL;
-+
-+ mutex_lock(&on_host_hw_engines_mutex);
-+ list_del(&engine->node);
-+ mutex_unlock(&on_host_hw_engines_mutex);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
-+
-+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
-+{
-+ struct nand_ecc_engine *item;
-+
-+ list_for_each_entry(item, &on_host_hw_engines, node)
-+ if (item->dev == dev)
-+ return item;
-+
-+ return NULL;
-+}
-+
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
-+{
-+ struct nand_ecc_engine *engine = NULL;
-+ struct device *dev = &nand->mtd.dev;
-+ struct platform_device *pdev;
-+ struct device_node *np;
-+
-+ if (list_empty(&on_host_hw_engines))
-+ return NULL;
-+
-+ /* Check for an explicit nand-ecc-engine property */
-+ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
-+ if (np) {
-+ pdev = of_find_device_by_node(np);
-+ if (!pdev)
-+ return ERR_PTR(-EPROBE_DEFER);
-+
-+ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
-+ platform_device_put(pdev);
-+ of_node_put(np);
-+
-+ if (!engine)
-+ return ERR_PTR(-EPROBE_DEFER);
-+ }
-+
-+ if (engine)
-+ get_device(engine->dev);
-+
-+ return engine;
-+}
-+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
-+
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
-+{
-+ put_device(nand->ecc.engine->dev);
-+}
-+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops {
- };
-
- /**
-+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated
-+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value
-+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly
-+ * correction, does not need to copy
-+ * data around
-+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the
-+ * data into its own area before use
-+ */
-+enum nand_ecc_engine_integration {
-+ NAND_ECC_ENGINE_INTEGRATION_INVALID,
-+ NAND_ECC_ENGINE_INTEGRATION_PIPELINED,
-+ NAND_ECC_ENGINE_INTEGRATION_EXTERNAL,
-+};
-+
-+/**
- * struct nand_ecc_engine - ECC engine abstraction for NAND devices
-+ * @dev: Host device
-+ * @node: Private field for registration time
- * @ops: ECC engine operations
-+ * @integration: How the engine is integrated with the host
-+ * (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)
-+ * @priv: Private data
- */
- struct nand_ecc_engine {
-+ struct device *dev;
-+ struct list_head node;
- struct nand_ecc_engine_ops *ops;
-+ enum nand_ecc_engine_integration integration;
-+ void *priv;
- };
-
- void of_get_nand_ecc_user_config(struct nand_device *nand);
-@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_
- int nand_ecc_finish_io_req(struct nand_device *nand,
- struct nand_page_io_req *req);
- bool nand_ecc_is_strong_enough(struct nand_device *nand);
-+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
-+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
- struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
-+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
-+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
-
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
+++ /dev/null
-From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:39 +0100
-Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context
-
-Introduce nand_to_ecc_ctx() which will allow to easily jump to the
-private pointer of an ECC context given a NAND device. This is very
-handy, from the prepare or finish ECC hook, to get the internal context
-out of the NAND device object.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com
-(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4)
----
- include/linux/mtd/nand.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *
- int nanddev_ecc_engine_init(struct nand_device *nand);
- void nanddev_ecc_engine_cleanup(struct nand_device *nand);
-
-+static inline void *nand_to_ecc_ctx(struct nand_device *nand)
-+{
-+ return nand->ecc.ctx.priv;
-+}
-+
- /* BBT related functions */
- enum nand_bbt_block_status {
- NAND_BBT_BLOCK_STATUS_UNKNOWN,
+++ /dev/null
-From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 16 Dec 2021 12:16:41 +0100
-Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a
- pilelined engine device
-
-In a pipelined engine situation, we might either have the host which
-internally has support for error correction, or have it using an
-external hardware block for this purpose. In the former case, the host
-is also the ECC engine. In the latter case, it is not. In order to get
-the right pointers on the right devices (for example: in order to devm_*
-allocate variables), let's introduce this helper which can safely be
-called by pipelined ECC engines in order to retrieve the right device
-structure.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com
-(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309)
----
- drivers/mtd/nand/ecc.c | 31 +++++++++++++++++++++++++++++++
- include/linux/mtd/nand.h | 1 +
- 2 files changed, 32 insertions(+)
-
---- a/drivers/mtd/nand/ecc.c
-+++ b/drivers/mtd/nand/ecc.c
-@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru
- }
- EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
-
-+/*
-+ * In the case of a pipelined engine, the device registering the ECC
-+ * engine is not necessarily the ECC engine itself but may be a host controller.
-+ * It is then useful to provide a helper to retrieve the right device object
-+ * which actually represents the ECC engine.
-+ */
-+struct device *nand_ecc_get_engine_dev(struct device *host)
-+{
-+ struct platform_device *ecc_pdev;
-+ struct device_node *np;
-+
-+ /*
-+ * If the device node contains this property, it means we need to follow
-+ * it in order to get the right ECC engine device we are looking for.
-+ */
-+ np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0);
-+ if (!np)
-+ return host;
-+
-+ ecc_pdev = of_find_device_by_node(np);
-+ if (!ecc_pdev) {
-+ of_node_put(np);
-+ return NULL;
-+ }
-+
-+ platform_device_put(ecc_pdev);
-+ of_node_put(np);
-+
-+ return &ecc_pdev->dev;
-+}
-+
- MODULE_LICENSE("GPL");
- MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
- MODULE_DESCRIPTION("Generic ECC engine");
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_
- struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
- struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
- void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
-+struct device *nand_ecc_get_engine_dev(struct device *host);
-
- #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
- struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
+++ /dev/null
-From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:17:56 +0100
-Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure
-
-Create a spi_controller_mem_caps structure and put it within the
-spi_controller structure close to the spi_controller_mem_ops
-strucure. So far the only field in this structure is the support for dtr
-operations, but soon we will add another parameter.
-
-Also create a helper to parse the capabilities and check if the
-requested capability has been set or not.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Reviewed-by: Mark Brown <broonie@kernel.org>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com
-(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20)
----
- include/linux/spi/spi-mem.h | 11 +++++++++++
- include/linux/spi/spi.h | 3 +++
- 2 files changed, 14 insertions(+)
-
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -286,6 +286,17 @@ struct spi_controller_mem_ops {
- };
-
- /**
-+ * struct spi_controller_mem_caps - SPI memory controller capabilities
-+ * @dtr: Supports DTR operations
-+ */
-+struct spi_controller_mem_caps {
-+ bool dtr;
-+};
-+
-+#define spi_mem_controller_is_capable(ctlr, cap) \
-+ ((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
-+
-+/**
- * struct spi_mem_driver - SPI memory driver
- * @spidrv: inherit from a SPI driver
- * @probe: probe a SPI memory. Usually where detection/initialization takes
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -23,6 +23,7 @@ struct software_node;
- struct spi_controller;
- struct spi_transfer;
- struct spi_controller_mem_ops;
-+struct spi_controller_mem_caps;
-
- /*
- * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
-@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill
- * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
- * This field is optional and should only be implemented if the
- * controller has native support for memory like operations.
-+ * @mem_caps: controller capabilities for the handling of memory operations.
- * @unprepare_message: undo any work done by prepare_message().
- * @slave_abort: abort the ongoing transfer request on an SPI slave controller
- * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
-@@ -643,6 +645,7 @@ struct spi_controller {
-
- /* Optimized handlers for SPI memory-like operations. */
- const struct spi_controller_mem_ops *mem_ops;
-+ const struct spi_controller_mem_caps *mem_caps;
-
- /* gpio chip select */
- int *cs_gpios;
+++ /dev/null
-From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:17:57 +0100
-Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities
-
-Controllers can now provide a spi-mem capabilities structure. Let's make
-use of it in spi_mem_controller_default_supports_op(). As we want to
-check for DTR operations as well as normal operations in a single
-helper, let's pull the necessary checks from spi_mem_dtr_supports_op()
-for now.
-
-However, because no controller provide these extra capabilities, this
-change has no effect so far.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com
-(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37)
----
- drivers/spi/spi-mem.c | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- const struct spi_mem_op *op)
- {
-- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
-- return false;
-+ struct spi_controller *ctlr = mem->spi->controller;
-+ bool op_is_dtr =
-+ op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
-
-- if (op->cmd.nbytes != 1)
-- return false;
-+ if (op_is_dtr) {
-+ if (!spi_mem_controller_is_capable(ctlr, dtr))
-+ return false;
-+
-+ if (op->cmd.nbytes != 2)
-+ return false;
-+ } else {
-+ if (op->cmd.nbytes != 1)
-+ return false;
-+ }
-
- return spi_mem_check_buswidth(mem, op);
- }
+++ /dev/null
-From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:00 +0100
-Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper
-
-Now that spi_mem_default_supports_op() has access to the static
-controller capabilities (relating to memory operations), and now that
-these capabilities have been filled by the relevant controllers, there
-is no need for a specific helper checking only DTR operations, so let's
-just kill spi_mem_dtr_supports_op() and simply use
-spi_mem_default_supports_op() instead.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com
-(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20)
----
- drivers/spi/spi-cadence-quadspi.c | 5 +----
- drivers/spi/spi-mem.c | 10 ----------
- drivers/spi/spi-mxic.c | 10 +---------
- include/linux/spi/spi-mem.h | 11 -----------
- 4 files changed, 2 insertions(+), 34 deletions(-)
-
---- a/drivers/spi/spi-cadence-quadspi.c
-+++ b/drivers/spi/spi-cadence-quadspi.c
-@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct
- return false;
- }
-
-- if (all_true)
-- return spi_mem_dtr_supports_op(mem, op);
-- else
-- return spi_mem_default_supports_op(mem, op);
-+ return spi_mem_default_supports_op(mem, op);
- }
-
- static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc
- return true;
- }
-
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
-- const struct spi_mem_op *op)
--{
-- if (op->cmd.nbytes != 2)
-- return false;
--
-- return spi_mem_check_buswidth(mem, op);
--}
--EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
--
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- const struct spi_mem_op *op)
- {
---- a/drivers/spi/spi-mxic.c
-+++ b/drivers/spi/spi-mxic.c
-@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi
- static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
- const struct spi_mem_op *op)
- {
-- bool all_false;
--
- if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
- op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
- return false;
-@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str
- if (op->addr.nbytes > 7)
- return false;
-
-- all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
-- !op->data.dtr;
--
-- if (all_false)
-- return spi_mem_default_supports_op(mem, op);
-- else
-- return spi_mem_dtr_supports_op(mem, op);
-+ return spi_mem_default_supports_op(mem, op);
- }
-
- static int mxic_spi_mem_exec_op(struct spi_mem *mem,
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat
-
- bool spi_mem_default_supports_op(struct spi_mem *mem,
- const struct spi_mem_op *op);
--
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
-- const struct spi_mem_op *op);
--
- #else
- static inline int
- spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
-@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct
- {
- return false;
- }
--
--static inline
--bool spi_mem_dtr_supports_op(struct spi_mem *mem,
-- const struct spi_mem_op *op)
--{
-- return false;
--}
- #endif /* CONFIG_SPI_MEM */
-
- int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
+++ /dev/null
-From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:01 +0100
-Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
- structure
-
-Soon the SPI-NAND core will need a way to request a SPI controller to
-enable ECC support for a given operation. This is because of the
-pipelined integration of certain ECC engines, which are directly managed
-by the SPI controller itself.
-
-Introduce a spi_mem_op additional field for this purpose: ecc.
-
-So far this field is left unset and checked to be false by all
-the SPI controller drivers in their ->supports_op() hook, as they all
-call spi_mem_default_supports_op().
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Acked-by: Pratyush Yadav <p.yadav@ti.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com
-(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
----
- drivers/spi/spi-mem.c | 5 +++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 9 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
- return false;
- }
-
-+ if (op->data.ecc) {
-+ if (!spi_mem_controller_is_capable(ctlr, ecc))
-+ return false;
-+ }
-+
- return spi_mem_check_buswidth(mem, op);
- }
- EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
- * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
- * @data.buswidth: number of IO lanes used to send/receive the data
- * @data.dtr: whether the data should be sent in DTR mode or not
-+ * @data.ecc: whether error correction is required or not
- * @data.dir: direction of the transfer
- * @data.nbytes: number of data bytes to send/receive. Can be zero if the
- * operation does not involve transferring data
-@@ -119,6 +120,7 @@ struct spi_mem_op {
- struct {
- u8 buswidth;
- u8 dtr : 1;
-+ u8 ecc : 1;
- enum spi_mem_data_dir dir;
- unsigned int nbytes;
- union {
-@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
- /**
- * struct spi_controller_mem_caps - SPI memory controller capabilities
- * @dtr: Supports DTR operations
-+ * @ecc: Supports operations with error correction
- */
- struct spi_controller_mem_caps {
- bool dtr;
-+ bool ecc;
- };
-
- #define spi_mem_controller_is_capable(ctlr, cap) \
+++ /dev/null
-From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:02 +0100
-Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation
-
-As we will soon tweak the dirmap creation to act a little bit
-differently depending on the picked ECC engine, we need to initialize
-dirmaps after ECC engines. This should not have any effect as dirmaps
-are not yet used at this point.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com
-(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949)
----
- drivers/mtd/nand/spi/core.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1221,14 +1221,6 @@ static int spinand_init(struct spinand_d
- if (ret)
- goto err_free_bufs;
-
-- ret = spinand_create_dirmaps(spinand);
-- if (ret) {
-- dev_err(dev,
-- "Failed to create direct mappings for read/write operations (err = %d)\n",
-- ret);
-- goto err_manuf_cleanup;
-- }
--
- ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
- if (ret)
- goto err_manuf_cleanup;
-@@ -1263,6 +1255,14 @@ static int spinand_init(struct spinand_d
- mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
- mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
-
-+ ret = spinand_create_dirmaps(spinand);
-+ if (ret) {
-+ dev_err(dev,
-+ "Failed to create direct mappings for read/write operations (err = %d)\n",
-+ ret);
-+ goto err_cleanup_ecc_engine;
-+ }
-+
- return 0;
-
- err_cleanup_ecc_engine:
+++ /dev/null
-From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Thu, 27 Jan 2022 10:18:03 +0100
-Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC
- operations
-
-In order for pipelined ECC engines to be able to enable/disable the ECC
-engine only when needed and avoid races when future parallel-operations
-will be supported, we need to provide the information about the use of
-the ECC engine in the direct mapping hooks. As direct mapping
-configurations are meant to be static, it is best to create two new
-mappings: one for regular 'raw' accesses and one for accesses involving
-correction. It is up to the driver to use or not the new ECC enable
-boolean contained in the spi-mem operation.
-
-As dirmaps are not free (they consume a few pages of MMIO address space)
-and because these extra entries are only meant to be used by pipelined
-engines, let's limit their use to this specific type of engine and save
-a bit of memory with all the other setups.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
-Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com
-(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2)
----
- drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++--
- include/linux/mtd/spinand.h | 2 ++
- 2 files changed, 35 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st
- }
- }
-
-- rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+ if (req->mode == MTD_OPS_RAW)
-+ rdesc = spinand->dirmaps[req->pos.plane].rdesc;
-+ else
-+ rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
-
- while (nbytes) {
- ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
-@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str
- req->ooblen);
- }
-
-- wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+ if (req->mode == MTD_OPS_RAW)
-+ wdesc = spinand->dirmaps[req->pos.plane].wdesc;
-+ else
-+ wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
-
- while (nbytes) {
- ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
-@@ -875,6 +881,31 @@ static int spinand_create_dirmap(struct
-
- spinand->dirmaps[plane].rdesc = desc;
-
-+ if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
-+ spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
-+ spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
-+
-+ return 0;
-+ }
-+
-+ info.op_tmpl = *spinand->op_templates.update_cache;
-+ info.op_tmpl.data.ecc = true;
-+ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+ spinand->spimem, &info);
-+ if (IS_ERR(desc))
-+ return PTR_ERR(desc);
-+
-+ spinand->dirmaps[plane].wdesc_ecc = desc;
-+
-+ info.op_tmpl = *spinand->op_templates.read_cache;
-+ info.op_tmpl.data.ecc = true;
-+ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
-+ spinand->spimem, &info);
-+ if (IS_ERR(desc))
-+ return PTR_ERR(desc);
-+
-+ spinand->dirmaps[plane].rdesc_ecc = desc;
-+
- return 0;
- }
-
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -392,6 +392,8 @@ struct spinand_info {
- struct spinand_dirmap {
- struct spi_mem_dirmap_desc *wdesc;
- struct spi_mem_dirmap_desc *rdesc;
-+ struct spi_mem_dirmap_desc *wdesc_ecc;
-+ struct spi_mem_dirmap_desc *rdesc_ecc;
- };
-
- /**
+++ /dev/null
-From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Tue, 22 Mar 2022 18:44:21 +0800
-Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module
-
-this code will be used in mediatek snfi spi-mem controller with
-pipelined ECC engine.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d)
----
- drivers/mtd/nand/Kconfig | 7 +++++++
- drivers/mtd/nand/Makefile | 1 +
- drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} | 3 +--
- drivers/mtd/nand/raw/Kconfig | 1 +
- drivers/mtd/nand/raw/Makefile | 2 +-
- drivers/mtd/nand/raw/mtk_nand.c | 2 +-
- .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0
- 7 files changed, 12 insertions(+), 4 deletions(-)
- rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%)
- rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%)
-
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT
- bool "Support MediaTek NAND Bad-block Management Table"
- default n
-
-+config MTD_NAND_ECC_MEDIATEK
-+ tristate "Mediatek hardware ECC engine"
-+ depends on HAS_IOMEM
-+ select MTD_NAND_ECC
-+ help
-+ This enables support for the hardware ECC engine from Mediatek.
-+
- endmenu
-
- endmenu
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -3,6 +3,7 @@
- nandcore-objs := core.o bbt.o
- obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
- obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
-+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
-
- obj-y += onenand/
- obj-y += raw/
---- a/drivers/mtd/nand/raw/mtk_ecc.c
-+++ /dev/null
-@@ -1,599 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0 OR MIT
--/*
-- * MTK ECC controller driver.
-- * Copyright (C) 2016 MediaTek Inc.
-- * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
-- * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-- */
--
--#include <linux/platform_device.h>
--#include <linux/dma-mapping.h>
--#include <linux/interrupt.h>
--#include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/iopoll.h>
--#include <linux/of.h>
--#include <linux/of_platform.h>
--#include <linux/mutex.h>
--
--#include "mtk_ecc.h"
--
--#define ECC_IDLE_MASK BIT(0)
--#define ECC_IRQ_EN BIT(0)
--#define ECC_PG_IRQ_SEL BIT(1)
--#define ECC_OP_ENABLE (1)
--#define ECC_OP_DISABLE (0)
--
--#define ECC_ENCCON (0x00)
--#define ECC_ENCCNFG (0x04)
--#define ECC_MS_SHIFT (16)
--#define ECC_ENCDIADDR (0x08)
--#define ECC_ENCIDLE (0x0C)
--#define ECC_DECCON (0x100)
--#define ECC_DECCNFG (0x104)
--#define DEC_EMPTY_EN BIT(31)
--#define DEC_CNFG_CORRECT (0x3 << 12)
--#define ECC_DECIDLE (0x10C)
--#define ECC_DECENUM0 (0x114)
--
--#define ECC_TIMEOUT (500000)
--
--#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
--#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
--
--struct mtk_ecc_caps {
-- u32 err_mask;
-- u32 err_shift;
-- const u8 *ecc_strength;
-- const u32 *ecc_regs;
-- u8 num_ecc_strength;
-- u8 ecc_mode_shift;
-- u32 parity_bits;
-- int pg_irq_sel;
--};
--
--struct mtk_ecc {
-- struct device *dev;
-- const struct mtk_ecc_caps *caps;
-- void __iomem *regs;
-- struct clk *clk;
--
-- struct completion done;
-- struct mutex lock;
-- u32 sectors;
--
-- u8 *eccdata;
--};
--
--/* ecc strength that each IP supports */
--static const u8 ecc_strength_mt2701[] = {
-- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-- 40, 44, 48, 52, 56, 60
--};
--
--static const u8 ecc_strength_mt2712[] = {
-- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-- 40, 44, 48, 52, 56, 60, 68, 72, 80
--};
--
--static const u8 ecc_strength_mt7622[] = {
-- 4, 6, 8, 10, 12
--};
--
--enum mtk_ecc_regs {
-- ECC_ENCPAR00,
-- ECC_ENCIRQ_EN,
-- ECC_ENCIRQ_STA,
-- ECC_DECDONE,
-- ECC_DECIRQ_EN,
-- ECC_DECIRQ_STA,
--};
--
--static int mt2701_ecc_regs[] = {
-- [ECC_ENCPAR00] = 0x10,
-- [ECC_ENCIRQ_EN] = 0x80,
-- [ECC_ENCIRQ_STA] = 0x84,
-- [ECC_DECDONE] = 0x124,
-- [ECC_DECIRQ_EN] = 0x200,
-- [ECC_DECIRQ_STA] = 0x204,
--};
--
--static int mt2712_ecc_regs[] = {
-- [ECC_ENCPAR00] = 0x300,
-- [ECC_ENCIRQ_EN] = 0x80,
-- [ECC_ENCIRQ_STA] = 0x84,
-- [ECC_DECDONE] = 0x124,
-- [ECC_DECIRQ_EN] = 0x200,
-- [ECC_DECIRQ_STA] = 0x204,
--};
--
--static int mt7622_ecc_regs[] = {
-- [ECC_ENCPAR00] = 0x10,
-- [ECC_ENCIRQ_EN] = 0x30,
-- [ECC_ENCIRQ_STA] = 0x34,
-- [ECC_DECDONE] = 0x11c,
-- [ECC_DECIRQ_EN] = 0x140,
-- [ECC_DECIRQ_STA] = 0x144,
--};
--
--static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
-- enum mtk_ecc_operation op)
--{
-- struct device *dev = ecc->dev;
-- u32 val;
-- int ret;
--
-- ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
-- val & ECC_IDLE_MASK,
-- 10, ECC_TIMEOUT);
-- if (ret)
-- dev_warn(dev, "%s NOT idle\n",
-- op == ECC_ENCODE ? "encoder" : "decoder");
--}
--
--static irqreturn_t mtk_ecc_irq(int irq, void *id)
--{
-- struct mtk_ecc *ecc = id;
-- u32 dec, enc;
--
-- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-- & ECC_IRQ_EN;
-- if (dec) {
-- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-- if (dec & ecc->sectors) {
-- /*
-- * Clear decode IRQ status once again to ensure that
-- * there will be no extra IRQ.
-- */
-- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
-- ecc->sectors = 0;
-- complete(&ecc->done);
-- } else {
-- return IRQ_HANDLED;
-- }
-- } else {
-- enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-- & ECC_IRQ_EN;
-- if (enc)
-- complete(&ecc->done);
-- else
-- return IRQ_NONE;
-- }
--
-- return IRQ_HANDLED;
--}
--
--static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
-- u32 ecc_bit, dec_sz, enc_sz;
-- u32 reg, i;
--
-- for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-- if (ecc->caps->ecc_strength[i] == config->strength)
-- break;
-- }
--
-- if (i == ecc->caps->num_ecc_strength) {
-- dev_err(ecc->dev, "invalid ecc strength %d\n",
-- config->strength);
-- return -EINVAL;
-- }
--
-- ecc_bit = i;
--
-- if (config->op == ECC_ENCODE) {
-- /* configure ECC encoder (in bits) */
-- enc_sz = config->len << 3;
--
-- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-- reg |= (enc_sz << ECC_MS_SHIFT);
-- writel(reg, ecc->regs + ECC_ENCCNFG);
--
-- if (config->mode != ECC_NFI_MODE)
-- writel(lower_32_bits(config->addr),
-- ecc->regs + ECC_ENCDIADDR);
--
-- } else {
-- /* configure ECC decoder (in bits) */
-- dec_sz = (config->len << 3) +
-- config->strength * ecc->caps->parity_bits;
--
-- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-- reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
-- reg |= DEC_EMPTY_EN;
-- writel(reg, ecc->regs + ECC_DECCNFG);
--
-- if (config->sectors)
-- ecc->sectors = 1 << (config->sectors - 1);
-- }
--
-- return 0;
--}
--
--void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
-- int sectors)
--{
-- u32 offset, i, err;
-- u32 bitflips = 0;
--
-- stats->corrected = 0;
-- stats->failed = 0;
--
-- for (i = 0; i < sectors; i++) {
-- offset = (i >> 2) << 2;
-- err = readl(ecc->regs + ECC_DECENUM0 + offset);
-- err = err >> ((i % 4) * ecc->caps->err_shift);
-- err &= ecc->caps->err_mask;
-- if (err == ecc->caps->err_mask) {
-- /* uncorrectable errors */
-- stats->failed++;
-- continue;
-- }
--
-- stats->corrected += err;
-- bitflips = max_t(u32, bitflips, err);
-- }
--
-- stats->bitflips = bitflips;
--}
--EXPORT_SYMBOL(mtk_ecc_get_stats);
--
--void mtk_ecc_release(struct mtk_ecc *ecc)
--{
-- clk_disable_unprepare(ecc->clk);
-- put_device(ecc->dev);
--}
--EXPORT_SYMBOL(mtk_ecc_release);
--
--static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
--{
-- mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-- writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
--
-- mtk_ecc_wait_idle(ecc, ECC_DECODE);
-- writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
--}
--
--static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
--{
-- struct platform_device *pdev;
-- struct mtk_ecc *ecc;
--
-- pdev = of_find_device_by_node(np);
-- if (!pdev)
-- return ERR_PTR(-EPROBE_DEFER);
--
-- ecc = platform_get_drvdata(pdev);
-- if (!ecc) {
-- put_device(&pdev->dev);
-- return ERR_PTR(-EPROBE_DEFER);
-- }
--
-- clk_prepare_enable(ecc->clk);
-- mtk_ecc_hw_init(ecc);
--
-- return ecc;
--}
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
--{
-- struct mtk_ecc *ecc = NULL;
-- struct device_node *np;
--
-- np = of_parse_phandle(of_node, "ecc-engine", 0);
-- if (np) {
-- ecc = mtk_ecc_get(np);
-- of_node_put(np);
-- }
--
-- return ecc;
--}
--EXPORT_SYMBOL(of_mtk_ecc_get);
--
--int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
--{
-- enum mtk_ecc_operation op = config->op;
-- u16 reg_val;
-- int ret;
--
-- ret = mutex_lock_interruptible(&ecc->lock);
-- if (ret) {
-- dev_err(ecc->dev, "interrupted when attempting to lock\n");
-- return ret;
-- }
--
-- mtk_ecc_wait_idle(ecc, op);
--
-- ret = mtk_ecc_config(ecc, config);
-- if (ret) {
-- mutex_unlock(&ecc->lock);
-- return ret;
-- }
--
-- if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
-- init_completion(&ecc->done);
-- reg_val = ECC_IRQ_EN;
-- /*
-- * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
-- * means this chip can only generate one ecc irq during page
-- * read / write. If is 0, generate one ecc irq each ecc step.
-- */
-- if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
-- reg_val |= ECC_PG_IRQ_SEL;
-- if (op == ECC_ENCODE)
-- writew(reg_val, ecc->regs +
-- ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-- else
-- writew(reg_val, ecc->regs +
-- ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-- }
--
-- writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
--
-- return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_enable);
--
--void mtk_ecc_disable(struct mtk_ecc *ecc)
--{
-- enum mtk_ecc_operation op = ECC_ENCODE;
--
-- /* find out the running operation */
-- if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
-- op = ECC_DECODE;
--
-- /* disable it */
-- mtk_ecc_wait_idle(ecc, op);
-- if (op == ECC_DECODE) {
-- /*
-- * Clear decode IRQ status in case there is a timeout to wait
-- * decode IRQ.
-- */
-- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-- } else {
-- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-- }
--
-- writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
--
-- mutex_unlock(&ecc->lock);
--}
--EXPORT_SYMBOL(mtk_ecc_disable);
--
--int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
--{
-- int ret;
--
-- ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
-- if (!ret) {
-- dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
-- (op == ECC_ENCODE) ? "encoder" : "decoder");
-- return -ETIMEDOUT;
-- }
--
-- return 0;
--}
--EXPORT_SYMBOL(mtk_ecc_wait_done);
--
--int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
-- u8 *data, u32 bytes)
--{
-- dma_addr_t addr;
-- u32 len;
-- int ret;
--
-- addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
-- ret = dma_mapping_error(ecc->dev, addr);
-- if (ret) {
-- dev_err(ecc->dev, "dma mapping error\n");
-- return -EINVAL;
-- }
--
-- config->op = ECC_ENCODE;
-- config->addr = addr;
-- ret = mtk_ecc_enable(ecc, config);
-- if (ret) {
-- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-- return ret;
-- }
--
-- ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
-- if (ret)
-- goto timeout;
--
-- mtk_ecc_wait_idle(ecc, ECC_ENCODE);
--
-- /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
-- len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
--
-- /* write the parity bytes generated by the ECC back to temp buffer */
-- __ioread32_copy(ecc->eccdata,
-- ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
-- round_up(len, 4));
--
-- /* copy into possibly unaligned OOB region with actual length */
-- memcpy(data + bytes, ecc->eccdata, len);
--timeout:
--
-- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-- mtk_ecc_disable(ecc);
--
-- return ret;
--}
--EXPORT_SYMBOL(mtk_ecc_encode);
--
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
--{
-- const u8 *ecc_strength = ecc->caps->ecc_strength;
-- int i;
--
-- for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-- if (*p <= ecc_strength[i]) {
-- if (!i)
-- *p = ecc_strength[i];
-- else if (*p != ecc_strength[i])
-- *p = ecc_strength[i - 1];
-- return;
-- }
-- }
--
-- *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
--}
--EXPORT_SYMBOL(mtk_ecc_adjust_strength);
--
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
--{
-- return ecc->caps->parity_bits;
--}
--EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-- .err_mask = 0x3f,
-- .err_shift = 8,
-- .ecc_strength = ecc_strength_mt2701,
-- .ecc_regs = mt2701_ecc_regs,
-- .num_ecc_strength = 20,
-- .ecc_mode_shift = 5,
-- .parity_bits = 14,
-- .pg_irq_sel = 0,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-- .err_mask = 0x7f,
-- .err_shift = 8,
-- .ecc_strength = ecc_strength_mt2712,
-- .ecc_regs = mt2712_ecc_regs,
-- .num_ecc_strength = 23,
-- .ecc_mode_shift = 5,
-- .parity_bits = 14,
-- .pg_irq_sel = 1,
--};
--
--static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-- .err_mask = 0x1f,
-- .err_shift = 5,
-- .ecc_strength = ecc_strength_mt7622,
-- .ecc_regs = mt7622_ecc_regs,
-- .num_ecc_strength = 5,
-- .ecc_mode_shift = 4,
-- .parity_bits = 13,
-- .pg_irq_sel = 0,
--};
--
--static const struct of_device_id mtk_ecc_dt_match[] = {
-- {
-- .compatible = "mediatek,mt2701-ecc",
-- .data = &mtk_ecc_caps_mt2701,
-- }, {
-- .compatible = "mediatek,mt2712-ecc",
-- .data = &mtk_ecc_caps_mt2712,
-- }, {
-- .compatible = "mediatek,mt7622-ecc",
-- .data = &mtk_ecc_caps_mt7622,
-- },
-- {},
--};
--
--static int mtk_ecc_probe(struct platform_device *pdev)
--{
-- struct device *dev = &pdev->dev;
-- struct mtk_ecc *ecc;
-- struct resource *res;
-- u32 max_eccdata_size;
-- int irq, ret;
--
-- ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
-- if (!ecc)
-- return -ENOMEM;
--
-- ecc->caps = of_device_get_match_data(dev);
--
-- max_eccdata_size = ecc->caps->num_ecc_strength - 1;
-- max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
-- max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
-- max_eccdata_size = round_up(max_eccdata_size, 4);
-- ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
-- if (!ecc->eccdata)
-- return -ENOMEM;
--
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- ecc->regs = devm_ioremap_resource(dev, res);
-- if (IS_ERR(ecc->regs))
-- return PTR_ERR(ecc->regs);
--
-- ecc->clk = devm_clk_get(dev, NULL);
-- if (IS_ERR(ecc->clk)) {
-- dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
-- return PTR_ERR(ecc->clk);
-- }
--
-- irq = platform_get_irq(pdev, 0);
-- if (irq < 0)
-- return irq;
--
-- ret = dma_set_mask(dev, DMA_BIT_MASK(32));
-- if (ret) {
-- dev_err(dev, "failed to set DMA mask\n");
-- return ret;
-- }
--
-- ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
-- if (ret) {
-- dev_err(dev, "failed to request irq\n");
-- return -EINVAL;
-- }
--
-- ecc->dev = dev;
-- mutex_init(&ecc->lock);
-- platform_set_drvdata(pdev, ecc);
-- dev_info(dev, "probed\n");
--
-- return 0;
--}
--
--#ifdef CONFIG_PM_SLEEP
--static int mtk_ecc_suspend(struct device *dev)
--{
-- struct mtk_ecc *ecc = dev_get_drvdata(dev);
--
-- clk_disable_unprepare(ecc->clk);
--
-- return 0;
--}
--
--static int mtk_ecc_resume(struct device *dev)
--{
-- struct mtk_ecc *ecc = dev_get_drvdata(dev);
-- int ret;
--
-- ret = clk_prepare_enable(ecc->clk);
-- if (ret) {
-- dev_err(dev, "failed to enable clk\n");
-- return ret;
-- }
--
-- return 0;
--}
--
--static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
--#endif
--
--MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
--
--static struct platform_driver mtk_ecc_driver = {
-- .probe = mtk_ecc_probe,
-- .driver = {
-- .name = "mtk-ecc",
-- .of_match_table = of_match_ptr(mtk_ecc_dt_match),
--#ifdef CONFIG_PM_SLEEP
-- .pm = &mtk_ecc_pm_ops,
--#endif
-- },
--};
--
--module_platform_driver(mtk_ecc_driver);
--
--MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
--MODULE_DESCRIPTION("MTK Nand ECC Driver");
--MODULE_LICENSE("Dual MIT/GPL");
---- /dev/null
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -0,0 +1,598 @@
-+// SPDX-License-Identifier: GPL-2.0 OR MIT
-+/*
-+ * MTK ECC controller driver.
-+ * Copyright (C) 2016 MediaTek Inc.
-+ * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
-+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <linux/module.h>
-+#include <linux/iopoll.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/mutex.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+
-+#define ECC_IDLE_MASK BIT(0)
-+#define ECC_IRQ_EN BIT(0)
-+#define ECC_PG_IRQ_SEL BIT(1)
-+#define ECC_OP_ENABLE (1)
-+#define ECC_OP_DISABLE (0)
-+
-+#define ECC_ENCCON (0x00)
-+#define ECC_ENCCNFG (0x04)
-+#define ECC_MS_SHIFT (16)
-+#define ECC_ENCDIADDR (0x08)
-+#define ECC_ENCIDLE (0x0C)
-+#define ECC_DECCON (0x100)
-+#define ECC_DECCNFG (0x104)
-+#define DEC_EMPTY_EN BIT(31)
-+#define DEC_CNFG_CORRECT (0x3 << 12)
-+#define ECC_DECIDLE (0x10C)
-+#define ECC_DECENUM0 (0x114)
-+
-+#define ECC_TIMEOUT (500000)
-+
-+#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
-+#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
-+
-+struct mtk_ecc_caps {
-+ u32 err_mask;
-+ u32 err_shift;
-+ const u8 *ecc_strength;
-+ const u32 *ecc_regs;
-+ u8 num_ecc_strength;
-+ u8 ecc_mode_shift;
-+ u32 parity_bits;
-+ int pg_irq_sel;
-+};
-+
-+struct mtk_ecc {
-+ struct device *dev;
-+ const struct mtk_ecc_caps *caps;
-+ void __iomem *regs;
-+ struct clk *clk;
-+
-+ struct completion done;
-+ struct mutex lock;
-+ u32 sectors;
-+
-+ u8 *eccdata;
-+};
-+
-+/* ecc strength that each IP supports */
-+static const u8 ecc_strength_mt2701[] = {
-+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+ 40, 44, 48, 52, 56, 60
-+};
-+
-+static const u8 ecc_strength_mt2712[] = {
-+ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
-+ 40, 44, 48, 52, 56, 60, 68, 72, 80
-+};
-+
-+static const u8 ecc_strength_mt7622[] = {
-+ 4, 6, 8, 10, 12
-+};
-+
-+enum mtk_ecc_regs {
-+ ECC_ENCPAR00,
-+ ECC_ENCIRQ_EN,
-+ ECC_ENCIRQ_STA,
-+ ECC_DECDONE,
-+ ECC_DECIRQ_EN,
-+ ECC_DECIRQ_STA,
-+};
-+
-+static int mt2701_ecc_regs[] = {
-+ [ECC_ENCPAR00] = 0x10,
-+ [ECC_ENCIRQ_EN] = 0x80,
-+ [ECC_ENCIRQ_STA] = 0x84,
-+ [ECC_DECDONE] = 0x124,
-+ [ECC_DECIRQ_EN] = 0x200,
-+ [ECC_DECIRQ_STA] = 0x204,
-+};
-+
-+static int mt2712_ecc_regs[] = {
-+ [ECC_ENCPAR00] = 0x300,
-+ [ECC_ENCIRQ_EN] = 0x80,
-+ [ECC_ENCIRQ_STA] = 0x84,
-+ [ECC_DECDONE] = 0x124,
-+ [ECC_DECIRQ_EN] = 0x200,
-+ [ECC_DECIRQ_STA] = 0x204,
-+};
-+
-+static int mt7622_ecc_regs[] = {
-+ [ECC_ENCPAR00] = 0x10,
-+ [ECC_ENCIRQ_EN] = 0x30,
-+ [ECC_ENCIRQ_STA] = 0x34,
-+ [ECC_DECDONE] = 0x11c,
-+ [ECC_DECIRQ_EN] = 0x140,
-+ [ECC_DECIRQ_STA] = 0x144,
-+};
-+
-+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
-+ enum mtk_ecc_operation op)
-+{
-+ struct device *dev = ecc->dev;
-+ u32 val;
-+ int ret;
-+
-+ ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
-+ val & ECC_IDLE_MASK,
-+ 10, ECC_TIMEOUT);
-+ if (ret)
-+ dev_warn(dev, "%s NOT idle\n",
-+ op == ECC_ENCODE ? "encoder" : "decoder");
-+}
-+
-+static irqreturn_t mtk_ecc_irq(int irq, void *id)
-+{
-+ struct mtk_ecc *ecc = id;
-+ u32 dec, enc;
-+
-+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
-+ & ECC_IRQ_EN;
-+ if (dec) {
-+ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+ if (dec & ecc->sectors) {
-+ /*
-+ * Clear decode IRQ status once again to ensure that
-+ * there will be no extra IRQ.
-+ */
-+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
-+ ecc->sectors = 0;
-+ complete(&ecc->done);
-+ } else {
-+ return IRQ_HANDLED;
-+ }
-+ } else {
-+ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
-+ & ECC_IRQ_EN;
-+ if (enc)
-+ complete(&ecc->done);
-+ else
-+ return IRQ_NONE;
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+ u32 ecc_bit, dec_sz, enc_sz;
-+ u32 reg, i;
-+
-+ for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+ if (ecc->caps->ecc_strength[i] == config->strength)
-+ break;
-+ }
-+
-+ if (i == ecc->caps->num_ecc_strength) {
-+ dev_err(ecc->dev, "invalid ecc strength %d\n",
-+ config->strength);
-+ return -EINVAL;
-+ }
-+
-+ ecc_bit = i;
-+
-+ if (config->op == ECC_ENCODE) {
-+ /* configure ECC encoder (in bits) */
-+ enc_sz = config->len << 3;
-+
-+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+ reg |= (enc_sz << ECC_MS_SHIFT);
-+ writel(reg, ecc->regs + ECC_ENCCNFG);
-+
-+ if (config->mode != ECC_NFI_MODE)
-+ writel(lower_32_bits(config->addr),
-+ ecc->regs + ECC_ENCDIADDR);
-+
-+ } else {
-+ /* configure ECC decoder (in bits) */
-+ dec_sz = (config->len << 3) +
-+ config->strength * ecc->caps->parity_bits;
-+
-+ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
-+ reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
-+ reg |= DEC_EMPTY_EN;
-+ writel(reg, ecc->regs + ECC_DECCNFG);
-+
-+ if (config->sectors)
-+ ecc->sectors = 1 << (config->sectors - 1);
-+ }
-+
-+ return 0;
-+}
-+
-+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
-+ int sectors)
-+{
-+ u32 offset, i, err;
-+ u32 bitflips = 0;
-+
-+ stats->corrected = 0;
-+ stats->failed = 0;
-+
-+ for (i = 0; i < sectors; i++) {
-+ offset = (i >> 2) << 2;
-+ err = readl(ecc->regs + ECC_DECENUM0 + offset);
-+ err = err >> ((i % 4) * ecc->caps->err_shift);
-+ err &= ecc->caps->err_mask;
-+ if (err == ecc->caps->err_mask) {
-+ /* uncorrectable errors */
-+ stats->failed++;
-+ continue;
-+ }
-+
-+ stats->corrected += err;
-+ bitflips = max_t(u32, bitflips, err);
-+ }
-+
-+ stats->bitflips = bitflips;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_stats);
-+
-+void mtk_ecc_release(struct mtk_ecc *ecc)
-+{
-+ clk_disable_unprepare(ecc->clk);
-+ put_device(ecc->dev);
-+}
-+EXPORT_SYMBOL(mtk_ecc_release);
-+
-+static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
-+{
-+ mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
-+
-+ mtk_ecc_wait_idle(ecc, ECC_DECODE);
-+ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
-+}
-+
-+static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
-+{
-+ struct platform_device *pdev;
-+ struct mtk_ecc *ecc;
-+
-+ pdev = of_find_device_by_node(np);
-+ if (!pdev)
-+ return ERR_PTR(-EPROBE_DEFER);
-+
-+ ecc = platform_get_drvdata(pdev);
-+ if (!ecc) {
-+ put_device(&pdev->dev);
-+ return ERR_PTR(-EPROBE_DEFER);
-+ }
-+
-+ clk_prepare_enable(ecc->clk);
-+ mtk_ecc_hw_init(ecc);
-+
-+ return ecc;
-+}
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
-+{
-+ struct mtk_ecc *ecc = NULL;
-+ struct device_node *np;
-+
-+ np = of_parse_phandle(of_node, "ecc-engine", 0);
-+ if (np) {
-+ ecc = mtk_ecc_get(np);
-+ of_node_put(np);
-+ }
-+
-+ return ecc;
-+}
-+EXPORT_SYMBOL(of_mtk_ecc_get);
-+
-+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
-+{
-+ enum mtk_ecc_operation op = config->op;
-+ u16 reg_val;
-+ int ret;
-+
-+ ret = mutex_lock_interruptible(&ecc->lock);
-+ if (ret) {
-+ dev_err(ecc->dev, "interrupted when attempting to lock\n");
-+ return ret;
-+ }
-+
-+ mtk_ecc_wait_idle(ecc, op);
-+
-+ ret = mtk_ecc_config(ecc, config);
-+ if (ret) {
-+ mutex_unlock(&ecc->lock);
-+ return ret;
-+ }
-+
-+ if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
-+ init_completion(&ecc->done);
-+ reg_val = ECC_IRQ_EN;
-+ /*
-+ * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
-+ * means this chip can only generate one ecc irq during page
-+ * read / write. If is 0, generate one ecc irq each ecc step.
-+ */
-+ if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
-+ reg_val |= ECC_PG_IRQ_SEL;
-+ if (op == ECC_ENCODE)
-+ writew(reg_val, ecc->regs +
-+ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+ else
-+ writew(reg_val, ecc->regs +
-+ ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+ }
-+
-+ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_enable);
-+
-+void mtk_ecc_disable(struct mtk_ecc *ecc)
-+{
-+ enum mtk_ecc_operation op = ECC_ENCODE;
-+
-+ /* find out the running operation */
-+ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
-+ op = ECC_DECODE;
-+
-+ /* disable it */
-+ mtk_ecc_wait_idle(ecc, op);
-+ if (op == ECC_DECODE) {
-+ /*
-+ * Clear decode IRQ status in case there is a timeout to wait
-+ * decode IRQ.
-+ */
-+ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
-+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
-+ } else {
-+ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
-+ }
-+
-+ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
-+
-+ mutex_unlock(&ecc->lock);
-+}
-+EXPORT_SYMBOL(mtk_ecc_disable);
-+
-+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
-+{
-+ int ret;
-+
-+ ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
-+ if (!ret) {
-+ dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
-+ (op == ECC_ENCODE) ? "encoder" : "decoder");
-+ return -ETIMEDOUT;
-+ }
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(mtk_ecc_wait_done);
-+
-+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
-+ u8 *data, u32 bytes)
-+{
-+ dma_addr_t addr;
-+ u32 len;
-+ int ret;
-+
-+ addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
-+ ret = dma_mapping_error(ecc->dev, addr);
-+ if (ret) {
-+ dev_err(ecc->dev, "dma mapping error\n");
-+ return -EINVAL;
-+ }
-+
-+ config->op = ECC_ENCODE;
-+ config->addr = addr;
-+ ret = mtk_ecc_enable(ecc, config);
-+ if (ret) {
-+ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+ return ret;
-+ }
-+
-+ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
-+ if (ret)
-+ goto timeout;
-+
-+ mtk_ecc_wait_idle(ecc, ECC_ENCODE);
-+
-+ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
-+ len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
-+
-+ /* write the parity bytes generated by the ECC back to temp buffer */
-+ __ioread32_copy(ecc->eccdata,
-+ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
-+ round_up(len, 4));
-+
-+ /* copy into possibly unaligned OOB region with actual length */
-+ memcpy(data + bytes, ecc->eccdata, len);
-+timeout:
-+
-+ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
-+ mtk_ecc_disable(ecc);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(mtk_ecc_encode);
-+
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
-+{
-+ const u8 *ecc_strength = ecc->caps->ecc_strength;
-+ int i;
-+
-+ for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
-+ if (*p <= ecc_strength[i]) {
-+ if (!i)
-+ *p = ecc_strength[i];
-+ else if (*p != ecc_strength[i])
-+ *p = ecc_strength[i - 1];
-+ return;
-+ }
-+ }
-+
-+ *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
-+}
-+EXPORT_SYMBOL(mtk_ecc_adjust_strength);
-+
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
-+{
-+ return ecc->caps->parity_bits;
-+}
-+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
-+ .err_mask = 0x3f,
-+ .err_shift = 8,
-+ .ecc_strength = ecc_strength_mt2701,
-+ .ecc_regs = mt2701_ecc_regs,
-+ .num_ecc_strength = 20,
-+ .ecc_mode_shift = 5,
-+ .parity_bits = 14,
-+ .pg_irq_sel = 0,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
-+ .err_mask = 0x7f,
-+ .err_shift = 8,
-+ .ecc_strength = ecc_strength_mt2712,
-+ .ecc_regs = mt2712_ecc_regs,
-+ .num_ecc_strength = 23,
-+ .ecc_mode_shift = 5,
-+ .parity_bits = 14,
-+ .pg_irq_sel = 1,
-+};
-+
-+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
-+ .err_mask = 0x1f,
-+ .err_shift = 5,
-+ .ecc_strength = ecc_strength_mt7622,
-+ .ecc_regs = mt7622_ecc_regs,
-+ .num_ecc_strength = 5,
-+ .ecc_mode_shift = 4,
-+ .parity_bits = 13,
-+ .pg_irq_sel = 0,
-+};
-+
-+static const struct of_device_id mtk_ecc_dt_match[] = {
-+ {
-+ .compatible = "mediatek,mt2701-ecc",
-+ .data = &mtk_ecc_caps_mt2701,
-+ }, {
-+ .compatible = "mediatek,mt2712-ecc",
-+ .data = &mtk_ecc_caps_mt2712,
-+ }, {
-+ .compatible = "mediatek,mt7622-ecc",
-+ .data = &mtk_ecc_caps_mt7622,
-+ },
-+ {},
-+};
-+
-+static int mtk_ecc_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct mtk_ecc *ecc;
-+ struct resource *res;
-+ u32 max_eccdata_size;
-+ int irq, ret;
-+
-+ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
-+ if (!ecc)
-+ return -ENOMEM;
-+
-+ ecc->caps = of_device_get_match_data(dev);
-+
-+ max_eccdata_size = ecc->caps->num_ecc_strength - 1;
-+ max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
-+ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
-+ max_eccdata_size = round_up(max_eccdata_size, 4);
-+ ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
-+ if (!ecc->eccdata)
-+ return -ENOMEM;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ ecc->regs = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(ecc->regs))
-+ return PTR_ERR(ecc->regs);
-+
-+ ecc->clk = devm_clk_get(dev, NULL);
-+ if (IS_ERR(ecc->clk)) {
-+ dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
-+ return PTR_ERR(ecc->clk);
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return irq;
-+
-+ ret = dma_set_mask(dev, DMA_BIT_MASK(32));
-+ if (ret) {
-+ dev_err(dev, "failed to set DMA mask\n");
-+ return ret;
-+ }
-+
-+ ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
-+ if (ret) {
-+ dev_err(dev, "failed to request irq\n");
-+ return -EINVAL;
-+ }
-+
-+ ecc->dev = dev;
-+ mutex_init(&ecc->lock);
-+ platform_set_drvdata(pdev, ecc);
-+ dev_info(dev, "probed\n");
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int mtk_ecc_suspend(struct device *dev)
-+{
-+ struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+
-+ clk_disable_unprepare(ecc->clk);
-+
-+ return 0;
-+}
-+
-+static int mtk_ecc_resume(struct device *dev)
-+{
-+ struct mtk_ecc *ecc = dev_get_drvdata(dev);
-+ int ret;
-+
-+ ret = clk_prepare_enable(ecc->clk);
-+ if (ret) {
-+ dev_err(dev, "failed to enable clk\n");
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
-+#endif
-+
-+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
-+
-+static struct platform_driver mtk_ecc_driver = {
-+ .probe = mtk_ecc_probe,
-+ .driver = {
-+ .name = "mtk-ecc",
-+ .of_match_table = of_match_ptr(mtk_ecc_dt_match),
-+#ifdef CONFIG_PM_SLEEP
-+ .pm = &mtk_ecc_pm_ops,
-+#endif
-+ },
-+};
-+
-+module_platform_driver(mtk_ecc_driver);
-+
-+MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
-+MODULE_DESCRIPTION("MTK Nand ECC Driver");
-+MODULE_LICENSE("Dual MIT/GPL");
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -360,6 +360,7 @@ config MTD_NAND_QCOM
-
- config MTD_NAND_MTK
- tristate "MTK NAND controller"
-+ depends on MTD_NAND_ECC_MEDIATEK
- depends on ARCH_MEDIATEK || COMPILE_TEST
- depends on HAS_IOMEM
- help
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
--obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
-+obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
- obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o
---- a/drivers/mtd/nand/raw/mtk_nand.c
-+++ b/drivers/mtd/nand/raw/mtk_nand.c
-@@ -17,7 +17,7 @@
- #include <linux/iopoll.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
--#include "mtk_ecc.h"
-+#include <linux/mtd/nand-ecc-mtk.h>
-
- /* NAND controller register definition */
- #define NFI_CNFG (0x00)
---- a/drivers/mtd/nand/raw/mtk_ecc.h
-+++ /dev/null
-@@ -1,47 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 OR MIT */
--/*
-- * MTK SDG1 ECC controller
-- *
-- * Copyright (c) 2016 Mediatek
-- * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
-- * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-- */
--
--#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
--#define __DRIVERS_MTD_NAND_MTK_ECC_H__
--
--#include <linux/types.h>
--
--enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
--enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
--
--struct device_node;
--struct mtk_ecc;
--
--struct mtk_ecc_stats {
-- u32 corrected;
-- u32 bitflips;
-- u32 failed;
--};
--
--struct mtk_ecc_config {
-- enum mtk_ecc_operation op;
-- enum mtk_ecc_mode mode;
-- dma_addr_t addr;
-- u32 strength;
-- u32 sectors;
-- u32 len;
--};
--
--int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
--void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
--int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
--int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
--void mtk_ecc_disable(struct mtk_ecc *);
--void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
--unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
--
--struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
--void mtk_ecc_release(struct mtk_ecc *);
--
--#endif
---- /dev/null
-+++ b/include/linux/mtd/nand-ecc-mtk.h
-@@ -0,0 +1,47 @@
-+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-+/*
-+ * MTK SDG1 ECC controller
-+ *
-+ * Copyright (c) 2016 Mediatek
-+ * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
-+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-+ */
-+
-+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
-+#define __DRIVERS_MTD_NAND_MTK_ECC_H__
-+
-+#include <linux/types.h>
-+
-+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
-+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
-+
-+struct device_node;
-+struct mtk_ecc;
-+
-+struct mtk_ecc_stats {
-+ u32 corrected;
-+ u32 bitflips;
-+ u32 failed;
-+};
-+
-+struct mtk_ecc_config {
-+ enum mtk_ecc_operation op;
-+ enum mtk_ecc_mode mode;
-+ dma_addr_t addr;
-+ u32 strength;
-+ u32 sectors;
-+ u32 len;
-+};
-+
-+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
-+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
-+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
-+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
-+void mtk_ecc_disable(struct mtk_ecc *);
-+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
-+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
-+
-+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
-+void mtk_ecc_release(struct mtk_ecc *);
-+
-+#endif
+++ /dev/null
-From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Sat, 2 Apr 2022 10:16:11 +0800
-Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface
-
-This driver implements support for the SPI-NAND mode of MTK NAND Flash
-Interface as a SPI-MEM controller with pipelined ECC capability.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
----
-Change since v1:
- fix CI warnings
-
-Changes since v2:
- use streamed DMA api to avoid an extra memory copy during read
- make ECC engine config a per-nand context
- take user-requested ECC strength into account
-
-Change since v3: none
-Changes since v4:
- fix missing OOB write
- print page format with dev_dbg
- replace uint*_t copied from vendor driver with u*
-
-Changes since v5:
- add missing nfi mode register configuration in probe
- fix an off-by-one bug in mtk_snand_mac_io
-
- drivers/spi/Kconfig | 10 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1481 insertions(+)
- create mode 100644 drivers/spi/spi-mtk-snfi.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -529,6 +529,16 @@ config SPI_MTK_NOR
- SPI interface as well as several SPI NOR specific instructions
- via SPI MEM interface.
-
-+config SPI_MTK_SNFI
-+ tristate "MediaTek SPI NAND Flash Interface"
-+ depends on ARCH_MEDIATEK || COMPILE_TEST
-+ depends on MTD_NAND_ECC_MEDIATEK
-+ help
-+ This enables support for SPI-NAND mode on the MediaTek NAND
-+ Flash Interface found on MediaTek ARM SoCs. This controller
-+ is implemented as a SPI-MEM controller with pipelined ECC
-+ capcability.
-+
- config SPI_NPCM_FIU
- tristate "Nuvoton NPCM FLASH Interface Unit"
- depends on ARCH_NPCM || COMPILE_TEST
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52x
- obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
- obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
- obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o
-+obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o
- obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
- obj-$(CONFIG_SPI_MXS) += spi-mxs.o
- obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o
---- /dev/null
-+++ b/drivers/spi/spi-mtk-snfi.c
-@@ -0,0 +1,1470 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface
-+//
-+// Copyright (c) 2022 Chuanhong Guo <gch981213@gmail.com>
-+//
-+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK:
-+//
-+// Copyright (C) 2020 MediaTek Inc.
-+// Author: Weijie Gao <weijie.gao@mediatek.com>
-+//
-+// This controller organize the page data as several interleaved sectors
-+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size)
-+// +---------+------+------+---------+------+------+-----+
-+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... |
-+// +---------+------+------+---------+------+------+-----+
-+// With auto-format turned on, DMA only returns this part:
-+// +---------+---------+-----+
-+// | Sector1 | Sector2 | ... |
-+// +---------+---------+-----+
-+// The FDM data will be filled to the registers, and ECC parity data isn't
-+// accessible.
-+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA
-+// in it's original order shown in the first table. ECC can't be turned on when
-+// auto-format is off.
-+//
-+// However, Linux SPI-NAND driver expects the data returned as:
-+// +------+-----+
-+// | Page | OOB |
-+// +------+-----+
-+// where the page data is continuously stored instead of interleaved.
-+// So we assume all instructions matching the page_op template between ECC
-+// prepare_io_req and finish_io_req are for page cache r/w.
-+// Here's how this spi-mem driver operates when reading:
-+// 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off).
-+// 2. Perform page ops and let the controller fill the DMA bounce buffer with
-+// de-interleaved sector data and set FDM registers.
-+// 3. Return the data as:
-+// +---------+---------+-----+------+------+-----+
-+// | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... |
-+// +---------+---------+-----+------+------+-----+
-+// 4. For other matching spi_mem ops outside a prepare/finish_io_req pair,
-+// read the data with auto-format off into the bounce buffer and copy
-+// needed data to the buffer specified in the request.
-+//
-+// Write requests operates in a similar manner.
-+// As a limitation of this strategy, we won't be able to access any ECC parity
-+// data at all in Linux.
-+//
-+// Here's the bad block mark situation on MTK chips:
-+// In older chips like mt7622, MTK uses the first FDM byte in the first sector
-+// as the bad block mark. After de-interleaving, this byte appears at [pagesize]
-+// in the returned data, which is the BBM position expected by kernel. However,
-+// the conventional bad block mark is the first byte of the OOB, which is part
-+// of the last sector data in the interleaved layout. Instead of fixing their
-+// hardware, MTK decided to address this inconsistency in software. On these
-+// later chips, the BootROM expects the following:
-+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at
-+// (page_size - (nsectors - 1) * spare_size) in the DMA buffer.
-+// 2. The original byte stored at that position in the DMA buffer will be stored
-+// as the first byte of the FDM section in the last sector.
-+// We can't disagree with the BootROM, so after de-interleaving, we need to
-+// perform the following swaps in read:
-+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size],
-+// which is the expected BBM position by kernel.
-+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to
-+// [page_size - (nsectors - 1) * spare_size]
-+// Similarly, when writing, we need to perform swaps in the other direction.
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/mutex.h>
-+#include <linux/clk.h>
-+#include <linux/interrupt.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/iopoll.h>
-+#include <linux/of_platform.h>
-+#include <linux/mtd/nand-ecc-mtk.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
-+#include <linux/mtd/nand.h>
-+
-+// NFI registers
-+#define NFI_CNFG 0x000
-+#define CNFG_OP_MODE_S 12
-+#define CNFG_OP_MODE_CUST 6
-+#define CNFG_OP_MODE_PROGRAM 3
-+#define CNFG_AUTO_FMT_EN BIT(9)
-+#define CNFG_HW_ECC_EN BIT(8)
-+#define CNFG_DMA_BURST_EN BIT(2)
-+#define CNFG_READ_MODE BIT(1)
-+#define CNFG_DMA_MODE BIT(0)
-+
-+#define NFI_PAGEFMT 0x0004
-+#define NFI_SPARE_SIZE_LS_S 16
-+#define NFI_FDM_ECC_NUM_S 12
-+#define NFI_FDM_NUM_S 8
-+#define NFI_SPARE_SIZE_S 4
-+#define NFI_SEC_SEL_512 BIT(2)
-+#define NFI_PAGE_SIZE_S 0
-+#define NFI_PAGE_SIZE_512_2K 0
-+#define NFI_PAGE_SIZE_2K_4K 1
-+#define NFI_PAGE_SIZE_4K_8K 2
-+#define NFI_PAGE_SIZE_8K_16K 3
-+
-+#define NFI_CON 0x008
-+#define CON_SEC_NUM_S 12
-+#define CON_BWR BIT(9)
-+#define CON_BRD BIT(8)
-+#define CON_NFI_RST BIT(1)
-+#define CON_FIFO_FLUSH BIT(0)
-+
-+#define NFI_INTR_EN 0x010
-+#define NFI_INTR_STA 0x014
-+#define NFI_IRQ_INTR_EN BIT(31)
-+#define NFI_IRQ_CUS_READ BIT(8)
-+#define NFI_IRQ_CUS_PG BIT(7)
-+
-+#define NFI_CMD 0x020
-+#define NFI_CMD_DUMMY_READ 0x00
-+#define NFI_CMD_DUMMY_WRITE 0x80
-+
-+#define NFI_STRDATA 0x040
-+#define STR_DATA BIT(0)
-+
-+#define NFI_STA 0x060
-+#define NFI_NAND_FSM GENMASK(28, 24)
-+#define NFI_FSM GENMASK(19, 16)
-+#define READ_EMPTY BIT(12)
-+
-+#define NFI_FIFOSTA 0x064
-+#define FIFO_WR_REMAIN_S 8
-+#define FIFO_RD_REMAIN_S 0
-+
-+#define NFI_ADDRCNTR 0x070
-+#define SEC_CNTR GENMASK(16, 12)
-+#define SEC_CNTR_S 12
-+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_STRADDR 0x080
-+
-+#define NFI_BYTELEN 0x084
-+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)
-+
-+#define NFI_FDM0L 0x0a0
-+#define NFI_FDM0M 0x0a4
-+#define NFI_FDML(n) (NFI_FDM0L + (n)*8)
-+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8)
-+
-+#define NFI_DEBUG_CON1 0x220
-+#define WBUF_EN BIT(2)
-+
-+#define NFI_MASTERSTA 0x224
-+#define MAS_ADDR GENMASK(11, 9)
-+#define MAS_RD GENMASK(8, 6)
-+#define MAS_WR GENMASK(5, 3)
-+#define MAS_RDDLY GENMASK(2, 0)
-+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
-+
-+// SNFI registers
-+#define SNF_MAC_CTL 0x500
-+#define MAC_XIO_SEL BIT(4)
-+#define SF_MAC_EN BIT(3)
-+#define SF_TRIG BIT(2)
-+#define WIP_READY BIT(1)
-+#define WIP BIT(0)
-+
-+#define SNF_MAC_OUTL 0x504
-+#define SNF_MAC_INL 0x508
-+
-+#define SNF_RD_CTL2 0x510
-+#define DATA_READ_DUMMY_S 8
-+#define DATA_READ_MAX_DUMMY 0xf
-+#define DATA_READ_CMD_S 0
-+
-+#define SNF_RD_CTL3 0x514
-+
-+#define SNF_PG_CTL1 0x524
-+#define PG_LOAD_CMD_S 8
-+
-+#define SNF_PG_CTL2 0x528
-+
-+#define SNF_MISC_CTL 0x538
-+#define SW_RST BIT(28)
-+#define FIFO_RD_LTC_S 25
-+#define PG_LOAD_X4_EN BIT(20)
-+#define DATA_READ_MODE_S 16
-+#define DATA_READ_MODE GENMASK(18, 16)
-+#define DATA_READ_MODE_X1 0
-+#define DATA_READ_MODE_X2 1
-+#define DATA_READ_MODE_X4 2
-+#define DATA_READ_MODE_DUAL 5
-+#define DATA_READ_MODE_QUAD 6
-+#define PG_LOAD_CUSTOM_EN BIT(7)
-+#define DATARD_CUSTOM_EN BIT(6)
-+#define CS_DESELECT_CYC_S 0
-+
-+#define SNF_MISC_CTL2 0x53c
-+#define PROGRAM_LOAD_BYTE_NUM_S 16
-+#define READ_DATA_BYTE_NUM_S 11
-+
-+#define SNF_DLY_CTL3 0x548
-+#define SFCK_SAM_DLY_S 0
-+
-+#define SNF_STA_CTL1 0x550
-+#define CUS_PG_DONE BIT(28)
-+#define CUS_READ_DONE BIT(27)
-+#define SPI_STATE_S 0
-+#define SPI_STATE GENMASK(3, 0)
-+
-+#define SNF_CFG 0x55c
-+#define SPI_MODE BIT(0)
-+
-+#define SNF_GPRAM 0x800
-+#define SNF_GPRAM_SIZE 0xa0
-+
-+#define SNFI_POLL_INTERVAL 1000000
-+
-+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
-+
-+struct mtk_snand_caps {
-+ u16 sector_size;
-+ u16 max_sectors;
-+ u16 fdm_size;
-+ u16 fdm_ecc_size;
-+ u16 fifo_size;
-+
-+ bool bbm_swap;
-+ bool empty_page_check;
-+ u32 mastersta_mask;
-+
-+ const u8 *spare_sizes;
-+ u32 num_spare_size;
-+};
-+
-+static const struct mtk_snand_caps mt7622_snand_caps = {
-+ .sector_size = 512,
-+ .max_sectors = 8,
-+ .fdm_size = 8,
-+ .fdm_ecc_size = 1,
-+ .fifo_size = 32,
-+ .bbm_swap = false,
-+ .empty_page_check = false,
-+ .mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+ .spare_sizes = mt7622_spare_sizes,
-+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+static const struct mtk_snand_caps mt7629_snand_caps = {
-+ .sector_size = 512,
-+ .max_sectors = 8,
-+ .fdm_size = 8,
-+ .fdm_ecc_size = 1,
-+ .fifo_size = 32,
-+ .bbm_swap = true,
-+ .empty_page_check = false,
-+ .mastersta_mask = NFI_MASTERSTA_MASK_7622,
-+ .spare_sizes = mt7622_spare_sizes,
-+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
-+};
-+
-+struct mtk_snand_conf {
-+ size_t page_size;
-+ size_t oob_size;
-+ u8 nsectors;
-+ u8 spare_size;
-+};
-+
-+struct mtk_snand {
-+ struct spi_controller *ctlr;
-+ struct device *dev;
-+ struct clk *nfi_clk;
-+ struct clk *pad_clk;
-+ void __iomem *nfi_base;
-+ int irq;
-+ struct completion op_done;
-+ const struct mtk_snand_caps *caps;
-+ struct mtk_ecc_config *ecc_cfg;
-+ struct mtk_ecc *ecc;
-+ struct mtk_snand_conf nfi_cfg;
-+ struct mtk_ecc_stats ecc_stats;
-+ struct nand_ecc_engine ecc_eng;
-+ bool autofmt;
-+ u8 *buf;
-+ size_t buf_len;
-+};
-+
-+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand)
-+{
-+ struct nand_ecc_engine *eng = nand->ecc.engine;
-+
-+ return container_of(eng, struct mtk_snand, ecc_eng);
-+}
-+
-+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size)
-+{
-+ if (snf->buf_len >= size)
-+ return 0;
-+ kfree(snf->buf);
-+ snf->buf = kmalloc(size, GFP_KERNEL);
-+ if (!snf->buf)
-+ return -ENOMEM;
-+ snf->buf_len = size;
-+ memset(snf->buf, 0xff, snf->buf_len);
-+ return 0;
-+}
-+
-+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg)
-+{
-+ return readl(snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val)
-+{
-+ writel(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val)
-+{
-+ writew(val, snf->nfi_base + reg);
-+}
-+
-+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set)
-+{
-+ u32 val;
-+
-+ val = readl(snf->nfi_base + reg);
-+ val &= ~clr;
-+ val |= set;
-+ writel(val, snf->nfi_base + reg);
-+}
-+
-+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len)
-+{
-+ u32 i, val = 0, es = sizeof(u32);
-+
-+ for (i = reg; i < reg + len; i++) {
-+ if (i == reg || i % es == 0)
-+ val = nfi_read32(snf, i & ~(es - 1));
-+
-+ *data++ = (u8)(val >> (8 * (i % es)));
-+ }
-+}
-+
-+static int mtk_nfi_reset(struct mtk_snand *snf)
-+{
-+ u32 val, fifo_mask;
-+ int ret;
-+
-+ nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);
-+
-+ ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+ !(val & snf->caps->mastersta_mask), 0,
-+ SNFI_POLL_INTERVAL);
-+ if (ret) {
-+ dev_err(snf->dev, "NFI master is still busy after reset\n");
-+ return ret;
-+ }
-+
-+ ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
-+ !(val & (NFI_FSM | NFI_NAND_FSM)), 0,
-+ SNFI_POLL_INTERVAL);
-+ if (ret) {
-+ dev_err(snf->dev, "Failed to reset NFI\n");
-+ return ret;
-+ }
-+
-+ fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) |
-+ ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S);
-+ ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,
-+ !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);
-+ if (ret) {
-+ dev_err(snf->dev, "NFI FIFOs are not empty\n");
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_snand_mac_reset(struct mtk_snand *snf)
-+{
-+ int ret;
-+ u32 val;
-+
-+ nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);
-+
-+ ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,
-+ !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);
-+ if (ret)
-+ dev_err(snf->dev, "Failed to reset SNFI MAC\n");
-+
-+ nfi_write32(snf, SNF_MISC_CTL,
-+ (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S));
-+
-+ return ret;
-+}
-+
-+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen)
-+{
-+ int ret;
-+ u32 val;
-+
-+ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);
-+ nfi_write32(snf, SNF_MAC_OUTL, outlen);
-+ nfi_write32(snf, SNF_MAC_INL, inlen);
-+
-+ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);
-+
-+ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,
-+ val & WIP_READY, 0, SNFI_POLL_INTERVAL);
-+ if (ret) {
-+ dev_err(snf->dev, "Timed out waiting for WIP_READY\n");
-+ goto cleanup;
-+ }
-+
-+ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP),
-+ 0, SNFI_POLL_INTERVAL);
-+ if (ret)
-+ dev_err(snf->dev, "Timed out waiting for WIP cleared\n");
-+
-+cleanup:
-+ nfi_write32(snf, SNF_MAC_CTL, 0);
-+
-+ return ret;
-+}
-+
-+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op)
-+{
-+ u32 rx_len = 0;
-+ u32 reg_offs = 0;
-+ u32 val = 0;
-+ const u8 *tx_buf = NULL;
-+ u8 *rx_buf = NULL;
-+ int i, ret;
-+ u8 b;
-+
-+ if (op->data.dir == SPI_MEM_DATA_IN) {
-+ rx_len = op->data.nbytes;
-+ rx_buf = op->data.buf.in;
-+ } else {
-+ tx_buf = op->data.buf.out;
-+ }
-+
-+ mtk_snand_mac_reset(snf);
-+
-+ for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) {
-+ b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff;
-+ val |= b << (8 * (reg_offs % 4));
-+ if (reg_offs % 4 == 3) {
-+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+ val = 0;
-+ }
-+ }
-+
-+ for (i = 0; i < op->addr.nbytes; i++, reg_offs++) {
-+ b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff;
-+ val |= b << (8 * (reg_offs % 4));
-+ if (reg_offs % 4 == 3) {
-+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+ val = 0;
-+ }
-+ }
-+
-+ for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) {
-+ if (reg_offs % 4 == 3) {
-+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+ val = 0;
-+ }
-+ }
-+
-+ if (op->data.dir == SPI_MEM_DATA_OUT) {
-+ for (i = 0; i < op->data.nbytes; i++, reg_offs++) {
-+ val |= tx_buf[i] << (8 * (reg_offs % 4));
-+ if (reg_offs % 4 == 3) {
-+ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);
-+ val = 0;
-+ }
-+ }
-+ }
-+
-+ if (reg_offs % 4)
-+ nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val);
-+
-+ for (i = 0; i < reg_offs; i += 4)
-+ dev_dbg(snf->dev, "%d: %08X", i,
-+ nfi_read32(snf, SNF_GPRAM + i));
-+
-+ dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len);
-+
-+ ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len);
-+ if (ret)
-+ return ret;
-+
-+ if (!rx_len)
-+ return 0;
-+
-+ nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len);
-+ return 0;
-+}
-+
-+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size,
-+ u32 oob_size)
-+{
-+ int spare_idx = -1;
-+ u32 spare_size, spare_size_shift, pagesize_idx;
-+ u32 sector_size_512;
-+ u8 nsectors;
-+ int i;
-+
-+ // skip if it's already configured as required.
-+ if (snf->nfi_cfg.page_size == page_size &&
-+ snf->nfi_cfg.oob_size == oob_size)
-+ return 0;
-+
-+ nsectors = page_size / snf->caps->sector_size;
-+ if (nsectors > snf->caps->max_sectors) {
-+ dev_err(snf->dev, "too many sectors required.\n");
-+ goto err;
-+ }
-+
-+ if (snf->caps->sector_size == 512) {
-+ sector_size_512 = NFI_SEC_SEL_512;
-+ spare_size_shift = NFI_SPARE_SIZE_S;
-+ } else {
-+ sector_size_512 = 0;
-+ spare_size_shift = NFI_SPARE_SIZE_LS_S;
-+ }
-+
-+ switch (page_size) {
-+ case SZ_512:
-+ pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+ break;
-+ case SZ_2K:
-+ if (snf->caps->sector_size == 512)
-+ pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+ else
-+ pagesize_idx = NFI_PAGE_SIZE_512_2K;
-+ break;
-+ case SZ_4K:
-+ if (snf->caps->sector_size == 512)
-+ pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+ else
-+ pagesize_idx = NFI_PAGE_SIZE_2K_4K;
-+ break;
-+ case SZ_8K:
-+ if (snf->caps->sector_size == 512)
-+ pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+ else
-+ pagesize_idx = NFI_PAGE_SIZE_4K_8K;
-+ break;
-+ case SZ_16K:
-+ pagesize_idx = NFI_PAGE_SIZE_8K_16K;
-+ break;
-+ default:
-+ dev_err(snf->dev, "unsupported page size.\n");
-+ goto err;
-+ }
-+
-+ spare_size = oob_size / nsectors;
-+ // If we're using the 1KB sector size, HW will automatically double the
-+ // spare size. We should only use half of the value in this case.
-+ if (snf->caps->sector_size == 1024)
-+ spare_size /= 2;
-+
-+ for (i = snf->caps->num_spare_size - 1; i >= 0; i--) {
-+ if (snf->caps->spare_sizes[i] <= spare_size) {
-+ spare_size = snf->caps->spare_sizes[i];
-+ if (snf->caps->sector_size == 1024)
-+ spare_size *= 2;
-+ spare_idx = i;
-+ break;
-+ }
-+ }
-+
-+ if (spare_idx < 0) {
-+ dev_err(snf->dev, "unsupported spare size: %u\n", spare_size);
-+ goto err;
-+ }
-+
-+ nfi_write32(snf, NFI_PAGEFMT,
-+ (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |
-+ (snf->caps->fdm_size << NFI_FDM_NUM_S) |
-+ (spare_idx << spare_size_shift) |
-+ (pagesize_idx << NFI_PAGE_SIZE_S) |
-+ sector_size_512);
-+
-+ snf->nfi_cfg.page_size = page_size;
-+ snf->nfi_cfg.oob_size = oob_size;
-+ snf->nfi_cfg.nsectors = nsectors;
-+ snf->nfi_cfg.spare_size = spare_size;
-+
-+ dev_dbg(snf->dev, "page format: (%u + %u) * %u\n",
-+ snf->caps->sector_size, spare_size, nsectors);
-+ return snand_prepare_bouncebuf(snf, page_size + oob_size);
-+err:
-+ dev_err(snf->dev, "page size %u + %u is not supported\n", page_size,
-+ oob_size);
-+ return -EOPNOTSUPP;
-+}
-+
-+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobecc)
-+{
-+ // ECC area is not accessible
-+ return -ERANGE;
-+}
-+
-+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobfree)
-+{
-+ struct nand_device *nand = mtd_to_nanddev(mtd);
-+ struct mtk_snand *ms = nand_to_mtk_snand(nand);
-+
-+ if (section >= ms->nfi_cfg.nsectors)
-+ return -ERANGE;
-+
-+ oobfree->length = ms->caps->fdm_size - 1;
-+ oobfree->offset = section * ms->caps->fdm_size + 1;
-+ return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {
-+ .ecc = mtk_snand_ooblayout_ecc,
-+ .free = mtk_snand_ooblayout_free,
-+};
-+
-+static int mtk_snand_ecc_init_ctx(struct nand_device *nand)
-+{
-+ struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
-+ struct nand_ecc_props *reqs = &nand->ecc.requirements;
-+ struct nand_ecc_props *user = &nand->ecc.user_conf;
-+ struct mtd_info *mtd = nanddev_to_mtd(nand);
-+ int step_size = 0, strength = 0, desired_correction = 0, steps;
-+ bool ecc_user = false;
-+ int ret;
-+ u32 parity_bits, max_ecc_bytes;
-+ struct mtk_ecc_config *ecc_cfg;
-+
-+ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+ nand->memorg.oobsize);
-+ if (ret)
-+ return ret;
-+
-+ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
-+ if (!ecc_cfg)
-+ return -ENOMEM;
-+
-+ nand->ecc.ctx.priv = ecc_cfg;
-+
-+ if (user->step_size && user->strength) {
-+ step_size = user->step_size;
-+ strength = user->strength;
-+ ecc_user = true;
-+ } else if (reqs->step_size && reqs->strength) {
-+ step_size = reqs->step_size;
-+ strength = reqs->strength;
-+ }
-+
-+ if (step_size && strength) {
-+ steps = mtd->writesize / step_size;
-+ desired_correction = steps * strength;
-+ strength = desired_correction / snf->nfi_cfg.nsectors;
-+ }
-+
-+ ecc_cfg->mode = ECC_NFI_MODE;
-+ ecc_cfg->sectors = snf->nfi_cfg.nsectors;
-+ ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;
-+
-+ // calculate the max possible strength under current page format
-+ parity_bits = mtk_ecc_get_parity_bits(snf->ecc);
-+ max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;
-+ ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;
-+ mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);
-+
-+ // if there's a user requested strength, find the minimum strength that
-+ // meets the requirement. Otherwise use the maximum strength which is
-+ // expected by BootROM.
-+ if (ecc_user && strength) {
-+ u32 s_next = ecc_cfg->strength - 1;
-+
-+ while (1) {
-+ mtk_ecc_adjust_strength(snf->ecc, &s_next);
-+ if (s_next >= ecc_cfg->strength)
-+ break;
-+ if (s_next < strength)
-+ break;
-+ s_next = ecc_cfg->strength - 1;
-+ }
-+ }
-+
-+ mtd_set_ooblayout(mtd, &mtk_snand_ooblayout);
-+
-+ conf->step_size = snf->caps->sector_size;
-+ conf->strength = ecc_cfg->strength;
-+
-+ if (ecc_cfg->strength < strength)
-+ dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n",
-+ strength);
-+ dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n",
-+ ecc_cfg->strength, snf->caps->sector_size);
-+
-+ return 0;
-+}
-+
-+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand)
-+{
-+ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+
-+ kfree(ecc_cfg);
-+}
-+
-+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand,
-+ struct nand_page_io_req *req)
-+{
-+ struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);
-+ int ret;
-+
-+ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,
-+ nand->memorg.oobsize);
-+ if (ret)
-+ return ret;
-+ snf->autofmt = true;
-+ snf->ecc_cfg = ecc_cfg;
-+ return 0;
-+}
-+
-+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand,
-+ struct nand_page_io_req *req)
-+{
-+ struct mtk_snand *snf = nand_to_mtk_snand(nand);
-+ struct mtd_info *mtd = nanddev_to_mtd(nand);
-+
-+ snf->ecc_cfg = NULL;
-+ snf->autofmt = false;
-+ if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ))
-+ return 0;
-+
-+ if (snf->ecc_stats.failed)
-+ mtd->ecc_stats.failed += snf->ecc_stats.failed;
-+ mtd->ecc_stats.corrected += snf->ecc_stats.corrected;
-+ return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;
-+}
-+
-+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
-+ .init_ctx = mtk_snand_ecc_init_ctx,
-+ .cleanup_ctx = mtk_snand_ecc_cleanup_ctx,
-+ .prepare_io_req = mtk_snand_ecc_prepare_io_req,
-+ .finish_io_req = mtk_snand_ecc_finish_io_req,
-+};
-+
-+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf)
-+{
-+ u32 vall, valm;
-+ u8 *oobptr = buf;
-+ int i, j;
-+
-+ for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+ vall = nfi_read32(snf, NFI_FDML(i));
-+ valm = nfi_read32(snf, NFI_FDMM(i));
-+
-+ for (j = 0; j < snf->caps->fdm_size; j++)
-+ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);
-+
-+ oobptr += snf->caps->fdm_size;
-+ }
-+}
-+
-+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf)
-+{
-+ u32 fdm_size = snf->caps->fdm_size;
-+ const u8 *oobptr = buf;
-+ u32 vall, valm;
-+ int i, j;
-+
-+ for (i = 0; i < snf->nfi_cfg.nsectors; i++) {
-+ vall = 0;
-+ valm = 0;
-+
-+ for (j = 0; j < 8; j++) {
-+ if (j < 4)
-+ vall |= (j < fdm_size ? oobptr[j] : 0xff)
-+ << (j * 8);
-+ else
-+ valm |= (j < fdm_size ? oobptr[j] : 0xff)
-+ << ((j - 4) * 8);
-+ }
-+
-+ nfi_write32(snf, NFI_FDML(i), vall);
-+ nfi_write32(snf, NFI_FDMM(i), valm);
-+
-+ oobptr += fdm_size;
-+ }
-+}
-+
-+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf)
-+{
-+ u32 buf_bbm_pos, fdm_bbm_pos;
-+
-+ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+ return;
-+
-+ // swap [pagesize] byte on nand with the first fdm byte
-+ // in the last sector.
-+ buf_bbm_pos = snf->nfi_cfg.page_size -
-+ (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size;
-+ fdm_bbm_pos = snf->nfi_cfg.page_size +
-+ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+
-+ swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]);
-+}
-+
-+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)
-+{
-+ u32 fdm_bbm_pos1, fdm_bbm_pos2;
-+
-+ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)
-+ return;
-+
-+ // swap the first fdm byte in the first and the last sector.
-+ fdm_bbm_pos1 = snf->nfi_cfg.page_size;
-+ fdm_bbm_pos2 = snf->nfi_cfg.page_size +
-+ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;
-+ swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]);
-+}
-+
-+static int mtk_snand_read_page_cache(struct mtk_snand *snf,
-+ const struct spi_mem_op *op)
-+{
-+ u8 *buf = snf->buf;
-+ u8 *buf_fdm = buf + snf->nfi_cfg.page_size;
-+ // the address part to be sent by the controller
-+ u32 op_addr = op->addr.val;
-+ // where to start copying data from bounce buffer
-+ u32 rd_offset = 0;
-+ u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth);
-+ u32 op_mode = 0;
-+ u32 dma_len = snf->buf_len;
-+ int ret = 0;
-+ u32 rd_mode, rd_bytes, val;
-+ dma_addr_t buf_dma;
-+
-+ if (snf->autofmt) {
-+ u32 last_bit;
-+ u32 mask;
-+
-+ dma_len = snf->nfi_cfg.page_size;
-+ op_mode = CNFG_AUTO_FMT_EN;
-+ if (op->data.ecc)
-+ op_mode |= CNFG_HW_ECC_EN;
-+ // extract the plane bit:
-+ // Find the highest bit set in (pagesize+oobsize).
-+ // Bits higher than that in op->addr are kept and sent over SPI
-+ // Lower bits are used as an offset for copying data from DMA
-+ // bounce buffer.
-+ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+ mask = (1 << last_bit) - 1;
-+ rd_offset = op_addr & mask;
-+ op_addr &= ~mask;
-+
-+ // check if we can dma to the caller memory
-+ if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size)
-+ buf = op->data.buf.in;
-+ }
-+ mtk_snand_mac_reset(snf);
-+ mtk_nfi_reset(snf);
-+
-+ // command and dummy cycles
-+ nfi_write32(snf, SNF_RD_CTL2,
-+ (dummy_clk << DATA_READ_DUMMY_S) |
-+ (op->cmd.opcode << DATA_READ_CMD_S));
-+
-+ // read address
-+ nfi_write32(snf, SNF_RD_CTL3, op_addr);
-+
-+ // Set read op_mode
-+ if (op->data.buswidth == 4)
-+ rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD :
-+ DATA_READ_MODE_X4;
-+ else if (op->data.buswidth == 2)
-+ rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL :
-+ DATA_READ_MODE_X2;
-+ else
-+ rd_mode = DATA_READ_MODE_X1;
-+ rd_mode <<= DATA_READ_MODE_S;
-+ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,
-+ rd_mode | DATARD_CUSTOM_EN);
-+
-+ // Set bytes to read
-+ rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+ snf->nfi_cfg.nsectors;
-+ nfi_write32(snf, SNF_MISC_CTL2,
-+ (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes);
-+
-+ // NFI read prepare
-+ nfi_write16(snf, NFI_CNFG,
-+ (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN |
-+ CNFG_READ_MODE | CNFG_DMA_MODE | op_mode);
-+
-+ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+
-+ buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE);
-+ if (dma_mapping_error(snf->dev, buf_dma)) {
-+ dev_err(snf->dev, "DMA mapping failed.\n");
-+ goto cleanup;
-+ }
-+ nfi_write32(snf, NFI_STRADDR, buf_dma);
-+ if (op->data.ecc) {
-+ snf->ecc_cfg->op = ECC_DECODE;
-+ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+ if (ret)
-+ goto cleanup_dma;
-+ }
-+ // Prepare for custom read interrupt
-+ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);
-+ reinit_completion(&snf->op_done);
-+
-+ // Trigger NFI into custom mode
-+ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);
-+
-+ // Start DMA read
-+ nfi_rmw32(snf, NFI_CON, 0, CON_BRD);
-+ nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+ if (!wait_for_completion_timeout(
-+ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+ dev_err(snf->dev, "DMA timed out for reading from cache.\n");
-+ ret = -ETIMEDOUT;
-+ goto cleanup;
-+ }
-+
-+ // Wait for BUS_SEC_CNTR returning expected value
-+ ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,
-+ BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+ SNFI_POLL_INTERVAL);
-+ if (ret) {
-+ dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n");
-+ goto cleanup2;
-+ }
-+
-+ // Wait for bus becoming idle
-+ ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,
-+ !(val & snf->caps->mastersta_mask), 0,
-+ SNFI_POLL_INTERVAL);
-+ if (ret) {
-+ dev_err(snf->dev, "Timed out waiting for bus becoming idle\n");
-+ goto cleanup2;
-+ }
-+
-+ if (op->data.ecc) {
-+ ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE);
-+ if (ret) {
-+ dev_err(snf->dev, "wait ecc done timeout\n");
-+ goto cleanup2;
-+ }
-+ // save status before disabling ecc
-+ mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats,
-+ snf->nfi_cfg.nsectors);
-+ }
-+
-+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+
-+ if (snf->autofmt) {
-+ mtk_snand_read_fdm(snf, buf_fdm);
-+ if (snf->caps->bbm_swap) {
-+ mtk_snand_bm_swap(snf, buf);
-+ mtk_snand_fdm_bm_swap(snf);
-+ }
-+ }
-+
-+ // copy data back
-+ if (nfi_read32(snf, NFI_STA) & READ_EMPTY) {
-+ memset(op->data.buf.in, 0xff, op->data.nbytes);
-+ snf->ecc_stats.bitflips = 0;
-+ snf->ecc_stats.failed = 0;
-+ snf->ecc_stats.corrected = 0;
-+ } else {
-+ if (buf == op->data.buf.in) {
-+ u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size;
-+ u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size;
-+
-+ if (req_left)
-+ memcpy(op->data.buf.in + snf->nfi_cfg.page_size,
-+ buf_fdm,
-+ cap_len < req_left ? cap_len : req_left);
-+ } else if (rd_offset < snf->buf_len) {
-+ u32 cap_len = snf->buf_len - rd_offset;
-+
-+ if (op->data.nbytes < cap_len)
-+ cap_len = op->data.nbytes;
-+ memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len);
-+ }
-+ }
-+cleanup2:
-+ if (op->data.ecc)
-+ mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+ // unmap dma only if any error happens. (otherwise it's done before
-+ // data copying)
-+ if (ret)
-+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);
-+cleanup:
-+ // Stop read
-+ nfi_write32(snf, NFI_CON, 0);
-+ nfi_write16(snf, NFI_CNFG, 0);
-+
-+ // Clear SNF done flag
-+ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);
-+ nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+ // Disable interrupt
-+ nfi_read32(snf, NFI_INTR_STA);
-+ nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);
-+ return ret;
-+}
-+
-+static int mtk_snand_write_page_cache(struct mtk_snand *snf,
-+ const struct spi_mem_op *op)
-+{
-+ // the address part to be sent by the controller
-+ u32 op_addr = op->addr.val;
-+ // where to start copying data from bounce buffer
-+ u32 wr_offset = 0;
-+ u32 op_mode = 0;
-+ int ret = 0;
-+ u32 wr_mode = 0;
-+ u32 dma_len = snf->buf_len;
-+ u32 wr_bytes, val;
-+ size_t cap_len;
-+ dma_addr_t buf_dma;
-+
-+ if (snf->autofmt) {
-+ u32 last_bit;
-+ u32 mask;
-+
-+ dma_len = snf->nfi_cfg.page_size;
-+ op_mode = CNFG_AUTO_FMT_EN;
-+ if (op->data.ecc)
-+ op_mode |= CNFG_HW_ECC_EN;
-+
-+ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);
-+ mask = (1 << last_bit) - 1;
-+ wr_offset = op_addr & mask;
-+ op_addr &= ~mask;
-+ }
-+ mtk_snand_mac_reset(snf);
-+ mtk_nfi_reset(snf);
-+
-+ if (wr_offset)
-+ memset(snf->buf, 0xff, wr_offset);
-+
-+ cap_len = snf->buf_len - wr_offset;
-+ if (op->data.nbytes < cap_len)
-+ cap_len = op->data.nbytes;
-+ memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len);
-+ if (snf->autofmt) {
-+ if (snf->caps->bbm_swap) {
-+ mtk_snand_fdm_bm_swap(snf);
-+ mtk_snand_bm_swap(snf, snf->buf);
-+ }
-+ mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size);
-+ }
-+
-+ // Command
-+ nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S));
-+
-+ // write address
-+ nfi_write32(snf, SNF_PG_CTL2, op_addr);
-+
-+ // Set read op_mode
-+ if (op->data.buswidth == 4)
-+ wr_mode = PG_LOAD_X4_EN;
-+
-+ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN,
-+ wr_mode | PG_LOAD_CUSTOM_EN);
-+
-+ // Set bytes to write
-+ wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *
-+ snf->nfi_cfg.nsectors;
-+ nfi_write32(snf, SNF_MISC_CTL2,
-+ (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes);
-+
-+ // NFI write prepare
-+ nfi_write16(snf, NFI_CNFG,
-+ (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |
-+ CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode);
-+
-+ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));
-+ buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE);
-+ if (dma_mapping_error(snf->dev, buf_dma)) {
-+ dev_err(snf->dev, "DMA mapping failed.\n");
-+ goto cleanup;
-+ }
-+ nfi_write32(snf, NFI_STRADDR, buf_dma);
-+ if (op->data.ecc) {
-+ snf->ecc_cfg->op = ECC_ENCODE;
-+ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);
-+ if (ret)
-+ goto cleanup_dma;
-+ }
-+ // Prepare for custom write interrupt
-+ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);
-+ reinit_completion(&snf->op_done);
-+ ;
-+
-+ // Trigger NFI into custom mode
-+ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);
-+
-+ // Start DMA write
-+ nfi_rmw32(snf, NFI_CON, 0, CON_BWR);
-+ nfi_write16(snf, NFI_STRDATA, STR_DATA);
-+
-+ if (!wait_for_completion_timeout(
-+ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {
-+ dev_err(snf->dev, "DMA timed out for program load.\n");
-+ ret = -ETIMEDOUT;
-+ goto cleanup_ecc;
-+ }
-+
-+ // Wait for NFI_SEC_CNTR returning expected value
-+ ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,
-+ NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,
-+ SNFI_POLL_INTERVAL);
-+ if (ret)
-+ dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n");
-+
-+cleanup_ecc:
-+ if (op->data.ecc)
-+ mtk_ecc_disable(snf->ecc);
-+cleanup_dma:
-+ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE);
-+cleanup:
-+ // Stop write
-+ nfi_write32(snf, NFI_CON, 0);
-+ nfi_write16(snf, NFI_CNFG, 0);
-+
-+ // Clear SNF done flag
-+ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);
-+ nfi_write32(snf, SNF_STA_CTL1, 0);
-+
-+ // Disable interrupt
-+ nfi_read32(snf, NFI_INTR_STA);
-+ nfi_write32(snf, NFI_INTR_EN, 0);
-+
-+ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);
-+
-+ return ret;
-+}
-+
-+/**
-+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op.
-+ * @op spi-mem op to check
-+ *
-+ * Check whether op can be executed with read_from_cache or program_load
-+ * mode in the controller.
-+ * This controller can execute typical Read From Cache and Program Load
-+ * instructions found on SPI-NAND with 2-byte address.
-+ * DTR and cmd buswidth & nbytes should be checked before calling this.
-+ *
-+ * Return: true if the op matches the instruction template
-+ */
-+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op)
-+{
-+ if (op->addr.nbytes != 2)
-+ return false;
-+
-+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
-+ op->addr.buswidth != 4)
-+ return false;
-+
-+ // match read from page instructions
-+ if (op->data.dir == SPI_MEM_DATA_IN) {
-+ // check dummy cycle first
-+ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >
-+ DATA_READ_MAX_DUMMY)
-+ return false;
-+ // quad io / quad out
-+ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&
-+ op->data.buswidth == 4)
-+ return true;
-+
-+ // dual io / dual out
-+ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&
-+ op->data.buswidth == 2)
-+ return true;
-+
-+ // standard spi
-+ if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+ return true;
-+ } else if (op->data.dir == SPI_MEM_DATA_OUT) {
-+ // check dummy cycle first
-+ if (op->dummy.nbytes)
-+ return false;
-+ // program load quad out
-+ if (op->addr.buswidth == 1 && op->data.buswidth == 4)
-+ return true;
-+ // standard spi
-+ if (op->addr.buswidth == 1 && op->data.buswidth == 1)
-+ return true;
-+ }
-+ return false;
-+}
-+
-+static bool mtk_snand_supports_op(struct spi_mem *mem,
-+ const struct spi_mem_op *op)
-+{
-+ if (!spi_mem_default_supports_op(mem, op))
-+ return false;
-+ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
-+ return false;
-+ if (mtk_snand_is_page_ops(op))
-+ return true;
-+ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&
-+ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&
-+ (op->data.nbytes == 0 || op->data.buswidth == 1));
-+}
-+
-+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
-+{
-+ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+ // page ops transfer size must be exactly ((sector_size + spare_size) *
-+ // nsectors). Limit the op size if the caller requests more than that.
-+ // exec_op will read more than needed and discard the leftover if the
-+ // caller requests less data.
-+ if (mtk_snand_is_page_ops(op)) {
-+ size_t l;
-+ // skip adjust_op_size for page ops
-+ if (ms->autofmt)
-+ return 0;
-+ l = ms->caps->sector_size + ms->nfi_cfg.spare_size;
-+ l *= ms->nfi_cfg.nsectors;
-+ if (op->data.nbytes > l)
-+ op->data.nbytes = l;
-+ } else {
-+ size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
-+
-+ if (hl >= SNF_GPRAM_SIZE)
-+ return -EOPNOTSUPP;
-+ if (op->data.nbytes > SNF_GPRAM_SIZE - hl)
-+ op->data.nbytes = SNF_GPRAM_SIZE - hl;
-+ }
-+ return 0;
-+}
-+
-+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
-+{
-+ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);
-+
-+ dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
-+ op->addr.val, op->addr.buswidth, op->addr.nbytes,
-+ op->data.buswidth, op->data.nbytes);
-+ if (mtk_snand_is_page_ops(op)) {
-+ if (op->data.dir == SPI_MEM_DATA_IN)
-+ return mtk_snand_read_page_cache(ms, op);
-+ else
-+ return mtk_snand_write_page_cache(ms, op);
-+ } else {
-+ return mtk_snand_mac_io(ms, op);
-+ }
-+}
-+
-+static const struct spi_controller_mem_ops mtk_snand_mem_ops = {
-+ .adjust_op_size = mtk_snand_adjust_op_size,
-+ .supports_op = mtk_snand_supports_op,
-+ .exec_op = mtk_snand_exec_op,
-+};
-+
-+static const struct spi_controller_mem_caps mtk_snand_mem_caps = {
-+ .ecc = true,
-+};
-+
-+static irqreturn_t mtk_snand_irq(int irq, void *id)
-+{
-+ struct mtk_snand *snf = id;
-+ u32 sta, ien;
-+
-+ sta = nfi_read32(snf, NFI_INTR_STA);
-+ ien = nfi_read32(snf, NFI_INTR_EN);
-+
-+ if (!(sta & ien))
-+ return IRQ_NONE;
-+
-+ nfi_write32(snf, NFI_INTR_EN, 0);
-+ complete(&snf->op_done);
-+ return IRQ_HANDLED;
-+}
-+
-+static const struct of_device_id mtk_snand_ids[] = {
-+ { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
-+ { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
-+ {},
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_snand_ids);
-+
-+static int mtk_snand_enable_clk(struct mtk_snand *ms)
-+{
-+ int ret;
-+
-+ ret = clk_prepare_enable(ms->nfi_clk);
-+ if (ret) {
-+ dev_err(ms->dev, "unable to enable nfi clk\n");
-+ return ret;
-+ }
-+ ret = clk_prepare_enable(ms->pad_clk);
-+ if (ret) {
-+ dev_err(ms->dev, "unable to enable pad clk\n");
-+ goto err1;
-+ }
-+ return 0;
-+err1:
-+ clk_disable_unprepare(ms->nfi_clk);
-+ return ret;
-+}
-+
-+static void mtk_snand_disable_clk(struct mtk_snand *ms)
-+{
-+ clk_disable_unprepare(ms->pad_clk);
-+ clk_disable_unprepare(ms->nfi_clk);
-+}
-+
-+static int mtk_snand_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ const struct of_device_id *dev_id;
-+ struct spi_controller *ctlr;
-+ struct mtk_snand *ms;
-+ int ret;
-+
-+ dev_id = of_match_node(mtk_snand_ids, np);
-+ if (!dev_id)
-+ return -EINVAL;
-+
-+ ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms));
-+ if (!ctlr)
-+ return -ENOMEM;
-+ platform_set_drvdata(pdev, ctlr);
-+
-+ ms = spi_controller_get_devdata(ctlr);
-+
-+ ms->ctlr = ctlr;
-+ ms->caps = dev_id->data;
-+
-+ ms->ecc = of_mtk_ecc_get(np);
-+ if (IS_ERR(ms->ecc))
-+ return PTR_ERR(ms->ecc);
-+ else if (!ms->ecc)
-+ return -ENODEV;
-+
-+ ms->nfi_base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(ms->nfi_base)) {
-+ ret = PTR_ERR(ms->nfi_base);
-+ goto release_ecc;
-+ }
-+
-+ ms->dev = &pdev->dev;
-+
-+ ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk");
-+ if (IS_ERR(ms->nfi_clk)) {
-+ ret = PTR_ERR(ms->nfi_clk);
-+ dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret);
-+ goto release_ecc;
-+ }
-+
-+ ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk");
-+ if (IS_ERR(ms->pad_clk)) {
-+ ret = PTR_ERR(ms->pad_clk);
-+ dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret);
-+ goto release_ecc;
-+ }
-+
-+ ret = mtk_snand_enable_clk(ms);
-+ if (ret)
-+ goto release_ecc;
-+
-+ init_completion(&ms->op_done);
-+
-+ ms->irq = platform_get_irq(pdev, 0);
-+ if (ms->irq < 0) {
-+ ret = ms->irq;
-+ goto disable_clk;
-+ }
-+ ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0,
-+ "mtk-snand", ms);
-+ if (ret) {
-+ dev_err(ms->dev, "failed to request snfi irq\n");
-+ goto disable_clk;
-+ }
-+
-+ ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32));
-+ if (ret) {
-+ dev_err(ms->dev, "failed to set dma mask\n");
-+ goto disable_clk;
-+ }
-+
-+ // switch to SNFI mode
-+ nfi_write32(ms, SNF_CFG, SPI_MODE);
-+
-+ // setup an initial page format for ops matching page_cache_op template
-+ // before ECC is called.
-+ ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size,
-+ ms->caps->spare_sizes[0]);
-+ if (ret) {
-+ dev_err(ms->dev, "failed to set initial page format\n");
-+ goto disable_clk;
-+ }
-+
-+ // setup ECC engine
-+ ms->ecc_eng.dev = &pdev->dev;
-+ ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
-+ ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops;
-+ ms->ecc_eng.priv = ms;
-+
-+ ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng);
-+ if (ret) {
-+ dev_err(&pdev->dev, "failed to register ecc engine.\n");
-+ goto disable_clk;
-+ }
-+
-+ ctlr->num_chipselect = 1;
-+ ctlr->mem_ops = &mtk_snand_mem_ops;
-+ ctlr->mem_caps = &mtk_snand_mem_caps;
-+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
-+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
-+ ctlr->dev.of_node = pdev->dev.of_node;
-+ ret = spi_register_controller(ctlr);
-+ if (ret) {
-+ dev_err(&pdev->dev, "spi_register_controller failed.\n");
-+ goto disable_clk;
-+ }
-+
-+ return 0;
-+disable_clk:
-+ mtk_snand_disable_clk(ms);
-+release_ecc:
-+ mtk_ecc_release(ms->ecc);
-+ return ret;
-+}
-+
-+static int mtk_snand_remove(struct platform_device *pdev)
-+{
-+ struct spi_controller *ctlr = platform_get_drvdata(pdev);
-+ struct mtk_snand *ms = spi_controller_get_devdata(ctlr);
-+
-+ spi_unregister_controller(ctlr);
-+ mtk_snand_disable_clk(ms);
-+ mtk_ecc_release(ms->ecc);
-+ kfree(ms->buf);
-+ return 0;
-+}
-+
-+static struct platform_driver mtk_snand_driver = {
-+ .probe = mtk_snand_probe,
-+ .remove = mtk_snand_remove,
-+ .driver = {
-+ .name = "mtk-snand",
-+ .of_match_table = mtk_snand_ids,
-+ },
-+};
-+
-+module_platform_driver(mtk_snand_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
-+MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver");
+++ /dev/null
-From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Mon, 4 Apr 2022 00:05:38 +0800
-Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if
- available
-
-The recently added ECC engine support introduced a generic property
-named nand-ecc-engine for ecc engine phandle. This patch adds support
-for this new property.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54)
----
- drivers/mtd/nand/ecc-mtk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/ecc-mtk.c
-+++ b/drivers/mtd/nand/ecc-mtk.c
-@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de
- struct mtk_ecc *ecc = NULL;
- struct device_node *np;
-
-- np = of_parse_phandle(of_node, "ecc-engine", 0);
-+ np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
-+ /* for backward compatibility */
-+ if (!np)
-+ np = of_parse_phandle(of_node, "ecc-engine", 0);
- if (np) {
- ecc = mtk_ecc_get(np);
- of_node_put(np);
+++ /dev/null
-From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Sun, 3 Apr 2022 10:19:29 +0800
-Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622
-
-This patch adds a device-tree node for the MTK SPI-NAND Flash Interface
-for MT7622 device tree.
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
-(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af)
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -553,6 +553,18 @@
- status = "disabled";
- };
-
-+ snfi: spi@1100d000 {
-+ compatible = "mediatek,mt7622-snand";
-+ reg = <0 0x1100d000 0 0x1000>;
-+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+ clock-names = "nfi_clk", "pad_clk";
-+ nand-ecc-engine = <&bch>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
- bch: ecc@1100e000 {
- compatible = "mediatek,mt7622-ecc";
- reg = <0 0x1100e000 0 0x1000>;
"mediatek,mt7622-spi";
--- a/arch/arm/boot/dts/mt7629-rfb.dts
+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -254,6 +254,50 @@
+@@ -255,6 +255,50 @@
};
};
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -539,6 +539,65 @@
+@@ -538,6 +538,65 @@
status = "disabled";
};
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -580,7 +580,7 @@
+@@ -579,7 +579,7 @@
reg = <0x140000 0x0080000>;
};
label = "Factory";
reg = <0x1c0000 0x0100000>;
};
-@@ -641,5 +641,6 @@
+@@ -640,5 +640,6 @@
&wmac {
pinctrl-names = "default";
pinctrl-0 = <&wmac_pins>;
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -951,17 +951,15 @@
+@@ -984,17 +984,15 @@
};
crypto: crypto@1b240000 {
+++ /dev/null
-From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
-From: Sungbo Eo <mans0n@gorani.run>
-Date: Sun, 8 Aug 2021 21:38:40 +0900
-Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
-
-MT7623 has an musb controller that is compatible with the one from MT2701.
-
-Signed-off-by: Sungbo Eo <mans0n@gorani.run>
----
- arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623a.dtsi | 4 ++++
- 2 files changed, 38 insertions(+)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -585,6 +585,40 @@
- status = "disabled";
- };
-
-+ usb0: usb@11200000 {
-+ compatible = "mediatek,mt7623-musb",
-+ "mediatek,mtk-musb";
-+ reg = <0 0x11200000 0 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "mc";
-+ phys = <&u2port2 PHY_TYPE_USB2>;
-+ dr_mode = "otg";
-+ clocks = <&pericfg CLK_PERI_USB0>,
-+ <&pericfg CLK_PERI_USB0_MCU>,
-+ <&pericfg CLK_PERI_USB_SLV>;
-+ clock-names = "main","mcu","univpll";
-+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-+ status = "disabled";
-+ };
-+
-+ u2phy1: t-phy@11210000 {
-+ compatible = "mediatek,mt7623-tphy",
-+ "mediatek,generic-tphy-v1";
-+ reg = <0 0x11210000 0 0x0800>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ status = "disabled";
-+
-+ u2port2: usb-phy@11210800 {
-+ reg = <0 0x11210800 0 0x0100>;
-+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
-+ clock-names = "ref";
-+ #phy-cells = <1>;
-+ status = "okay";
-+ };
-+ };
-+
- audsys: clock-controller@11220000 {
- compatible = "mediatek,mt7623-audsys",
- "mediatek,mt2701-audsys",
---- a/arch/arm/boot/dts/mt7623a.dtsi
-+++ b/arch/arm/boot/dts/mt7623a.dtsi
-@@ -35,6 +35,10 @@
- clock-names = "ethif";
- };
-
-+&usb0 {
-+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
-+};
-+
- &usb1 {
- power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;
- };
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -160,6 +160,10 @@
+@@ -156,6 +156,10 @@
switch@0 {
compatible = "mediatek,mt7531";
reg = <0>;
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -339,7 +339,7 @@
+@@ -346,7 +346,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10310000 0 0x1000>,
+++ /dev/null
-From patchwork Thu Apr 28 22:57:55 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Rui Salvaterra <rsalvaterra@gmail.com>
-X-Patchwork-Id: 12831311
-Return-Path:
- <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
-X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
- aws-us-west-2-korg-lkml-1.web.codeaurora.org
-Received: from bombadil.infradead.org (bombadil.infradead.org
- [198.137.202.133])
- (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
- (No client certificate requested)
- by smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF
- for <linux-arm-kernel@archiver.kernel.org>;
- Thu, 28 Apr 2022 22:59:15 +0000 (UTC)
-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
- d=lists.infradead.org; s=bombadil.20210309; h=Sender:
- Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:
- List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc
- :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
- Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:
- List-Owner; bh=SerBW8MOw68wFFCbuq25LJzAcmqCfKMO2cFJxwFvZ+M=; b=nN4CYEO6VOGVbq
- GSvQPGoya0L2IzQ/ZfknzQ853lY97zEPJk14ndK+TGQ+8ySjBSTu0xKgxlBoJj5G+DGubgRP1eZRJ
- bktFqX2tohnrRavlceRxgVA3YFGBhjXE7AC0YzGC7auH2S6nSPUrH7cTVuaeIacIoV1AXPazc2hRU
- u8RaJl1XHQwuhdZOsFBH99M5an3Zsmq0tsoIOYwB+gQaI307ZkqscxzcXFiCYCHlDvZlhHlW/WbdG
- J+3iUnfq1KJWI2kE7TkPXMYaJzbEgG+LDrgYr3deADArCfCmnzbf0U29EZd6cR5D19GMVqGFDvsTX
- H69W8qxVzJ+mR2HQd3GQ==;
-Received: from localhost ([::1] helo=bombadil.infradead.org)
- by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))
- id 1nkD5T-008uVi-54; Thu, 28 Apr 2022 22:58:15 +0000
-Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533])
- by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))
- id 1nkD5P-008uUW-Px; Thu, 28 Apr 2022 22:58:13 +0000
-Received: by mail-ed1-x533.google.com with SMTP id p18so7146795edr.7;
- Thu, 28 Apr 2022 15:58:08 -0700 (PDT)
-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112;
- h=from:to:cc:subject:date:message-id:mime-version
- :content-transfer-encoding;
- bh=R5/7OCxhqk5o9giaTDUQztGpi5IgQbeepSeYSbhWdII=;
- b=BZQqEcfqgYTQ01yTJ3p6tPu0vaoYxHxTZYXAPCQDyng2F9JErAwf+wBYyeCYL3jbyn
- fu7P7HVw2JjagdSunf6J7t0o3nqtfHGPh/ZLJHzYdg1s5shotJ5wMbZpAHCMdC4+K+BV
- uL4JNuQnZmCRBiUFM+rtrpfaTepwEclOBBGoL9iE+tm/pWzx/WIR5WB9W8CutqsrDxF5
- 8r5IwxNz3GLYfDgZMejyxQ0BjUIeQeCMTqhf73P19V3Bgg4MUbJ2q163D/OWSpHCbJdH
- OfKEAdrVw4U7Rx0/SOnvPBxeiyCVH2uAkdPiFk+O3ZvsaiODty7uqGGjbN4chYEWRdp+
- 7WBQ==
-X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
- d=1e100.net; s=20210112;
- h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version
- :content-transfer-encoding;
- bh=R5/7OCxhqk5o9giaTDUQztGpi5IgQbeepSeYSbhWdII=;
- b=mvuzYrIKVAnpUgnlEa+S84XOruFt2VxxK25dib+Az/UPt4CzDO0h1u3SckfcmsFT4h
- lUKka66CkdkHCJWC5JqKwSD0lbgtu2KWEsvtCWVDS+S6XKuAu99o2kvNyHC+/xW07dKL
- zB7WAkyG53lrX0KH7fZ46uzHoRKWATW/idDhXBA49B+vaPqHKroSOn5JBKsu/hDwsQdf
- zWA5tmOJweFjVZYe0ChD8OUDYOv+6RYlGqVvsQ5quMKJDBoC7KC8YMqvHc3K6DbQbnvZ
- vJyXlcHgHSpadLRgg6wIY+ZyJyZsGqVyRD1TmcByRxSrUTGc3VSQeXUcUPv+3JFk9Esu
- PqoA==
-X-Gm-Message-State: AOAM530veLoWc1JsDUuaRxe8Wi4N5UaD7cH5c9nhGlW7j5aj9gwvCDya
- /uqAd6FaNeLuB5hEWmAEXXugS+7njg==
-X-Google-Smtp-Source:
- ABdhPJyLbUuBj/1YYm+3qmglf7zy9b/YbbcMub3/HL40okdVxkr6/TVxIZulAoEV9PjbfrGkO2N3Bw==
-X-Received: by 2002:a05:6402:2920:b0:425:d7c7:41f with SMTP id
- ee32-20020a056402292000b00425d7c7041fmr29248373edb.370.1651186687432;
- Thu, 28 Apr 2022 15:58:07 -0700 (PDT)
-Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt.
- [109.49.0.175]) by smtp.gmail.com with ESMTPSA id
- a25-20020a056402169900b0042617ba63c8sm2219102edv.82.2022.04.28.15.58.06
- (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
- Thu, 28 Apr 2022 15:58:06 -0700 (PDT)
-From: Rui Salvaterra <rsalvaterra@gmail.com>
-To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
- linux-kernel@vger.kernel.org
-Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org,
- Rui Salvaterra <rsalvaterra@gmail.com>
-Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
-Date: Thu, 28 Apr 2022 23:57:55 +0100
-Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com>
-X-Mailer: git-send-email 2.36.0
-MIME-Version: 1.0
-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
-X-CRM114-CacheID: sfid-20220428_155811_895571_B63D2806
-X-CRM114-Status: GOOD ( 10.27 )
-X-BeenThere: linux-arm-kernel@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-arm-kernel.lists.infradead.org>
-List-Unsubscribe:
- <http://lists.infradead.org/mailman/options/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>
-List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
-List-Post: <mailto:linux-arm-kernel@lists.infradead.org>
-List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>
-List-Subscribe:
- <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
-Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
-Errors-To:
- linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
-
-On an MT7622 system, the kernel complains of not being able to detect the cache
-hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
-order to fix this.
-
-Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -80,6 +80,7 @@
- enable-method = "psci";
- clock-frequency = <1300000000>;
- cci-control-port = <&cci_control2>;
-+ next-level-cache = <&L2>;
- };
-
- cpu1: cpu@1 {
-@@ -94,6 +95,12 @@
- enable-method = "psci";
- clock-frequency = <1300000000>;
- cci-control-port = <&cci_control2>;
-+ next-level-cache = <&L2>;
-+ };
-+
-+ L2: l2-cache {
-+ compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
+++ /dev/null
-From patchwork Fri Apr 29 08:42:25 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Rui Salvaterra <rsalvaterra@gmail.com>
-X-Patchwork-Id: 12831649
-Return-Path:
- <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
-X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
- aws-us-west-2-korg-lkml-1.web.codeaurora.org
-Received: from bombadil.infradead.org (bombadil.infradead.org
- [198.137.202.133])
- (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
- (No client certificate requested)
- by smtp.lore.kernel.org (Postfix) with ESMTPS id 386E2C433FE
- for <linux-arm-kernel@archiver.kernel.org>;
- Fri, 29 Apr 2022 08:43:49 +0000 (UTC)
-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
- d=lists.infradead.org; s=bombadil.20210309; h=Sender:
- Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:
- List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc
- :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
- Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:
- List-Owner; bh=8o7lZT3r9rAaTm8HKh4V0xpz9VW91LuZAYfrXGv0Xic=; b=bS+249v3+UY+qs
- bxuupjLqBetRQqMAaPjTn6GKQJtca75PMdLf3okoQban7PNqWO9WOgCJWgY2eyzOSjxHBPr1dsGzy
- 6c3CZBbMy8pXl/zf80YRmikPFXehOzAvOpZjco4QUCCqXNsJM9FKzAqYIaZDSlLOTmADDepsh481G
- k/h/g39ztzn09LVqwF2Bh0DopIbHiq/BepTeU8jFt5GTj3EGPTdCU7Vq7mf2pP6P6oPk6vswKVYaQ
- opq96BDGIEpeKViuMWt07vdJX2meQBHhY/Rte/aAO5pdLpusY2OPvEKv0/49swpAEsNYIYFcgtCtm
- vaKUqN85QlQznqd/NaHw==;
-Received: from localhost ([::1] helo=bombadil.infradead.org)
- by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))
- id 1nkMD3-00AFVb-Co; Fri, 29 Apr 2022 08:42:42 +0000
-Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534])
- by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))
- id 1nkMCy-00AFSn-Rp; Fri, 29 Apr 2022 08:42:38 +0000
-Received: by mail-ed1-x534.google.com with SMTP id be20so8231068edb.12;
- Fri, 29 Apr 2022 01:42:33 -0700 (PDT)
-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112;
- h=from:to:cc:subject:date:message-id:mime-version
- :content-transfer-encoding;
- bh=XJkVawFXvwQH7kz0CHPfmxuFkQ6+ipcLhCSvCaul0jQ=;
- b=HSFxl4yM5hEns1ZYq8D5pL88/nYNfulhELpJyhaF8XIrymlck2o40/lATRsLIEWMyb
- 8MiL8d5eAOEMSb7rUrqWodLDPZld7ZzCvoVt6XQeVmJLkAw0teNdQXvlCZgu/3Q6MwUw
- Wx+QkzqUjCODOLk224RVZGvnKY9YRu/WmZEnWqBjzQIF90DLNXyni+yS7XbUn8CnPbdM
- M3s/Ty7YsgPGsibKem1EI6yma15sXRNi1Vz1o0ArcPpsB/6x/ym8sCQemxSvrmer5ps9
- wrBnmlH558mrlj7rSHK9l5SmsGlkJiXB3DTLSrnynxHTY9gX9lSBsQxxjiqu1sEMvDVY
- toUA==
-X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
- d=1e100.net; s=20210112;
- h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version
- :content-transfer-encoding;
- bh=XJkVawFXvwQH7kz0CHPfmxuFkQ6+ipcLhCSvCaul0jQ=;
- b=LtdsZ9M/Im1hyxdJYYHttN4wtxcqRThm/H/oV8driFRB4KuwxO2iP2OqycVsS1sN2y
- quWFM6L8v0KaUZRUR85rRRr8JX9P84kqTu4szOEuSIQQ/aUDUbJxVi7rICLPZ890DqTY
- APplzuMhuNr6unYQO5Lxrj5IHHtrsmKP8ttR7VVWPNHpJseXc1kQ+HDLgylQLHVsb/5U
- 8KpUG0LvxhvqsNU6HbTwLD/Q/88ELP5MfoWHUocYXKPrBJ8K6rCHsmjH6z6tFLfXgce7
- 619waAHXFhCBCflRbAC+D9VemoNe5wJlu9mzyQ4Xavbo8NZgDobVFWOTEQ1iRdua/oRT
- tbxw==
-X-Gm-Message-State: AOAM532GrwQ/whp0buK64HysYJy6aLBD/xGE/8Dr7NSW150Jds7jTjor
- eVhdzOGjuWywij/s3mwA9XfPjST+Cg==
-X-Google-Smtp-Source:
- ABdhPJxU9goI5zXE0GQP90hO7TH0IDw++6UHpkGFSUH/chvzvE0L/pQF0XqDkdwzbbTmxsOBUMGcZg==
-X-Received: by 2002:a05:6402:84c:b0:423:e5a2:3655 with SMTP id
- b12-20020a056402084c00b00423e5a23655mr40374113edz.28.1651221752304;
- Fri, 29 Apr 2022 01:42:32 -0700 (PDT)
-Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt.
- [109.49.0.175]) by smtp.gmail.com with ESMTPSA id
- el10-20020a170907284a00b006f3ef214e32sm429064ejc.152.2022.04.29.01.42.31
- (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
- Fri, 29 Apr 2022 01:42:31 -0700 (PDT)
-From: Rui Salvaterra <rsalvaterra@gmail.com>
-To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
- linux-kernel@vger.kernel.org
-Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org,
- Rui Salvaterra <rsalvaterra@gmail.com>
-Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests
-Date: Fri, 29 Apr 2022 09:42:25 +0100
-Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com>
-X-Mailer: git-send-email 2.36.0
-MIME-Version: 1.0
-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
-X-CRM114-CacheID: sfid-20220429_014236_944696_097D1E73
-X-CRM114-Status: UNSURE ( 8.85 )
-X-CRM114-Notice: Please train this message.
-X-BeenThere: linux-arm-kernel@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-arm-kernel.lists.infradead.org>
-List-Unsubscribe:
- <http://lists.infradead.org/mailman/options/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>
-List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
-List-Post: <mailto:linux-arm-kernel@lists.infradead.org>
-List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>
-List-Subscribe:
- <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
-Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
-Errors-To:
- linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
-
-The MT7622 device tree never bothered to specify the number of virtual DMA
-channels for the HSDMA controller, always falling back to the default value of
-3. Make this value explicit, in order to avoid the following dmesg notification:
-
-mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property
-
-Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -942,6 +942,7 @@
- clock-names = "hsdma";
- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- #dma-cells = <1>;
-+ dma-requests = <3>;
- };
-
- pcie_mirror: pcie-mirror@10000400 {
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -18,6 +18,8 @@
+@@ -17,6 +17,8 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
- /* version V1 sub-banks offset base address */
- /* banks shared by multiple phys */
-@@ -311,6 +313,9 @@
+ #include "phy-mtk-io.h"
+
+@@ -264,6 +266,9 @@
#define TPHY_CLKS_CNT 2
enum mtk_phy_version {
MTK_PHY_V1 = 1,
MTK_PHY_V2,
-@@ -377,6 +382,7 @@ struct mtk_tphy {
+@@ -331,6 +336,7 @@ struct mtk_tphy {
void __iomem *sif_base; /* only shared sif */
const struct mtk_phy_pdata *pdata;
struct mtk_phy_instance **phys;
int nphys;
int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
int src_coef; /* coefficient for slew rate calibrate */
-@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc
+@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc
if (tphy->pdata->version != MTK_PHY_V1)
return;
+ regmap_update_bits(tphy->hif, HIF_SYSCFG1,
+ HIF_SYSCFG1_PHY2_MASK, 0);
+
- tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
- tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
- tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
-@@ -1437,6 +1447,16 @@ static int mtk_tphy_probe(struct platfor
+ mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
+ P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
+ FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
+@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor
&tphy->src_coef);
}
+++ /dev/null
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK_MOORE
-
-+config PINCTRL_MT7986
-+ bool "Mediatek MT7986 pin control"
-+ depends on OF
-+ depends on ARM64 || COMPILE_TEST
-+ default ARM64 && ARCH_MEDIATEK
-+ select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- bool "Mediatek MT8167 pin control"
- depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
--- /dev/null
+From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sat, 8 Oct 2022 18:48:06 +0200
+Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
+ separately
+
+Some mt7986 boards use uart rts/cts pins as gpio,
+This patch allows to change rts/cts to gpio mode, but keep
+rx/tx as UART function.
+
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
+ 1 file changed, 25 insertions(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
+ static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
+ static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
+
+-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
+-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
++static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
++static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
+
+-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
+-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
++static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
++static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
++
++static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
++static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
++
++static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
++static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
+
+ static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
+ static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
+@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
+ static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
+ static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+
++static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
++static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
++
++static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
++static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
++
+ static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
+ static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
+
+@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
+ PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
+ PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
+ PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
++ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
++ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
+ PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
+ PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
+ PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
+@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
+ PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
+ PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
+ PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
+- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
+- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
++ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
++ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
++ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
++ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
+ PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
+ PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
+@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
+ static const char *mt7986_spi_groups[] = {
+ "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
+ static const char *mt7986_uart_groups[] = {
+- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
++ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
++ "uart1_2_rx_tx", "uart1_2_cts_rts",
++ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
+ "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
+ };
+ static const char *mt7986_wdt_groups[] = { "watchdog", };
+++ /dev/null
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -43,6 +43,15 @@ err_out:
- return NULL;
- }
-
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data)
-+{
-+ if (!clk_data)
-+ return;
-+
-+ kfree(clk_data->clks);
-+ kfree(clk_data);
-+}
-+
- void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
- int num, struct clk_onecell_data *clk_data)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -202,6 +202,7 @@ void mtk_clk_register_dividers(const str
- struct clk_onecell_data *clk_data);
-
- struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-+void mtk_free_clk_data(struct clk_onecell_data *clk_data);
-
- #define HAVE_RST_BAR BIT(0)
- #define PLL_AO BIT(1)
--- /dev/null
+From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Sun, 6 Nov 2022 09:01:13 +0100
+Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
+ MT7986 SoC
+
+Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
+add SoC specify 'pull_type' attribute for bias configuration.
+
+This patch add pull_type attribute to pinctrl-mt7986.c, and make
+bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
+ PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+ };
+
++static const unsigned int mt7986_pull_type[] = {
++ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
++ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
++ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
++ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
++ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
++ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
++ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
++ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
++ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
++ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
++ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
++ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
++ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
++ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
++ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
++ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
++ MTK_PULL_PU_PD_TYPE,/*100*/
++};
++
+ static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
+@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
+ .ies_present = false,
+ .base_names = mt7986_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++ .pull_type = mt7986_pull_type,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
+ .ies_present = false,
+ .base_names = mt7986_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++ .pull_type = mt7986_pull_type,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+++ /dev/null
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- This driver supports MediaTek MT7629 HIFSYS clocks providing
- to PCI-E and USB.
-
-+config COMMON_CLK_MT7986
-+ bool "Clock driver for MediaTek MT7986"
-+ depends on ARCH_MEDIATEK || COMPILE_TEST
-+ select COMMON_CLK_MEDIATEK
-+ default ARCH_MEDIATEK
-+ help
-+ This driver supports MediaTek MT7986 basic clocks and clocks
-+ required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7986_ETHSYS
-+ bool "Clock driver for MediaTek MT7986 ETHSYS"
-+ depends on COMMON_CLK_MT7986
-+ default COMMON_CLK_MT7986
-+ help
-+ This driver add support for clocks for Ethernet and SGMII
-+ required on MediaTek MT7986 SoC.
-+
- config COMMON_CLK_MT8135
- bool "Clock driver for MediaTek MT8135"
- depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+++ /dev/null
-From 7d99750f96fc6904d54affebdc8c9b0bfae1e9e8 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Apr 2022 11:40:22 +0800
-Subject: [PATCH] spi: mediatek: backport document and driver to support mt7986
- spi design
-
-this patch add the support of ipm design and upgrade devicetree binding
-
-The patch is comming from following threads
-- https://lore.kernel.org/all/20220315032411.2826-1-leilk.liu@mediatek.com/
-- https://lore.kernel.org/all/20220401071616.8874-1-leilk.liu@mediatek.com/
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- .../bindings/spi/mediatek,spi-mt65xx.yaml | 111 ++++
- drivers/spi/spi-mt65xx.c | 509 ++++++++++++++++--
- 2 files changed, 572 insertions(+), 48 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
-@@ -0,0 +1,111 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: SPI Bus controller for MediaTek ARM SoCs
-+
-+maintainers:
-+ - Leilk Liu <leilk.liu@mediatek.com>
-+
-+allOf:
-+ - $ref: "/schemas/spi/spi-controller.yaml#"
-+
-+properties:
-+ compatible:
-+ oneOf:
-+ - items:
-+ - enum:
-+ - mediatek,mt7629-spi
-+ - const: mediatek,mt7622-spi
-+ - items:
-+ - enum:
-+ - mediatek,mt8516-spi
-+ - const: mediatek,mt2712-spi
-+ - items:
-+ - enum:
-+ - mediatek,mt6779-spi
-+ - mediatek,mt8186-spi
-+ - mediatek,mt8192-spi
-+ - mediatek,mt8195-spi
-+ - const: mediatek,mt6765-spi
-+ - items:
-+ - enum:
-+ - mediatek,mt7986-spi-ipm
-+ - const: mediatek,spi-ipm
-+ - items:
-+ - enum:
-+ - mediatek,mt2701-spi
-+ - mediatek,mt2712-spi
-+ - mediatek,mt6589-spi
-+ - mediatek,mt6765-spi
-+ - mediatek,mt6893-spi
-+ - mediatek,mt7622-spi
-+ - mediatek,mt8135-spi
-+ - mediatek,mt8173-spi
-+ - mediatek,mt8183-spi
-+
-+ reg:
-+ maxItems: 1
-+
-+ interrupts:
-+ maxItems: 1
-+
-+ clocks:
-+ minItems: 3
-+ items:
-+ - description: clock used for the parent clock
-+ - description: clock used for the muxes clock
-+ - description: clock used for the clock gate
-+ - description: clock used for the AHB bus, this clock is optional
-+
-+ clock-names:
-+ minItems: 3
-+ items:
-+ - const: parent-clk
-+ - const: sel-clk
-+ - const: spi-clk
-+ - const: hclk
-+
-+ mediatek,pad-select:
-+ $ref: /schemas/types.yaml#/definitions/uint32-array
-+ minItems: 1
-+ maxItems: 4
-+ items:
-+ enum: [0, 1, 2, 3]
-+ description:
-+ specify which pins group(ck/mi/mo/cs) spi controller used.
-+ This is an array.
-+
-+required:
-+ - compatible
-+ - reg
-+ - interrupts
-+ - clocks
-+ - clock-names
-+ - '#address-cells'
-+ - '#size-cells'
-+
-+unevaluatedProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/clock/mt8173-clk.h>
-+ #include <dt-bindings/gpio/gpio.h>
-+ #include <dt-bindings/interrupt-controller/arm-gic.h>
-+ #include <dt-bindings/interrupt-controller/irq.h>
-+
-+ spi@1100a000 {
-+ compatible = "mediatek,mt8173-spi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x1100a000 0x1000>;
-+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
-+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
-+ <&topckgen CLK_TOP_SPI_SEL>,
-+ <&pericfg CLK_PERI_SPI0>;
-+ clock-names = "parent-clk", "sel-clk", "spi-clk";
-+ cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
-+ mediatek,pad-select = <1>, <0>;
-+ };
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -12,11 +12,12 @@
- #include <linux/ioport.h>
- #include <linux/module.h>
- #include <linux/of.h>
--#include <linux/of_gpio.h>
-+#include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
- #include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
-+#include <linux/spi/spi-mem.h>
- #include <linux/dma-mapping.h>
-
- #define SPI_CFG0_REG 0x0000
-@@ -31,6 +32,7 @@
- #define SPI_CFG2_REG 0x0028
- #define SPI_TX_SRC_REG_64 0x002c
- #define SPI_RX_DST_REG_64 0x0030
-+#define SPI_CFG3_IPM_REG 0x0040
-
- #define SPI_CFG0_SCK_HIGH_OFFSET 0
- #define SPI_CFG0_SCK_LOW_OFFSET 8
-@@ -51,6 +53,7 @@
- #define SPI_CFG1_CS_IDLE_MASK 0xff
- #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
- #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
-+#define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16)
- #define SPI_CFG2_SCK_HIGH_OFFSET 0
- #define SPI_CFG2_SCK_LOW_OFFSET 16
-
-@@ -71,6 +74,24 @@
- #define SPI_CMD_TX_ENDIAN BIT(15)
- #define SPI_CMD_FINISH_IE BIT(16)
- #define SPI_CMD_PAUSE_IE BIT(17)
-+#define SPI_CMD_IPM_NONIDLE_MODE BIT(19)
-+#define SPI_CMD_IPM_SPIM_LOOP BIT(21)
-+#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22
-+
-+#define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22)
-+
-+#define PIN_MODE_CFG(x) ((x) / 2)
-+
-+#define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2)
-+#define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3)
-+#define SPI_CFG3_IPM_XMODE_EN BIT(4)
-+#define SPI_CFG3_IPM_NODATA_FLAG BIT(5)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12
-+
-+#define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0)
-+#define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8)
-+#define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12)
-
- #define MT8173_SPI_MAX_PAD_SEL 3
-
-@@ -81,6 +102,9 @@
-
- #define MTK_SPI_MAX_FIFO_SIZE 32U
- #define MTK_SPI_PACKET_SIZE 1024
-+#define MTK_SPI_IPM_PACKET_SIZE SZ_64K
-+#define MTK_SPI_IPM_PACKET_LOOP SZ_256
-+
- #define MTK_SPI_32BITS_MASK (0xffffffff)
-
- #define DMA_ADDR_EXT_BITS (36)
-@@ -96,6 +120,8 @@ struct mtk_spi_compatible {
- bool dma_ext;
- /* some IC no need unprepare SPI clk */
- bool no_need_unprepare;
-+ /* IPM design adjust and extend register to support more features */
-+ bool ipm_design;
- };
-
- struct mtk_spi {
-@@ -103,7 +129,7 @@ struct mtk_spi {
- u32 state;
- int pad_num;
- u32 *pad_sel;
-- struct clk *parent_clk, *sel_clk, *spi_clk;
-+ struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
- struct spi_transfer *cur_transfer;
- u32 xfer_len;
- u32 num_xfered;
-@@ -111,6 +137,11 @@ struct mtk_spi {
- u32 tx_sgl_len, rx_sgl_len;
- const struct mtk_spi_compatible *dev_comp;
- u32 spi_clk_hz;
-+ struct completion spimem_done;
-+ bool use_spimem;
-+ struct device *dev;
-+ dma_addr_t tx_dma;
-+ dma_addr_t rx_dma;
- };
-
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -119,6 +150,12 @@ static const struct mtk_spi_compatible m
- .must_tx = true,
- };
-
-+static const struct mtk_spi_compatible mtk_ipm_compat = {
-+ .enhance_timing = true,
-+ .dma_ext = true,
-+ .ipm_design = true,
-+};
-+
- static const struct mtk_spi_compatible mt6765_compat = {
- .need_pad_sel = true,
- .must_tx = true,
-@@ -160,6 +197,9 @@ static const struct mtk_chip_config mtk_
- };
-
- static const struct of_device_id mtk_spi_of_match[] = {
-+ { .compatible = "mediatek,spi-ipm",
-+ .data = (void *)&mtk_ipm_compat,
-+ },
- { .compatible = "mediatek,mt2701-spi",
- .data = (void *)&mtk_common_compat,
- },
-@@ -278,12 +318,11 @@ static int mtk_spi_set_hw_cs_timing(stru
- return 0;
- }
-
--static int mtk_spi_prepare_message(struct spi_master *master,
-- struct spi_message *msg)
-+static int mtk_spi_hw_init(struct spi_master *master,
-+ struct spi_device *spi)
- {
- u16 cpha, cpol;
- u32 reg_val;
-- struct spi_device *spi = msg->spi;
- struct mtk_chip_config *chip_config = spi->controller_data;
- struct mtk_spi *mdata = spi_master_get_devdata(master);
-
-@@ -291,6 +330,15 @@ static int mtk_spi_prepare_message(struc
- cpol = spi->mode & SPI_CPOL ? 1 : 0;
-
- reg_val = readl(mdata->base + SPI_CMD_REG);
-+ if (mdata->dev_comp->ipm_design) {
-+ /* SPI transfer without idle time until packet length done */
-+ reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
-+ if (spi->mode & SPI_LOOP)
-+ reg_val |= SPI_CMD_IPM_SPIM_LOOP;
-+ else
-+ reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
-+ }
-+
- if (cpha)
- reg_val |= SPI_CMD_CPHA;
- else
-@@ -348,23 +396,39 @@ static int mtk_spi_prepare_message(struc
- mdata->base + SPI_PAD_SEL_REG);
-
- /* tick delay */
-- reg_val = readl(mdata->base + SPI_CFG1_REG);
- if (mdata->dev_comp->enhance_timing) {
-- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-- reg_val |= ((chip_config->tick_delay & 0x7)
-- << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+ if (mdata->dev_comp->ipm_design) {
-+ reg_val = readl(mdata->base + SPI_CMD_REG);
-+ reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
-+ reg_val |= ((chip_config->tick_delay & 0x7)
-+ << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
-+ writel(reg_val, mdata->base + SPI_CMD_REG);
-+ } else {
-+ reg_val = readl(mdata->base + SPI_CFG1_REG);
-+ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-+ reg_val |= ((chip_config->tick_delay & 0x7)
-+ << SPI_CFG1_GET_TICK_DLY_OFFSET);
-+ writel(reg_val, mdata->base + SPI_CFG1_REG);
-+ }
- } else {
-+ reg_val = readl(mdata->base + SPI_CFG1_REG);
- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
- reg_val |= ((chip_config->tick_delay & 0x3)
- << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
-+ writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
-- writel(reg_val, mdata->base + SPI_CFG1_REG);
-
- /* set hw cs timing */
- mtk_spi_set_hw_cs_timing(spi);
- return 0;
- }
-
-+static int mtk_spi_prepare_message(struct spi_master *master,
-+ struct spi_message *msg)
-+{
-+ return mtk_spi_hw_init(master, msg->spi);
-+}
-+
- static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
- {
- u32 reg_val;
-@@ -386,13 +450,13 @@ static void mtk_spi_set_cs(struct spi_de
- }
-
- static void mtk_spi_prepare_transfer(struct spi_master *master,
-- struct spi_transfer *xfer)
-+ u32 speed_hz)
- {
- u32 div, sck_time, reg_val;
- struct mtk_spi *mdata = spi_master_get_devdata(master);
-
-- if (xfer->speed_hz < mdata->spi_clk_hz / 2)
-- div = DIV_ROUND_UP(mdata->spi_clk_hz, xfer->speed_hz);
-+ if (speed_hz < mdata->spi_clk_hz / 2)
-+ div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
- else
- div = 1;
-
-@@ -423,12 +487,24 @@ static void mtk_spi_setup_packet(struct
- u32 packet_size, packet_loop, reg_val;
- struct mtk_spi *mdata = spi_master_get_devdata(master);
-
-- packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
-+ if (mdata->dev_comp->ipm_design)
-+ packet_size = min_t(u32,
-+ mdata->xfer_len,
-+ MTK_SPI_IPM_PACKET_SIZE);
-+ else
-+ packet_size = min_t(u32,
-+ mdata->xfer_len,
-+ MTK_SPI_PACKET_SIZE);
-+
- packet_loop = mdata->xfer_len / packet_size;
-
- reg_val = readl(mdata->base + SPI_CFG1_REG);
-- reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK);
-+ if (mdata->dev_comp->ipm_design)
-+ reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
-+ else
-+ reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
- reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
-+ reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
- reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
- writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
-@@ -523,7 +599,7 @@ static int mtk_spi_fifo_transfer(struct
- mdata->cur_transfer = xfer;
- mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
- mdata->num_xfered = 0;
-- mtk_spi_prepare_transfer(master, xfer);
-+ mtk_spi_prepare_transfer(master, xfer->speed_hz);
- mtk_spi_setup_packet(master);
-
- if (xfer->tx_buf) {
-@@ -556,7 +632,7 @@ static int mtk_spi_dma_transfer(struct s
- mdata->cur_transfer = xfer;
- mdata->num_xfered = 0;
-
-- mtk_spi_prepare_transfer(master, xfer);
-+ mtk_spi_prepare_transfer(master, xfer->speed_hz);
-
- cmd = readl(mdata->base + SPI_CMD_REG);
- if (xfer->tx_buf)
-@@ -591,6 +667,19 @@ static int mtk_spi_transfer_one(struct s
- struct spi_device *spi,
- struct spi_transfer *xfer)
- {
-+ struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
-+ u32 reg_val = 0;
-+
-+ /* prepare xfer direction and duplex mode */
-+ if (mdata->dev_comp->ipm_design) {
-+ if (!xfer->tx_buf || !xfer->rx_buf) {
-+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+ if (xfer->rx_buf)
-+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+ }
-+ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+ }
-+
- if (master->can_dma(master, spi, xfer))
- return mtk_spi_dma_transfer(master, spi, xfer);
- else
-@@ -614,8 +703,9 @@ static int mtk_spi_setup(struct spi_devi
- if (!spi->controller_data)
- spi->controller_data = (void *)&mtk_default_chip_info;
-
-- if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio))
-- gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
-+ if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
-+ /* CS de-asserted, gpiolib will handle inversion */
-+ gpiod_direction_output(spi->cs_gpiod, 0);
-
- return 0;
- }
-@@ -633,6 +723,12 @@ static irqreturn_t mtk_spi_interrupt(int
- else
- mdata->state = MTK_SPI_IDLE;
-
-+ /* SPI-MEM ops */
-+ if (mdata->use_spimem) {
-+ complete(&mdata->spimem_done);
-+ return IRQ_HANDLED;
-+ }
-+
- if (!master->can_dma(master, NULL, trans)) {
- if (trans->rx_buf) {
- cnt = mdata->xfer_len / 4;
-@@ -716,6 +812,274 @@ static irqreturn_t mtk_spi_interrupt(int
- return IRQ_HANDLED;
- }
-
-+static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
-+ struct spi_mem_op *op)
-+{
-+ int opcode_len;
-+
-+ if (op->data.dir != SPI_MEM_NO_DATA) {
-+ opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
-+ if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+ op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
-+ /* force data buffer dma-aligned. */
-+ op->data.nbytes -= op->data.nbytes % 4;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
-+ const struct spi_mem_op *op)
-+{
-+ if (!spi_mem_default_supports_op(mem, op))
-+ return false;
-+
-+ if (op->addr.nbytes && op->dummy.nbytes &&
-+ op->addr.buswidth != op->dummy.buswidth)
-+ return false;
-+
-+ if (op->addr.nbytes + op->dummy.nbytes > 16)
-+ return false;
-+
-+ if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
-+ if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
-+ MTK_SPI_IPM_PACKET_LOOP ||
-+ op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
-+ return false;
-+ }
-+
-+ return true;
-+}
-+
-+static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master,
-+ const struct spi_mem_op *op)
-+{
-+ struct mtk_spi *mdata = spi_master_get_devdata(master);
-+
-+ writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
-+ mdata->base + SPI_TX_SRC_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+ if (mdata->dev_comp->dma_ext)
-+ writel((u32)(mdata->tx_dma >> 32),
-+ mdata->base + SPI_TX_SRC_REG_64);
-+#endif
-+
-+ if (op->data.dir == SPI_MEM_DATA_IN) {
-+ writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
-+ mdata->base + SPI_RX_DST_REG);
-+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
-+ if (mdata->dev_comp->dma_ext)
-+ writel((u32)(mdata->rx_dma >> 32),
-+ mdata->base + SPI_RX_DST_REG_64);
-+#endif
-+ }
-+}
-+
-+static int mtk_spi_transfer_wait(struct spi_mem *mem,
-+ const struct spi_mem_op *op)
-+{
-+ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+ /*
-+ * For each byte we wait for 8 cycles of the SPI clock.
-+ * Since speed is defined in Hz and we want milliseconds,
-+ * so it should be 8 * 1000.
-+ */
-+ u64 ms = 8000LL;
-+
-+ if (op->data.dir == SPI_MEM_NO_DATA)
-+ ms *= 32; /* prevent we may get 0 for short transfers. */
-+ else
-+ ms *= op->data.nbytes;
-+ ms = div_u64(ms, mem->spi->max_speed_hz);
-+ ms += ms + 1000; /* 1s tolerance */
-+
-+ if (ms > UINT_MAX)
-+ ms = UINT_MAX;
-+
-+ if (!wait_for_completion_timeout(&mdata->spimem_done,
-+ msecs_to_jiffies(ms))) {
-+ dev_err(mdata->dev, "spi-mem transfer timeout\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_spi_mem_exec_op(struct spi_mem *mem,
-+ const struct spi_mem_op *op)
-+{
-+ struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
-+ u32 reg_val, nio, tx_size;
-+ char *tx_tmp_buf, *rx_tmp_buf;
-+ int ret = 0;
-+
-+ mdata->use_spimem = true;
-+ reinit_completion(&mdata->spimem_done);
-+
-+ mtk_spi_reset(mdata);
-+ mtk_spi_hw_init(mem->spi->master, mem->spi);
-+ mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz);
-+
-+ reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
-+ /* opcode byte len */
-+ reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
-+ reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
-+
-+ /* addr & dummy byte len */
-+ reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
-+ if (op->addr.nbytes || op->dummy.nbytes)
-+ reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
-+ SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
-+
-+ /* data byte len */
-+ if (op->data.dir == SPI_MEM_NO_DATA) {
-+ reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
-+ writel(0, mdata->base + SPI_CFG1_REG);
-+ } else {
-+ reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
-+ mdata->xfer_len = op->data.nbytes;
-+ mtk_spi_setup_packet(mem->spi->master);
-+ }
-+
-+ if (op->addr.nbytes || op->dummy.nbytes) {
-+ if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
-+ reg_val |= SPI_CFG3_IPM_XMODE_EN;
-+ else
-+ reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
-+ }
-+
-+ if (op->addr.buswidth == 2 ||
-+ op->dummy.buswidth == 2 ||
-+ op->data.buswidth == 2)
-+ nio = 2;
-+ else if (op->addr.buswidth == 4 ||
-+ op->dummy.buswidth == 4 ||
-+ op->data.buswidth == 4)
-+ nio = 4;
-+ else
-+ nio = 1;
-+
-+ reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
-+ reg_val |= PIN_MODE_CFG(nio);
-+
-+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-+ if (op->data.dir == SPI_MEM_DATA_IN)
-+ reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+ else
-+ reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
-+ writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
-+
-+ tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
-+ if (op->data.dir == SPI_MEM_DATA_OUT)
-+ tx_size += op->data.nbytes;
-+
-+ tx_size = max_t(u32, tx_size, 32);
-+
-+ tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA);
-+ if (!tx_tmp_buf) {
-+ mdata->use_spimem = false;
-+ return -ENOMEM;
-+ }
-+
-+ tx_tmp_buf[0] = op->cmd.opcode;
-+
-+ if (op->addr.nbytes) {
-+ int i;
-+
-+ for (i = 0; i < op->addr.nbytes; i++)
-+ tx_tmp_buf[i + 1] = op->addr.val >>
-+ (8 * (op->addr.nbytes - i - 1));
-+ }
-+
-+ if (op->dummy.nbytes)
-+ memset(tx_tmp_buf + op->addr.nbytes + 1,
-+ 0xff,
-+ op->dummy.nbytes);
-+
-+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
-+ memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
-+ op->data.buf.out,
-+ op->data.nbytes);
-+
-+ mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf,
-+ tx_size, DMA_TO_DEVICE);
-+ if (dma_mapping_error(mdata->dev, mdata->tx_dma)) {
-+ ret = -ENOMEM;
-+ goto err_exit;
-+ }
-+
-+ if (op->data.dir == SPI_MEM_DATA_IN) {
-+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
-+ rx_tmp_buf = kzalloc(op->data.nbytes,
-+ GFP_KERNEL | GFP_DMA);
-+ if (!rx_tmp_buf) {
-+ ret = -ENOMEM;
-+ goto unmap_tx_dma;
-+ }
-+ } else {
-+ rx_tmp_buf = op->data.buf.in;
-+ }
-+
-+ mdata->rx_dma = dma_map_single(mdata->dev,
-+ rx_tmp_buf,
-+ op->data.nbytes,
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
-+ ret = -ENOMEM;
-+ goto kfree_rx_tmp_buf;
-+ }
-+ }
-+
-+ reg_val = readl(mdata->base + SPI_CMD_REG);
-+ reg_val |= SPI_CMD_TX_DMA;
-+ if (op->data.dir == SPI_MEM_DATA_IN)
-+ reg_val |= SPI_CMD_RX_DMA;
-+ writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+ mtk_spi_mem_setup_dma_xfer(mem->spi->master, op);
-+
-+ mtk_spi_enable_transfer(mem->spi->master);
-+
-+ /* Wait for the interrupt. */
-+ ret = mtk_spi_transfer_wait(mem, op);
-+ if (ret)
-+ goto unmap_rx_dma;
-+
-+ /* spi disable dma */
-+ reg_val = readl(mdata->base + SPI_CMD_REG);
-+ reg_val &= ~SPI_CMD_TX_DMA;
-+ if (op->data.dir == SPI_MEM_DATA_IN)
-+ reg_val &= ~SPI_CMD_RX_DMA;
-+ writel(reg_val, mdata->base + SPI_CMD_REG);
-+
-+unmap_rx_dma:
-+ if (op->data.dir == SPI_MEM_DATA_IN) {
-+ dma_unmap_single(mdata->dev, mdata->rx_dma,
-+ op->data.nbytes, DMA_FROM_DEVICE);
-+ if (!IS_ALIGNED((size_t)op->data.buf.in, 4))
-+ memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
-+ }
-+kfree_rx_tmp_buf:
-+ if (op->data.dir == SPI_MEM_DATA_IN &&
-+ !IS_ALIGNED((size_t)op->data.buf.in, 4))
-+ kfree(rx_tmp_buf);
-+unmap_tx_dma:
-+ dma_unmap_single(mdata->dev, mdata->tx_dma,
-+ tx_size, DMA_TO_DEVICE);
-+err_exit:
-+ kfree(tx_tmp_buf);
-+ mdata->use_spimem = false;
-+
-+ return ret;
-+}
-+
-+static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
-+ .adjust_op_size = mtk_spi_mem_adjust_op_size,
-+ .supports_op = mtk_spi_mem_supports_op,
-+ .exec_op = mtk_spi_mem_exec_op,
-+};
-+
- static int mtk_spi_probe(struct platform_device *pdev)
- {
- struct spi_master *master;
-@@ -739,6 +1103,7 @@ static int mtk_spi_probe(struct platform
- master->can_dma = mtk_spi_can_dma;
- master->setup = mtk_spi_setup;
- master->set_cs_timing = mtk_spi_set_hw_cs_timing;
-+ master->use_gpio_descriptors = true;
-
- of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- if (!of_id) {
-@@ -755,6 +1120,14 @@ static int mtk_spi_probe(struct platform
-
- if (mdata->dev_comp->must_tx)
- master->flags = SPI_MASTER_MUST_TX;
-+ if (mdata->dev_comp->ipm_design)
-+ master->mode_bits |= SPI_LOOP;
-+
-+ if (mdata->dev_comp->ipm_design) {
-+ mdata->dev = &pdev->dev;
-+ master->mem_ops = &mtk_spi_mem_ops;
-+ init_completion(&mdata->spimem_done);
-+ }
-
- if (mdata->dev_comp->need_pad_sel) {
- mdata->pad_num = of_property_count_u32_elems(
-@@ -831,25 +1204,40 @@ static int mtk_spi_probe(struct platform
- goto err_put_master;
- }
-
-+ mdata->spi_hclk = devm_clk_get_optional(&pdev->dev, "hclk");
-+ if (IS_ERR(mdata->spi_hclk)) {
-+ ret = PTR_ERR(mdata->spi_hclk);
-+ dev_err(&pdev->dev, "failed to get hclk: %d\n", ret);
-+ goto err_put_master;
-+ }
-+
-+ ret = clk_prepare_enable(mdata->spi_hclk);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to enable hclk (%d)\n", ret);
-+ goto err_put_master;
-+ }
-+
- ret = clk_prepare_enable(mdata->spi_clk);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
-- goto err_put_master;
-+ goto err_disable_spi_hclk;
- }
-
- ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
-- clk_disable_unprepare(mdata->spi_clk);
-- goto err_put_master;
-+ goto err_disable_spi_clk;
- }
-
- mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
-
-- if (mdata->dev_comp->no_need_unprepare)
-+ if (mdata->dev_comp->no_need_unprepare) {
- clk_disable(mdata->spi_clk);
-- else
-+ clk_disable(mdata->spi_hclk);
-+ } else {
- clk_disable_unprepare(mdata->spi_clk);
-+ clk_disable_unprepare(mdata->spi_hclk);
-+ }
-
- pm_runtime_enable(&pdev->dev);
-
-@@ -862,25 +1250,12 @@ static int mtk_spi_probe(struct platform
- goto err_disable_runtime_pm;
- }
-
-- if (!master->cs_gpios && master->num_chipselect > 1) {
-+ if (!master->cs_gpiods && master->num_chipselect > 1) {
- dev_err(&pdev->dev,
- "cs_gpios not specified and num_chipselect > 1\n");
- ret = -EINVAL;
- goto err_disable_runtime_pm;
- }
--
-- if (master->cs_gpios) {
-- for (i = 0; i < master->num_chipselect; i++) {
-- ret = devm_gpio_request(&pdev->dev,
-- master->cs_gpios[i],
-- dev_name(&pdev->dev));
-- if (ret) {
-- dev_err(&pdev->dev,
-- "can't get CS GPIO %i\n", i);
-- goto err_disable_runtime_pm;
-- }
-- }
-- }
- }
-
- if (mdata->dev_comp->dma_ext)
-@@ -902,6 +1277,10 @@ static int mtk_spi_probe(struct platform
-
- err_disable_runtime_pm:
- pm_runtime_disable(&pdev->dev);
-+err_disable_spi_clk:
-+ clk_disable_unprepare(mdata->spi_clk);
-+err_disable_spi_hclk:
-+ clk_disable_unprepare(mdata->spi_hclk);
- err_put_master:
- spi_master_put(master);
-
-@@ -920,8 +1299,10 @@ static int mtk_spi_remove(struct platfor
-
- mtk_spi_reset(mdata);
-
-- if (mdata->dev_comp->no_need_unprepare)
-+ if (mdata->dev_comp->no_need_unprepare) {
- clk_unprepare(mdata->spi_clk);
-+ clk_unprepare(mdata->spi_hclk);
-+ }
-
- pm_runtime_put_noidle(&pdev->dev);
- pm_runtime_disable(&pdev->dev);
-@@ -940,8 +1321,10 @@ static int mtk_spi_suspend(struct device
- if (ret)
- return ret;
-
-- if (!pm_runtime_suspended(dev))
-+ if (!pm_runtime_suspended(dev)) {
- clk_disable_unprepare(mdata->spi_clk);
-+ clk_disable_unprepare(mdata->spi_hclk);
-+ }
-
- return ret;
- }
-@@ -958,11 +1341,20 @@ static int mtk_spi_resume(struct device
- dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
- return ret;
- }
-+
-+ ret = clk_prepare_enable(mdata->spi_hclk);
-+ if (ret < 0) {
-+ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+ clk_disable_unprepare(mdata->spi_clk);
-+ return ret;
-+ }
- }
-
- ret = spi_master_resume(master);
-- if (ret < 0)
-+ if (ret < 0) {
- clk_disable_unprepare(mdata->spi_clk);
-+ clk_disable_unprepare(mdata->spi_hclk);
-+ }
-
- return ret;
- }
-@@ -974,10 +1366,13 @@ static int mtk_spi_runtime_suspend(struc
- struct spi_master *master = dev_get_drvdata(dev);
- struct mtk_spi *mdata = spi_master_get_devdata(master);
-
-- if (mdata->dev_comp->no_need_unprepare)
-+ if (mdata->dev_comp->no_need_unprepare) {
- clk_disable(mdata->spi_clk);
-- else
-+ clk_disable(mdata->spi_hclk);
-+ } else {
- clk_disable_unprepare(mdata->spi_clk);
-+ clk_disable_unprepare(mdata->spi_hclk);
-+ }
-
- return 0;
- }
-@@ -988,13 +1383,31 @@ static int mtk_spi_runtime_resume(struct
- struct mtk_spi *mdata = spi_master_get_devdata(master);
- int ret;
-
-- if (mdata->dev_comp->no_need_unprepare)
-+ if (mdata->dev_comp->no_need_unprepare) {
- ret = clk_enable(mdata->spi_clk);
-- else
-+ if (ret < 0) {
-+ dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
-+ return ret;
-+ }
-+ ret = clk_enable(mdata->spi_hclk);
-+ if (ret < 0) {
-+ dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
-+ clk_disable(mdata->spi_clk);
-+ return ret;
-+ }
-+ } else {
- ret = clk_prepare_enable(mdata->spi_clk);
-- if (ret < 0) {
-- dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
-- return ret;
-+ if (ret < 0) {
-+ dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret);
-+ return ret;
-+ }
-+
-+ ret = clk_prepare_enable(mdata->spi_hclk);
-+ if (ret < 0) {
-+ dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret);
-+ clk_disable_unprepare(mdata->spi_clk);
-+ return ret;
-+ }
- }
-
- return 0;
+++ /dev/null
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
- This driver supports MediaTek MT7629 HIFSYS clocks providing
- to PCI-E and USB.
-
-+config COMMON_CLK_MT7981
-+ bool "Clock driver for MediaTek MT7981"
-+ depends on ARCH_MEDIATEK || COMPILE_TEST
-+ select COMMON_CLK_MEDIATEK
-+ default ARCH_MEDIATEK
-+ help
-+ This driver supports MediaTek MT7981 basic clocks and clocks
-+ required for various periperals found on MediaTek.
-+
-+config COMMON_CLK_MT7981_ETHSYS
-+ bool "Clock driver for MediaTek MT7981 ETHSYS"
-+ depends on COMMON_CLK_MT7981
-+ default COMMON_CLK_MT7981
-+ help
-+ This driver add support for clocks for Ethernet and SGMII
-+ required on MediaTek MT7981 SoC.
-+
- config COMMON_CLK_MT7986
- bool "Clock driver for MediaTek MT7986"
- depends on ARCH_MEDIATEK || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
--- /dev/null
+From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 26 Jan 2023 00:34:56 +0000
+Subject: [PATCH] pinctrl: add mt7981 pinctrl driver
+
+Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver
+which can also be found the SDK.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/mediatek/Kconfig | 5 +
+ drivers/pinctrl/mediatek/Makefile | 1 +
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++
+ 3 files changed, 1054 insertions(+)
+ create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
+
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -127,6 +127,11 @@ config PINCTRL_MT7622
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_MOORE
+
++config PINCTRL_MT7981
++ bool "Mediatek MT7981 pin control"
++ depends on OF
++ select PINCTRL_MTK_MOORE
++
+ config PINCTRL_MT7986
+ bool "Mediatek MT7986 pin control"
+ depends on OF
+--- a/drivers/pinctrl/mediatek/Makefile
++++ b/drivers/pinctrl/mediatek/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-
+ obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
+ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
+ obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
++obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
+ obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
+ obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
+--- /dev/null
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -0,0 +1,1048 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * The MT7981 driver based on Linux generic pinctrl binding.
++ *
++ * Copyright (C) 2020 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ */
++
++#include "pinctrl-moore.h"
++
++#define MT7981_PIN(_number, _name) \
++ MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
++
++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
++ _x_bits, 32, 0)
++
++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
++ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
++ _x_bits, 32, 1)
++
++static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
++ PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
++ PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
++ PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
++ PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
++ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
++ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
++ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
++ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
++ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
++ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
++ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
++ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
++ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
++
++ PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
++ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
++ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
++ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
++ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
++
++ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
++ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
++ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
++ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
++ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
++ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
++ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
++ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
++ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
++ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
++ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
++ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
++ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
++ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
++ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
++ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
++
++ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
++ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
++
++ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
++ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
++
++ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
++ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
++ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
++ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
++
++ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
++ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
++ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
++ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
++ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
++ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
++ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
++ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
++ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
++
++ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
++ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
++ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
++ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
++ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
++ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
++ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
++ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
++ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
++ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
++ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
++ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
++ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
++ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
++ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
++ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
++
++ PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
++ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
++ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
++ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
++ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
++
++ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
++ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
++ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
++ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
++ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
++ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
++ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
++ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
++ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
++ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
++ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
++ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
++ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
++ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
++ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
++ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
++
++ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
++ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
++
++ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
++ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
++
++ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
++ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
++ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
++ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
++
++ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
++ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
++ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
++ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
++ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
++ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
++ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
++ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
++ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
++ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
++
++ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
++ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
++ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
++ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
++ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
++ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
++ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
++ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
++ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
++ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
++ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
++ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
++ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
++ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
++ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
++ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
++ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
++
++ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
++ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
++ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
++ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
++ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
++ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
++ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
++ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
++ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
++ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
++ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
++ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
++ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
++ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
++ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
++ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
++
++ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
++ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
++ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
++ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
++ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
++ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
++ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
++ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
++ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
++
++ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
++
++ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
++ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
++ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
++ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
++
++ PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
++ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
++ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
++ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
++
++ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
++
++ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
++ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
++ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
++ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
++ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
++ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
++ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
++ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
++
++ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
++ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
++ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
++ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
++
++ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
++
++ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
++ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
++
++ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
++ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
++
++ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
++ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
++ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
++ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
++ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
++ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
++ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
++ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
++
++ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
++ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
++ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
++ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
++ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
++ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
++ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
++ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
++ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
++ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
++ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
++ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
++ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
++ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
++ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
++
++ PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
++ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
++ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
++ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
++ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
++
++ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
++ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
++ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
++ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
++ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
++ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
++ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
++ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
++ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
++ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
++ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
++ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
++ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
++ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
++
++ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
++ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
++
++ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
++ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
++
++ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
++ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
++ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
++ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
++ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
++ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
++ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
++ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
++ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
++ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
++ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
++ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
++
++ PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
++ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
++ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
++ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
++ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
++
++ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
++ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
++ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
++ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
++ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
++ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
++ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
++ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
++ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
++ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
++ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
++ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
++ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
++ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
++ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
++ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
++
++ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
++ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
++
++ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
++ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
++
++ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
++ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
++ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
++ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
++ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
++ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
++ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
++ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
++ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
++ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
++ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
++ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
++ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
++
++ PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
++ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
++ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
++ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
++ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
++
++ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
++ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
++ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
++ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
++ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
++ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
++ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
++ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
++ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
++ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
++ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
++
++ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
++ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
++ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
++ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
++ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
++ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
++
++ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
++ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
++
++ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
++ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
++
++ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
++ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
++ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
++ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
++};
++
++static const unsigned int mt7981_pull_type[] = {
++ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
++ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
++ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
++ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
++ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
++ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
++ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
++ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
++ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
++ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
++ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
++ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
++ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
++ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
++ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
++ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
++ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
++ MTK_PULL_PU_PD_TYPE,/*100*/
++};
++
++static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
++ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
++ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
++ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
++ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
++ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
++};
++
++static const struct mtk_pin_desc mt7981_pins[] = {
++ MT7981_PIN(0, "GPIO_WPS"),
++ MT7981_PIN(1, "GPIO_RESET"),
++ MT7981_PIN(2, "SYS_WATCHDOG"),
++ MT7981_PIN(3, "PCIE_PERESET_N"),
++ MT7981_PIN(4, "JTAG_JTDO"),
++ MT7981_PIN(5, "JTAG_JTDI"),
++ MT7981_PIN(6, "JTAG_JTMS"),
++ MT7981_PIN(7, "JTAG_JTCLK"),
++ MT7981_PIN(8, "JTAG_JTRST_N"),
++ MT7981_PIN(9, "WO_JTAG_JTDO"),
++ MT7981_PIN(10, "WO_JTAG_JTDI"),
++ MT7981_PIN(11, "WO_JTAG_JTMS"),
++ MT7981_PIN(12, "WO_JTAG_JTCLK"),
++ MT7981_PIN(13, "WO_JTAG_JTRST_N"),
++ MT7981_PIN(14, "USB_VBUS"),
++ MT7981_PIN(15, "PWM0"),
++ MT7981_PIN(16, "SPI0_CLK"),
++ MT7981_PIN(17, "SPI0_MOSI"),
++ MT7981_PIN(18, "SPI0_MISO"),
++ MT7981_PIN(19, "SPI0_CS"),
++ MT7981_PIN(20, "SPI0_HOLD"),
++ MT7981_PIN(21, "SPI0_WP"),
++ MT7981_PIN(22, "SPI1_CLK"),
++ MT7981_PIN(23, "SPI1_MOSI"),
++ MT7981_PIN(24, "SPI1_MISO"),
++ MT7981_PIN(25, "SPI1_CS"),
++ MT7981_PIN(26, "SPI2_CLK"),
++ MT7981_PIN(27, "SPI2_MOSI"),
++ MT7981_PIN(28, "SPI2_MISO"),
++ MT7981_PIN(29, "SPI2_CS"),
++ MT7981_PIN(30, "SPI2_HOLD"),
++ MT7981_PIN(31, "SPI2_WP"),
++ MT7981_PIN(32, "UART0_RXD"),
++ MT7981_PIN(33, "UART0_TXD"),
++ MT7981_PIN(34, "PCIE_CLK_REQ"),
++ MT7981_PIN(35, "PCIE_WAKE_N"),
++ MT7981_PIN(36, "SMI_MDC"),
++ MT7981_PIN(37, "SMI_MDIO"),
++ MT7981_PIN(38, "GBE_INT"),
++ MT7981_PIN(39, "GBE_RESET"),
++ MT7981_PIN(40, "WF_DIG_RESETB"),
++ MT7981_PIN(41, "WF_CBA_RESETB"),
++ MT7981_PIN(42, "WF_XO_REQ"),
++ MT7981_PIN(43, "WF_TOP_CLK"),
++ MT7981_PIN(44, "WF_TOP_DATA"),
++ MT7981_PIN(45, "WF_HB1"),
++ MT7981_PIN(46, "WF_HB2"),
++ MT7981_PIN(47, "WF_HB3"),
++ MT7981_PIN(48, "WF_HB4"),
++ MT7981_PIN(49, "WF_HB0"),
++ MT7981_PIN(50, "WF_HB0_B"),
++ MT7981_PIN(51, "WF_HB5"),
++ MT7981_PIN(52, "WF_HB6"),
++ MT7981_PIN(53, "WF_HB7"),
++ MT7981_PIN(54, "WF_HB8"),
++ MT7981_PIN(55, "WF_HB9"),
++ MT7981_PIN(56, "WF_HB10"),
++};
++
++/* List all groups consisting of these pins dedicated to the enablement of
++ * certain hardware block and the corresponding mode for all of the pins.
++ * The hardware probably has multiple combinations of these pinouts.
++ */
++
++/* WA_AICE */
++static int mt7981_wa_aice1_pins[] = { 0, 1, };
++static int mt7981_wa_aice1_funcs[] = { 2, 2, };
++
++static int mt7981_wa_aice2_pins[] = { 0, 1, };
++static int mt7981_wa_aice2_funcs[] = { 3, 3, };
++
++static int mt7981_wa_aice3_pins[] = { 28, 29, };
++static int mt7981_wa_aice3_funcs[] = { 3, 3, };
++
++static int mt7981_wm_aice1_pins[] = { 9, 10, };
++static int mt7981_wm_aice1_funcs[] = { 2, 2, };
++
++static int mt7981_wm_aice2_pins[] = { 30, 31, };
++static int mt7981_wm_aice2_funcs[] = { 5, 5, };
++
++/* WM_UART */
++static int mt7981_wm_uart_0_pins[] = { 0, 1, };
++static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
++
++static int mt7981_wm_uart_1_pins[] = { 20, 21, };
++static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
++
++static int mt7981_wm_uart_2_pins[] = { 30, 31, };
++static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
++
++/* DFD */
++static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
++static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
++
++/* SYS_WATCHDOG */
++static int mt7981_watchdog_pins[] = { 2, };
++static int mt7981_watchdog_funcs[] = { 1, };
++
++static int mt7981_watchdog1_pins[] = { 13, };
++static int mt7981_watchdog1_funcs[] = { 5, };
++
++/* PCIE_PERESET_N */
++static int mt7981_pcie_pereset_pins[] = { 3, };
++static int mt7981_pcie_pereset_funcs[] = { 1, };
++
++/* JTAG */
++static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
++static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
++
++/* WM_JTAG */
++static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
++static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
++
++static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
++static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
++
++/* WO0_JTAG */
++static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
++static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
++
++static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
++static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
++
++/* UART2 */
++static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
++static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
++
++/* GBE_LED0 */
++static int mt7981_gbe_led0_pins[] = { 8, };
++static int mt7981_gbe_led0_funcs[] = { 3, };
++
++/* PTA_EXT */
++static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
++static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
++
++static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
++static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
++
++/* PWM2 */
++static int mt7981_pwm2_pins[] = { 7, };
++static int mt7981_pwm2_funcs[] = { 4, };
++
++/* NET_WO0_UART_TXD */
++static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
++static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
++
++static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
++static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
++
++static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
++static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
++
++/* SPI1 */
++static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
++static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
++
++/* I2C */
++static int mt7981_i2c0_0_pins[] = { 6, 7, };
++static int mt7981_i2c0_0_funcs[] = { 6, 6, };
++
++static int mt7981_i2c0_1_pins[] = { 30, 31, };
++static int mt7981_i2c0_1_funcs[] = { 4, 4, };
++
++static int mt7981_i2c0_2_pins[] = { 36, 37, };
++static int mt7981_i2c0_2_funcs[] = { 2, 2, };
++
++static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
++static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
++
++static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
++
++static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
++
++static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
++
++/* DFD_NTRST */
++static int mt7981_dfd_ntrst_pins[] = { 8, };
++static int mt7981_dfd_ntrst_funcs[] = { 6, };
++
++/* PWM0 */
++static int mt7981_pwm0_0_pins[] = { 13, };
++static int mt7981_pwm0_0_funcs[] = { 2, };
++
++static int mt7981_pwm0_1_pins[] = { 15, };
++static int mt7981_pwm0_1_funcs[] = { 1, };
++
++/* PWM1 */
++static int mt7981_pwm1_0_pins[] = { 14, };
++static int mt7981_pwm1_0_funcs[] = { 2, };
++
++static int mt7981_pwm1_1_pins[] = { 15, };
++static int mt7981_pwm1_1_funcs[] = { 3, };
++
++/* GBE_LED1 */
++static int mt7981_gbe_led1_pins[] = { 13, };
++static int mt7981_gbe_led1_funcs[] = { 3, };
++
++/* PCM */
++static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
++static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
++
++/* UDI */
++static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
++static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
++
++/* DRV_VBUS */
++static int mt7981_drv_vbus_pins[] = { 14, };
++static int mt7981_drv_vbus_funcs[] = { 1, };
++
++/* EMMC */
++static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
++static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
++
++/* SNFI */
++static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
++static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
++
++/* SPI0 */
++static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
++static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI0 */
++static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
++static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
++
++/* SPI1 */
++static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
++static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI2 */
++static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
++static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI2 */
++static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
++static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
++
++/* UART1 */
++static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
++static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
++
++static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
++static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
++
++/* UART2 */
++static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
++static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
++
++/* UART0 */
++static int mt7981_uart0_pins[] = { 32, 33, };
++static int mt7981_uart0_funcs[] = { 1, 1, };
++
++/* PCIE_CLK_REQ */
++static int mt7981_pcie_clk_pins[] = { 34, };
++static int mt7981_pcie_clk_funcs[] = { 2, };
++
++/* PCIE_WAKE_N */
++static int mt7981_pcie_wake_pins[] = { 35, };
++static int mt7981_pcie_wake_funcs[] = { 2, };
++
++/* MDC_MDIO */
++static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
++static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
++
++static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
++static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
++
++/* WF0_MODE1 */
++static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
++static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
++
++/* WF0_MODE3 */
++static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
++static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
++
++/* WF2G_LED */
++static int mt7981_wf2g_led0_pins[] = { 30, };
++static int mt7981_wf2g_led0_funcs[] = { 2, };
++
++static int mt7981_wf2g_led1_pins[] = { 34, };
++static int mt7981_wf2g_led1_funcs[] = { 1, };
++
++/* WF5G_LED */
++static int mt7981_wf5g_led0_pins[] = { 31, };
++static int mt7981_wf5g_led0_funcs[] = { 2, };
++
++static int mt7981_wf5g_led1_pins[] = { 35, };
++static int mt7981_wf5g_led1_funcs[] = { 1, };
++
++/* MT7531_INT */
++static int mt7981_mt7531_int_pins[] = { 38, };
++static int mt7981_mt7531_int_funcs[] = { 1, };
++
++/* ANT_SEL */
++static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
++static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
++
++static const struct group_desc mt7981_groups[] = {
++ /* @GPIO(0,1): WA_AICE(2) */
++ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
++ /* @GPIO(0,1): WA_AICE(3) */
++ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
++ /* @GPIO(0,1): WM_UART(5) */
++ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
++ /* @GPIO(0,1,4,5): DFD(6) */
++ PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
++ /* @GPIO(2): SYS_WATCHDOG(1) */
++ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
++ /* @GPIO(3): PCIE_PERESET_N(1) */
++ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
++ /* @GPIO(4,8) JTAG(1) */
++ PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
++ /* @GPIO(4,8) WM_JTAG(2) */
++ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
++ /* @GPIO(9,13) WO0_JTAG(1) */
++ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
++ /* @GPIO(4,7) WM_JTAG(3) */
++ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
++ /* @GPIO(8) GBE_LED0(3) */
++ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
++ /* @GPIO(4,6) PTA_EXT(4) */
++ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
++ /* @GPIO(7) PWM2(4) */
++ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
++ /* @GPIO(8) NET_WO0_UART_TXD(4) */
++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
++ /* @GPIO(4,7) SPI1(5) */
++ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
++ /* @GPIO(6,7) I2C(5) */
++ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
++ /* @GPIO(0,1,4,5): DFD_NTRST(6) */
++ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
++ /* @GPIO(9,10): WM_AICE(2) */
++ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
++ /* @GPIO(13): PWM0(2) */
++ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
++ /* @GPIO(15): PWM0(1) */
++ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
++ /* @GPIO(14): PWM1(2) */
++ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
++ /* @GPIO(15): PWM1(3) */
++ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
++ /* @GPIO(14) NET_WO0_UART_TXD(3) */
++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
++ /* @GPIO(15) NET_WO0_UART_TXD(4) */
++ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
++ /* @GPIO(13) GBE_LED0(3) */
++ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
++ /* @GPIO(9,13) PCM(4) */
++ PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
++ /* @GPIO(13): SYS_WATCHDOG1(5) */
++ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
++ /* @GPIO(9,13) UDI(4) */
++ PINCTRL_PIN_GROUP("udi", mt7981_udi),
++ /* @GPIO(14) DRV_VBUS(1) */
++ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
++ /* @GPIO(15,25): EMMC(2) */
++ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
++ /* @GPIO(16,21): SNFI(3) */
++ PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
++ /* @GPIO(16,19): SPI0(1) */
++ PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
++ /* @GPIO(20,21): SPI0(1) */
++ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
++ /* @GPIO(22,25) SPI1(1) */
++ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
++ /* @GPIO(26,29): SPI2(1) */
++ PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
++ /* @GPIO(30,31): SPI0(1) */
++ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
++ /* @GPIO(16,19): UART1(4) */
++ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
++ /* @GPIO(26,29): UART1(2) */
++ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
++ /* @GPIO(22,25): UART1(3) */
++ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
++ /* @GPIO(22,24) PTA_EXT(4) */
++ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
++ /* @GPIO(20,21): WM_UART(4) */
++ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
++ /* @GPIO(30,31): WM_UART(3) */
++ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
++ /* @GPIO(20,24) WM_JTAG(5) */
++ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
++ /* @GPIO(25,29) WO0_JTAG(5) */
++ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
++ /* @GPIO(28,29): WA_AICE(3) */
++ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
++ /* @GPIO(30,31): WM_AICE(5) */
++ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
++ /* @GPIO(30,31): I2C(4) */
++ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
++ /* @GPIO(30,31): I2C(6) */
++ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
++ /* @GPIO(32,33): I2C(1) */
++ PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
++ /* @GPIO(32,33): I2C(2) */
++ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
++ /* @GPIO(32,33): I2C(3) */
++ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
++ /* @GPIO(32,33): I2C(5) */
++ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
++ /* @GPIO(34): PCIE_CLK_REQ(2) */
++ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
++ /* @GPIO(35): PCIE_WAKE_N(2) */
++ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
++ /* @GPIO(36,37): I2C(2) */
++ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
++ /* @GPIO(36,37): MDC_MDIO(1) */
++ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
++ /* @GPIO(36,37): MDC_MDIO(3) */
++ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
++ /* @GPIO(69,85): WF0_MODE1(1) */
++ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
++ /* @GPIO(74,80): WF0_MODE3(3) */
++ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
++ /* @GPIO(30): WF2G_LED(2) */
++ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
++ /* @GPIO(34): WF2G_LED(1) */
++ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
++ /* @GPIO(31): WF5G_LED(2) */
++ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
++ /* @GPIO(35): WF5G_LED(1) */
++ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
++ /* @GPIO(38): MT7531_INT(1) */
++ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
++ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
++ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
++};
++
++/* Joint those groups owning the same capability in user point of view which
++ * allows that people tend to use through the device tree.
++ */
++static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
++ "wa_aice3", "wm_aice1_2", };
++static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
++ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
++ "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
++static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
++static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
++static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
++static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
++ "wo0_jtag_1", "wm_jtag_1", };
++static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
++ "wf2g_led1", "wf5g_led0", "wf5g_led1", };
++static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
++static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
++ "pwm1_0", "pwm1_1", };
++static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
++ "spi2_wp_hold", };
++static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
++ "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
++static const char *mt7981_pcm_groups[] = { "pcm", };
++static const char *mt7981_udi_groups[] = { "udi", };
++static const char *mt7981_usb_groups[] = { "drv_vbus", };
++static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
++static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
++ "wf0_mode1", "wf0_mode3", "mt7531_int", };
++static const char *mt7981_ant_groups[] = { "ant_sel", };
++
++static const struct function_desc mt7981_functions[] = {
++ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
++ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
++ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
++ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
++ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
++ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
++ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
++ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
++ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
++ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
++ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
++ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
++ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
++ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
++ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
++ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
++ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
++};
++
++static const struct mtk_eint_hw mt7981_eint_hw = {
++ .port_mask = 7,
++ .ports = 7,
++ .ap_num = ARRAY_SIZE(mt7981_pins),
++ .db_cnt = 16,
++};
++
++static const char * const mt7981_pinctrl_register_base_names[] = {
++ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
++ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
++};
++
++static struct mtk_pin_soc mt7981_data = {
++ .reg_cal = mt7981_reg_cals,
++ .pins = mt7981_pins,
++ .npins = ARRAY_SIZE(mt7981_pins),
++ .grps = mt7981_groups,
++ .ngrps = ARRAY_SIZE(mt7981_groups),
++ .funcs = mt7981_functions,
++ .nfuncs = ARRAY_SIZE(mt7981_functions),
++ .eint_hw = &mt7981_eint_hw,
++ .gpio_m = 0,
++ .ies_present = false,
++ .base_names = mt7981_pinctrl_register_base_names,
++ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
++ .pull_type = mt7981_pull_type,
++ .bias_set_combo = mtk_pinconf_bias_set_combo,
++ .bias_get_combo = mtk_pinconf_bias_get_combo,
++ .drive_set = mtk_pinconf_drive_set_rev1,
++ .drive_get = mtk_pinconf_drive_get_rev1,
++ .adv_pull_get = mtk_pinconf_adv_pull_get,
++ .adv_pull_set = mtk_pinconf_adv_pull_set,
++};
++
++static const struct of_device_id mt7981_pinctrl_of_match[] = {
++ { .compatible = "mediatek,mt7981-pinctrl", },
++ {}
++};
++
++static int mt7981_pinctrl_probe(struct platform_device *pdev)
++{
++ return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
++}
++
++static struct platform_driver mt7981_pinctrl_driver = {
++ .driver = {
++ .name = "mt7981-pinctrl",
++ .of_match_table = mt7981_pinctrl_of_match,
++ },
++ .probe = mt7981_pinctrl_probe,
++};
++
++static int __init mt7981_pinctrl_init(void)
++{
++ return platform_driver_register(&mt7981_pinctrl_driver);
++}
++arch_initcall(mt7981_pinctrl_init);
+++ /dev/null
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -120,6 +120,13 @@ config PINCTRL_MT7622
- default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK_MOORE
-
-+config PINCTRL_MT7981
-+ bool "Mediatek MT7981 pin control"
-+ depends on OF
-+ depends on ARM64 || COMPILE_TEST
-+ default ARM64 && ARCH_MEDIATEK
-+ select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT7986
- bool "Mediatek MT7986 pin control"
- depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
--- /dev/null
+From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sat, 18 Feb 2023 09:51:06 +0300
+Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are options missing from PINCTRL_MT7981 whilst being on every other
+pin controller. Add them.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/mediatek/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -130,6 +130,8 @@ config PINCTRL_MT7622
+ config PINCTRL_MT7981
+ bool "Mediatek MT7981 pin control"
+ depends on OF
++ depends on ARM64 || COMPILE_TEST
++ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_MOORE
+
+ config PINCTRL_MT7986
--- /dev/null
+From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:33 +0100
+Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
+ mtk_clk_register_gates()
+
+Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
+introduces a helper function for the sole purpose of propagating a
+struct device pointer to the clk API when registering the mtk-gate
+clocks to take advantage of Runtime PM when/where needed and where
+a power domain is defined in devicetree.
+
+Function mtk_clk_register_gates() then becomes a wrapper around the
+new mtk_clk_register_gates_with_dev() function that will simply pass
+NULL as struct device: this is essential when registering drivers
+with CLK_OF_DECLARE instead of as a platform device, as there will
+be no struct device to pass... but we can as well simply have only
+one function that always takes such pointer as a param and pass NULL
+when unavoidable.
+
+This commit removes the mtk_clk_register_gates() wrapper and renames
+mtk_clk_register_gates_with_dev() to the former and all of the calls
+to either of the two functions were fixed in all drivers in order to
+reflect this change; also, to improve consistency with other kernel
+functions, the pointer to struct device was moved as the first param.
+
+Since a lot of MediaTek clock drivers are actually registering as a
+platform device, but were still registering the mtk-gate clocks
+without passing any struct device to the clock framework, they've
+been changed to pass a valid one now, as to make all those platforms
+able to use runtime power management where available.
+
+While at it, some much needed indentation changes were also done.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+
+[daniel@makrotopia.org: dropped parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-gate.c | 23 +++++++---------------
+ drivers/clk/mediatek/clk-gate.h | 7 +------
+ drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++--
+ drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++--
+ drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +-
+ drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++--
+ drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++--
+ drivers/clk/mediatek/clk-mt2701.c | 12 +++++------
+ drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++--
+ drivers/clk/mediatek/clk-mt2712.c | 12 +++++------
+ drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++--
+ drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++----
+ drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++----
+ drivers/clk/mediatek/clk-mt7622.c | 14 ++++++-------
+ drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++---
+ drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++----
+ drivers/clk/mediatek/clk-mt7629.c | 10 +++++-----
+ drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++-----
+ drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++--
+ 19 files changed, 68 insertions(+), 81 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-gate.c
++++ b/drivers/clk/mediatek/clk-gate.c
+@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
+ };
+ EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
+
+-static struct clk_hw *mtk_clk_register_gate(const char *name,
++static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name,
+ struct regmap *regmap, int set_ofs,
+ int clr_ofs, int sta_ofs, u8 bit,
+ const struct clk_ops *ops,
+- unsigned long flags, struct device *dev)
++ unsigned long flags)
+ {
+ struct mtk_clk_gate *cg;
+ int ret;
+@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
+ kfree(cg);
+ }
+
+-int mtk_clk_register_gates_with_dev(struct device_node *node,
+- const struct mtk_gate *clks, int num,
+- struct clk_hw_onecell_data *clk_data,
+- struct device *dev)
++int mtk_clk_register_gates(struct device *dev, struct device_node *node,
++ const struct mtk_gate *clks, int num,
++ struct clk_hw_onecell_data *clk_data)
+ {
+ int i;
+ struct clk_hw *hw;
+@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
+ continue;
+ }
+
+- hw = mtk_clk_register_gate(gate->name, gate->parent_name,
++ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
+ regmap,
+ gate->regs->set_ofs,
+ gate->regs->clr_ofs,
+ gate->regs->sta_ofs,
+ gate->shift, gate->ops,
+- gate->flags, dev);
++ gate->flags);
+
+ if (IS_ERR(hw)) {
+ pr_err("Failed to register clk %s: %pe\n", gate->name,
+@@ -261,14 +260,6 @@ err:
+
+ return PTR_ERR(hw);
+ }
+-EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
+-
+-int mtk_clk_register_gates(struct device_node *node,
+- const struct mtk_gate *clks, int num,
+- struct clk_hw_onecell_data *clk_data)
+-{
+- return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
+-}
+ EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
+
+ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
+--- a/drivers/clk/mediatek/clk-gate.h
++++ b/drivers/clk/mediatek/clk-gate.h
+@@ -50,15 +50,10 @@ struct mtk_gate {
+ #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
+ GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
+
+-int mtk_clk_register_gates(struct device_node *node,
++int mtk_clk_register_gates(struct device *dev, struct device_node *node,
+ const struct mtk_gate *clks, int num,
+ struct clk_hw_onecell_data *clk_data);
+
+-int mtk_clk_register_gates_with_dev(struct device_node *node,
+- const struct mtk_gate *clks, int num,
+- struct clk_hw_onecell_data *clk_data,
+- struct device *dev);
+-
+ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
+ struct clk_hw_onecell_data *clk_data);
+
+--- a/drivers/clk/mediatek/clk-mt2701-aud.c
++++ b/drivers/clk/mediatek/clk-mt2701-aud.c
+@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
+
+ clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+
+- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, audio_clks,
++ ARRAY_SIZE(audio_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+--- a/drivers/clk/mediatek/clk-mt2701-eth.c
++++ b/drivers/clk/mediatek/clk-mt2701-eth.c
+@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
+
+ clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+
+- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++ ARRAY_SIZE(eth_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
+@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
+
+ clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+
+- mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
++ mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
+ clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mt2701-hif.c
++++ b/drivers/clk/mediatek/clk-mt2701-hif.c
+@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
+
+ clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+
+- mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, hif_clks,
++ ARRAY_SIZE(hif_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+--- a/drivers/clk/mediatek/clk-mt2701-mm.c
++++ b/drivers/clk/mediatek/clk-mt2701-mm.c
+@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+
+- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, mm_clks,
++ ARRAY_SIZE(mm_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -683,8 +683,8 @@ static int mtk_topckgen_init(struct plat
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ base, &mt2701_clk_lock, clk_data);
+
+- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, top_clks,
++ ARRAY_SIZE(top_clks), clk_data);
+
+ return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ }
+@@ -783,8 +783,8 @@ static int mtk_infrasys_init(struct plat
+ }
+ }
+
+- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+- infra_clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++ ARRAY_SIZE(infra_clks), infra_clk_data);
+ mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ infra_clk_data);
+
+@@ -894,8 +894,8 @@ static int mtk_pericfg_init(struct platf
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
+
+- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++ ARRAY_SIZE(peri_clks), clk_data);
+
+ mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+ &mt2701_clk_lock, clk_data);
+--- a/drivers/clk/mediatek/clk-mt2712-mm.c
++++ b/drivers/clk/mediatek/clk-mt2712-mm.c
+@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, mm_clks,
++ ARRAY_SIZE(mm_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
+ &mt2712_clk_lock, top_clk_data);
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ &mt2712_clk_lock, top_clk_data);
+- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+- top_clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, top_clks,
++ ARRAY_SIZE(top_clks), top_clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
+
+@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++ ARRAY_SIZE(infra_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++ ARRAY_SIZE(peri_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+--- a/drivers/clk/mediatek/clk-mt7622-aud.c
++++ b/drivers/clk/mediatek/clk-mt7622-aud.c
+@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
+
+ clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+
+- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, audio_clks,
++ ARRAY_SIZE(audio_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+--- a/drivers/clk/mediatek/clk-mt7622-eth.c
++++ b/drivers/clk/mediatek/clk-mt7622-eth.c
+@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
+
+ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+
+- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++ ARRAY_SIZE(eth_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
+
+ clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+
+- mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
++ ARRAY_SIZE(sgmii_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt7622-hif.c
++++ b/drivers/clk/mediatek/clk-mt7622-hif.c
+@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
+
+ clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+
+- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
++ ARRAY_SIZE(ssusb_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
+
+ clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+
+- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
++ ARRAY_SIZE(pcie_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ base, &mt7622_clk_lock, clk_data);
+
+- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, top_clks,
++ ARRAY_SIZE(top_clks), clk_data);
+
+ return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ }
+@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++ ARRAY_SIZE(infra_clks), clk_data);
+
+ mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ clk_data);
+@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ clk_data);
+
+- mtk_clk_register_gates(node, apmixed_clks,
++ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
+ ARRAY_SIZE(apmixed_clks), clk_data);
+
+ return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++ ARRAY_SIZE(peri_clks), clk_data);
+
+ mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ &mt7622_clk_lock, clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629-eth.c
++++ b/drivers/clk/mediatek/clk-mt7629-eth.c
+@@ -80,7 +80,8 @@ static int clk_mt7629_ethsys_init(struct
+
+ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+
+- mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++ CLK_ETH_NR_CLK, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+@@ -102,8 +103,8 @@ static int clk_mt7629_sgmiisys_init(stru
+
+ clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+
+- mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
++ CLK_SGMII_NR_CLK, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt7629-hif.c
++++ b/drivers/clk/mediatek/clk-mt7629-hif.c
+@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
+
+ clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+
+- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
++ ARRAY_SIZE(ssusb_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
+
+ clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+
+- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
++ ARRAY_SIZE(pcie_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -581,8 +581,8 @@ static int mtk_infrasys_init(struct plat
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++ ARRAY_SIZE(infra_clks), clk_data);
+
+ mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ clk_data);
+@@ -604,8 +604,8 @@ static int mtk_pericfg_init(struct platf
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++ ARRAY_SIZE(peri_clks), clk_data);
+
+ mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ &mt7629_clk_lock, clk_data);
+@@ -631,7 +631,7 @@ static int mtk_apmixedsys_init(struct pl
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ clk_data);
+
+- mtk_clk_register_gates(node, apmixed_clks,
++ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
+ ARRAY_SIZE(apmixed_clks), clk_data);
+
+ clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+--- a/drivers/clk/mediatek/clk-mt7986-eth.c
++++ b/drivers/clk/mediatek/clk-mt7986-eth.c
+@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
+
+- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
+- clk_data);
++ mtk_clk_register_gates(NULL, node, sgmii0_clks,
++ ARRAY_SIZE(sgmii0_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
+
+- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
+- clk_data);
++ mtk_clk_register_gates(NULL, node, sgmii1_clks,
++ ARRAY_SIZE(sgmii1_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
+
+- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
++ mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
+@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+ mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
+ &mt7986_clk_lock, clk_data);
+- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+- clk_data);
++ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++ ARRAY_SIZE(infra_clks), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
+ if (!clk_data)
+ return -ENOMEM;
+
+- r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
+- clk_data, &pdev->dev);
++ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
++ clk_data);
+ if (r)
+ goto free_data;
+
--- /dev/null
+From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:34 +0100
+Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where
+ possible
+
+Take a pointer to a struct device in mtk_clk_register_cpumuxes() and
+propagate the same to mtk_clk_register_cpumux() => clk_hw_register().
+Even though runtime pm is unlikely to be used with CPU muxes, this
+helps with code consistency and possibly opens to commonization of
+some mtk_clk_register_(x) functions.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-cpumux.c | 8 ++++----
+ drivers/clk/mediatek/clk-cpumux.h | 2 +-
+ drivers/clk/mediatek/clk-mt2701.c | 2 +-
+ drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++-
+ drivers/clk/mediatek/clk-mt7622.c | 4 ++--
+ drivers/clk/mediatek/clk-mt7629.c | 4 ++--
+ drivers/clk/mediatek/clk-mt8173.c | 4 ++--
+ 7 files changed, 14 insertions(+), 13 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-cpumux.c
++++ b/drivers/clk/mediatek/clk-cpumux.c
+@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o
+ };
+
+ static struct clk_hw *
+-mtk_clk_register_cpumux(const struct mtk_composite *mux,
++mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
+ struct regmap *regmap)
+ {
+ struct mtk_clk_cpumux *cpumux;
+@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk
+ cpumux->regmap = regmap;
+ cpumux->hw.init = &init;
+
+- ret = clk_hw_register(NULL, &cpumux->hw);
++ ret = clk_hw_register(dev, &cpumux->hw);
+ if (ret) {
+ kfree(cpumux);
+ return ERR_PTR(ret);
+@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st
+ kfree(cpumux);
+ }
+
+-int mtk_clk_register_cpumuxes(struct device_node *node,
++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
+ const struct mtk_composite *clks, int num,
+ struct clk_hw_onecell_data *clk_data)
+ {
+@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev
+ continue;
+ }
+
+- hw = mtk_clk_register_cpumux(mux, regmap);
++ hw = mtk_clk_register_cpumux(dev, mux, regmap);
+ if (IS_ERR(hw)) {
+ pr_err("Failed to register clk %s: %pe\n", mux->name,
+ hw);
+--- a/drivers/clk/mediatek/clk-cpumux.h
++++ b/drivers/clk/mediatek/clk-cpumux.h
+@@ -11,7 +11,7 @@ struct clk_hw_onecell_data;
+ struct device_node;
+ struct mtk_composite;
+
+-int mtk_clk_register_cpumuxes(struct device_node *node,
++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
+ const struct mtk_composite *clks, int num,
+ struct clk_hw_onecell_data *clk_data);
+
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -757,7 +757,7 @@ static void __init mtk_infrasys_init_ear
+ mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ infra_clk_data);
+
+- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ infra_clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
+@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str
+ if (ret)
+ goto free_clk_data;
+
+- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
++ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
++ ARRAY_SIZE(cpu_muxes), clk_data);
+ if (ret)
+ goto unregister_gates;
+
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
+
+- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+- clk_data);
++ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
++ ARRAY_SIZE(infra_muxes), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+ clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -584,8 +584,8 @@ static int mtk_infrasys_init(struct plat
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
+
+- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+- clk_data);
++ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
++ ARRAY_SIZE(infra_muxes), clk_data);
+
+ return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+ clk_data);
+--- a/drivers/clk/mediatek/clk-mt8173.c
++++ b/drivers/clk/mediatek/clk-mt8173.c
+@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str
+ clk_data);
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+
+- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+- clk_data);
++ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes,
++ ARRAY_SIZE(cpu_muxes), clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
--- /dev/null
+From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:35 +0100
+Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
+ composites
+
+Like done for cpumux clocks, propagate struct device for composite
+clocks registered through clk-mtk helpers to be able to get runtime
+pm support for MTK clocks.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+
+[daniel@makrotopia.org: remove parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
+ drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
+ drivers/clk/mediatek/clk-mt7622.c | 8 +++++---
+ drivers/clk/mediatek/clk-mt7629.c | 8 +++++---
+ drivers/clk/mediatek/clk-mtk.c | 11 ++++++-----
+ drivers/clk/mediatek/clk-mtk.h | 3 ++-
+ 6 files changed, 32 insertions(+), 20 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -677,8 +677,9 @@ static int mtk_topckgen_init(struct plat
+ mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
+ clk_data);
+
+- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+- base, &mt2701_clk_lock, clk_data);
++ mtk_clk_register_composites(&pdev->dev, top_muxes,
++ ARRAY_SIZE(top_muxes), base,
++ &mt2701_clk_lock, clk_data);
+
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ base, &mt2701_clk_lock, clk_data);
+@@ -897,8 +898,9 @@ static int mtk_pericfg_init(struct platf
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
+
+- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+- &mt2701_clk_lock, clk_data);
++ mtk_clk_register_composites(&pdev->dev, peri_muxs,
++ ARRAY_SIZE(peri_muxs), base,
++ &mt2701_clk_lock, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
+ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ top_clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+- &mt2712_clk_lock, top_clk_data);
++ mtk_clk_register_composites(&pdev->dev, top_muxes,
++ ARRAY_SIZE(top_muxes), base,
++ &mt2712_clk_lock, top_clk_data);
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ &mt2712_clk_lock, top_clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
+@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
+
+ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+
+- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
+- &mt2712_clk_lock, clk_data);
++ r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
++ ARRAY_SIZE(mcu_muxes), base,
++ &mt2712_clk_lock, clk_data);
++ if (r)
++ dev_err(&pdev->dev, "Could not register composites: %d\n", r);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ clk_data);
+
+- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+- base, &mt7622_clk_lock, clk_data);
++ mtk_clk_register_composites(&pdev->dev, top_muxes,
++ ARRAY_SIZE(top_muxes), base,
++ &mt7622_clk_lock, clk_data);
+
+ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ base, &mt7622_clk_lock, clk_data);
+@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
+
+- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
++ mtk_clk_register_composites(&pdev->dev, peri_muxes,
++ ARRAY_SIZE(peri_muxes), base,
+ &mt7622_clk_lock, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -564,8 +564,9 @@ static int mtk_topckgen_init(struct plat
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ clk_data);
+
+- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+- base, &mt7629_clk_lock, clk_data);
++ mtk_clk_register_composites(&pdev->dev, top_muxes,
++ ARRAY_SIZE(top_muxes), base,
++ &mt7629_clk_lock, clk_data);
+
+ clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
+ clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
+@@ -607,7 +608,8 @@ static int mtk_pericfg_init(struct platf
+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ ARRAY_SIZE(peri_clks), clk_data);
+
+- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
++ mtk_clk_register_composites(&pdev->dev, peri_muxes,
++ ARRAY_SIZE(peri_muxes), base,
+ &mt7629_clk_lock, clk_data);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
+ }
+ EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
+
+-static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
+- void __iomem *base, spinlock_t *lock)
++static struct clk_hw *mtk_clk_register_composite(struct device *dev,
++ const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
+ {
+ struct clk_hw *hw;
+ struct clk_mux *mux = NULL;
+@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
+ div_ops = &clk_divider_ops;
+ }
+
+- hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
++ hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
+ mux_hw, mux_ops,
+ div_hw, div_ops,
+ gate_hw, gate_ops,
+@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
+ kfree(mux);
+ }
+
+-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
++int mtk_clk_register_composites(struct device *dev,
++ const struct mtk_composite *mcs, int num,
+ void __iomem *base, spinlock_t *lock,
+ struct clk_hw_onecell_data *clk_data)
+ {
+@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
+ continue;
+ }
+
+- hw = mtk_clk_register_composite(mc, base, lock);
++ hw = mtk_clk_register_composite(dev, mc, base, lock);
+
+ if (IS_ERR(hw)) {
+ pr_err("Failed to register clk %s: %pe\n", mc->name,
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -149,7 +149,8 @@ struct mtk_composite {
+ .flags = 0, \
+ }
+
+-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
++int mtk_clk_register_composites(struct device *dev,
++ const struct mtk_composite *mcs, int num,
+ void __iomem *base, spinlock_t *lock,
+ struct clk_hw_onecell_data *clk_data);
+ void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
--- /dev/null
+From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:36 +0100
+Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
+ mtk-mux
+
+Like done for other clocks, propagate struct device for mtk mux clocks
+registered through clk-mux helpers to enable runtime pm support.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+
+[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++-
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++-
+ drivers/clk/mediatek/clk-mux.c | 14 ++++++++------
+ drivers/clk/mediatek/clk-mux.h | 3 ++-
+ 4 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
+@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
+ return -ENOMEM;
+
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
++ mtk_clk_register_muxes(&pdev->dev, infra_muxes,
++ ARRAY_SIZE(infra_muxes), node,
+ &mt7986_clk_lock, clk_data);
+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ ARRAY_SIZE(infra_clks), clk_data);
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
++ mtk_clk_register_muxes(&pdev->dev, top_muxes,
++ ARRAY_SIZE(top_muxes), node,
+ &mt7986_clk_lock, clk_data);
+
+ clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+--- a/drivers/clk/mediatek/clk-mux.c
++++ b/drivers/clk/mediatek/clk-mux.c
+@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
+ };
+ EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
+
+-static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
+- struct regmap *regmap,
+- spinlock_t *lock)
++static struct clk_hw *mtk_clk_register_mux(struct device *dev,
++ const struct mtk_mux *mux,
++ struct regmap *regmap,
++ spinlock_t *lock)
+ {
+ struct mtk_clk_mux *clk_mux;
+ struct clk_init_data init = {};
+@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
+ clk_mux->lock = lock;
+ clk_mux->hw.init = &init;
+
+- ret = clk_hw_register(NULL, &clk_mux->hw);
++ ret = clk_hw_register(dev, &clk_mux->hw);
+ if (ret) {
+ kfree(clk_mux);
+ return ERR_PTR(ret);
+@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
+ kfree(mux);
+ }
+
+-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
++int mtk_clk_register_muxes(struct device *dev,
++ const struct mtk_mux *muxes,
+ int num, struct device_node *node,
+ spinlock_t *lock,
+ struct clk_hw_onecell_data *clk_data)
+@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
+ continue;
+ }
+
+- hw = mtk_clk_register_mux(mux, regmap, lock);
++ hw = mtk_clk_register_mux(dev, mux, regmap, lock);
+
+ if (IS_ERR(hw)) {
+ pr_err("Failed to register clk %s: %pe\n", mux->name,
+--- a/drivers/clk/mediatek/clk-mux.h
++++ b/drivers/clk/mediatek/clk-mux.h
+@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
+ 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
+ mtk_mux_clr_set_upd_ops)
+
+-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
++int mtk_clk_register_muxes(struct device *dev,
++ const struct mtk_mux *muxes,
+ int num, struct device_node *node,
+ spinlock_t *lock,
+ struct clk_hw_onecell_data *clk_data);
--- /dev/null
+From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:37 +0100
+Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops
+
+In order to migrate some (few) old clock drivers to the common
+mtk_clk_simple_probe() function, add dummy clock ops to be able
+to insert a dummy clock with ID 0 at the beginning of the list.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Miles Chen <miles.chen@mediatek.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
+ drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -18,6 +18,22 @@
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
+
++const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
++EXPORT_SYMBOL_GPL(cg_regs_dummy);
++
++static int mtk_clk_dummy_enable(struct clk_hw *hw)
++{
++ return 0;
++}
++
++static void mtk_clk_dummy_disable(struct clk_hw *hw) { }
++
++const struct clk_ops mtk_clk_dummy_ops = {
++ .enable = mtk_clk_dummy_enable,
++ .disable = mtk_clk_dummy_disable,
++};
++EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops);
++
+ static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data,
+ unsigned int clk_num)
+ {
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -22,6 +22,25 @@
+
+ struct platform_device;
+
++/*
++ * We need the clock IDs to start from zero but to maintain devicetree
++ * backwards compatibility we can't change bindings to start from zero.
++ * Only a few platforms are affected, so we solve issues given by the
++ * commonized MTK clocks probe function(s) by adding a dummy clock at
++ * the beginning where needed.
++ */
++#define CLK_DUMMY 0
++
++extern const struct clk_ops mtk_clk_dummy_ops;
++extern const struct mtk_gate_regs cg_regs_dummy;
++
++#define GATE_DUMMY(_id, _name) { \
++ .id = _id, \
++ .name = _name, \
++ .regs = &cg_regs_dummy, \
++ .ops = &mtk_clk_dummy_ops, \
++ }
++
+ struct mtk_fixed_clk {
+ int id;
+ const char *name;
--- /dev/null
+From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:41 +0100
+Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
+ possible
+
+mtk_clk_simple_probe() is a function that registers mtk gate clocks
+and, if reset data is present, a reset controller and across all of
+the MTK clock drivers, such a function is duplicated many times:
+switch to the common mtk_clk_simple_probe() function for all of the
+clock drivers that are registering as platform drivers.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Miles Chen <miles.chen@mediatek.com>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+
+[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
+ drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
+ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
+ drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
+ drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++----------------
+ drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
+ drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
+ drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
+ drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
+ 9 files changed, 144 insertions(+), 406 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701-aud.c
++++ b/drivers/clk/mediatek/clk-mt2701-aud.c
+@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
+ };
+
+ static const struct mtk_gate audio_clks[] = {
++ GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
+ /* AUDIO0 */
+ GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+ GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
+ GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+ };
+
++static const struct mtk_clk_desc audio_desc = {
++ .clks = audio_clks,
++ .num_clks = ARRAY_SIZE(audio_clks),
++};
++
+ static const struct of_device_id of_match_clk_mt2701_aud[] = {
+- { .compatible = "mediatek,mt2701-audsys", },
+- {}
++ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
++ { /* sentinel */ }
+ };
+
+ static int clk_mt2701_aud_probe(struct platform_device *pdev)
+ {
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+ int r;
+
+- clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+-
+- mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+- ARRAY_SIZE(audio_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++ r = mtk_clk_simple_probe(pdev);
+ if (r) {
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+- goto err_clk_provider;
++ return r;
+ }
+
+ r = devm_of_platform_populate(&pdev->dev);
+@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
+ return 0;
+
+ err_plat_populate:
+- of_clk_del_provider(node);
+-err_clk_provider:
++ mtk_clk_simple_remove(pdev);
+ return r;
+ }
+
++static int clk_mt2701_aud_remove(struct platform_device *pdev)
++{
++ of_platform_depopulate(&pdev->dev);
++ return mtk_clk_simple_remove(pdev);
++}
++
+ static struct platform_driver clk_mt2701_aud_drv = {
+ .probe = clk_mt2701_aud_probe,
++ .remove = clk_mt2701_aud_remove,
+ .driver = {
+ .name = "clk-mt2701-aud",
+ .of_match_table = of_match_clk_mt2701_aud,
+--- a/drivers/clk/mediatek/clk-mt2701-eth.c
++++ b/drivers/clk/mediatek/clk-mt2701-eth.c
+@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
+ GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+ static const struct mtk_gate eth_clks[] = {
++ GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
+ GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
+ GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
+ GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
+@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
+ .rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+
+-static const struct of_device_id of_match_clk_mt2701_eth[] = {
+- { .compatible = "mediatek,mt2701-ethsys", },
+- {}
++static const struct mtk_clk_desc eth_desc = {
++ .clks = eth_clks,
++ .num_clks = ARRAY_SIZE(eth_clks),
++ .rst_desc = &clk_rst_desc,
+ };
+
+-static int clk_mt2701_eth_probe(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- int r;
+- struct device_node *node = pdev->dev.of_node;
+-
+- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+-
+- mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+- ARRAY_SIZE(eth_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+- return r;
+-}
++static const struct of_device_id of_match_clk_mt2701_eth[] = {
++ { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc },
++ { /* sentinel */ }
++};
+
+ static struct platform_driver clk_mt2701_eth_drv = {
+- .probe = clk_mt2701_eth_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt2701-eth",
+ .of_match_table = of_match_clk_mt2701_eth,
+--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
+@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
+ };
+
+ static const struct mtk_gate g3d_clks[] = {
++ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
+ GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
+ };
+
+@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
+ .rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+
+-static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+-
+- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
+- clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+- return r;
+-}
++static const struct mtk_clk_desc g3d_desc = {
++ .clks = g3d_clks,
++ .num_clks = ARRAY_SIZE(g3d_clks),
++ .rst_desc = &clk_rst_desc,
++};
+
+ static const struct of_device_id of_match_clk_mt2701_g3d[] = {
+- {
+- .compatible = "mediatek,mt2701-g3dsys",
+- .data = clk_mt2701_g3dsys_init,
+- }, {
+- /* sentinel */
+- }
++ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
++ { /* sentinel */ }
+ };
+
+-static int clk_mt2701_g3d_probe(struct platform_device *pdev)
+-{
+- int (*clk_init)(struct platform_device *);
+- int r;
+-
+- clk_init = of_device_get_match_data(&pdev->dev);
+- if (!clk_init)
+- return -EINVAL;
+-
+- r = clk_init(pdev);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- return r;
+-}
+-
+ static struct platform_driver clk_mt2701_g3d_drv = {
+- .probe = clk_mt2701_g3d_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt2701-g3d",
+ .of_match_table = of_match_clk_mt2701_g3d,
+--- a/drivers/clk/mediatek/clk-mt2701-hif.c
++++ b/drivers/clk/mediatek/clk-mt2701-hif.c
+@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
+ GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+ static const struct mtk_gate hif_clks[] = {
++ GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
+ GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
+ GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
+ GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
+@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
+ .rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+
+-static const struct of_device_id of_match_clk_mt2701_hif[] = {
+- { .compatible = "mediatek,mt2701-hifsys", },
+- {}
++static const struct mtk_clk_desc hif_desc = {
++ .clks = hif_clks,
++ .num_clks = ARRAY_SIZE(hif_clks),
++ .rst_desc = &clk_rst_desc,
+ };
+
+-static int clk_mt2701_hif_probe(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- int r;
+- struct device_node *node = pdev->dev.of_node;
+-
+- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+-
+- mtk_clk_register_gates(&pdev->dev, node, hif_clks,
+- ARRAY_SIZE(hif_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r) {
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+- return r;
+- }
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+- return 0;
+-}
++static const struct of_device_id of_match_clk_mt2701_hif[] = {
++ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
++ { /* sentinel */ }
++};
+
+ static struct platform_driver clk_mt2701_hif_drv = {
+- .probe = clk_mt2701_hif_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt2701-hif",
+ .of_match_table = of_match_clk_mt2701_hif,
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
+ return r;
+ }
+
+-static int clk_mt2712_infra_probe(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- int r;
+- struct device_node *node = pdev->dev.of_node;
+-
+- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+- ARRAY_SIZE(infra_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+- if (r != 0)
+- pr_err("%s(): could not register clock provider: %d\n",
+- __func__, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
+-
+- return r;
+-}
+-
+-static int clk_mt2712_peri_probe(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- int r;
+- struct device_node *node = pdev->dev.of_node;
+-
+- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+- ARRAY_SIZE(peri_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+- if (r != 0)
+- pr_err("%s(): could not register clock provider: %d\n",
+- __func__, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
+-
+- return r;
+-}
+-
+ static int clk_mt2712_mcu_probe(struct platform_device *pdev)
+ {
+ struct clk_hw_onecell_data *clk_data;
+@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
+ .compatible = "mediatek,mt2712-topckgen",
+ .data = clk_mt2712_top_probe,
+ }, {
+- .compatible = "mediatek,mt2712-infracfg",
+- .data = clk_mt2712_infra_probe,
+- }, {
+- .compatible = "mediatek,mt2712-pericfg",
+- .data = clk_mt2712_peri_probe,
+- }, {
+ .compatible = "mediatek,mt2712-mcucfg",
+ .data = clk_mt2712_mcu_probe,
+ }, {
+@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
+ return r;
+ }
+
++static const struct mtk_clk_desc infra_desc = {
++ .clks = infra_clks,
++ .num_clks = ARRAY_SIZE(infra_clks),
++ .rst_desc = &clk_rst_desc[0],
++};
++
++static const struct mtk_clk_desc peri_desc = {
++ .clks = peri_clks,
++ .num_clks = ARRAY_SIZE(peri_clks),
++ .rst_desc = &clk_rst_desc[1],
++};
++
++static const struct of_device_id of_match_clk_mt2712_simple[] = {
++ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
++ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
++ { /* sentinel */ }
++};
++
++static struct platform_driver clk_mt2712_simple_drv = {
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
++ .driver = {
++ .name = "clk-mt2712-simple",
++ .of_match_table = of_match_clk_mt2712_simple,
++ },
++};
++
+ static struct platform_driver clk_mt2712_drv = {
+ .probe = clk_mt2712_probe,
+ .driver = {
+@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
+
+ static int __init clk_mt2712_init(void)
+ {
+- return platform_driver_register(&clk_mt2712_drv);
++ int ret = platform_driver_register(&clk_mt2712_drv);
++
++ if (ret)
++ return ret;
++ return platform_driver_register(&clk_mt2712_simple_drv);
+ }
+
+ arch_initcall(clk_mt2712_init);
+--- a/drivers/clk/mediatek/clk-mt7622-aud.c
++++ b/drivers/clk/mediatek/clk-mt7622-aud.c
+@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
+ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+ };
+
+-static int clk_mt7622_audiosys_init(struct platform_device *pdev)
++static const struct mtk_clk_desc audio_desc = {
++ .clks = audio_clks,
++ .num_clks = ARRAY_SIZE(audio_clks),
++};
++
++static int clk_mt7622_aud_probe(struct platform_device *pdev)
+ {
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+ int r;
+
+- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+- ARRAY_SIZE(audio_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++ r = mtk_clk_simple_probe(pdev);
+ if (r) {
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+- goto err_clk_provider;
++ return r;
+ }
+
+ r = devm_of_platform_populate(&pdev->dev);
+@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
+ return 0;
+
+ err_plat_populate:
+- of_clk_del_provider(node);
+-err_clk_provider:
++ mtk_clk_simple_remove(pdev);
+ return r;
+ }
+
+-static const struct of_device_id of_match_clk_mt7622_aud[] = {
+- {
+- .compatible = "mediatek,mt7622-audsys",
+- .data = clk_mt7622_audiosys_init,
+- }, {
+- /* sentinel */
+- }
+-};
+-
+-static int clk_mt7622_aud_probe(struct platform_device *pdev)
++static int clk_mt7622_aud_remove(struct platform_device *pdev)
+ {
+- int (*clk_init)(struct platform_device *);
+- int r;
+-
+- clk_init = of_device_get_match_data(&pdev->dev);
+- if (!clk_init)
+- return -EINVAL;
+-
+- r = clk_init(pdev);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- return r;
++ of_platform_depopulate(&pdev->dev);
++ return mtk_clk_simple_remove(pdev);
+ }
+
++static const struct of_device_id of_match_clk_mt7622_aud[] = {
++ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
++ { /* sentinel */ }
++};
++
+ static struct platform_driver clk_mt7622_aud_drv = {
+ .probe = clk_mt7622_aud_probe,
++ .remove = clk_mt7622_aud_remove,
+ .driver = {
+ .name = "clk-mt7622-aud",
+ .of_match_table = of_match_clk_mt7622_aud,
+--- a/drivers/clk/mediatek/clk-mt7622-eth.c
++++ b/drivers/clk/mediatek/clk-mt7622-eth.c
+@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
+ .rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+
+-static int clk_mt7622_ethsys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+- ARRAY_SIZE(eth_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+- return r;
+-}
+-
+-static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
+- ARRAY_SIZE(sgmii_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
++static const struct mtk_clk_desc eth_desc = {
++ .clks = eth_clks,
++ .num_clks = ARRAY_SIZE(eth_clks),
++ .rst_desc = &clk_rst_desc,
++};
+
+- return r;
+-}
++static const struct mtk_clk_desc sgmii_desc = {
++ .clks = sgmii_clks,
++ .num_clks = ARRAY_SIZE(sgmii_clks),
++};
+
+ static const struct of_device_id of_match_clk_mt7622_eth[] = {
+- {
+- .compatible = "mediatek,mt7622-ethsys",
+- .data = clk_mt7622_ethsys_init,
+- }, {
+- .compatible = "mediatek,mt7622-sgmiisys",
+- .data = clk_mt7622_sgmiisys_init,
+- }, {
+- /* sentinel */
+- }
++ { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc },
++ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
++ { /* sentinel */ }
+ };
+
+-static int clk_mt7622_eth_probe(struct platform_device *pdev)
+-{
+- int (*clk_init)(struct platform_device *);
+- int r;
+-
+- clk_init = of_device_get_match_data(&pdev->dev);
+- if (!clk_init)
+- return -EINVAL;
+-
+- r = clk_init(pdev);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- return r;
+-}
+-
+ static struct platform_driver clk_mt7622_eth_drv = {
+- .probe = clk_mt7622_eth_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7622-eth",
+ .of_match_table = of_match_clk_mt7622_eth,
+--- a/drivers/clk/mediatek/clk-mt7622-hif.c
++++ b/drivers/clk/mediatek/clk-mt7622-hif.c
+@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
+ .rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+
+-static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+- ARRAY_SIZE(ssusb_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+- return r;
+-}
+-
+-static int clk_mt7622_pciesys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+- ARRAY_SIZE(pcie_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
++static const struct mtk_clk_desc ssusb_desc = {
++ .clks = ssusb_clks,
++ .num_clks = ARRAY_SIZE(ssusb_clks),
++ .rst_desc = &clk_rst_desc,
++};
+
+- return r;
+-}
++static const struct mtk_clk_desc pcie_desc = {
++ .clks = pcie_clks,
++ .num_clks = ARRAY_SIZE(pcie_clks),
++ .rst_desc = &clk_rst_desc,
++};
+
+ static const struct of_device_id of_match_clk_mt7622_hif[] = {
+- {
+- .compatible = "mediatek,mt7622-pciesys",
+- .data = clk_mt7622_pciesys_init,
+- }, {
+- .compatible = "mediatek,mt7622-ssusbsys",
+- .data = clk_mt7622_ssusbsys_init,
+- }, {
+- /* sentinel */
+- }
++ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
++ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
++ { /* sentinel */ }
+ };
+
+-static int clk_mt7622_hif_probe(struct platform_device *pdev)
+-{
+- int (*clk_init)(struct platform_device *);
+- int r;
+-
+- clk_init = of_device_get_match_data(&pdev->dev);
+- if (!clk_init)
+- return -EINVAL;
+-
+- r = clk_init(pdev);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- return r;
+-}
+-
+ static struct platform_driver clk_mt7622_hif_drv = {
+- .probe = clk_mt7622_hif_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7622-hif",
+ .of_match_table = of_match_clk_mt7622_hif,
+--- a/drivers/clk/mediatek/clk-mt7629-hif.c
++++ b/drivers/clk/mediatek/clk-mt7629-hif.c
+@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
+ .rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+
+-static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+- ARRAY_SIZE(ssusb_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+- return r;
+-}
+-
+-static int clk_mt7629_pciesys_init(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+-
+- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+-
+- mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+- ARRAY_SIZE(pcie_clks), clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
++static const struct mtk_clk_desc ssusb_desc = {
++ .clks = ssusb_clks,
++ .num_clks = ARRAY_SIZE(ssusb_clks),
++ .rst_desc = &clk_rst_desc,
++};
+
+- return r;
+-}
++static const struct mtk_clk_desc pcie_desc = {
++ .clks = pcie_clks,
++ .num_clks = ARRAY_SIZE(pcie_clks),
++ .rst_desc = &clk_rst_desc,
++};
+
+ static const struct of_device_id of_match_clk_mt7629_hif[] = {
+- {
+- .compatible = "mediatek,mt7629-pciesys",
+- .data = clk_mt7629_pciesys_init,
+- }, {
+- .compatible = "mediatek,mt7629-ssusbsys",
+- .data = clk_mt7629_ssusbsys_init,
+- }, {
+- /* sentinel */
+- }
++ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
++ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
++ { /* sentinel */ }
+ };
+
+-static int clk_mt7629_hif_probe(struct platform_device *pdev)
+-{
+- int (*clk_init)(struct platform_device *);
+- int r;
+-
+- clk_init = of_device_get_match_data(&pdev->dev);
+- if (!clk_init)
+- return -EINVAL;
+-
+- r = clk_init(pdev);
+- if (r)
+- dev_err(&pdev->dev,
+- "could not register clock provider: %s: %d\n",
+- pdev->name, r);
+-
+- return r;
+-}
+-
+ static struct platform_driver clk_mt7629_hif_drv = {
+- .probe = clk_mt7629_hif_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7629-hif",
+ .of_match_table = of_match_clk_mt7629_hif,
--- /dev/null
+From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:42 +0100
+Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
+
+As a preparation to increase probe functions commonization across
+various MediaTek SoC clock controller drivers, extend function
+mtk_clk_simple_probe() to be able to register not only gates, but
+also fixed clocks, factors, muxes and composites.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Miles Chen <miles.chen@mediatek.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Tested-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++---
+ drivers/clk/mediatek/clk-mtk.h | 10 ++++
+ 2 files changed, 103 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -11,12 +11,14 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-mux.h"
+
+ const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
+ EXPORT_SYMBOL_GPL(cg_regs_dummy);
+@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform
+ const struct mtk_clk_desc *mcd;
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+- int r;
++ void __iomem *base;
++ int num_clks, r;
+
+ mcd = of_device_get_match_data(&pdev->dev);
+ if (!mcd)
+ return -EINVAL;
+
+- clk_data = mtk_alloc_clk_data(mcd->num_clks);
++ /* Composite clocks needs us to pass iomem pointer */
++ if (mcd->composite_clks) {
++ if (!mcd->shared_io)
++ base = devm_platform_ioremap_resource(pdev, 0);
++ else
++ base = of_iomap(node, 0);
++
++ if (IS_ERR_OR_NULL(base))
++ return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM;
++ }
++
++ /* Calculate how many clk_hw_onecell_data entries to allocate */
++ num_clks = mcd->num_clks + mcd->num_composite_clks;
++ num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
++ num_clks += mcd->num_mux_clks;
++
++ clk_data = mtk_alloc_clk_data(num_clks);
+ if (!clk_data)
+ return -ENOMEM;
+
+- r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
+- clk_data);
+- if (r)
+- goto free_data;
++ if (mcd->fixed_clks) {
++ r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
++ mcd->num_fixed_clks, clk_data);
++ if (r)
++ goto free_data;
++ }
++
++ if (mcd->factor_clks) {
++ r = mtk_clk_register_factors(mcd->factor_clks,
++ mcd->num_factor_clks, clk_data);
++ if (r)
++ goto unregister_fixed_clks;
++ }
++
++ if (mcd->mux_clks) {
++ r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks,
++ mcd->num_mux_clks, node,
++ mcd->clk_lock, clk_data);
++ if (r)
++ goto unregister_factors;
++ };
++
++ if (mcd->composite_clks) {
++ /* We don't check composite_lock because it's optional */
++ r = mtk_clk_register_composites(&pdev->dev,
++ mcd->composite_clks,
++ mcd->num_composite_clks,
++ base, mcd->clk_lock, clk_data);
++ if (r)
++ goto unregister_muxes;
++ }
++
++ if (mcd->clks) {
++ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
++ mcd->num_clks, clk_data);
++ if (r)
++ goto unregister_composites;
++ }
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform
+ return r;
+
+ unregister_clks:
+- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++ if (mcd->clks)
++ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++unregister_composites:
++ if (mcd->composite_clks)
++ mtk_clk_unregister_composites(mcd->composite_clks,
++ mcd->num_composite_clks, clk_data);
++unregister_muxes:
++ if (mcd->mux_clks)
++ mtk_clk_unregister_muxes(mcd->mux_clks,
++ mcd->num_mux_clks, clk_data);
++unregister_factors:
++ if (mcd->factor_clks)
++ mtk_clk_unregister_factors(mcd->factor_clks,
++ mcd->num_factor_clks, clk_data);
++unregister_fixed_clks:
++ if (mcd->fixed_clks)
++ mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
++ mcd->num_fixed_clks, clk_data);
+ free_data:
+ mtk_free_clk_data(clk_data);
++ if (mcd->shared_io && base)
++ iounmap(base);
+ return r;
+ }
+ EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
+@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor
+ struct device_node *node = pdev->dev.of_node;
+
+ of_clk_del_provider(node);
+- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++ if (mcd->clks)
++ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++ if (mcd->composite_clks)
++ mtk_clk_unregister_composites(mcd->composite_clks,
++ mcd->num_composite_clks, clk_data);
++ if (mcd->mux_clks)
++ mtk_clk_unregister_muxes(mcd->mux_clks,
++ mcd->num_mux_clks, clk_data);
++ if (mcd->factor_clks)
++ mtk_clk_unregister_factors(mcd->factor_clks,
++ mcd->num_factor_clks, clk_data);
++ if (mcd->fixed_clks)
++ mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
++ mcd->num_fixed_clks, clk_data);
+ mtk_free_clk_data(clk_data);
+
+ return 0;
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc
+ struct mtk_clk_desc {
+ const struct mtk_gate *clks;
+ size_t num_clks;
++ const struct mtk_composite *composite_clks;
++ size_t num_composite_clks;
++ const struct mtk_fixed_clk *fixed_clks;
++ size_t num_fixed_clks;
++ const struct mtk_fixed_factor *factor_clks;
++ size_t num_factor_clks;
++ const struct mtk_mux *mux_clks;
++ size_t num_mux_clks;
+ const struct mtk_clk_rst_desc *rst_desc;
++ spinlock_t *clk_lock;
++ bool shared_io;
+ };
+
+ int mtk_clk_simple_probe(struct platform_device *pdev);
--- /dev/null
+From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:52 +0100
+Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
+ clocks enabled
+
+Instead of calling clk_prepare_enable() on a bunch of clocks at probe
+time, set the CLK_IS_CRITICAL flag to the same as these are required
+to be always on, and this is the right way of achieving that.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Reviewed-by: Miles Chen <miles.chen@mediatek.com>
+Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
+ 1 file changed, 24 insertions(+), 22 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
+ f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
+ 0x1C0, 10),
+- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
+- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
++ f_26m_adc_parents, 0x020, 0x024, 0x028,
++ 24, 1, 31, 0x1C0, 11,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ /* CLK_CFG_3 */
+- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
+- 0x1C0, 12),
+- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
+- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
+- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
+- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
++ dramc_md32_parents, 0x030, 0x034, 0x038,
++ 0, 1, 7, 0x1C0, 12,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
++ sysaxi_parents, 0x030, 0x034, 0x038,
++ 8, 2, 15, 0x1C0, 13,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
++ sysapb_parents, 0x030, 0x034, 0x038,
++ 16, 2, 23, 0x1C0, 14,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
+ 31, 0x1C0, 15),
+@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 0x1C0, 21),
+- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
+- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
+- 0x1C0, 22),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
++ sgm_reg_parents, 0x050, 0x054, 0x058,
++ 16, 1, 23, 0x1C0, 22,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+ 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
+ /* CLK_CFG_6 */
+@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
+ f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
+ 0x1C0, 27),
+ /* CLK_CFG_7 */
+- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
+- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
+- 0x1C0, 28),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
++ f_26m_adc_parents, 0x070, 0x074, 0x078,
++ 0, 1, 7, 0x1C0, 28,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+ 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
+@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
+ ARRAY_SIZE(top_muxes), node,
+ &mt7986_clk_lock, clk_data);
+
+- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
+- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
+- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
+- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
+- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
+-
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+
+ if (r) {
--- /dev/null
+From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Fri, 20 Jan 2023 10:20:53 +0100
+Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
+ mtk_clk_simple_probe()
+
+There are no more non-common calls in clk_mt7986_topckgen_probe():
+migrate this driver to mtk_clk_simple_probe().
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Miles Chen <miles.chen@mediatek.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com
+Tested-by: Mingming Su <mingming.su@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
+ 1 file changed, 13 insertions(+), 42 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
+ 0x1C4, 5),
+ };
+
+-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
+-{
+- struct clk_hw_onecell_data *clk_data;
+- struct device_node *node = pdev->dev.of_node;
+- int r;
+- void __iomem *base;
+- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
+- ARRAY_SIZE(top_muxes);
+-
+- base = of_iomap(node, 0);
+- if (!base) {
+- pr_err("%s(): ioremap failed\n", __func__);
+- return -ENOMEM;
+- }
+-
+- clk_data = mtk_alloc_clk_data(nr);
+- if (!clk_data)
+- return -ENOMEM;
+-
+- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+- clk_data);
+- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+- mtk_clk_register_muxes(&pdev->dev, top_muxes,
+- ARRAY_SIZE(top_muxes), node,
+- &mt7986_clk_lock, clk_data);
+-
+- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+- if (r) {
+- pr_err("%s(): could not register clock provider: %d\n",
+- __func__, r);
+- goto free_topckgen_data;
+- }
+- return r;
+-
+-free_topckgen_data:
+- mtk_free_clk_data(clk_data);
+- return r;
+-}
++static const struct mtk_clk_desc topck_desc = {
++ .fixed_clks = top_fixed_clks,
++ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++ .factor_clks = top_divs,
++ .num_factor_clks = ARRAY_SIZE(top_divs),
++ .mux_clks = top_muxes,
++ .num_mux_clks = ARRAY_SIZE(top_muxes),
++ .clk_lock = &mt7986_clk_lock,
++};
+
+ static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
+- { .compatible = "mediatek,mt7986-topckgen", },
+- {}
++ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
++ { /* sentinel */ }
+ };
+
+ static struct platform_driver clk_mt7986_topckgen_drv = {
+- .probe = clk_mt7986_topckgen_probe,
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt7986-topckgen",
+ .of_match_table = of_match_clk_mt7986_topckgen,
--- /dev/null
+From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Date: Mon, 6 Mar 2023 15:05:21 +0100
+Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
+ critical clock
+
+Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
+flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
++++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
+@@ -42,7 +42,7 @@
+ "clkxtal")
+
+ static const struct mtk_pll_data plls[] = {
+- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
+ 0x0200, 4, 0, 0x0204, 0),
+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
+ 0x0210, 4, 0, 0x0214, 0),
+@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+-
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r) {
+ pr_err("%s(): could not register clock provider: %d\n",
--- /dev/null
+From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 26 Jan 2023 03:34:05 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
+
+Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
+infracfg, and ethernet subsystem clocks.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++
+ 1 file changed, 215 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
+@@ -0,0 +1,215 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
++ * Author: Jianhui Zhao <zhaojh329@gmail.com>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7981_H
++#define _DT_BINDINGS_CLK_MT7981_H
++
++/* TOPCKGEN */
++#define CLK_TOP_CB_CKSQ_40M 0
++#define CLK_TOP_CB_M_416M 1
++#define CLK_TOP_CB_M_D2 2
++#define CLK_TOP_CB_M_D3 3
++#define CLK_TOP_M_D3_D2 4
++#define CLK_TOP_CB_M_D4 5
++#define CLK_TOP_CB_M_D8 6
++#define CLK_TOP_M_D8_D2 7
++#define CLK_TOP_CB_MM_720M 8
++#define CLK_TOP_CB_MM_D2 9
++#define CLK_TOP_CB_MM_D3 10
++#define CLK_TOP_CB_MM_D3_D5 11
++#define CLK_TOP_CB_MM_D4 12
++#define CLK_TOP_CB_MM_D6 13
++#define CLK_TOP_MM_D6_D2 14
++#define CLK_TOP_CB_MM_D8 15
++#define CLK_TOP_CB_APLL2_196M 16
++#define CLK_TOP_APLL2_D2 17
++#define CLK_TOP_APLL2_D4 18
++#define CLK_TOP_NET1_2500M 19
++#define CLK_TOP_CB_NET1_D4 20
++#define CLK_TOP_CB_NET1_D5 21
++#define CLK_TOP_NET1_D5_D2 22
++#define CLK_TOP_NET1_D5_D4 23
++#define CLK_TOP_CB_NET1_D8 24
++#define CLK_TOP_NET1_D8_D2 25
++#define CLK_TOP_NET1_D8_D4 26
++#define CLK_TOP_CB_NET2_800M 27
++#define CLK_TOP_CB_NET2_D2 28
++#define CLK_TOP_CB_NET2_D4 29
++#define CLK_TOP_NET2_D4_D2 30
++#define CLK_TOP_NET2_D4_D4 31
++#define CLK_TOP_CB_NET2_D6 32
++#define CLK_TOP_CB_WEDMCU_208M 33
++#define CLK_TOP_CB_SGM_325M 34
++#define CLK_TOP_CKSQ_40M_D2 35
++#define CLK_TOP_CB_RTC_32K 36
++#define CLK_TOP_CB_RTC_32P7K 37
++#define CLK_TOP_USB_TX250M 38
++#define CLK_TOP_FAUD 39
++#define CLK_TOP_NFI1X 40
++#define CLK_TOP_USB_EQ_RX250M 41
++#define CLK_TOP_USB_CDR_CK 42
++#define CLK_TOP_USB_LN0_CK 43
++#define CLK_TOP_SPINFI_BCK 44
++#define CLK_TOP_SPI 45
++#define CLK_TOP_SPIM_MST 46
++#define CLK_TOP_UART_BCK 47
++#define CLK_TOP_PWM_BCK 48
++#define CLK_TOP_I2C_BCK 49
++#define CLK_TOP_PEXTP_TL 50
++#define CLK_TOP_EMMC_208M 51
++#define CLK_TOP_EMMC_400M 52
++#define CLK_TOP_DRAMC_REF 53
++#define CLK_TOP_DRAMC_MD32 54
++#define CLK_TOP_SYSAXI 55
++#define CLK_TOP_SYSAPB 56
++#define CLK_TOP_ARM_DB_MAIN 57
++#define CLK_TOP_AP2CNN_HOST 58
++#define CLK_TOP_NETSYS 59
++#define CLK_TOP_NETSYS_500M 60
++#define CLK_TOP_NETSYS_WED_MCU 61
++#define CLK_TOP_NETSYS_2X 62
++#define CLK_TOP_SGM_325M 63
++#define CLK_TOP_SGM_REG 64
++#define CLK_TOP_F26M 65
++#define CLK_TOP_EIP97B 66
++#define CLK_TOP_USB3_PHY 67
++#define CLK_TOP_AUD 68
++#define CLK_TOP_A1SYS 69
++#define CLK_TOP_AUD_L 70
++#define CLK_TOP_A_TUNER 71
++#define CLK_TOP_U2U3_REF 72
++#define CLK_TOP_U2U3_SYS 73
++#define CLK_TOP_U2U3_XHCI 74
++#define CLK_TOP_USB_FRMCNT 75
++#define CLK_TOP_NFI1X_SEL 76
++#define CLK_TOP_SPINFI_SEL 77
++#define CLK_TOP_SPI_SEL 78
++#define CLK_TOP_SPIM_MST_SEL 79
++#define CLK_TOP_UART_SEL 80
++#define CLK_TOP_PWM_SEL 81
++#define CLK_TOP_I2C_SEL 82
++#define CLK_TOP_PEXTP_TL_SEL 83
++#define CLK_TOP_EMMC_208M_SEL 84
++#define CLK_TOP_EMMC_400M_SEL 85
++#define CLK_TOP_F26M_SEL 86
++#define CLK_TOP_DRAMC_SEL 87
++#define CLK_TOP_DRAMC_MD32_SEL 88
++#define CLK_TOP_SYSAXI_SEL 89
++#define CLK_TOP_SYSAPB_SEL 90
++#define CLK_TOP_ARM_DB_MAIN_SEL 91
++#define CLK_TOP_AP2CNN_HOST_SEL 92
++#define CLK_TOP_NETSYS_SEL 93
++#define CLK_TOP_NETSYS_500M_SEL 94
++#define CLK_TOP_NETSYS_MCU_SEL 95
++#define CLK_TOP_NETSYS_2X_SEL 96
++#define CLK_TOP_SGM_325M_SEL 97
++#define CLK_TOP_SGM_REG_SEL 98
++#define CLK_TOP_EIP97B_SEL 99
++#define CLK_TOP_USB3_PHY_SEL 100
++#define CLK_TOP_AUD_SEL 101
++#define CLK_TOP_A1SYS_SEL 102
++#define CLK_TOP_AUD_L_SEL 103
++#define CLK_TOP_A_TUNER_SEL 104
++#define CLK_TOP_U2U3_SEL 105
++#define CLK_TOP_U2U3_SYS_SEL 106
++#define CLK_TOP_U2U3_XHCI_SEL 107
++#define CLK_TOP_USB_FRMCNT_SEL 108
++#define CLK_TOP_AUD_I2S_M 109
++
++/* INFRACFG */
++#define CLK_INFRA_66M_MCK 0
++#define CLK_INFRA_UART0_SEL 1
++#define CLK_INFRA_UART1_SEL 2
++#define CLK_INFRA_UART2_SEL 3
++#define CLK_INFRA_SPI0_SEL 4
++#define CLK_INFRA_SPI1_SEL 5
++#define CLK_INFRA_SPI2_SEL 6
++#define CLK_INFRA_PWM1_SEL 7
++#define CLK_INFRA_PWM2_SEL 8
++#define CLK_INFRA_PWM3_SEL 9
++#define CLK_INFRA_PWM_BSEL 10
++#define CLK_INFRA_PCIE_SEL 11
++#define CLK_INFRA_GPT_STA 12
++#define CLK_INFRA_PWM_HCK 13
++#define CLK_INFRA_PWM_STA 14
++#define CLK_INFRA_PWM1_CK 15
++#define CLK_INFRA_PWM2_CK 16
++#define CLK_INFRA_PWM3_CK 17
++#define CLK_INFRA_CQ_DMA_CK 18
++#define CLK_INFRA_AUD_BUS_CK 19
++#define CLK_INFRA_AUD_26M_CK 20
++#define CLK_INFRA_AUD_L_CK 21
++#define CLK_INFRA_AUD_AUD_CK 22
++#define CLK_INFRA_AUD_EG2_CK 23
++#define CLK_INFRA_DRAMC_26M_CK 24
++#define CLK_INFRA_DBG_CK 25
++#define CLK_INFRA_AP_DMA_CK 26
++#define CLK_INFRA_SEJ_CK 27
++#define CLK_INFRA_SEJ_13M_CK 28
++#define CLK_INFRA_THERM_CK 29
++#define CLK_INFRA_I2C0_CK 30
++#define CLK_INFRA_UART0_CK 31
++#define CLK_INFRA_UART1_CK 32
++#define CLK_INFRA_UART2_CK 33
++#define CLK_INFRA_SPI2_CK 34
++#define CLK_INFRA_SPI2_HCK_CK 35
++#define CLK_INFRA_NFI1_CK 36
++#define CLK_INFRA_SPINFI1_CK 37
++#define CLK_INFRA_NFI_HCK_CK 38
++#define CLK_INFRA_SPI0_CK 39
++#define CLK_INFRA_SPI1_CK 40
++#define CLK_INFRA_SPI0_HCK_CK 41
++#define CLK_INFRA_SPI1_HCK_CK 42
++#define CLK_INFRA_FRTC_CK 43
++#define CLK_INFRA_MSDC_CK 44
++#define CLK_INFRA_MSDC_HCK_CK 45
++#define CLK_INFRA_MSDC_133M_CK 46
++#define CLK_INFRA_MSDC_66M_CK 47
++#define CLK_INFRA_ADC_26M_CK 48
++#define CLK_INFRA_ADC_FRC_CK 49
++#define CLK_INFRA_FBIST2FPC_CK 50
++#define CLK_INFRA_I2C_MCK_CK 51
++#define CLK_INFRA_I2C_PCK_CK 52
++#define CLK_INFRA_IUSB_133_CK 53
++#define CLK_INFRA_IUSB_66M_CK 54
++#define CLK_INFRA_IUSB_SYS_CK 55
++#define CLK_INFRA_IUSB_CK 56
++#define CLK_INFRA_IPCIE_CK 57
++#define CLK_INFRA_IPCIE_PIPE_CK 58
++#define CLK_INFRA_IPCIER_CK 59
++#define CLK_INFRA_IPCIEB_CK 60
++
++/* APMIXEDSYS */
++#define CLK_APMIXED_ARMPLL 0
++#define CLK_APMIXED_NET2PLL 1
++#define CLK_APMIXED_MMPLL 2
++#define CLK_APMIXED_SGMPLL 3
++#define CLK_APMIXED_WEDMCUPLL 4
++#define CLK_APMIXED_NET1PLL 5
++#define CLK_APMIXED_MPLL 6
++#define CLK_APMIXED_APLL2 7
++
++/* SGMIISYS_0 */
++#define CLK_SGM0_TX_EN 0
++#define CLK_SGM0_RX_EN 1
++#define CLK_SGM0_CK0_EN 2
++#define CLK_SGM0_CDR_CK0_EN 3
++
++/* SGMIISYS_1 */
++#define CLK_SGM1_TX_EN 0
++#define CLK_SGM1_RX_EN 1
++#define CLK_SGM1_CK1_EN 2
++#define CLK_SGM1_CDR_CK1_EN 3
++
++/* ETHSYS */
++#define CLK_ETH_FE_EN 0
++#define CLK_ETH_GP2_EN 1
++#define CLK_ETH_GP1_EN 2
++#define CLK_ETH_WOCPU0_EN 3
++
++#endif /* _DT_BINDINGS_CLK_MT7981_H */
--- /dev/null
+From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 26 Jan 2023 03:34:24 +0000
+Subject: [PATCH] clk: mediatek: add MT7981 clock support
+
+Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
+ethernet subsystem clocks.
+
+The drivers are based on clk-mt7981.c which can be found in MediaTek's
+SDK sources. To be fit for upstream inclusion the driver has been split
+into clock domains and the infracfg part has been significantly
+de-bloated by removing all the 1:1 factors (aliases).
+
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+[sboyd@kernel.org: Add module license]
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/mediatek/Kconfig | 17 +
+ drivers/clk/mediatek/Makefile | 4 +
+ drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++
+ drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++
+ drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++
+ drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++
+ 6 files changed, 870 insertions(+)
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c
+
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS
+ This driver supports MediaTek MT7629 HIFSYS clocks providing
+ to PCI-E and USB.
+
++config COMMON_CLK_MT7981
++ bool "Clock driver for MediaTek MT7981"
++ depends on ARCH_MEDIATEK || COMPILE_TEST
++ select COMMON_CLK_MEDIATEK
++ default ARCH_MEDIATEK
++ help
++ This driver supports MediaTek MT7981 basic clocks and clocks
++ required for various peripherals found on this SoC.
++
++config COMMON_CLK_MT7981_ETHSYS
++ tristate "Clock driver for MediaTek MT7981 ETHSYS"
++ depends on COMMON_CLK_MT7981
++ default COMMON_CLK_MT7981
++ help
++ This driver adds support for clocks for Ethernet and SGMII
++ required on MediaTek MT7981 SoC.
++
+ config COMMON_CLK_MT7986
+ bool "Clock driver for MediaTek MT7986"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
+ obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
+ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
+ obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
++obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
+@@ -0,0 +1,102 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
++ * Author: Jianhui Zhao <zhaojh329@gmail.com>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include "clk-gate.h"
++#include "clk-mtk.h"
++#include "clk-mux.h"
++#include "clk-pll.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++#include <linux/clk.h>
++
++#define MT7981_PLL_FMAX (2500UL * MHZ)
++#define CON0_MT7981_RST_BAR BIT(27)
++
++#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
++ _div_table, _parent_name) \
++ { \
++ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
++ .en_mask = _en_mask, .flags = _flags, \
++ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
++ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
++ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
++ .pcw_shift = _pcw_shift, .div_table = _div_table, \
++ .parent_name = _parent_name, \
++ }
++
++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
++ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
++ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
++ "clkxtal")
++
++static const struct mtk_pll_data plls[] = {
++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
++ 32, 0x0200, 4, 0, 0x0204, 0),
++ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
++ 0x0210, 4, 0, 0x0214, 0),
++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
++ 0x0220, 4, 0, 0x0224, 0),
++ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
++ 0x0230, 4, 0, 0x0234, 0),
++ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
++ 0x0240, 4, 0, 0x0244, 0),
++ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
++ 0x0250, 4, 0, 0x0254, 0),
++ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
++ 0x0260, 4, 0, 0x0264, 0),
++ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
++ 0x0278, 4, 0, 0x027C, 0),
++};
++
++static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
++ { .compatible = "mediatek,mt7981-apmixedsys", },
++ { /* sentinel */ }
++};
++
++static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
++{
++ struct clk_hw_onecell_data *clk_data;
++ struct device_node *node = pdev->dev.of_node;
++ int r;
++
++ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
++ if (!clk_data)
++ return -ENOMEM;
++
++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
++
++ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++ if (r) {
++ pr_err("%s(): could not register clock provider: %d\n",
++ __func__, r);
++ goto free_apmixed_data;
++ }
++ return r;
++
++free_apmixed_data:
++ mtk_free_clk_data(clk_data);
++ return r;
++}
++
++static struct platform_driver clk_mt7981_apmixed_drv = {
++ .probe = clk_mt7981_apmixed_probe,
++ .driver = {
++ .name = "clk-mt7981-apmixed",
++ .of_match_table = of_match_clk_mt7981_apmixed,
++ },
++};
++builtin_platform_driver(clk_mt7981_apmixed_drv);
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-eth.c
+@@ -0,0 +1,118 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
++ * Author: Jianhui Zhao <zhaojh329@gmail.com>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++
++static const struct mtk_gate_regs sgmii0_cg_regs = {
++ .set_ofs = 0xE4,
++ .clr_ofs = 0xE4,
++ .sta_ofs = 0xE4,
++};
++
++#define GATE_SGMII0(_id, _name, _parent, _shift) { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = &sgmii0_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_gate sgmii0_clks[] __initconst = {
++ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
++ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
++ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
++ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
++};
++
++static const struct mtk_gate_regs sgmii1_cg_regs = {
++ .set_ofs = 0xE4,
++ .clr_ofs = 0xE4,
++ .sta_ofs = 0xE4,
++};
++
++#define GATE_SGMII1(_id, _name, _parent, _shift) { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = &sgmii1_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_gate sgmii1_clks[] __initconst = {
++ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
++ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
++ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
++ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
++};
++
++static const struct mtk_gate_regs eth_cg_regs = {
++ .set_ofs = 0x30,
++ .clr_ofs = 0x30,
++ .sta_ofs = 0x30,
++};
++
++#define GATE_ETH(_id, _name, _parent, _shift) { \
++ .id = _id, \
++ .name = _name, \
++ .parent_name = _parent, \
++ .regs = ð_cg_regs, \
++ .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
++ }
++
++static const struct mtk_gate eth_clks[] __initconst = {
++ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
++ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
++ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
++ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
++};
++
++static const struct mtk_clk_desc eth_desc = {
++ .clks = eth_clks,
++ .num_clks = ARRAY_SIZE(eth_clks),
++};
++
++static const struct mtk_clk_desc sgmii0_desc = {
++ .clks = sgmii0_clks,
++ .num_clks = ARRAY_SIZE(sgmii0_clks),
++};
++
++static const struct mtk_clk_desc sgmii1_desc = {
++ .clks = sgmii1_clks,
++ .num_clks = ARRAY_SIZE(sgmii1_clks),
++};
++
++static const struct of_device_id of_match_clk_mt7981_eth[] = {
++ { .compatible = "mediatek,mt7981-ethsys", .data = ð_desc },
++ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
++ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
++ { /* sentinel */ }
++};
++
++static struct platform_driver clk_mt7981_eth_drv = {
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
++ .driver = {
++ .name = "clk-mt7981-eth",
++ .of_match_table = of_match_clk_mt7981_eth,
++ },
++};
++module_platform_driver(clk_mt7981_eth_drv);
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
+@@ -0,0 +1,207 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
++ * Author: Jianhui Zhao <zhaojh329@gmail.com>
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++#include <linux/clk.h>
++
++static DEFINE_SPINLOCK(mt7981_clk_lock);
++
++static const struct mtk_fixed_factor infra_divs[] = {
++ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
++};
++
++static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
++ "uart_sel" };
++
++static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
++ "spi_sel" };
++
++static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
++ "spim_mst_sel" };
++
++static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
++
++static const char *const infra_pwm_bsel_parents[] __initconst = {
++ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
++};
++
++static const char *const infra_pcie_parents[] __initconst = {
++ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
++};
++
++static const struct mtk_mux infra_muxes[] = {
++ /* MODULE_CLK_SEL_0 */
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
++ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
++ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
++ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
++ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
++ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
++ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
++ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
++ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
++ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
++ -1, -1, -1),
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
++ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
++ 2, -1, -1, -1),
++ /* MODULE_CLK_SEL_1 */
++ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
++ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
++ -1, -1, -1),
++};
++
++static const struct mtk_gate_regs infra0_cg_regs = {
++ .set_ofs = 0x40,
++ .clr_ofs = 0x44,
++ .sta_ofs = 0x48,
++};
++
++static const struct mtk_gate_regs infra1_cg_regs = {
++ .set_ofs = 0x50,
++ .clr_ofs = 0x54,
++ .sta_ofs = 0x58,
++};
++
++static const struct mtk_gate_regs infra2_cg_regs = {
++ .set_ofs = 0x60,
++ .clr_ofs = 0x64,
++ .sta_ofs = 0x68,
++};
++
++#define GATE_INFRA0(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, .name = _name, .parent_name = _parent, \
++ .regs = &infra0_cg_regs, .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_setclr, \
++ }
++
++#define GATE_INFRA1(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, .name = _name, .parent_name = _parent, \
++ .regs = &infra1_cg_regs, .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_setclr, \
++ }
++
++#define GATE_INFRA2(_id, _name, _parent, _shift) \
++ { \
++ .id = _id, .name = _name, .parent_name = _parent, \
++ .regs = &infra2_cg_regs, .shift = _shift, \
++ .ops = &mtk_clk_gate_ops_setclr, \
++ }
++
++static const struct mtk_gate infra_clks[] = {
++ /* INFRA0 */
++ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
++ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
++ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
++ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
++ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
++ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
++
++ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
++ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
++ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
++ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
++ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
++ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
++ 14),
++ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
++ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
++ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
++ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
++ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
++ /* INFRA1 */
++ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
++ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
++ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
++ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
++ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
++ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
++ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
++ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
++ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
++ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
++ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
++ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
++ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
++ 13),
++ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
++ 14),
++ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
++ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
++ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
++ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
++ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
++ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
++ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
++ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
++ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
++ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
++ /* INFRA2 */
++ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
++ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
++ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
++ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
++ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
++ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
++ 13),
++ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
++ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
++};
++
++static const struct mtk_clk_desc infracfg_desc = {
++ .factor_clks = infra_divs,
++ .num_factor_clks = ARRAY_SIZE(infra_divs),
++ .mux_clks = infra_muxes,
++ .num_mux_clks = ARRAY_SIZE(infra_muxes),
++ .clks = infra_clks,
++ .num_clks = ARRAY_SIZE(infra_clks),
++ .clk_lock = &mt7981_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
++ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
++ { /* sentinel */ }
++};
++
++static struct platform_driver clk_mt7981_infracfg_drv = {
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
++ .driver = {
++ .name = "clk-mt7981-infracfg",
++ .of_match_table = of_match_clk_mt7981_infracfg,
++ },
++};
++builtin_platform_driver(clk_mt7981_infracfg_drv);
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
+@@ -0,0 +1,422 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <sam.shih@mediatek.com>
++ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
++ * Author: Jianhui Zhao <zhaojh329@gmail.com>
++ */
++
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++#include <linux/clk.h>
++
++static DEFINE_SPINLOCK(mt7981_clk_lock);
++
++static const struct mtk_fixed_factor top_divs[] = {
++ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
++ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
++ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
++ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
++ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
++ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
++ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
++ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
++ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
++ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
++ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
++ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
++ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
++ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
++ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
++ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
++ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
++ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
++ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
++ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
++ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
++ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
++ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
++ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
++ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
++ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
++ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
++ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
++ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
++ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
++ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
++ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
++ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
++ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
++ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
++ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
++ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
++ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
++ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
++ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
++ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
++ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
++ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
++ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
++ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
++ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
++ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
++ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
++ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
++ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
++ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
++ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
++ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
++ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
++ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
++ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
++ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
++ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
++ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
++ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
++ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
++ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
++ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
++ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
++ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
++ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
++ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
++ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
++ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
++ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
++ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
++ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
++ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
++ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
++ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
++ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
++};
++
++static const char * const nfi1x_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_mm_d4",
++ "net1_d8_d2",
++ "cb_net2_d6",
++ "cb_m_d4",
++ "cb_mm_d8",
++ "net1_d8_d4",
++ "cb_m_d8"
++};
++
++static const char * const spinfi_parents[] __initconst = {
++ "cksq_40m_d2",
++ "cb_cksq_40m",
++ "net1_d5_d4",
++ "cb_m_d4",
++ "cb_mm_d8",
++ "net1_d8_d4",
++ "mm_d6_d2",
++ "cb_m_d8"
++};
++
++static const char * const spi_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_m_d2",
++ "cb_mm_d4",
++ "net1_d8_d2",
++ "cb_net2_d6",
++ "net1_d5_d4",
++ "cb_m_d4",
++ "net1_d8_d4"
++};
++
++static const char * const uart_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_m_d8",
++ "m_d8_d2"
++};
++
++static const char * const pwm_parents[] __initconst = {
++ "cb_cksq_40m",
++ "net1_d8_d2",
++ "net1_d5_d4",
++ "cb_m_d4",
++ "m_d8_d2",
++ "cb_rtc_32k"
++};
++
++static const char * const i2c_parents[] __initconst = {
++ "cb_cksq_40m",
++ "net1_d5_d4",
++ "cb_m_d4",
++ "net1_d8_d4"
++};
++
++static const char * const pextp_tl_ck_parents[] __initconst = {
++ "cb_cksq_40m",
++ "net1_d5_d4",
++ "cb_m_d4",
++ "cb_rtc_32k"
++};
++
++static const char * const emmc_208m_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_m_d2",
++ "cb_net2_d4",
++ "cb_apll2_196m",
++ "cb_mm_d4",
++ "net1_d8_d2",
++ "cb_mm_d6"
++};
++
++static const char * const emmc_400m_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_net2_d2",
++ "cb_mm_d2",
++ "cb_net2_d2"
++};
++
++static const char * const csw_f26m_parents[] __initconst = {
++ "cksq_40m_d2",
++ "m_d8_d2"
++};
++
++static const char * const dramc_md32_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_m_d2",
++ "cb_wedmcu_208m"
++};
++
++static const char * const sysaxi_parents[] __initconst = {
++ "cb_cksq_40m",
++ "net1_d8_d2"
++};
++
++static const char * const sysapb_parents[] __initconst = {
++ "cb_cksq_40m",
++ "m_d3_d2"
++};
++
++static const char * const arm_db_main_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_net2_d6"
++};
++
++static const char * const ap2cnn_host_parents[] __initconst = {
++ "cb_cksq_40m",
++ "net1_d8_d4"
++};
++
++static const char * const netsys_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_mm_d2"
++};
++
++static const char * const netsys_500m_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_net1_d5"
++};
++
++static const char * const netsys_mcu_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_mm_720m",
++ "cb_net1_d4",
++ "cb_net1_d5",
++ "cb_m_416m"
++};
++
++static const char * const netsys_2x_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_net2_800m",
++ "cb_mm_720m"
++};
++
++static const char * const sgm_325m_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_sgm_325m"
++};
++
++static const char * const sgm_reg_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_net2_d4"
++};
++
++static const char * const eip97b_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_net1_d5",
++ "cb_m_416m",
++ "cb_mm_d2",
++ "net1_d5_d2"
++};
++
++static const char * const aud_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_apll2_196m"
++};
++
++static const char * const a1sys_parents[] __initconst = {
++ "cb_cksq_40m",
++ "apll2_d4"
++};
++
++static const char * const aud_l_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_apll2_196m",
++ "m_d8_d2"
++};
++
++static const char * const a_tuner_parents[] __initconst = {
++ "cb_cksq_40m",
++ "apll2_d4",
++ "m_d8_d2"
++};
++
++static const char * const u2u3_parents[] __initconst = {
++ "cb_cksq_40m",
++ "m_d8_d2"
++};
++
++static const char * const u2u3_sys_parents[] __initconst = {
++ "cb_cksq_40m",
++ "net1_d5_d4"
++};
++
++static const char * const usb_frmcnt_parents[] __initconst = {
++ "cb_cksq_40m",
++ "cb_mm_d3_d5"
++};
++
++static const struct mtk_mux top_muxes[] = {
++ /* CLK_CFG_0 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
++ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
++ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
++ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
++ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
++ /* CLK_CFG_1 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
++ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
++ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
++ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
++ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
++ 0x1C0, 7),
++ /* CLK_CFG_2 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
++ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
++ 0x1C0, 8),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
++ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
++ 0x1C0, 9),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
++ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
++ 0x1C0, 10,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
++ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
++ 31, 0x1C0, 11,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ /* CLK_CFG_3 */
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
++ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
++ 7, 0x1C0, 12,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
++ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
++ 0x1C0, 13,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
++ sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
++ 23, 0x1C0, 14,
++ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
++ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
++ 0x1C0, 15),
++ /* CLK_CFG_4 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
++ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
++ 0x1C0, 16),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
++ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
++ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
++ 0x1C0, 18),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
++ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
++ 0x1C0, 19),
++ /* CLK_CFG_5 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
++ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
++ 0x1C0, 20),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
++ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
++ 0x1C0, 21),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
++ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
++ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
++ /* CLK_CFG_6 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
++ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
++ 7, 0x1C0, 24),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
++ 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
++ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
++ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
++ /* CLK_CFG_7 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
++ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
++ 0x1C0, 28),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
++ 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
++ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
++ 0x1C0, 30),
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
++ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
++ 0x1C4, 0),
++ /* CLK_CFG_8 */
++ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
++ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
++ 0x1C4, 1),
++};
++
++static struct mtk_composite top_aud_divs[] = {
++ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
++ 0x0420, 0, 0x0420, 8, 8),
++};
++
++static const struct mtk_clk_desc topck_desc = {
++ .factor_clks = top_divs,
++ .num_factor_clks = ARRAY_SIZE(top_divs),
++ .mux_clks = top_muxes,
++ .num_mux_clks = ARRAY_SIZE(top_muxes),
++ .composite_clks = top_aud_divs,
++ .num_composite_clks = ARRAY_SIZE(top_aud_divs),
++ .clk_lock = &mt7981_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
++ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
++ { /* sentinel */ }
++};
++
++static struct platform_driver clk_mt7981_topckgen_drv = {
++ .probe = mtk_clk_simple_probe,
++ .remove = mtk_clk_simple_remove,
++ .driver = {
++ .name = "clk-mt7981-topckgen",
++ .of_match_table = of_match_clk_mt7981_topckgen,
++ },
++};
++builtin_platform_driver(clk_mt7981_topckgen_drv);
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -134,6 +134,13 @@ config PINCTRL_MT7986
+@@ -141,6 +141,13 @@ config PINCTRL_MT7986
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
depends on OF
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
+@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -233,6 +233,7 @@ struct mtk_pll_data {
- u32 pcw_reg;
- int pcw_shift;
- u32 pcw_chg_reg;
-+ int pcw_chg_shift;
- const struct mtk_pll_div_table *div_table;
- const char *parent_name;
- u32 en_reg;
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct
+@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct
pll->data->pcw_shift);
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
writel(chg, pll->pcw_chg_addr);
if (pll->tuner_addr)
writel(val + 1, pll->tuner_addr);
+--- a/drivers/clk/mediatek/clk-pll.h
++++ b/drivers/clk/mediatek/clk-pll.h
+@@ -42,6 +42,7 @@ struct mtk_pll_data {
+ u32 pcw_reg;
+ int pcw_shift;
+ u32 pcw_chg_reg;
++ int pcw_chg_shift;
+ const struct mtk_pll_div_table *div_table;
+ const char *parent_name;
+ u32 en_reg;
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
-@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS
- This driver add support for clocks for Ethernet and SGMII
+@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
+ This driver adds support for clocks for Ethernet and SGMII
required on MediaTek MT7986 SoC.
+config COMMON_CLK_MT7988
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
-@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
+@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
+++ /dev/null
-From 1a7963e9843f6f1e4b02a30926d20b314c03e4df Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sat, 25 Jun 2022 02:10:13 +0800
-Subject: [PATCH] mmc: mediatek: add support for MT7986 SoC
-
-Adding mt7986 own characteristics and of_device_id to have support
-of MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Change-Id: I07cf8406cbe8c1a7114b304f35fc3e689e512e5a
----
- drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -540,6 +540,19 @@ static const struct mtk_mmc_compatible m
- .support_64g = false,
- };
-
-+static const struct mtk_mmc_compatible mt7986_compat = {
-+ .clk_div_bits = 12,
-+ .recheck_sdio_irq = true,
-+ .hs400_tune = false,
-+ .pad_tune_reg = MSDC_PAD_TUNE0,
-+ .async_fifo = true,
-+ .data_tune = true,
-+ .busy_check = true,
-+ .stop_clk_fix = true,
-+ .enhance_rx = true,
-+ .support_64g = true,
-+};
-+
- static const struct mtk_mmc_compatible mt8516_compat = {
- .clk_div_bits = 12,
- .recheck_sdio_irq = true,
-@@ -584,6 +597,7 @@ static const struct of_device_id msdc_of
- { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
- { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
- { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
-+ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
- { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
- { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
- { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
--- /dev/null
+From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Tue, 25 Oct 2022 15:29:53 +0200
+Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC
+
+Adding mt7986 own characteristics and of_device_id to have support
+of MT7986 SoC.
+
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m
+ .support_64g = false,
+ };
+
++static const struct mtk_mmc_compatible mt7986_compat = {
++ .clk_div_bits = 12,
++ .recheck_sdio_irq = true,
++ .hs400_tune = false,
++ .pad_tune_reg = MSDC_PAD_TUNE0,
++ .async_fifo = true,
++ .data_tune = true,
++ .busy_check = true,
++ .stop_clk_fix = true,
++ .enhance_rx = true,
++ .support_64g = true,
++};
++
+ static const struct mtk_mmc_compatible mt8135_compat = {
+ .clk_div_bits = 8,
+ .recheck_sdio_irq = true,
+@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of
+ { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
+ { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
+ { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
++ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
+ { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
+ { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
+ { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
--- /dev/null
+From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001
+From: Mengqi Zhang <mengqi.zhang@mediatek.com>
+Date: Sun, 6 Nov 2022 11:39:24 +0800
+Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control
+
+Add crypto clock control and ungate it before CQHCI init.
+
+Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -452,6 +452,7 @@ struct msdc_host {
+ struct clk *bus_clk; /* bus clock which used to access register */
+ struct clk *src_clk_cg; /* msdc source clock control gate */
+ struct clk *sys_clk_cg; /* msdc subsys clock control gate */
++ struct clk *crypto_clk; /* msdc crypto clock control gate */
+ struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
+ u32 mclk; /* mmc subsystem clock frequency */
+ u32 src_clk_freq; /* source clock frequency */
+@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct
+ static void msdc_gate_clock(struct msdc_host *host)
+ {
+ clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
++ clk_disable_unprepare(host->crypto_clk);
+ clk_disable_unprepare(host->src_clk_cg);
+ clk_disable_unprepare(host->src_clk);
+ clk_disable_unprepare(host->bus_clk);
+@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc
+ clk_prepare_enable(host->bus_clk);
+ clk_prepare_enable(host->src_clk);
+ clk_prepare_enable(host->src_clk_cg);
++ clk_prepare_enable(host->crypto_clk);
+ ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
+ if (ret) {
+ dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
+@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor
+ goto host_free;
+ }
+
++ /* only eMMC has crypto property */
++ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
++ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
++ if (IS_ERR(host->crypto_clk))
++ host->crypto_clk = NULL;
++ else
++ mmc->caps2 |= MMC_CAP2_CRYPTO;
++ }
++
+ host->irq = platform_get_irq(pdev, 0);
+ if (host->irq < 0) {
+ ret = host->irq;
--- /dev/null
+From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001
+From: Yu Zhe <yuzhe@nfschina.com>
+Date: Thu, 10 Nov 2022 15:28:19 +0800
+Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment
+
+spelling mistake fix : "alreay" -> "already"
+ "checksume" -> "checksum"
+
+Signed-off-by: Yu Zhe <yuzhe@nfschina.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/mtk-sd.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct
+ else
+ bd[j].bd_info &= ~BDMA_DESC_EOL;
+
+- /* checksume need to clear first */
++ /* checksum need to clear first */
+ bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
+ bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
+ }
+@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho
+ !host->hs400_tuning))
+ /*
+ * should not clear fifo/interrupt as the tune data
+- * may have alreay come when cmd19/cmd21 gets response
++ * may have already come when cmd19/cmd21 gets response
+ * CRC error.
+ */
+ msdc_reset_hw(host);
--- /dev/null
+From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001
+From: ChanWoo Lee <cw9316.lee@samsung.com>
+Date: Thu, 24 Nov 2022 17:00:31 +0900
+Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning()
+
+Replace code with the already defined function. No functional changes.
+
+Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com>
+Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/mtk-sd.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho
+
+ if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
+ if (events & MSDC_INT_CMDTMO ||
+- (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
+- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
+- !host->hs400_tuning))
++ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
+ /*
+ * should not clear fifo/interrupt as the tune data
+ * may have already come when cmd19/cmd21 gets response
+@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho
+ {
+ if ((cmd->error &&
+ !(cmd->error == -EILSEQ &&
+- (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
+- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
+- host->hs400_tuning))) ||
++ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
+ (mrq->sbc && mrq->sbc->error))
+ msdc_request_done(host, mrq);
+ else if (cmd == mrq->sbc)
static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
{
-@@ -1343,6 +1344,7 @@ static int spinand_probe(struct spi_mem
+@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem
if (ret)
return ret;
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
goto err_spinand_cleanup;
-@@ -1350,6 +1352,7 @@ static int spinand_probe(struct spi_mem
+@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem
return 0;
err_spinand_cleanup:
spinand_cleanup(spinand);
return ret;
-@@ -1368,6 +1371,7 @@ static int spinand_remove(struct spi_mem
+@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem
if (ret)
return ret;
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -553,6 +553,7 @@
+@@ -552,6 +552,7 @@
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
nand-ecc-engine = <&snfi>;
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
--spinand-objs := core.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
-+spinand-objs := core.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
+-spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
++spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
-@@ -939,6 +939,7 @@ static const struct nand_ops spinand_ops
-
+@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops
static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ &ato_spinand_manufacturer,
&esmt_c8_spinand_manufacturer,
+ &fidelix_spinand_manufacturer,
- &gigadevice_spinand_manufacturer,
&etron_spinand_manufacturer,
+ &gigadevice_spinand_manufacturer,
¯onix_spinand_manufacturer,
--- /dev/null
+++ b/drivers/mtd/nand/spi/fidelix.c
+};
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
-@@ -262,6 +262,7 @@ struct spinand_manufacturer {
- /* SPI NAND manufacturers */
+@@ -263,6 +263,7 @@ struct spinand_manufacturer {
+ extern const struct spinand_manufacturer ato_spinand_manufacturer;
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
extern const struct spinand_manufacturer etron_spinand_manufacturer;
+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
+++ /dev/null
-From 7a768326fdba542144833b9198a6d0edab52fad2 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:56 +0800
-Subject: [PATCH 01/21] cpufreq: mediatek: Cleanup variables and error handling
- in mtk_cpu_dvfs_info_init()
-
-- Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init().
-- Unify error message format and use dev_err_probe() if possible.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 89 ++++++++++++------------------
- 1 file changed, 34 insertions(+), 55 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -302,96 +302,75 @@ static int mtk_cpufreq_set_target(struct
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- struct device *cpu_dev;
-- struct regulator *proc_reg = ERR_PTR(-ENODEV);
-- struct regulator *sram_reg = ERR_PTR(-ENODEV);
-- struct clk *cpu_clk = ERR_PTR(-ENODEV);
-- struct clk *inter_clk = ERR_PTR(-ENODEV);
- struct dev_pm_opp *opp;
- unsigned long rate;
- int ret;
-
- cpu_dev = get_cpu_device(cpu);
- if (!cpu_dev) {
-- pr_err("failed to get cpu%d device\n", cpu);
-+ dev_err(cpu_dev, "failed to get cpu%d device\n", cpu);
- return -ENODEV;
- }
-+ info->cpu_dev = cpu_dev;
-
-- cpu_clk = clk_get(cpu_dev, "cpu");
-- if (IS_ERR(cpu_clk)) {
-- if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
-- pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
-- else
-- pr_err("failed to get cpu clk for cpu%d\n", cpu);
--
-- ret = PTR_ERR(cpu_clk);
-- return ret;
-- }
--
-- inter_clk = clk_get(cpu_dev, "intermediate");
-- if (IS_ERR(inter_clk)) {
-- if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
-- pr_warn("intermediate clk for cpu%d not ready, retry.\n",
-- cpu);
-- else
-- pr_err("failed to get intermediate clk for cpu%d\n",
-- cpu);
-+ info->cpu_clk = clk_get(cpu_dev, "cpu");
-+ if (IS_ERR(info->cpu_clk)) {
-+ ret = PTR_ERR(info->cpu_clk);
-+ return dev_err_probe(cpu_dev, ret,
-+ "cpu%d: failed to get cpu clk\n", cpu);
-+ }
-
-- ret = PTR_ERR(inter_clk);
-+ info->inter_clk = clk_get(cpu_dev, "intermediate");
-+ if (IS_ERR(info->inter_clk)) {
-+ ret = PTR_ERR(info->inter_clk);
-+ dev_err_probe(cpu_dev, ret,
-+ "cpu%d: failed to get intermediate clk\n", cpu);
- goto out_free_resources;
- }
-
-- proc_reg = regulator_get_optional(cpu_dev, "proc");
-- if (IS_ERR(proc_reg)) {
-- if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
-- pr_warn("proc regulator for cpu%d not ready, retry.\n",
-- cpu);
-- else
-- pr_err("failed to get proc regulator for cpu%d\n",
-- cpu);
--
-- ret = PTR_ERR(proc_reg);
-+ info->proc_reg = regulator_get_optional(cpu_dev, "proc");
-+ if (IS_ERR(info->proc_reg)) {
-+ ret = PTR_ERR(info->proc_reg);
-+ dev_err_probe(cpu_dev, ret,
-+ "cpu%d: failed to get proc regulator\n", cpu);
- goto out_free_resources;
- }
-
- /* Both presence and absence of sram regulator are valid cases. */
-- sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+ info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+ if (IS_ERR(info->sram_reg))
-+ info->sram_reg = NULL;
-
- /* Get OPP-sharing information from "operating-points-v2" bindings */
- ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
- if (ret) {
-- pr_err("failed to get OPP-sharing information for cpu%d\n",
-- cpu);
-+ dev_err(cpu_dev,
-+ "cpu%d: failed to get OPP-sharing information\n", cpu);
- goto out_free_resources;
- }
-
- ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
- if (ret) {
-- pr_warn("no OPP table for cpu%d\n", cpu);
-+ dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
- goto out_free_resources;
- }
-
- /* Search a safe voltage for intermediate frequency. */
-- rate = clk_get_rate(inter_clk);
-+ rate = clk_get_rate(info->inter_clk);
- opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
- if (IS_ERR(opp)) {
-- pr_err("failed to get intermediate opp for cpu%d\n", cpu);
-+ dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
- ret = PTR_ERR(opp);
- goto out_free_opp_table;
- }
- info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- dev_pm_opp_put(opp);
-
-- info->cpu_dev = cpu_dev;
-- info->proc_reg = proc_reg;
-- info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
-- info->cpu_clk = cpu_clk;
-- info->inter_clk = inter_clk;
--
- /*
- * If SRAM regulator is present, software "voltage tracking" is needed
- * for this CPU power domain.
- */
-- info->need_voltage_tracking = !IS_ERR(sram_reg);
-+ info->need_voltage_tracking = (info->sram_reg != NULL);
-
- return 0;
-
-@@ -399,14 +378,14 @@ out_free_opp_table:
- dev_pm_opp_of_cpumask_remove_table(&info->cpus);
-
- out_free_resources:
-- if (!IS_ERR(proc_reg))
-- regulator_put(proc_reg);
-- if (!IS_ERR(sram_reg))
-- regulator_put(sram_reg);
-- if (!IS_ERR(cpu_clk))
-- clk_put(cpu_clk);
-- if (!IS_ERR(inter_clk))
-- clk_put(inter_clk);
-+ if (!IS_ERR(info->proc_reg))
-+ regulator_put(info->proc_reg);
-+ if (!IS_ERR(info->sram_reg))
-+ regulator_put(info->sram_reg);
-+ if (!IS_ERR(info->cpu_clk))
-+ clk_put(info->cpu_clk);
-+ if (!IS_ERR(info->inter_clk))
-+ clk_put(info->inter_clk);
-
- return ret;
- }
+++ /dev/null
-From 756104b856d4bc3121420af3ced342f5fc2b2123 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:57 +0800
-Subject: [PATCH 02/21] cpufreq: mediatek: Remove unused headers
-
-Remove unused headers.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -13,8 +13,6 @@
- #include <linux/platform_device.h>
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
--#include <linux/slab.h>
--#include <linux/thermal.h>
-
- #define MIN_VOLT_SHIFT (100000)
- #define MAX_VOLT_SHIFT (200000)
+++ /dev/null
-From 342d5545e9f40496db9ae0d31c2427dd5f369a43 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 8 Apr 2022 12:58:58 +0800
-Subject: [PATCH 03/21] cpufreq: mediatek: Enable clocks and regulators
-
-We need to enable regulators so that the max and min requested values will
-be recorded.
-The intermediate clock is not always enabled by CCF in different projects,
-so we should enable it in the cpufreq driver.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 50 +++++++++++++++++++++++++++---
- 1 file changed, 45 insertions(+), 5 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -334,10 +334,23 @@ static int mtk_cpu_dvfs_info_init(struct
- goto out_free_resources;
- }
-
-+ ret = regulator_enable(info->proc_reg);
-+ if (ret) {
-+ dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
-+ goto out_free_resources;
-+ }
-+
- /* Both presence and absence of sram regulator are valid cases. */
- info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
- if (IS_ERR(info->sram_reg))
- info->sram_reg = NULL;
-+ else {
-+ ret = regulator_enable(info->sram_reg);
-+ if (ret) {
-+ dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
-+ goto out_free_resources;
-+ }
-+ }
-
- /* Get OPP-sharing information from "operating-points-v2" bindings */
- ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
-@@ -353,13 +366,21 @@ static int mtk_cpu_dvfs_info_init(struct
- goto out_free_resources;
- }
-
-+ ret = clk_prepare_enable(info->cpu_clk);
-+ if (ret)
-+ goto out_free_opp_table;
-+
-+ ret = clk_prepare_enable(info->inter_clk);
-+ if (ret)
-+ goto out_disable_mux_clock;
-+
- /* Search a safe voltage for intermediate frequency. */
- rate = clk_get_rate(info->inter_clk);
- opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
- if (IS_ERR(opp)) {
- dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu);
- ret = PTR_ERR(opp);
-- goto out_free_opp_table;
-+ goto out_disable_inter_clock;
- }
- info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- dev_pm_opp_put(opp);
-@@ -372,10 +393,21 @@ static int mtk_cpu_dvfs_info_init(struct
-
- return 0;
-
-+out_disable_inter_clock:
-+ clk_disable_unprepare(info->inter_clk);
-+
-+out_disable_mux_clock:
-+ clk_disable_unprepare(info->cpu_clk);
-+
- out_free_opp_table:
- dev_pm_opp_of_cpumask_remove_table(&info->cpus);
-
- out_free_resources:
-+ if (regulator_is_enabled(info->proc_reg))
-+ regulator_disable(info->proc_reg);
-+ if (info->sram_reg && regulator_is_enabled(info->sram_reg))
-+ regulator_disable(info->sram_reg);
-+
- if (!IS_ERR(info->proc_reg))
- regulator_put(info->proc_reg);
- if (!IS_ERR(info->sram_reg))
-@@ -390,14 +422,22 @@ out_free_resources:
-
- static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
- {
-- if (!IS_ERR(info->proc_reg))
-+ if (!IS_ERR(info->proc_reg)) {
-+ regulator_disable(info->proc_reg);
- regulator_put(info->proc_reg);
-- if (!IS_ERR(info->sram_reg))
-+ }
-+ if (!IS_ERR(info->sram_reg)) {
-+ regulator_disable(info->sram_reg);
- regulator_put(info->sram_reg);
-- if (!IS_ERR(info->cpu_clk))
-+ }
-+ if (!IS_ERR(info->cpu_clk)) {
-+ clk_disable_unprepare(info->cpu_clk);
- clk_put(info->cpu_clk);
-- if (!IS_ERR(info->inter_clk))
-+ }
-+ if (!IS_ERR(info->inter_clk)) {
-+ clk_disable_unprepare(info->inter_clk);
- clk_put(info->inter_clk);
-+ }
-
- dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- }
+++ /dev/null
-From a02e2b359141035d2d6999940bc1b9f83ec88587 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:27 +0800
-Subject: [PATCH 04/21] cpufreq: mediatek: Use device print to show logs
-
-- Replace pr_* with dev_* to show logs.
-- Remove usage of __func__.
-
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++--------------
- 1 file changed, 28 insertions(+), 26 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -67,7 +67,8 @@ static int mtk_cpufreq_voltage_tracking(
-
- old_vproc = regulator_get_voltage(proc_reg);
- if (old_vproc < 0) {
-- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
-+ dev_err(info->cpu_dev,
-+ "invalid Vproc value: %d\n", old_vproc);
- return old_vproc;
- }
- /* Vsram should not exceed the maximum allowed voltage of SoC. */
-@@ -83,14 +84,14 @@ static int mtk_cpufreq_voltage_tracking(
- do {
- old_vsram = regulator_get_voltage(sram_reg);
- if (old_vsram < 0) {
-- pr_err("%s: invalid Vsram value: %d\n",
-- __func__, old_vsram);
-+ dev_err(info->cpu_dev,
-+ "invalid Vsram value: %d\n", old_vsram);
- return old_vsram;
- }
- old_vproc = regulator_get_voltage(proc_reg);
- if (old_vproc < 0) {
-- pr_err("%s: invalid Vproc value: %d\n",
-- __func__, old_vproc);
-+ dev_err(info->cpu_dev,
-+ "invalid Vproc value: %d\n", old_vproc);
- return old_vproc;
- }
-
-@@ -138,14 +139,14 @@ static int mtk_cpufreq_voltage_tracking(
- do {
- old_vproc = regulator_get_voltage(proc_reg);
- if (old_vproc < 0) {
-- pr_err("%s: invalid Vproc value: %d\n",
-- __func__, old_vproc);
-+ dev_err(info->cpu_dev,
-+ "invalid Vproc value: %d\n", old_vproc);
- return old_vproc;
- }
- old_vsram = regulator_get_voltage(sram_reg);
- if (old_vsram < 0) {
-- pr_err("%s: invalid Vsram value: %d\n",
-- __func__, old_vsram);
-+ dev_err(info->cpu_dev,
-+ "invalid Vsram value: %d\n", old_vsram);
- return old_vsram;
- }
-
-@@ -216,7 +217,7 @@ static int mtk_cpufreq_set_target(struct
- old_freq_hz = clk_get_rate(cpu_clk);
- old_vproc = regulator_get_voltage(info->proc_reg);
- if (old_vproc < 0) {
-- pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
-+ dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc);
- return old_vproc;
- }
-
-@@ -224,8 +225,8 @@ static int mtk_cpufreq_set_target(struct
-
- opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
- if (IS_ERR(opp)) {
-- pr_err("cpu%d: failed to find OPP for %ld\n",
-- policy->cpu, freq_hz);
-+ dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
-+ policy->cpu, freq_hz);
- return PTR_ERR(opp);
- }
- vproc = dev_pm_opp_get_voltage(opp);
-@@ -239,8 +240,8 @@ static int mtk_cpufreq_set_target(struct
- if (old_vproc < target_vproc) {
- ret = mtk_cpufreq_set_voltage(info, target_vproc);
- if (ret) {
-- pr_err("cpu%d: failed to scale up voltage!\n",
-- policy->cpu);
-+ dev_err(cpu_dev,
-+ "cpu%d: failed to scale up voltage!\n", policy->cpu);
- mtk_cpufreq_set_voltage(info, old_vproc);
- return ret;
- }
-@@ -249,8 +250,8 @@ static int mtk_cpufreq_set_target(struct
- /* Reparent the CPU clock to intermediate clock. */
- ret = clk_set_parent(cpu_clk, info->inter_clk);
- if (ret) {
-- pr_err("cpu%d: failed to re-parent cpu clock!\n",
-- policy->cpu);
-+ dev_err(cpu_dev,
-+ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- mtk_cpufreq_set_voltage(info, old_vproc);
- WARN_ON(1);
- return ret;
-@@ -259,8 +260,8 @@ static int mtk_cpufreq_set_target(struct
- /* Set the original PLL to target rate. */
- ret = clk_set_rate(armpll, freq_hz);
- if (ret) {
-- pr_err("cpu%d: failed to scale cpu clock rate!\n",
-- policy->cpu);
-+ dev_err(cpu_dev,
-+ "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- clk_set_parent(cpu_clk, armpll);
- mtk_cpufreq_set_voltage(info, old_vproc);
- return ret;
-@@ -269,8 +270,8 @@ static int mtk_cpufreq_set_target(struct
- /* Set parent of CPU clock back to the original PLL. */
- ret = clk_set_parent(cpu_clk, armpll);
- if (ret) {
-- pr_err("cpu%d: failed to re-parent cpu clock!\n",
-- policy->cpu);
-+ dev_err(cpu_dev,
-+ "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- mtk_cpufreq_set_voltage(info, inter_vproc);
- WARN_ON(1);
- return ret;
-@@ -283,8 +284,8 @@ static int mtk_cpufreq_set_target(struct
- if (vproc < inter_vproc || vproc < old_vproc) {
- ret = mtk_cpufreq_set_voltage(info, vproc);
- if (ret) {
-- pr_err("cpu%d: failed to scale down voltage!\n",
-- policy->cpu);
-+ dev_err(cpu_dev,
-+ "cpu%d: failed to scale down voltage!\n", policy->cpu);
- clk_set_parent(cpu_clk, info->inter_clk);
- clk_set_rate(armpll, old_freq_hz);
- clk_set_parent(cpu_clk, armpll);
-@@ -450,15 +451,16 @@ static int mtk_cpufreq_init(struct cpufr
-
- info = mtk_cpu_dvfs_info_lookup(policy->cpu);
- if (!info) {
-- pr_err("dvfs info for cpu%d is not initialized.\n",
-- policy->cpu);
-+ dev_err(info->cpu_dev,
-+ "dvfs info for cpu%d is not initialized.\n", policy->cpu);
- return -EINVAL;
- }
-
- ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
- if (ret) {
-- pr_err("failed to init cpufreq table for cpu%d: %d\n",
-- policy->cpu, ret);
-+ dev_err(info->cpu_dev,
-+ "failed to init cpufreq table for cpu%d: %d\n",
-+ policy->cpu, ret);
- return ret;
- }
-
+++ /dev/null
-From 35832d9f9c5c1da01420d962dc56e7e61d104829 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:28 +0800
-Subject: [PATCH 05/21] cpufreq: mediatek: Replace old_* with pre_*
-
-To make driver more readable, replace old_* with pre_*.
-
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++---------------
- 1 file changed, 42 insertions(+), 42 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -63,18 +63,18 @@ static int mtk_cpufreq_voltage_tracking(
- {
- struct regulator *proc_reg = info->proc_reg;
- struct regulator *sram_reg = info->sram_reg;
-- int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
-+ int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-
-- old_vproc = regulator_get_voltage(proc_reg);
-- if (old_vproc < 0) {
-+ pre_vproc = regulator_get_voltage(proc_reg);
-+ if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
-- "invalid Vproc value: %d\n", old_vproc);
-- return old_vproc;
-+ "invalid Vproc value: %d\n", pre_vproc);
-+ return pre_vproc;
- }
- /* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
-
-- if (old_vproc < new_vproc) {
-+ if (pre_vproc < new_vproc) {
- /*
- * When scaling up voltages, Vsram and Vproc scale up step
- * by step. At each step, set Vsram to (Vproc + 200mV) first,
-@@ -82,20 +82,20 @@ static int mtk_cpufreq_voltage_tracking(
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
-- old_vsram = regulator_get_voltage(sram_reg);
-- if (old_vsram < 0) {
-+ pre_vsram = regulator_get_voltage(sram_reg);
-+ if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
-- "invalid Vsram value: %d\n", old_vsram);
-- return old_vsram;
-+ "invalid Vsram value: %d\n", pre_vsram);
-+ return pre_vsram;
- }
-- old_vproc = regulator_get_voltage(proc_reg);
-- if (old_vproc < 0) {
-+ pre_vproc = regulator_get_voltage(proc_reg);
-+ if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
-- "invalid Vproc value: %d\n", old_vproc);
-- return old_vproc;
-+ "invalid Vproc value: %d\n", pre_vproc);
-+ return pre_vproc;
- }
-
-- vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
-+ vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
-
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
-@@ -124,12 +124,12 @@ static int mtk_cpufreq_voltage_tracking(
- ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
- if (ret) {
-- regulator_set_voltage(sram_reg, old_vsram,
-- old_vsram);
-+ regulator_set_voltage(sram_reg, pre_vsram,
-+ pre_vsram);
- return ret;
- }
- } while (vproc < new_vproc || vsram < new_vsram);
-- } else if (old_vproc > new_vproc) {
-+ } else if (pre_vproc > new_vproc) {
- /*
- * When scaling down voltages, Vsram and Vproc scale down step
- * by step. At each step, set Vproc to (Vsram - 200mV) first,
-@@ -137,20 +137,20 @@ static int mtk_cpufreq_voltage_tracking(
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
-- old_vproc = regulator_get_voltage(proc_reg);
-- if (old_vproc < 0) {
-+ pre_vproc = regulator_get_voltage(proc_reg);
-+ if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
-- "invalid Vproc value: %d\n", old_vproc);
-- return old_vproc;
-+ "invalid Vproc value: %d\n", pre_vproc);
-+ return pre_vproc;
- }
-- old_vsram = regulator_get_voltage(sram_reg);
-- if (old_vsram < 0) {
-+ pre_vsram = regulator_get_voltage(sram_reg);
-+ if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
-- "invalid Vsram value: %d\n", old_vsram);
-- return old_vsram;
-+ "invalid Vsram value: %d\n", pre_vsram);
-+ return pre_vsram;
- }
-
-- vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
-+ vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
- ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
- if (ret)
-@@ -180,8 +180,8 @@ static int mtk_cpufreq_voltage_tracking(
- }
-
- if (ret) {
-- regulator_set_voltage(proc_reg, old_vproc,
-- old_vproc);
-+ regulator_set_voltage(proc_reg, pre_vproc,
-+ pre_vproc);
- return ret;
- }
- } while (vproc > new_vproc + VOLT_TOL ||
-@@ -209,16 +209,16 @@ static int mtk_cpufreq_set_target(struct
- struct mtk_cpu_dvfs_info *info = policy->driver_data;
- struct device *cpu_dev = info->cpu_dev;
- struct dev_pm_opp *opp;
-- long freq_hz, old_freq_hz;
-- int vproc, old_vproc, inter_vproc, target_vproc, ret;
-+ long freq_hz, pre_freq_hz;
-+ int vproc, pre_vproc, inter_vproc, target_vproc, ret;
-
- inter_vproc = info->intermediate_voltage;
-
-- old_freq_hz = clk_get_rate(cpu_clk);
-- old_vproc = regulator_get_voltage(info->proc_reg);
-- if (old_vproc < 0) {
-- dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc);
-- return old_vproc;
-+ pre_freq_hz = clk_get_rate(cpu_clk);
-+ pre_vproc = regulator_get_voltage(info->proc_reg);
-+ if (pre_vproc < 0) {
-+ dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
-+ return pre_vproc;
- }
-
- freq_hz = freq_table[index].frequency * 1000;
-@@ -237,12 +237,12 @@ static int mtk_cpufreq_set_target(struct
- * current voltage, scale up voltage first.
- */
- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
-- if (old_vproc < target_vproc) {
-+ if (pre_vproc < target_vproc) {
- ret = mtk_cpufreq_set_voltage(info, target_vproc);
- if (ret) {
- dev_err(cpu_dev,
- "cpu%d: failed to scale up voltage!\n", policy->cpu);
-- mtk_cpufreq_set_voltage(info, old_vproc);
-+ mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
- }
- }
-@@ -252,7 +252,7 @@ static int mtk_cpufreq_set_target(struct
- if (ret) {
- dev_err(cpu_dev,
- "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
-- mtk_cpufreq_set_voltage(info, old_vproc);
-+ mtk_cpufreq_set_voltage(info, pre_vproc);
- WARN_ON(1);
- return ret;
- }
-@@ -263,7 +263,7 @@ static int mtk_cpufreq_set_target(struct
- dev_err(cpu_dev,
- "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- clk_set_parent(cpu_clk, armpll);
-- mtk_cpufreq_set_voltage(info, old_vproc);
-+ mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
- }
-
-@@ -281,13 +281,13 @@ static int mtk_cpufreq_set_target(struct
- * If the new voltage is lower than the intermediate voltage or the
- * original voltage, scale down to the new voltage.
- */
-- if (vproc < inter_vproc || vproc < old_vproc) {
-+ if (vproc < inter_vproc || vproc < pre_vproc) {
- ret = mtk_cpufreq_set_voltage(info, vproc);
- if (ret) {
- dev_err(cpu_dev,
- "cpu%d: failed to scale down voltage!\n", policy->cpu);
- clk_set_parent(cpu_clk, info->inter_clk);
-- clk_set_rate(armpll, old_freq_hz);
-+ clk_set_rate(armpll, pre_freq_hz);
- clk_set_parent(cpu_clk, armpll);
- return ret;
- }
+++ /dev/null
-From 34737eb8d0daa0d4183f10286a2f55d8788066bc Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:29 +0800
-Subject: [PATCH 06/21] cpufreq: mediatek: Record previous target vproc value
-
-We found the buck voltage may not be exactly the same with what we set
-because CPU may share the same buck with other module.
-Therefore, we need to record the previous desired value instead of reading
-it from regulators.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info {
- struct list_head list_head;
- int intermediate_voltage;
- bool need_voltage_tracking;
-+ int pre_vproc;
- };
-
- static struct platform_device *cpufreq_pdev;
-@@ -193,11 +194,17 @@ static int mtk_cpufreq_voltage_tracking(
-
- static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
- {
-+ int ret;
-+
- if (info->need_voltage_tracking)
-- return mtk_cpufreq_voltage_tracking(info, vproc);
-+ ret = mtk_cpufreq_voltage_tracking(info, vproc);
- else
-- return regulator_set_voltage(info->proc_reg, vproc,
-- vproc + VOLT_TOL);
-+ ret = regulator_set_voltage(info->proc_reg, vproc,
-+ MAX_VOLT_LIMIT);
-+ if (!ret)
-+ info->pre_vproc = vproc;
-+
-+ return ret;
- }
-
- static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
-@@ -215,7 +222,12 @@ static int mtk_cpufreq_set_target(struct
- inter_vproc = info->intermediate_voltage;
-
- pre_freq_hz = clk_get_rate(cpu_clk);
-- pre_vproc = regulator_get_voltage(info->proc_reg);
-+
-+ if (unlikely(info->pre_vproc <= 0))
-+ pre_vproc = regulator_get_voltage(info->proc_reg);
-+ else
-+ pre_vproc = info->pre_vproc;
-+
- if (pre_vproc < 0) {
- dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
+++ /dev/null
-From f6114c2bc563a8050e9dc874ad87e1448865f031 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 22 Apr 2022 15:52:33 +0800
-Subject: [PATCH 07/21] cpufreq: mediatek: Make sram regulator optional
-
-For some MediaTek SoCs, like MT8186, it's possible that the sram regulator
-is shared between CPU and CCI.
-We hope regulator framework can return error for error handling rather
-than a dummy handler from regulator_get api.
-Therefore, we choose to use regulator_get_optional.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -354,7 +354,7 @@ static int mtk_cpu_dvfs_info_init(struct
- }
-
- /* Both presence and absence of sram regulator are valid cases. */
-- info->sram_reg = regulator_get_exclusive(cpu_dev, "sram");
-+ info->sram_reg = regulator_get_optional(cpu_dev, "sram");
- if (IS_ERR(info->sram_reg))
- info->sram_reg = NULL;
- else {
+++ /dev/null
-From fa7030d8ad4638acfd9e0fac84a20716d031dc95 Mon Sep 17 00:00:00 2001
-From: Wan Jiabing <wanjiabing@vivo.com>
-Date: Tue, 26 Apr 2022 19:17:14 +0800
-Subject: [PATCH 08/21] cpufreq: mediatek: Fix NULL pointer dereference in
- mediatek-cpufreq
-
-Fix following coccicheck error:
-drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced.
-
-Use pr_err instead of dev_err to avoid dereferring a NULL pointer.
-
-Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs")
-Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -463,8 +463,8 @@ static int mtk_cpufreq_init(struct cpufr
-
- info = mtk_cpu_dvfs_info_lookup(policy->cpu);
- if (!info) {
-- dev_err(info->cpu_dev,
-- "dvfs info for cpu%d is not initialized.\n", policy->cpu);
-+ pr_err("dvfs info for cpu%d is not initialized.\n",
-+ policy->cpu);
- return -EINVAL;
- }
-
+++ /dev/null
-From be2354b064e6bafbbad599ae2e10569ba4f7d5a6 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:19 +0800
-Subject: [PATCH 09/21] cpufreq: mediatek: Move voltage limits to platform data
-
-Voltages and shifts are defined as macros originally.
-There are different requirements of these values for each MediaTek SoCs.
-Therefore, we add the platform data and move these values into it.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
- 1 file changed, 58 insertions(+), 26 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -10,15 +10,21 @@
- #include <linux/cpumask.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_platform.h>
- #include <linux/platform_device.h>
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
-
--#define MIN_VOLT_SHIFT (100000)
--#define MAX_VOLT_SHIFT (200000)
--#define MAX_VOLT_LIMIT (1150000)
- #define VOLT_TOL (10000)
-
-+struct mtk_cpufreq_platform_data {
-+ int min_volt_shift;
-+ int max_volt_shift;
-+ int proc_max_volt;
-+ int sram_min_volt;
-+ int sram_max_volt;
-+};
-+
- /*
- * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
- * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
-@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- int intermediate_voltage;
- bool need_voltage_tracking;
- int pre_vproc;
-+ const struct mtk_cpufreq_platform_data *soc_data;
- };
-
- static struct platform_device *cpufreq_pdev;
-@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu
- static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
- int new_vproc)
- {
-+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
- struct regulator *proc_reg = info->proc_reg;
- struct regulator *sram_reg = info->sram_reg;
- int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(
- return pre_vproc;
- }
- /* Vsram should not exceed the maximum allowed voltage of SoC. */
-- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
-+ new_vsram = min(new_vproc + soc_data->min_volt_shift,
-+ soc_data->sram_max_volt);
-
- if (pre_vproc < new_vproc) {
- /*
-@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(
- return pre_vproc;
- }
-
-- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
-+ vsram = min(new_vsram,
-+ pre_vproc + soc_data->min_volt_shift);
-
-- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
-- vsram = MAX_VOLT_LIMIT;
-+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-+ vsram = soc_data->sram_max_volt;
-
- /*
- * If the target Vsram hits the maximum voltage,
-@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
-
-- vproc = vsram - MIN_VOLT_SHIFT;
-+ vproc = vsram - soc_data->min_volt_shift;
- }
- if (ret)
- return ret;
-@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(
- return pre_vsram;
- }
-
-- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
-+ vproc = max(new_vproc,
-+ pre_vsram - soc_data->max_volt_shift);
- ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
- if (ret)
-@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(
- if (vproc == new_vproc)
- vsram = new_vsram;
- else
-- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
-+ vsram = max(new_vsram,
-+ vproc + soc_data->min_volt_shift);
-
-- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
-- vsram = MAX_VOLT_LIMIT;
-+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-+ vsram = soc_data->sram_max_volt;
-
- /*
- * If the target Vsram hits the maximum voltage,
-@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(
-
- static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
- {
-+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
- int ret;
-
- if (info->need_voltage_tracking)
- ret = mtk_cpufreq_voltage_tracking(info, vproc);
- else
- ret = regulator_set_voltage(info->proc_reg, vproc,
-- MAX_VOLT_LIMIT);
-+ soc_data->proc_max_volt);
- if (!ret)
- info->pre_vproc = vproc;
-
-@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq
-
- static int mtk_cpufreq_probe(struct platform_device *pdev)
- {
-+ const struct mtk_cpufreq_platform_data *data;
- struct mtk_cpu_dvfs_info *info, *tmp;
- int cpu, ret;
-
-+ data = dev_get_platdata(&pdev->dev);
-+ if (!data) {
-+ dev_err(&pdev->dev,
-+ "failed to get mtk cpufreq platform data\n");
-+ return -ENODEV;
-+ }
-+
- for_each_possible_cpu(cpu) {
- info = mtk_cpu_dvfs_info_lookup(cpu);
- if (info)
-@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct plat
- goto release_dvfs_info_list;
- }
-
-+ info->soc_data = data;
- ret = mtk_cpu_dvfs_info_init(info, cpu);
- if (ret) {
- dev_err(&pdev->dev,
-@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufre
- .probe = mtk_cpufreq_probe,
- };
-
-+static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
-+ .min_volt_shift = 100000,
-+ .max_volt_shift = 200000,
-+ .proc_max_volt = 1150000,
-+ .sram_min_volt = 0,
-+ .sram_max_volt = 1150000,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
-- { .compatible = "mediatek,mt2701", },
-- { .compatible = "mediatek,mt2712", },
-- { .compatible = "mediatek,mt7622", },
-- { .compatible = "mediatek,mt7623", },
-- { .compatible = "mediatek,mt8167", },
-- { .compatible = "mediatek,mt817x", },
-- { .compatible = "mediatek,mt8173", },
-- { .compatible = "mediatek,mt8176", },
-- { .compatible = "mediatek,mt8183", },
-- { .compatible = "mediatek,mt8365", },
-- { .compatible = "mediatek,mt8516", },
--
-+ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- { }
- };
- MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
-@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_ini
- {
- struct device_node *np;
- const struct of_device_id *match;
-+ const struct mtk_cpufreq_platform_data *data;
- int err;
-
- np = of_find_node_by_path("/");
-@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_ini
- pr_debug("Machine is not compatible with mtk-cpufreq\n");
- return -ENODEV;
- }
-+ data = match->data;
-
- err = platform_driver_register(&mtk_cpufreq_platdrv);
- if (err)
-@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_ini
- * and the device registration codes are put here to handle defer
- * probing.
- */
-- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
-+ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
-+ data, sizeof(*data));
- if (IS_ERR(cpufreq_pdev)) {
- pr_err("failed to register mtk-cpufreq platform device\n");
- platform_driver_unregister(&mtk_cpufreq_platdrv);
+++ /dev/null
-From 944b041c91f1e1cd762c39c1222f078550149486 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Thu, 5 May 2022 19:52:20 +0800
-Subject: [PATCH 10/21] cpufreq: mediatek: Refine
- mtk_cpufreq_voltage_tracking()
-
-Because the difference of sram and proc should in a range of min_volt_shift
-and max_volt_shift. We need to adjust the sram and proc step by step.
-
-We replace VOLT_TOL (voltage tolerance) with the platform data and update the
-logic to determine the voltage boundary and invoking regulator_set_voltage.
-
-- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary
- of sram regulator.
-- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the
- voltage boundary of vproc regulator.
-
-Moreover, to prevent infinite loop when tracking voltage, we calculate the
-maximum value for each platform data.
-We assume min voltage is 0 and tracking target voltage using
-min_volt_shift for each iteration.
-The retry_max is 3 times of expeted iteration count.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++-------------------
- 1 file changed, 51 insertions(+), 96 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -8,6 +8,7 @@
- #include <linux/cpu.h>
- #include <linux/cpufreq.h>
- #include <linux/cpumask.h>
-+#include <linux/minmax.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_platform.h>
-@@ -15,8 +16,6 @@
- #include <linux/pm_opp.h>
- #include <linux/regulator/consumer.h>
-
--#define VOLT_TOL (10000)
--
- struct mtk_cpufreq_platform_data {
- int min_volt_shift;
- int max_volt_shift;
-@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- bool need_voltage_tracking;
- int pre_vproc;
- const struct mtk_cpufreq_platform_data *soc_data;
-+ int vtrack_max;
- };
-
- static struct platform_device *cpufreq_pdev;
-@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(
- struct regulator *proc_reg = info->proc_reg;
- struct regulator *sram_reg = info->sram_reg;
- int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
-+ int retry = info->vtrack_max;
-
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
-@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
-- /* Vsram should not exceed the maximum allowed voltage of SoC. */
-- new_vsram = min(new_vproc + soc_data->min_volt_shift,
-- soc_data->sram_max_volt);
--
-- if (pre_vproc < new_vproc) {
-- /*
-- * When scaling up voltages, Vsram and Vproc scale up step
-- * by step. At each step, set Vsram to (Vproc + 200mV) first,
-- * then set Vproc to (Vsram - 100mV).
-- * Keep doing it until Vsram and Vproc hit target voltages.
-- */
-- do {
-- pre_vsram = regulator_get_voltage(sram_reg);
-- if (pre_vsram < 0) {
-- dev_err(info->cpu_dev,
-- "invalid Vsram value: %d\n", pre_vsram);
-- return pre_vsram;
-- }
-- pre_vproc = regulator_get_voltage(proc_reg);
-- if (pre_vproc < 0) {
-- dev_err(info->cpu_dev,
-- "invalid Vproc value: %d\n", pre_vproc);
-- return pre_vproc;
-- }
-
-- vsram = min(new_vsram,
-- pre_vproc + soc_data->min_volt_shift);
-+ pre_vsram = regulator_get_voltage(sram_reg);
-+ if (pre_vsram < 0) {
-+ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
-+ return pre_vsram;
-+ }
-
-- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-- vsram = soc_data->sram_max_volt;
-+ new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
-+ soc_data->sram_min_volt, soc_data->sram_max_volt);
-+
-+ do {
-+ if (pre_vproc <= new_vproc) {
-+ vsram = clamp(pre_vproc + soc_data->max_volt_shift,
-+ soc_data->sram_min_volt, new_vsram);
-+ ret = regulator_set_voltage(sram_reg, vsram,
-+ soc_data->sram_max_volt);
-
-- /*
-- * If the target Vsram hits the maximum voltage,
-- * try to set the exact voltage value first.
-- */
-- ret = regulator_set_voltage(sram_reg, vsram,
-- vsram);
-- if (ret)
-- ret = regulator_set_voltage(sram_reg,
-- vsram - VOLT_TOL,
-- vsram);
-+ if (ret)
-+ return ret;
-
-+ if (vsram == soc_data->sram_max_volt ||
-+ new_vsram == soc_data->sram_min_volt)
- vproc = new_vproc;
-- } else {
-- ret = regulator_set_voltage(sram_reg, vsram,
-- vsram + VOLT_TOL);
--
-+ else
- vproc = vsram - soc_data->min_volt_shift;
-- }
-- if (ret)
-- return ret;
-
- ret = regulator_set_voltage(proc_reg, vproc,
-- vproc + VOLT_TOL);
-+ soc_data->proc_max_volt);
- if (ret) {
- regulator_set_voltage(sram_reg, pre_vsram,
-- pre_vsram);
-+ soc_data->sram_max_volt);
- return ret;
- }
-- } while (vproc < new_vproc || vsram < new_vsram);
-- } else if (pre_vproc > new_vproc) {
-- /*
-- * When scaling down voltages, Vsram and Vproc scale down step
-- * by step. At each step, set Vproc to (Vsram - 200mV) first,
-- * then set Vproc to (Vproc + 100mV).
-- * Keep doing it until Vsram and Vproc hit target voltages.
-- */
-- do {
-- pre_vproc = regulator_get_voltage(proc_reg);
-- if (pre_vproc < 0) {
-- dev_err(info->cpu_dev,
-- "invalid Vproc value: %d\n", pre_vproc);
-- return pre_vproc;
-- }
-- pre_vsram = regulator_get_voltage(sram_reg);
-- if (pre_vsram < 0) {
-- dev_err(info->cpu_dev,
-- "invalid Vsram value: %d\n", pre_vsram);
-- return pre_vsram;
-- }
--
-+ } else if (pre_vproc > new_vproc) {
- vproc = max(new_vproc,
- pre_vsram - soc_data->max_volt_shift);
- ret = regulator_set_voltage(proc_reg, vproc,
-- vproc + VOLT_TOL);
-+ soc_data->proc_max_volt);
- if (ret)
- return ret;
-
-@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(
- vsram = max(new_vsram,
- vproc + soc_data->min_volt_shift);
-
-- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
-- vsram = soc_data->sram_max_volt;
--
-- /*
-- * If the target Vsram hits the maximum voltage,
-- * try to set the exact voltage value first.
-- */
-- ret = regulator_set_voltage(sram_reg, vsram,
-- vsram);
-- if (ret)
-- ret = regulator_set_voltage(sram_reg,
-- vsram - VOLT_TOL,
-- vsram);
-- } else {
-- ret = regulator_set_voltage(sram_reg, vsram,
-- vsram + VOLT_TOL);
-- }
--
-+ ret = regulator_set_voltage(sram_reg, vsram,
-+ soc_data->sram_max_volt);
- if (ret) {
- regulator_set_voltage(proc_reg, pre_vproc,
-- pre_vproc);
-+ soc_data->proc_max_volt);
- return ret;
- }
-- } while (vproc > new_vproc + VOLT_TOL ||
-- vsram > new_vsram + VOLT_TOL);
-- }
-+ }
-+
-+ pre_vproc = vproc;
-+ pre_vsram = vsram;
-+
-+ if (--retry < 0) {
-+ dev_err(info->cpu_dev,
-+ "over loop count, failed to set voltage\n");
-+ return -EINVAL;
-+ }
-+ } while (vproc != new_vproc || vsram != new_vsram);
-
- return 0;
- }
-@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct
- * If the new voltage or the intermediate voltage is higher than the
- * current voltage, scale up voltage first.
- */
-- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
-- if (pre_vproc < target_vproc) {
-+ target_vproc = max(inter_vproc, vproc);
-+ if (pre_vproc <= target_vproc) {
- ret = mtk_cpufreq_set_voltage(info, target_vproc);
- if (ret) {
- dev_err(cpu_dev,
-@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct
- */
- info->need_voltage_tracking = (info->sram_reg != NULL);
-
-+ /*
-+ * We assume min voltage is 0 and tracking target voltage using
-+ * min_volt_shift for each iteration.
-+ * The vtrack_max is 3 times of expeted iteration count.
-+ */
-+ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
-+ info->soc_data->proc_max_volt),
-+ info->soc_data->min_volt_shift);
-+
- return 0;
-
- out_disable_inter_clock:
+++ /dev/null
-From 01be227eff7e5fc01f7c8de8f6daddd5fb17ddd1 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:21 +0800
-Subject: [PATCH 11/21] cpufreq: mediatek: Add opp notification support
-
-From this opp notifier, cpufreq should listen to opp notification and do
-proper actions when receiving events of disable and voltage adjustment.
-
-One of the user for this opp notifier is MediaTek SVS.
-The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
-suitable SVS bank voltages to OPP voltage table.
-
-Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[ Viresh: Renamed opp_freq as current_freq and moved its initialization ]
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 90 +++++++++++++++++++++++++++---
- 1 file changed, 82 insertions(+), 8 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
- int intermediate_voltage;
- bool need_voltage_tracking;
- int pre_vproc;
-+ /* Avoid race condition for regulators between notify and policy */
-+ struct mutex reg_lock;
-+ struct notifier_block opp_nb;
-+ unsigned int opp_cpu;
-+ unsigned long current_freq;
- const struct mtk_cpufreq_platform_data *soc_data;
- int vtrack_max;
- };
-@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
-
- pre_freq_hz = clk_get_rate(cpu_clk);
-
-+ mutex_lock(&info->reg_lock);
-+
- if (unlikely(info->pre_vproc <= 0))
- pre_vproc = regulator_get_voltage(info->proc_reg);
- else
-@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
- dev_err(cpu_dev,
- "cpu%d: failed to scale up voltage!\n", policy->cpu);
- mtk_cpufreq_set_voltage(info, pre_vproc);
-- return ret;
-+ goto out;
- }
- }
-
-@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
- dev_err(cpu_dev,
- "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- mtk_cpufreq_set_voltage(info, pre_vproc);
-- WARN_ON(1);
-- return ret;
-+ goto out;
- }
-
- /* Set the original PLL to target rate. */
-@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
- "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
- clk_set_parent(cpu_clk, armpll);
- mtk_cpufreq_set_voltage(info, pre_vproc);
-- return ret;
-+ goto out;
- }
-
- /* Set parent of CPU clock back to the original PLL. */
-@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
- dev_err(cpu_dev,
- "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
- mtk_cpufreq_set_voltage(info, inter_vproc);
-- WARN_ON(1);
-- return ret;
-+ goto out;
- }
-
- /*
-@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
- clk_set_parent(cpu_clk, info->inter_clk);
- clk_set_rate(armpll, pre_freq_hz);
- clk_set_parent(cpu_clk, armpll);
-- return ret;
-+ goto out;
- }
- }
-
-- return 0;
-+ info->current_freq = freq_hz;
-+
-+out:
-+ mutex_unlock(&info->reg_lock);
-+
-+ return ret;
- }
-
- #define DYNAMIC_POWER "dynamic-power-coefficient"
-
-+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
-+ unsigned long event, void *data)
-+{
-+ struct dev_pm_opp *opp = data;
-+ struct dev_pm_opp *new_opp;
-+ struct mtk_cpu_dvfs_info *info;
-+ unsigned long freq, volt;
-+ struct cpufreq_policy *policy;
-+ int ret = 0;
-+
-+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
-+
-+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
-+ freq = dev_pm_opp_get_freq(opp);
-+
-+ mutex_lock(&info->reg_lock);
-+ if (info->current_freq == freq) {
-+ volt = dev_pm_opp_get_voltage(opp);
-+ ret = mtk_cpufreq_set_voltage(info, volt);
-+ if (ret)
-+ dev_err(info->cpu_dev,
-+ "failed to scale voltage: %d\n", ret);
-+ }
-+ mutex_unlock(&info->reg_lock);
-+ } else if (event == OPP_EVENT_DISABLE) {
-+ freq = dev_pm_opp_get_freq(opp);
-+
-+ /* case of current opp item is disabled */
-+ if (info->current_freq == freq) {
-+ freq = 1;
-+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
-+ &freq);
-+ if (IS_ERR(new_opp)) {
-+ dev_err(info->cpu_dev,
-+ "all opp items are disabled\n");
-+ ret = PTR_ERR(new_opp);
-+ return notifier_from_errno(ret);
-+ }
-+
-+ dev_pm_opp_put(new_opp);
-+ policy = cpufreq_cpu_get(info->opp_cpu);
-+ if (policy) {
-+ cpufreq_driver_target(policy, freq / 1000,
-+ CPUFREQ_RELATION_L);
-+ cpufreq_cpu_put(policy);
-+ }
-+ }
-+ }
-+
-+ return notifier_from_errno(ret);
-+}
-+
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- struct device *cpu_dev;
-@@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct
- info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
- dev_pm_opp_put(opp);
-
-+ mutex_init(&info->reg_lock);
-+ info->current_freq = clk_get_rate(info->cpu_clk);
-+
-+ info->opp_cpu = cpu;
-+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
-+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
-+ if (ret) {
-+ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
-+ goto out_disable_inter_clock;
-+ }
-+
- /*
- * If SRAM regulator is present, software "voltage tracking" is needed
- * for this CPU power domain.
-@@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(st
- }
-
- dev_pm_opp_of_cpumask_remove_table(&info->cpus);
-+ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
- }
-
- static int mtk_cpufreq_init(struct cpufreq_policy *policy)
+++ /dev/null
-From 6a1bd7cf4ed7a1948f564aaf16d34b7352c0029b Mon Sep 17 00:00:00 2001
-From: Wan Jiabing <wanjiabing@vivo.com>
-Date: Tue, 10 May 2022 17:05:31 +0800
-Subject: [PATCH 12/21] cpufreq: mediatek: Fix potential deadlock problem in
- mtk_cpufreq_set_target
-
-Fix following coccichek error:
-./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line
-./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line
-
-mutex_lock is acquired but not released before return.
-Use 'goto out' to help releasing the mutex_lock.
-
-Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support")
-Signed-off-by: Wan Jiabing <wanjiabing@vivo.com>
-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct
-
- if (pre_vproc < 0) {
- dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc);
-- return pre_vproc;
-+ ret = pre_vproc;
-+ goto out;
- }
-
- freq_hz = freq_table[index].frequency * 1000;
-@@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct
- if (IS_ERR(opp)) {
- dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n",
- policy->cpu, freq_hz);
-- return PTR_ERR(opp);
-+ ret = PTR_ERR(opp);
-+ goto out;
- }
- vproc = dev_pm_opp_get_voltage(opp);
- dev_pm_opp_put(opp);
+++ /dev/null
-From 15aaf74fb734a3e69b10d00b97b322711b81e222 Mon Sep 17 00:00:00 2001
-From: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Date: Thu, 5 May 2022 19:52:22 +0800
-Subject: [PATCH 13/21] cpufreq: mediatek: Link CCI device to CPU
-
-In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
-supplies. Cpufreq needs to check if CCI devfreq exists and wait until
-CCI devfreq ready before scaling frequency.
-
-Before CCI devfreq is ready, we record the voltage when booting to
-kernel and use the max(cpu target voltage, booting voltage) to
-prevent cpufreq adjust to the lower voltage which will cause the CCI
-crash because of high frequency and low voltage.
-
-- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
- DVFS when CCI is ready.
-- Add platform data for MT8183.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Kevin Hilman <khilman@baylibre.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++-
- 1 file changed, 81 insertions(+), 1 deletion(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data {
- int proc_max_volt;
- int sram_min_volt;
- int sram_max_volt;
-+ bool ccifreq_supported;
- };
-
- /*
-@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data {
- struct mtk_cpu_dvfs_info {
- struct cpumask cpus;
- struct device *cpu_dev;
-+ struct device *cci_dev;
- struct regulator *proc_reg;
- struct regulator *sram_reg;
- struct clk *cpu_clk;
-@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info {
- struct list_head list_head;
- int intermediate_voltage;
- bool need_voltage_tracking;
-+ int vproc_on_boot;
- int pre_vproc;
- /* Avoid race condition for regulators between notify and policy */
- struct mutex reg_lock;
-@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info {
- unsigned long current_freq;
- const struct mtk_cpufreq_platform_data *soc_data;
- int vtrack_max;
-+ bool ccifreq_bound;
- };
-
- static struct platform_device *cpufreq_pdev;
-@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struc
- return ret;
- }
-
-+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
-+{
-+ struct device_link *sup_link;
-+
-+ if (info->ccifreq_bound)
-+ return true;
-+
-+ sup_link = device_link_add(info->cpu_dev, info->cci_dev,
-+ DL_FLAG_AUTOREMOVE_CONSUMER);
-+ if (!sup_link) {
-+ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
-+ return false;
-+ }
-+
-+ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
-+ return false;
-+
-+ info->ccifreq_bound = true;
-+
-+ return true;
-+}
-+
- static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
- unsigned int index)
- {
-@@ -213,6 +239,14 @@ static int mtk_cpufreq_set_target(struct
- dev_pm_opp_put(opp);
-
- /*
-+ * If MediaTek cci is supported but is not ready, we will use the value
-+ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
-+ * low voltage crash.
-+ */
-+ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
-+ vproc = max(vproc, info->vproc_on_boot);
-+
-+ /*
- * If the new voltage or the intermediate voltage is higher than the
- * current voltage, scale up voltage first.
- */
-@@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(stru
- return notifier_from_errno(ret);
- }
-
-+static struct device *of_get_cci(struct device *cpu_dev)
-+{
-+ struct device_node *np;
-+ struct platform_device *pdev;
-+
-+ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
-+ if (IS_ERR_OR_NULL(np))
-+ return NULL;
-+
-+ pdev = of_find_device_by_node(np);
-+ of_node_put(np);
-+ if (IS_ERR_OR_NULL(pdev))
-+ return NULL;
-+
-+ return &pdev->dev;
-+}
-+
- static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
- {
- struct device *cpu_dev;
-@@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct
- }
- info->cpu_dev = cpu_dev;
-
-+ info->ccifreq_bound = false;
-+ if (info->soc_data->ccifreq_supported) {
-+ info->cci_dev = of_get_cci(info->cpu_dev);
-+ if (IS_ERR_OR_NULL(info->cci_dev)) {
-+ ret = PTR_ERR(info->cci_dev);
-+ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
-+ return -ENODEV;
-+ }
-+ }
-+
- info->cpu_clk = clk_get(cpu_dev, "cpu");
- if (IS_ERR(info->cpu_clk)) {
- ret = PTR_ERR(info->cpu_clk);
-@@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct
- if (ret)
- goto out_disable_mux_clock;
-
-+ if (info->soc_data->ccifreq_supported) {
-+ info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
-+ if (info->vproc_on_boot < 0) {
-+ dev_err(info->cpu_dev,
-+ "invalid Vproc value: %d\n", info->vproc_on_boot);
-+ goto out_disable_inter_clock;
-+ }
-+ }
-+
- /* Search a safe voltage for intermediate frequency. */
- rate = clk_get_rate(info->inter_clk);
- opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
-@@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform
- .proc_max_volt = 1150000,
- .sram_min_volt = 0,
- .sram_max_volt = 1150000,
-+ .ccifreq_supported = false,
-+};
-+
-+static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
-+ .min_volt_shift = 100000,
-+ .max_volt_shift = 200000,
-+ .proc_max_volt = 1150000,
-+ .sram_min_volt = 0,
-+ .sram_max_volt = 1150000,
-+ .ccifreq_supported = true,
- };
-
- /* List of machines supported by this driver */
-@@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpu
- { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
-- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
- { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- { }
+++ /dev/null
-From b6be0baa6615afc65c3963adab674e36af1d4d5f Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Thu, 5 May 2022 19:52:23 +0800
-Subject: [PATCH 14/21] cpufreq: mediatek: Add support for MT8186
-
-The platform data of MT8186 is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform
- .ccifreq_supported = true,
- };
-
-+static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
-+ .min_volt_shift = 100000,
-+ .max_volt_shift = 250000,
-+ .proc_max_volt = 1118750,
-+ .sram_min_volt = 850000,
-+ .sram_max_volt = 1118750,
-+ .ccifreq_supported = true,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
-@@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpu
- { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
-+ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
- { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
- { }
+++ /dev/null
-From 75d19b24aa3203d6c78e4c431c2cc07157ce12fe Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 13 Jul 2022 13:15:36 +0200
-Subject: [PATCH 15/21] cpufreq: mediatek: Handle sram regulator probe deferral
-
-If the regulator_get_optional() call for the SRAM regulator returns
-a probe deferral, we must bail out and retry probing later: failing
-to do this will produce unstabilities on platforms requiring the
-handling for this regulator.
-
-Fixes: ffa7bdf7f344 ("cpufreq: mediatek: Make sram regulator optional")
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -439,9 +439,13 @@ static int mtk_cpu_dvfs_info_init(struct
-
- /* Both presence and absence of sram regulator are valid cases. */
- info->sram_reg = regulator_get_optional(cpu_dev, "sram");
-- if (IS_ERR(info->sram_reg))
-+ if (IS_ERR(info->sram_reg)) {
-+ ret = PTR_ERR(info->sram_reg);
-+ if (ret == -EPROBE_DEFER)
-+ goto out_free_resources;
-+
- info->sram_reg = NULL;
-- else {
-+ } else {
- ret = regulator_enable(info->sram_reg);
- if (ret) {
- dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
+++ /dev/null
-From dd1174c21dacacd6c0129c1dabc5decad35c02c2 Mon Sep 17 00:00:00 2001
-From: Yang Yingliang <yangyingliang@huawei.com>
-Date: Tue, 17 May 2022 21:34:50 +0800
-Subject: [PATCH 16/21] cpufreq: mediatek: fix error return code in
- mtk_cpu_dvfs_info_init()
-
-If regulator_get_voltage() fails, it should return the error code in
-mtk_cpu_dvfs_info_init().
-
-Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU")
-Reported-by: Hulk Robot <hulkci@huawei.com>
-Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -478,6 +478,7 @@ static int mtk_cpu_dvfs_info_init(struct
- if (info->soc_data->ccifreq_supported) {
- info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
- if (info->vproc_on_boot < 0) {
-+ ret = info->vproc_on_boot;
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", info->vproc_on_boot);
- goto out_disable_inter_clock;
+++ /dev/null
-From 230a74d459244411db91bfd678f17fcf7aedfcd0 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:27 +0800
-Subject: [PATCH 17/21] cpufreq: mediatek: fix passing zero to 'PTR_ERR'
-
-In order to prevent passing zero to 'PTR_ERR' in
-mtk_cpu_dvfs_info_init(), we fix the return value of of_get_cci() using
-error pointer by explicitly casting error number.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: 0daa47325bae ("cpufreq: mediatek: Link CCI device to CPU")
-Reported-by: Dan Carpenter <error27@gmail.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -373,13 +373,13 @@ static struct device *of_get_cci(struct
- struct platform_device *pdev;
-
- np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
-- if (IS_ERR_OR_NULL(np))
-- return NULL;
-+ if (!np)
-+ return ERR_PTR(-ENODEV);
-
- pdev = of_find_device_by_node(np);
- of_node_put(np);
-- if (IS_ERR_OR_NULL(pdev))
-- return NULL;
-+ if (!pdev)
-+ return ERR_PTR(-ENODEV);
-
- return &pdev->dev;
- }
-@@ -401,7 +401,7 @@ static int mtk_cpu_dvfs_info_init(struct
- info->ccifreq_bound = false;
- if (info->soc_data->ccifreq_supported) {
- info->cci_dev = of_get_cci(info->cpu_dev);
-- if (IS_ERR_OR_NULL(info->cci_dev)) {
-+ if (IS_ERR(info->cci_dev)) {
- ret = PTR_ERR(info->cci_dev);
- dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
- return -ENODEV;
+++ /dev/null
-From fced531b7c7e18192e7982637c8e8f20c29aad64 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:28 +0800
-Subject: [PATCH 18/21] cpufreq: mediatek: fix KP caused by handler usage after
- regulator_put/clk_put
-
-Any kind of failure in mtk_cpu_dvfs_info_init() will lead to calling
-regulator_put() or clk_put() and the KP will occur since the regulator/clk
-handlers are used after released in mtk_cpu_dvfs_info_release().
-
-To prevent the usage after regulator_put()/clk_put(), the regulator/clk
-handlers are addressed in a way of "Free the Last Thing Style".
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: 4b9ceb757bbb ("cpufreq: mediatek: Enable clocks and regulators")
-Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Suggested-by: Dan Carpenter <error27@gmail.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 62 +++++++++++++++---------------
- 1 file changed, 30 insertions(+), 32 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -420,7 +420,7 @@ static int mtk_cpu_dvfs_info_init(struct
- ret = PTR_ERR(info->inter_clk);
- dev_err_probe(cpu_dev, ret,
- "cpu%d: failed to get intermediate clk\n", cpu);
-- goto out_free_resources;
-+ goto out_free_mux_clock;
- }
-
- info->proc_reg = regulator_get_optional(cpu_dev, "proc");
-@@ -428,13 +428,13 @@ static int mtk_cpu_dvfs_info_init(struct
- ret = PTR_ERR(info->proc_reg);
- dev_err_probe(cpu_dev, ret,
- "cpu%d: failed to get proc regulator\n", cpu);
-- goto out_free_resources;
-+ goto out_free_inter_clock;
- }
-
- ret = regulator_enable(info->proc_reg);
- if (ret) {
- dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu);
-- goto out_free_resources;
-+ goto out_free_proc_reg;
- }
-
- /* Both presence and absence of sram regulator are valid cases. */
-@@ -442,14 +442,14 @@ static int mtk_cpu_dvfs_info_init(struct
- if (IS_ERR(info->sram_reg)) {
- ret = PTR_ERR(info->sram_reg);
- if (ret == -EPROBE_DEFER)
-- goto out_free_resources;
-+ goto out_disable_proc_reg;
-
- info->sram_reg = NULL;
- } else {
- ret = regulator_enable(info->sram_reg);
- if (ret) {
- dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu);
-- goto out_free_resources;
-+ goto out_free_sram_reg;
- }
- }
-
-@@ -458,13 +458,13 @@ static int mtk_cpu_dvfs_info_init(struct
- if (ret) {
- dev_err(cpu_dev,
- "cpu%d: failed to get OPP-sharing information\n", cpu);
-- goto out_free_resources;
-+ goto out_disable_sram_reg;
- }
-
- ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
- if (ret) {
- dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu);
-- goto out_free_resources;
-+ goto out_disable_sram_reg;
- }
-
- ret = clk_prepare_enable(info->cpu_clk);
-@@ -533,43 +533,41 @@ out_disable_mux_clock:
- out_free_opp_table:
- dev_pm_opp_of_cpumask_remove_table(&info->cpus);
-
--out_free_resources:
-- if (regulator_is_enabled(info->proc_reg))
-- regulator_disable(info->proc_reg);
-- if (info->sram_reg && regulator_is_enabled(info->sram_reg))
-+out_disable_sram_reg:
-+ if (info->sram_reg)
- regulator_disable(info->sram_reg);
-
-- if (!IS_ERR(info->proc_reg))
-- regulator_put(info->proc_reg);
-- if (!IS_ERR(info->sram_reg))
-+out_free_sram_reg:
-+ if (info->sram_reg)
- regulator_put(info->sram_reg);
-- if (!IS_ERR(info->cpu_clk))
-- clk_put(info->cpu_clk);
-- if (!IS_ERR(info->inter_clk))
-- clk_put(info->inter_clk);
-+
-+out_disable_proc_reg:
-+ regulator_disable(info->proc_reg);
-+
-+out_free_proc_reg:
-+ regulator_put(info->proc_reg);
-+
-+out_free_inter_clock:
-+ clk_put(info->inter_clk);
-+
-+out_free_mux_clock:
-+ clk_put(info->cpu_clk);
-
- return ret;
- }
-
- static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
- {
-- if (!IS_ERR(info->proc_reg)) {
-- regulator_disable(info->proc_reg);
-- regulator_put(info->proc_reg);
-- }
-- if (!IS_ERR(info->sram_reg)) {
-+ regulator_disable(info->proc_reg);
-+ regulator_put(info->proc_reg);
-+ if (info->sram_reg) {
- regulator_disable(info->sram_reg);
- regulator_put(info->sram_reg);
- }
-- if (!IS_ERR(info->cpu_clk)) {
-- clk_disable_unprepare(info->cpu_clk);
-- clk_put(info->cpu_clk);
-- }
-- if (!IS_ERR(info->inter_clk)) {
-- clk_disable_unprepare(info->inter_clk);
-- clk_put(info->inter_clk);
-- }
--
-+ clk_disable_unprepare(info->cpu_clk);
-+ clk_put(info->cpu_clk);
-+ clk_disable_unprepare(info->inter_clk);
-+ clk_put(info->inter_clk);
- dev_pm_opp_of_cpumask_remove_table(&info->cpus);
- dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
- }
+++ /dev/null
-From 24bc42a2d44cb821818717a5c607270921ec5d20 Mon Sep 17 00:00:00 2001
-From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Date: Fri, 24 Mar 2023 18:11:29 +0800
-Subject: [PATCH 19/21] cpufreq: mediatek: raise proc/sram max voltage for
- MT8516
-
-Since the upper boundary of proc/sram voltage of MT8516 is 1300 mV,
-which is greater than the value of MT2701 1150 mV, we fix it by adding
-the corresponding platform data and specify proc/sram_max_volt to
-support MT8516.
-
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data")
-Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-Reported-by: Nick Hainke <vincent@systemli.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -711,20 +711,29 @@ static const struct mtk_cpufreq_platform
- .ccifreq_supported = true,
- };
-
-+static const struct mtk_cpufreq_platform_data mt8516_platform_data = {
-+ .min_volt_shift = 100000,
-+ .max_volt_shift = 200000,
-+ .proc_max_volt = 1310000,
-+ .sram_min_volt = 0,
-+ .sram_max_volt = 1310000,
-+ .ccifreq_supported = false,
-+};
-+
- /* List of machines supported by this driver */
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-- { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
- { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
- { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
-- { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt8516", .data = &mt8516_platform_data },
- { }
- };
- MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
+++ /dev/null
-From fe6ef09358dc0cfead9d383a8676fbe7a40fcef7 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 24 Mar 2023 18:11:30 +0800
-Subject: [PATCH 20/21] cpufreq: mediatek: Raise proc and sram max voltage for
- MT7622/7623
-
-During the addition of SRAM voltage tracking for CCI scaling, this
-driver got some voltage limits set for the vtrack algorithm: these
-were moved to platform data first, then enforced in a later commit
-6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-using these as max values for the regulator_set_voltage() calls.
-
-In this case, the vsram/vproc constraints for MT7622 and MT7623
-were supposed to be the same as MT2701 (and a number of other SoCs),
-but that turned out to be a mistake because the aforementioned two
-SoCs' maximum voltage for both VPROC and VPROC_SRAM is 1.36V.
-
-Fix that by adding new platform data for MT7622/7623 declaring the
-right {proc,sram}_max_volt parameter.
-
-Fixes: ead858bd128d ("cpufreq: mediatek: Move voltage limits to platform data")
-Fixes: 6a17b3876bc8 ("cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()")
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/mediatek-cpufreq.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -693,6 +693,15 @@ static const struct mtk_cpufreq_platform
- .ccifreq_supported = false,
- };
-
-+static const struct mtk_cpufreq_platform_data mt7622_platform_data = {
-+ .min_volt_shift = 100000,
-+ .max_volt_shift = 200000,
-+ .proc_max_volt = 1360000,
-+ .sram_min_volt = 0,
-+ .sram_max_volt = 1360000,
-+ .ccifreq_supported = false,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- .min_volt_shift = 100000,
- .max_volt_shift = 200000,
-@@ -724,8 +733,8 @@ static const struct mtk_cpufreq_platform
- static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
-- { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
-- { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
-+ { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
-+ { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data },
- { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
+++ /dev/null
-From f6ba5e17bee38f8ffe118c47fbfef3cf90eb87ff Mon Sep 17 00:00:00 2001
-From: "Mingming.Su" <Mingming.Su@mediatek.com>
-Date: Wed, 30 Jun 2021 16:59:32 +0800
-Subject: [PATCH] mt7986: trng: add rng support
-
-1. Add trng compatible name for MT7986
-2. Fix mtk_rng_wait_ready() function
-
-Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
----
- drivers/char/hw_random/mtk-rng.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/char/hw_random/mtk-rng.c
-+++ b/drivers/char/hw_random/mtk-rng.c
-@@ -22,7 +22,7 @@
- #define RNG_AUTOSUSPEND_TIMEOUT 100
-
- #define USEC_POLL 2
--#define TIMEOUT_POLL 20
-+#define TIMEOUT_POLL 60
-
- #define RNG_CTRL 0x00
- #define RNG_EN BIT(0)
-@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
- readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
- ready & RNG_READY, USEC_POLL,
- TIMEOUT_POLL);
-- return !!ready;
-+ return !!(ready & RNG_READY);
- }
-
- static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
- #endif /* CONFIG_PM */
-
- static const struct of_device_id mtk_rng_match[] = {
-+ { .compatible = "mediatek,mt7986-rng" },
- { .compatible = "mediatek,mt7623-rng" },
- {},
- };
--- /dev/null
+From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001
+From: "Mingming.Su" <Mingming.Su@mediatek.com>
+Date: Sat, 8 Oct 2022 18:45:53 +0200
+Subject: [PATCH] hwrng: mtk - add mt7986 support
+
+1. Add trng compatible name for MT7986
+2. Fix mtk_rng_wait_ready() function
+
+Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ drivers/char/hw_random/mtk-rng.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/char/hw_random/mtk-rng.c
++++ b/drivers/char/hw_random/mtk-rng.c
+@@ -22,7 +22,7 @@
+ #define RNG_AUTOSUSPEND_TIMEOUT 100
+
+ #define USEC_POLL 2
+-#define TIMEOUT_POLL 20
++#define TIMEOUT_POLL 60
+
+ #define RNG_CTRL 0x00
+ #define RNG_EN BIT(0)
+@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
+ readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
+ ready & RNG_READY, USEC_POLL,
+ TIMEOUT_POLL);
+- return !!ready;
++ return !!(ready & RNG_READY);
+ }
+
+ static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
+ #endif /* CONFIG_PM */
+
+ static const struct of_device_id mtk_rng_match[] = {
++ { .compatible = "mediatek,mt7986-rng" },
+ { .compatible = "mediatek,mt7623-rng" },
+ {},
+ };
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
-@@ -85,6 +85,7 @@ struct serial8250_config {
- #define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks:
+@@ -86,6 +86,7 @@ struct serial8250_config {
* STOP PARITY EPAR SPAR WLEN5 WLEN6
*/
-+#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */
+ #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
++#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */
#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -289,7 +289,7 @@ static const struct serial8250_config ua
+@@ -287,7 +287,7 @@ static const struct serial8250_config ua
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
},
[PORT_NPCM] = {
.name = "Nuvoton 16550",
-@@ -2766,6 +2766,11 @@ serial8250_do_set_termios(struct uart_po
+@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po
unsigned long flags;
unsigned int baud, quot, frac = 0;
+++ /dev/null
-From: David Bauer <mail@david-bauer.net>
-To: linux-mtd@lists.infradead.org
-Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV
-Date: Sat, 13 Feb 2021 16:10:47 +0100
-
-The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K
-sectors as well as block protection and Dual-/Quad-read.
-
-Tested on: Ubiquiti UniFi 6 LR
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/mtd/spi-nor/winbond.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/spi-nor/winbond.c
-+++ b/drivers/mtd/spi-nor/winbond.c
-@@ -98,6 +98,10 @@ static const struct flash_info winbond_p
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024,
-+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ |
-+ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
-+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
- { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
- SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
- { "w25q512jvq", INFO(0xef4020, 0, 64 * 1024, 1024,
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
-@@ -142,6 +141,8 @@ struct mtk_spi {
+@@ -171,6 +170,8 @@ struct mtk_spi {
struct device *dev;
dma_addr_t tx_dma;
dma_addr_t rx_dma;
};
static const struct mtk_spi_compatible mtk_common_compat;
-@@ -187,15 +188,6 @@ static const struct mtk_spi_compatible m
+@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
.no_need_unprepare = true,
};
static const struct of_device_id mtk_spi_of_match[] = {
{ .compatible = "mediatek,spi-ipm",
.data = (void *)&mtk_ipm_compat,
-@@ -323,7 +315,6 @@ static int mtk_spi_hw_init(struct spi_ma
+@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
{
u16 cpha, cpol;
u32 reg_val;
struct mtk_spi *mdata = spi_master_get_devdata(master);
cpha = spi->mode & SPI_CPHA ? 1 : 0;
-@@ -373,7 +364,7 @@ static int mtk_spi_hw_init(struct spi_ma
+@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
else
reg_val &= ~SPI_CMD_CS_POL;
reg_val |= SPI_CMD_SAMPLE_SEL;
else
reg_val &= ~SPI_CMD_SAMPLE_SEL;
-@@ -400,20 +391,20 @@ static int mtk_spi_hw_init(struct spi_ma
+@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
if (mdata->dev_comp->ipm_design) {
reg_val = readl(mdata->base + SPI_CMD_REG);
reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
writel(reg_val, mdata->base + SPI_CFG1_REG);
}
-@@ -700,9 +691,6 @@ static int mtk_spi_setup(struct spi_devi
+@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
{
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
/* CS de-asserted, gpiolib will handle inversion */
gpiod_direction_output(spi->cs_gpiod, 0);
-@@ -1115,6 +1103,10 @@ static int mtk_spi_probe(struct platform
+@@ -1138,6 +1126,10 @@ static int mtk_spi_probe(struct platform
mdata = spi_master_get_devdata(master);
- mdata->dev_comp = of_id->data;
+ mdata->dev_comp = device_get_match_data(dev);
+ /* Set device configs to default first. Calibrate it later. */
+ mdata->sample_sel = 0;
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
-@@ -1234,6 +1234,70 @@ static int spi_transfer_wait(struct spi_
+@@ -1374,6 +1374,70 @@ static int spi_transfer_wait(struct spi_
return 0;
}
static void _spi_transfer_delay_ns(u32 ns)
{
if (!ns)
-@@ -2021,6 +2085,75 @@ void spi_flush_queue(struct spi_controll
+@@ -2208,6 +2272,75 @@ void spi_flush_queue(struct spi_controll
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_OF)
static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
struct device_node *nc)
{
-@@ -2139,6 +2272,10 @@ of_register_spi_device(struct spi_contro
+@@ -2326,6 +2459,10 @@ of_register_spi_device(struct spi_contro
if (rc)
goto err_out;
spi->dev.of_node = nc;
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
-@@ -290,6 +290,40 @@ struct spi_driver {
+@@ -298,6 +298,40 @@ struct spi_driver {
struct device_driver driver;
};
static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
{
return drv ? container_of(drv, struct spi_driver, driver) : NULL;
-@@ -665,6 +699,11 @@ struct spi_controller {
+@@ -682,6 +716,11 @@ struct spi_controller {
void *dummy_rx;
void *dummy_tx;
int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
/*
-@@ -1477,6 +1516,9 @@ spi_register_board_info(struct spi_board
+@@ -1489,6 +1528,9 @@ spi_register_board_info(struct spi_board
{ return 0; }
#endif
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
-@@ -410,6 +410,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
+@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
}
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
-@@ -800,6 +800,21 @@ static irqreturn_t mtk_spi_interrupt(int
+@@ -832,6 +832,21 @@ static irqreturn_t mtk_spi_interrupt(int
return IRQ_HANDLED;
}
static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
struct spi_mem_op *op)
{
-@@ -1092,6 +1107,7 @@ static int mtk_spi_probe(struct platform
+@@ -1122,6 +1137,7 @@ static int mtk_spi_probe(struct platform
master->setup = mtk_spi_setup;
master->set_cs_timing = mtk_spi_set_hw_cs_timing;
master->use_gpio_descriptors = true;
+ master->append_caldata = mtk_spi_append_caldata;
- of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
- if (!of_id) {
+ mdata = spi_master_get_devdata(master);
+ mdata->dev_comp = device_get_match_data(dev);
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
-@@ -977,6 +977,56 @@ static int spinand_manufacturer_match(st
+@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st
return -ENOTSUPP;
}
static int spinand_id_detect(struct spinand_device *spinand)
{
u8 *id = spinand->id.data;
-@@ -1227,6 +1277,10 @@ static int spinand_init(struct spinand_d
+@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d
if (!spinand->scratchbuf)
return -ENOMEM;
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
-@@ -1018,7 +1018,10 @@ int spinand_cal_read(void *priv, u32 *ad
+@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad
if (ret)
return ret;
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -3060,6 +3060,18 @@ static void spi_nor_debugfs_init(struct
- info->id_len, info->id);
+@@ -2899,6 +2899,18 @@ static const struct flash_info *spi_nor_
+ return NULL;
}
+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
const char *name)
{
-@@ -3133,6 +3145,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3002,6 +3014,9 @@ int spi_nor_scan(struct spi_nor *nor, co
if (!nor->bouncebuf)
return -ENOMEM;
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -367,6 +367,12 @@ config ROCKCHIP_PHY
+@@ -382,6 +382,12 @@ config ROCKCHIP_PHY
help
Currently supports the integrated Ethernet PHY.
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+@@ -98,6 +98,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
+++ /dev/null
-From: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Date: Mon, 23 Aug 2021 11:27:59 +0800
-Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
-
-There are two independent PCIe controllers in MT2712 and MT7622
-platform. Each of them should contain an independent MSI domain.
-
-In old dts architecture, MSI domain will be inherited from the root
-bridge, and all of the devices will share the same MSI domain.
-Hence that, the PCIe devices will not work properly if the irq number
-which required is more than 32.
-
-Split the PCIe node for MT2712 and MT7622 platform to comply with
-the hardware design and fix MSI issue.
-
-Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
-Acked-by: Ryder Lee <ryder.lee@mediatek.com>
-Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
-@@ -915,64 +915,67 @@
- };
- };
-
-- pcie: pcie@11700000 {
-+ pcie1: pcie@112ff000 {
- compatible = "mediatek,mt2712-pcie";
- device_type = "pci";
-- reg = <0 0x11700000 0 0x1000>,
-- <0 0x112ff000 0 0x1000>;
-- reg-names = "port0", "port1";
-+ reg = <0 0x112ff000 0 0x1000>;
-+ reg-names = "port1";
-+ linux,pci-domain = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
-- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
-- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
-- <&pericfg CLK_PERI_PCIE0>,
-+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pcie_irq";
-+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
- <&pericfg CLK_PERI_PCIE1>;
-- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
-- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
-- phy-names = "pcie-phy0", "pcie-phy1";
-+ clock-names = "sys_ck1", "ahb_ck1";
-+ phys = <&u3port1 PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy1";
- bus-range = <0x00 0xff>;
-- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
-+ status = "disabled";
-
-- pcie0: pcie@0,0 {
-- device_type = "pci";
-- status = "disabled";
-- reg = <0x0000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+ <0 0 0 2 &pcie_intc1 1>,
-+ <0 0 0 3 &pcie_intc1 2>,
-+ <0 0 0 4 &pcie_intc1 3>;
-+ pcie_intc1: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-- <0 0 0 2 &pcie_intc0 1>,
-- <0 0 0 3 &pcie_intc0 2>,
-- <0 0 0 4 &pcie_intc0 3>;
-- pcie_intc0: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
- };
-+ };
-+
-+ pcie0: pcie@11700000 {
-+ compatible = "mediatek,mt2712-pcie";
-+ device_type = "pci";
-+ reg = <0 0x11700000 0 0x1000>;
-+ reg-names = "port0";
-+ linux,pci-domain = <0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pcie_irq";
-+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
-+ <&pericfg CLK_PERI_PCIE0>;
-+ clock-names = "sys_ck0", "ahb_ck0";
-+ phys = <&u3port0 PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy0";
-+ bus-range = <0x00 0xff>;
-+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+ status = "disabled";
-
-- pcie1: pcie@1,0 {
-- device_type = "pci";
-- status = "disabled";
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+ <0 0 0 2 &pcie_intc0 1>,
-+ <0 0 0 3 &pcie_intc0 2>,
-+ <0 0 0 4 &pcie_intc0 3>;
-+ pcie_intc0: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
- #interrupt-cells = <1>;
-- ranges;
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-- <0 0 0 2 &pcie_intc1 1>,
-- <0 0 0 3 &pcie_intc1 2>,
-- <0 0 0 4 &pcie_intc1 3>;
-- pcie_intc1: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
- };
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -302,18 +302,16 @@
- };
- };
-
--&pcie {
-+&pcie0 {
- pinctrl-names = "default";
-- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+ pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-+};
-
-- pcie@0,0 {
-- status = "okay";
-- };
--
-- pcie@1,0 {
-- status = "okay";
-- };
-+&pcie1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie1_pins>;
-+ status = "okay";
- };
-
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -232,18 +232,16 @@
- };
- };
-
--&pcie {
-+&pcie0 {
- pinctrl-names = "default";
-- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
-+ pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-+};
-
-- pcie@0,0 {
-- status = "okay";
-- };
--
-- pcie@1,0 {
-- status = "okay";
-- };
-+&pcie1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie1_pins>;
-+ status = "okay";
- };
-
- &pio {
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -809,75 +809,83 @@
- #reset-cells = <1>;
- };
-
-- pcie: pcie@1a140000 {
-+ pciecfg: pciecfg@1a140000 {
-+ compatible = "mediatek,generic-pciecfg", "syscon";
-+ reg = <0 0x1a140000 0 0x1000>;
-+ };
-+
-+ pcie0: pcie@1a143000 {
- compatible = "mediatek,mt7622-pcie";
- device_type = "pci";
-- reg = <0 0x1a140000 0 0x1000>,
-- <0 0x1a143000 0 0x1000>,
-- <0 0x1a145000 0 0x1000>;
-- reg-names = "subsys", "port0", "port1";
-+ reg = <0 0x1a143000 0 0x1000>;
-+ reg-names = "port0";
-+ linux,pci-domain = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
-- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
-- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "pcie_irq";
- clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
-- <&pciesys CLK_PCIE_P1_MAC_EN>,
-- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P0_AUX_EN>,
-- <&pciesys CLK_PCIE_P1_AUX_EN>,
- <&pciesys CLK_PCIE_P0_AXI_EN>,
-- <&pciesys CLK_PCIE_P1_AXI_EN>,
- <&pciesys CLK_PCIE_P0_OBFF_EN>,
-- <&pciesys CLK_PCIE_P1_OBFF_EN>,
-- <&pciesys CLK_PCIE_P0_PIPE_EN>,
-- <&pciesys CLK_PCIE_P1_PIPE_EN>;
-- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
-- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
-- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
-+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
-+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
-+ "axi_ck0", "obff_ck0", "pipe_ck0";
-+
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- bus-range = <0x00 0xff>;
-- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
-+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- status = "disabled";
-
-- pcie0: pcie@0,0 {
-- reg = <0x0000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+ <0 0 0 2 &pcie_intc0 1>,
-+ <0 0 0 3 &pcie_intc0 2>,
-+ <0 0 0 4 &pcie_intc0 3>;
-+ pcie_intc0: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
- #interrupt-cells = <1>;
-- ranges;
-- status = "disabled";
--
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-- <0 0 0 2 &pcie_intc0 1>,
-- <0 0 0 3 &pcie_intc0 2>,
-- <0 0 0 4 &pcie_intc0 3>;
-- pcie_intc0: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
- };
-+ };
-
-- pcie1: pcie@1,0 {
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- #interrupt-cells = <1>;
-- ranges;
-- status = "disabled";
-+ pcie1: pcie@1a145000 {
-+ compatible = "mediatek,mt7622-pcie";
-+ device_type = "pci";
-+ reg = <0 0x1a145000 0 0x1000>;
-+ reg-names = "port1";
-+ linux,pci-domain = <1>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "pcie_irq";
-+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
-+ /* designer has connect RC1 with p0_ahb clock */
-+ <&pciesys CLK_PCIE_P0_AHB_EN>,
-+ <&pciesys CLK_PCIE_P1_AUX_EN>,
-+ <&pciesys CLK_PCIE_P1_AXI_EN>,
-+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
-+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
-+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
-+ "axi_ck1", "obff_ck1", "pipe_ck1";
-+
-+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
-+ bus-range = <0x00 0xff>;
-+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
-+ status = "disabled";
-
-- interrupt-map-mask = <0 0 0 7>;
-- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-- <0 0 0 2 &pcie_intc1 1>,
-- <0 0 0 3 &pcie_intc1 2>,
-- <0 0 0 4 &pcie_intc1 3>;
-- pcie_intc1: interrupt-controller {
-- interrupt-controller;
-- #address-cells = <0>;
-- #interrupt-cells = <1>;
-- };
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+ <0 0 0 2 &pcie_intc1 1>,
-+ <0 0 0 3 &pcie_intc1 2>,
-+ <0 0 0 4 &pcie_intc1 3>;
-+ pcie_intc1: interrupt-controller {
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
- };
- };
-
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
*/
- writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
+ msleep(100);
+ /*
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
+++ /dev/null
-From patchwork Thu May 28 06:16:48 2020
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Chuanjia Liu <chuanjia.liu@mediatek.com>
-X-Patchwork-Id: 11574797
-Return-Path:
- <SRS0=ftSA=7K=lists.infradead.org=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@kernel.org>
-Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org
- [172.30.200.123])
- by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30A5E1392
- for <patchwork-linux-mediatek@patchwork.kernel.org>;
- Thu, 28 May 2020 06:29:05 +0000 (UTC)
-Received: from bombadil.infradead.org (bombadil.infradead.org
- [198.137.202.133])
- (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
- (No client certificate requested)
- by mail.kernel.org (Postfix) with ESMTPS id 08B6320721
- for <patchwork-linux-mediatek@patchwork.kernel.org>;
- Thu, 28 May 2020 06:29:05 +0000 (UTC)
-Authentication-Results: mail.kernel.org;
- dkim=pass (2048-bit key) header.d=lists.infradead.org
- header.i=@lists.infradead.org header.b="auhxDafY";
- dkim=fail reason="signature verification failed" (1024-bit key)
- header.d=mediatek.com header.i=@mediatek.com header.b="Kj09Arxb"
-DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 08B6320721
-Authentication-Results: mail.kernel.org;
- dmarc=fail (p=none dis=none) header.from=mediatek.com
-Authentication-Results: mail.kernel.org;
- spf=none
- smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
- d=lists.infradead.org; s=bombadil.20170209; h=Sender:
- Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:
- List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:
- Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:
- Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:
- List-Owner; bh=+QPxF1vlOH7StIZYuXJa3V40x8QVDxCLF9AFXHblB9M=; b=auhxDafYBeaUZO
- aYp2KVO8Aie0v4tYtRwBon7hF+x55JwD78SAxQR2RsSvrlOo9cMYYby+ToUWflVUWQ60FapAl+w+l
- nkEjIOrLBErHwxNOcsD8T5kjyCBMqlz4OMAQYUDNJ3fSugRlGhOtxkjCGd9ebB8N2Rvu6/U8P1A9n
- P15mEQoc+RLonR1+9mBgwTEXErjsraxkimTD4Txsp4IvMs3UdsMkP+r3OT5S/p+Uj6O9ES0h7xIon
- aL79KaVqRLHrfZxnrVwuGiecAiTp8qLy9clHuJU32NA6ZcXH1OnWipKApgp8Ck7ys80WPKaMrat9B
- XuskJ63w13DZAbCVvuGQ==;
-Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org)
- by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux))
- id 1jeC2J-00014n-M9; Thu, 28 May 2020 06:29:03 +0000
-Received: from mailgw02.mediatek.com ([216.200.240.185])
- by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux))
- id 1jeC2H-00013t-Li; Thu, 28 May 2020 06:29:03 +0000
-X-UUID: a4877c1586e64afeb2d6172e10605d2b-20200527
-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
- d=mediatek.com;
- s=dk;
- h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;
- bh=CIwcBFK1x0LbOjDt1BG6/knHFxDHRiqj8ov/jWEZDBY=;
- b=Kj09ArxbnLVTc9bpaVPT3jQrIVjhL87sSYyVF9dFypS976k78Ce9gZd0f4K3zAZbYZHYoQtuyOQ9TOeufQfgD+Cr+j5VR7pTdO2E1iXHFs/eQAz5gAjvjlK01z1JiunrLnn9dvIr6c1gEkjQHny0VpuZ1duxx79jwYusg/Nw6Wc=;
-X-UUID: a4877c1586e64afeb2d6172e10605d2b-20200527
-Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by
- mailgw02.mediatek.com
- (envelope-from <chuanjia.liu@mediatek.com>)
- (musrelay.mediatek.com ESMTP with TLS)
- with ESMTP id 899663677; Wed, 27 May 2020 22:29:21 -0800
-Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by
- MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id
- 15.0.1497.2; Wed, 27 May 2020 23:18:50 -0700
-Received: from mtkcas07.mediatek.inc (172.21.101.84) by
- mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id
- 15.0.1497.2; Thu, 28 May 2020 14:18:54 +0800
-Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc
- (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend
- Transport; Thu, 28 May 2020 14:18:52 +0800
-From: <chuanjia.liu@mediatek.com>
-To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
-Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
-Date: Thu, 28 May 2020 14:16:48 +0800
-Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com>
-X-Mailer: git-send-email 2.18.0
-In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com>
-References: <20200528061648.32078-1-chuanjia.liu@mediatek.com>
-MIME-Version: 1.0
-X-MTK: N
-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
-X-CRM114-CacheID: sfid-20200527_232901_719172_E5A99C62
-X-CRM114-Status: GOOD ( 11.61 )
-X-Spam-Score: -0.2 (/)
-X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary:
- Content analysis details: (-0.2 points)
- pts rule name description
- ---- ----------------------
- --------------------------------------------------
- -0.0 SPF_PASS SPF: sender matches SPF record
- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record
- 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64
- encoding
- -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from
- author's domain
- 0.1 DKIM_SIGNED Message has a DKIM or DK signature,
- not necessarily
- valid
- -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature
- -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from
- envelope-from domain
- 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay
- lines
-X-BeenThere: linux-mediatek@lists.infradead.org
-X-Mailman-Version: 2.1.29
-Precedence: list
-List-Id: <linux-mediatek.lists.infradead.org>
-List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-mediatek>,
- <mailto:linux-mediatek-request@lists.infradead.org?subject=unsubscribe>
-List-Archive: <http://lists.infradead.org/pipermail/linux-mediatek/>
-List-Post: <mailto:linux-mediatek@lists.infradead.org>
-List-Help: <mailto:linux-mediatek-request@lists.infradead.org?subject=help>
-List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mediatek>,
- <mailto:linux-mediatek-request@lists.infradead.org?subject=subscribe>
-Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
- srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
- linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
- jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,
- yong.wu@mediatek.com, bhelgaas@google.com,
- linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk
-Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
-Errors-To:
- linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
-
-From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
-
-Remove unused property and add pciecfg node.
-
-Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts | 3 ++-
- arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++----------
- 2 files changed, 15 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -149,9 +149,10 @@
- };
- };
-
--&pcie {
-+&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
-+ status = "okay";
- };
-
- &pciephy1 {
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -382,16 +382,21 @@
- #reset-cells = <1>;
- };
-
-- pcie: pcie@1a140000 {
-+ pciecfg: pciecfg@1a140000 {
-+ compatible = "mediatek,mt7629-pciecfg", "syscon";
-+ reg = <0x1a140000 0x1000>;
-+ };
-+
-+ pcie1: pcie@1a145000 {
- compatible = "mediatek,mt7629-pcie";
- device_type = "pci";
-- reg = <0x1a140000 0x1000>,
-- <0x1a145000 0x1000>;
-- reg-names = "subsys","port1";
-+ reg = <0x1a145000 0x1000>;
-+ reg-names = "port1";
-+ mediatek,pcie-cfg = <&pciecfg>;
- #address-cells = <3>;
- #size-cells = <2>;
-- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
-- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "pcie_irq";
- clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P1_AUX_EN>,
-@@ -412,21 +417,19 @@
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- bus-range = <0x00 0xff>;
- ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
-+ status = "disabled";
-
-- pcie1: pcie@1,0 {
-- device_type = "pci";
-+ slot1: pcie@1,0 {
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
-- num-lanes = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
--
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct
+@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct
if (status & INTX_MASK) {
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
/* Clear the INTx */
+++ /dev/null
-From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Tue, 4 Jan 2022 12:07:00 +0000
-Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and
- devad fields
-
-Add a couple of helpers and definitions to extract the clause 45 regad
-and devad fields from the regnum passed into MDIO drivers.
-
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- include/linux/mdio.h | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/include/linux/mdio.h
-+++ b/include/linux/mdio.h
-@@ -7,6 +7,7 @@
- #define __LINUX_MDIO_H__
-
- #include <uapi/linux/mdio.h>
-+#include <linux/bitfield.h>
- #include <linux/mod_devicetable.h>
-
- /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
-@@ -14,6 +15,7 @@
- */
- #define MII_ADDR_C45 (1<<30)
- #define MII_DEVADDR_C45_SHIFT 16
-+#define MII_DEVADDR_C45_MASK GENMASK(20, 16)
- #define MII_REGADDR_C45_MASK GENMASK(15, 0)
-
- struct gpio_desc;
-@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d
- return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
- }
-
-+static inline u16 mdiobus_c45_regad(u32 regnum)
-+{
-+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
-+}
-+
-+static inline u16 mdiobus_c45_devad(u32 regnum)
-+{
-+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
-+}
-+
- static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
- u16 regnum)
- {
+++ /dev/null
-From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 4 Jan 2022 12:07:46 +0000
-Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
- access
-
-Implement read and write access to IEEE 802.3 Clause 45 Ethernet
-phy registers while making use of new mdiobus_c45_regad and
-mdiobus_c45_devad helpers.
-
-Tested on the Ubiquiti UniFi 6 LR access point featuring
-MediaTek MT7622BV WiSoC with Aquantia AQR112C.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +
- 2 files changed, 60 insertions(+), 13 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -323,13 +323,35 @@ static int _mtk_mdio_write(struct mtk_et
- if (ret < 0)
- return ret;
-
-- mtk_w32(eth, PHY_IAC_ACCESS |
-- PHY_IAC_START_C22 |
-- PHY_IAC_CMD_WRITE |
-- PHY_IAC_REG(phy_reg) |
-- PHY_IAC_ADDR(phy_addr) |
-- PHY_IAC_DATA(write_data),
-- MTK_PHY_IAC);
-+ if (phy_reg & MII_ADDR_C45) {
-+ mtk_w32(eth, PHY_IAC_ACCESS |
-+ PHY_IAC_START_C45 |
-+ PHY_IAC_CMD_C45_ADDR |
-+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+ PHY_IAC_ADDR(phy_addr) |
-+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
-+ MTK_PHY_IAC);
-+
-+ ret = mtk_mdio_busy_wait(eth);
-+ if (ret < 0)
-+ return ret;
-+
-+ mtk_w32(eth, PHY_IAC_ACCESS |
-+ PHY_IAC_START_C45 |
-+ PHY_IAC_CMD_WRITE |
-+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+ PHY_IAC_ADDR(phy_addr) |
-+ PHY_IAC_DATA(write_data),
-+ MTK_PHY_IAC);
-+ } else {
-+ mtk_w32(eth, PHY_IAC_ACCESS |
-+ PHY_IAC_START_C22 |
-+ PHY_IAC_CMD_WRITE |
-+ PHY_IAC_REG(phy_reg) |
-+ PHY_IAC_ADDR(phy_addr) |
-+ PHY_IAC_DATA(write_data),
-+ MTK_PHY_IAC);
-+ }
-
- ret = mtk_mdio_busy_wait(eth);
- if (ret < 0)
-@@ -346,12 +368,33 @@ static int _mtk_mdio_read(struct mtk_eth
- if (ret < 0)
- return ret;
-
-- mtk_w32(eth, PHY_IAC_ACCESS |
-- PHY_IAC_START_C22 |
-- PHY_IAC_CMD_C22_READ |
-- PHY_IAC_REG(phy_reg) |
-- PHY_IAC_ADDR(phy_addr),
-- MTK_PHY_IAC);
-+ if (phy_reg & MII_ADDR_C45) {
-+ mtk_w32(eth, PHY_IAC_ACCESS |
-+ PHY_IAC_START_C45 |
-+ PHY_IAC_CMD_C45_ADDR |
-+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+ PHY_IAC_ADDR(phy_addr) |
-+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),
-+ MTK_PHY_IAC);
-+
-+ ret = mtk_mdio_busy_wait(eth);
-+ if (ret < 0)
-+ return ret;
-+
-+ mtk_w32(eth, PHY_IAC_ACCESS |
-+ PHY_IAC_START_C45 |
-+ PHY_IAC_CMD_C45_READ |
-+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |
-+ PHY_IAC_ADDR(phy_addr),
-+ MTK_PHY_IAC);
-+ } else {
-+ mtk_w32(eth, PHY_IAC_ACCESS |
-+ PHY_IAC_START_C22 |
-+ PHY_IAC_CMD_C22_READ |
-+ PHY_IAC_REG(phy_reg) |
-+ PHY_IAC_ADDR(phy_addr),
-+ MTK_PHY_IAC);
-+ }
-
- ret = mtk_mdio_busy_wait(eth);
- if (ret < 0)
-@@ -1013,6 +1056,7 @@ static int mtk_mdio_init(struct mtk_eth
- eth->mii_bus->name = "mdio";
- eth->mii_bus->read = mtk_mdio_read;
- eth->mii_bus->write = mtk_mdio_write;
-+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
- eth->mii_bus->priv = eth;
- eth->mii_bus->parent = eth->dev;
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -382,9 +382,12 @@
- #define PHY_IAC_ADDR_MASK GENMASK(24, 20)
- #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
- #define PHY_IAC_CMD_MASK GENMASK(19, 18)
-+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
- #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
- #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
-+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
- #define PHY_IAC_START_MASK GENMASK(17, 16)
-+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
- #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
- #define PHY_IAC_DATA_MASK GENMASK(15, 0)
- #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
+++ /dev/null
-From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 13 Feb 2023 02:33:14 +0000
-Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
-
-Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
-PHYs which require calibration data from the SoC's efuse.
-Despite the similar design the driver doesn't share any code with the
-existing mediatek-ge.c, so add support for these PHYs by introducing a
-new driver for only MediaTek's ARM64 SoCs.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- MAINTAINERS | 9 +
- drivers/net/phy/Kconfig | 12 +
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++
- drivers/net/phy/mediatek-ge.c | 3 +-
- 5 files changed, 1287 insertions(+), 1 deletion(-)
- create mode 100644 drivers/net/phy/mediatek-ge-soc.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -11797,6 +11797,15 @@ S: Maintained
- F: drivers/net/pcs/pcs-mtk-lynxi.c
- F: include/linux/pcs/pcs-mtk-lynxi.h
-
-+MEDIATEK ETHERNET PHY DRIVERS
-+M: Daniel Golle <daniel@makrotopia.org>
-+M: Qingfang Deng <dqfext@gmail.com>
-+M: SkyLake Huang <SkyLake.Huang@mediatek.com>
-+L: netdev@vger.kernel.org
-+S: Maintained
-+F: drivers/net/phy/mediatek-ge-soc.c
-+F: drivers/net/phy/mediatek-ge.c
-+
- MEDIATEK I2C CONTROLLER DRIVER
- M: Qii Wang <qii.wang@mediatek.com>
- L: linux-i2c@vger.kernel.org
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -293,6 +293,18 @@ config MEDIATEK_GE_PHY
- help
- Supports the MediaTek Gigabit Ethernet PHYs.
-
-+config MEDIATEK_GE_SOC_PHY
-+ tristate "MediaTek SoC Ethernet PHYs"
-+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
-+ select NVMEM_MTK_EFUSE
-+ help
-+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
-+
-+ Include support for built-in Ethernet PHYs which are present in
-+ the MT7981 and MT7988 SoCs. These PHYs need calibration data
-+ present in the SoCs efuse and will dynamically calibrate VCM
-+ (common-mode voltage) during startup.
-+
- config MICREL_PHY
- tristate "Micrel PHYs"
- help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
- obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
-+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
- obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
- obj-$(CONFIG_MICREL_PHY) += micrel.o
---- a/drivers/net/phy/mediatek-ge.c
-+++ b/drivers/net/phy/mediatek-ge.c
-@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
- module_phy_driver(mtk_gephy_driver);
-
- static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
-- { PHY_ID_MATCH_VENDOR(0x03a29400) },
-+ { PHY_ID_MATCH_EXACT(0x03a29441) },
-+ { PHY_ID_MATCH_EXACT(0x03a29412) },
- { }
- };
-
--- /dev/null
+From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 11 Jun 2023 00:48:10 +0100
+Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
+
+Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
+PHYs which require calibration data from the SoC's efuse.
+Despite the similar design the driver doesn't share any code with the
+existing mediatek-ge.c.
+Add support for such PHYs by introducing a new driver with basic
+support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS | 9 +
+ drivers/net/phy/Kconfig | 12 +
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++
+ drivers/net/phy/mediatek-ge.c | 3 +-
+ 5 files changed, 1140 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/net/phy/mediatek-ge-soc.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -12934,6 +12934,15 @@ S: Maintained
+ F: drivers/net/pcs/pcs-mtk-lynxi.c
+ F: include/linux/pcs/pcs-mtk-lynxi.h
+
++MEDIATEK ETHERNET PHY DRIVERS
++M: Daniel Golle <daniel@makrotopia.org>
++M: Qingfang Deng <dqfext@gmail.com>
++M: SkyLake Huang <SkyLake.Huang@mediatek.com>
++L: netdev@vger.kernel.org
++S: Maintained
++F: drivers/net/phy/mediatek-ge-soc.c
++F: drivers/net/phy/mediatek-ge.c
++
+ MEDIATEK I2C CONTROLLER DRIVER
+ M: Qii Wang <qii.wang@mediatek.com>
+ L: linux-i2c@vger.kernel.org
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -307,6 +307,18 @@ config MEDIATEK_GE_PHY
+ help
+ Supports the MediaTek Gigabit Ethernet PHYs.
+
++config MEDIATEK_GE_SOC_PHY
++ tristate "MediaTek SoC Ethernet PHYs"
++ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
++ select NVMEM_MTK_EFUSE
++ help
++ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
++
++ Include support for built-in Ethernet PHYs which are present in
++ the MT7981 and MT7988 SoCs. These PHYs need calibration data
++ present in the SoCs efuse and will dynamically calibrate VCM
++ (common-mode voltage) during startup.
++
+ config MICREL_PHY
+ tristate "Micrel PHYs"
+ depends on PTP_1588_CLOCK_OPTIONAL
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -84,6 +84,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
+ obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
+ obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
+ obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
++obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
+ obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
+ obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
+ obj-$(CONFIG_MICREL_PHY) += micrel.o
+--- /dev/null
++++ b/drivers/net/phy/mediatek-ge-soc.c
+@@ -0,0 +1,1116 @@
++// SPDX-License-Identifier: GPL-2.0+
++#include <linux/bitfield.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/phy.h>
++
++#define MTK_GPHY_ID_MT7981 0x03a29461
++#define MTK_GPHY_ID_MT7988 0x03a29481
++
++#define MTK_EXT_PAGE_ACCESS 0x1f
++#define MTK_PHY_PAGE_STANDARD 0x0000
++#define MTK_PHY_PAGE_EXTENDED_3 0x0003
++
++#define MTK_PHY_LPI_REG_14 0x14
++#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
++
++#define MTK_PHY_LPI_REG_1c 0x1c
++#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
++
++#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
++#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
++
++#define ANALOG_INTERNAL_OPERATION_MAX_US 20
++#define TXRESERVE_MIN 0
++#define TXRESERVE_MAX 7
++
++#define MTK_PHY_ANARG_RG 0x10
++#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
++
++/* Registers on MDIO_MMD_VEND1 */
++#define MTK_PHY_TXVLD_DA_RG 0x12
++#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
++#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
++#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
++#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
++#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
++#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
++#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
++#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
++#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
++
++#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
++#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
++#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
++
++#define MTK_PHY_RXADC_CTRL_RG7 0xc6
++#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
++
++#define MTK_PHY_RXADC_CTRL_RG9 0xc8
++#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
++#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
++#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
++#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
++
++#define MTK_PHY_LDO_OUTPUT_V 0xd7
++
++#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
++#define MTK_PHY_RG_CAL_CKINV BIT(12)
++#define MTK_PHY_RG_ANA_CALEN BIT(8)
++#define MTK_PHY_RG_ZCALEN_A BIT(0)
++
++#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
++#define MTK_PHY_RG_ZCALEN_B BIT(12)
++#define MTK_PHY_RG_ZCALEN_C BIT(8)
++#define MTK_PHY_RG_ZCALEN_D BIT(4)
++#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
++
++#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
++#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
++
++#define MTK_PHY_RG_TX_FILTER 0xfe
++
++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
++#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
++#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
++
++#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
++#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
++
++#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
++#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
++
++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
++#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
++#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
++
++#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
++#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
++#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
++
++#define MTK_PHY_RG_AD_CAL_COMP 0x17a
++#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
++
++#define MTK_PHY_RG_AD_CAL_CLK 0x17b
++#define MTK_PHY_DA_CAL_CLK BIT(0)
++
++#define MTK_PHY_RG_AD_CALIN 0x17c
++#define MTK_PHY_DA_CALIN_FLAG BIT(0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
++#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
++#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
++#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
++#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
++#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
++#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
++#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
++#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
++
++#define MTK_PHY_RG_DEV1E_REG19b 0x19b
++#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
++
++#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
++#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
++#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
++#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
++#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
++#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
++#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
++#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
++#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
++#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
++
++#define MTK_PHY_RG_DEV1E_REG234 0x234
++#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
++#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
++#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
++
++#define MTK_PHY_RG_LPF_CNT_VAL 0x235
++
++#define MTK_PHY_RG_DEV1E_REG238 0x238
++#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
++#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
++
++#define MTK_PHY_RG_DEV1E_REG239 0x239
++#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
++#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
++
++#define MTK_PHY_RG_DEV1E_REG27C 0x27c
++#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
++#define MTK_PHY_RG_DEV1E_REG27D 0x27d
++#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
++
++#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
++#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
++#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
++
++#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
++#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
++#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
++#define MTK_PHY_LPI_TR_READY BIT(9)
++#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
++
++#define MTK_PHY_RG_DEV1E_REG323 0x323
++#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
++#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
++
++#define MTK_PHY_RG_DEV1E_REG324 0x324
++#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
++#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
++
++#define MTK_PHY_RG_DEV1E_REG326 0x326
++#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
++#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
++#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
++#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
++#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
++
++#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
++#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
++
++#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
++#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
++#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
++#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
++
++#define MTK_PHY_RG_BG_RASEL 0x115
++#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
++
++/* These macro privides efuse parsing for internal phy. */
++#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
++#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
++#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
++#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
++#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
++
++#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
++#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
++#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
++#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
++#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
++
++#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
++#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
++
++#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
++#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
++
++enum {
++ NO_PAIR,
++ PAIR_A,
++ PAIR_B,
++ PAIR_C,
++ PAIR_D,
++};
++
++enum {
++ GPHY_PORT0,
++ GPHY_PORT1,
++ GPHY_PORT2,
++ GPHY_PORT3,
++};
++
++enum calibration_mode {
++ EFUSE_K,
++ SW_K
++};
++
++enum CAL_ITEM {
++ REXT,
++ TX_OFFSET,
++ TX_AMP,
++ TX_R50,
++ TX_VCM
++};
++
++enum CAL_MODE {
++ EFUSE_M,
++ SW_M
++};
++
++static int mtk_socphy_read_page(struct phy_device *phydev)
++{
++ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
++}
++
++static int mtk_socphy_write_page(struct phy_device *phydev, int page)
++{
++ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
++}
++
++/* One calibration cycle consists of:
++ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
++ * until AD_CAL_COMP is ready to output calibration result.
++ * 2.Wait until DA_CAL_CLK is available.
++ * 3.Fetch AD_CAL_COMP_OUT.
++ */
++static int cal_cycle(struct phy_device *phydev, int devad,
++ u32 regnum, u16 mask, u16 cal_val)
++{
++ int reg_val;
++ int ret;
++
++ phy_modify_mmd(phydev, devad, regnum,
++ mask, cal_val);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
++ MTK_PHY_DA_CALIN_FLAG);
++
++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_AD_CAL_CLK, reg_val,
++ reg_val & MTK_PHY_DA_CAL_CLK, 500,
++ ANALOG_INTERNAL_OPERATION_MAX_US, false);
++ if (ret) {
++ phydev_err(phydev, "Calibration cycle timeout\n");
++ return ret;
++ }
++
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
++ MTK_PHY_DA_CALIN_FLAG);
++ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
++ MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
++ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
++
++ return ret;
++}
++
++static int rext_fill_result(struct phy_device *phydev, u16 *buf)
++{
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
++ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
++ MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
++
++ return 0;
++}
++
++static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
++{
++ u16 rext_cal_val[2];
++
++ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
++ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
++ rext_fill_result(phydev, rext_cal_val);
++
++ return 0;
++}
++
++static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
++{
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
++ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
++ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
++ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
++ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
++
++ return 0;
++}
++
++static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
++{
++ u16 tx_offset_cal_val[4];
++
++ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
++ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
++ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
++ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
++
++ tx_offset_fill_result(phydev, tx_offset_cal_val);
++
++ return 0;
++}
++
++static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
++{
++ int i;
++ int bias[16] = {};
++ const int vals_9461[16] = { 7, 1, 4, 7,
++ 7, 1, 4, 7,
++ 7, 1, 4, 7,
++ 7, 1, 4, 7 };
++ const int vals_9481[16] = { 10, 6, 6, 10,
++ 10, 6, 6, 10,
++ 10, 6, 6, 10,
++ 10, 6, 6, 10 };
++ switch (phydev->drv->phy_id) {
++ case MTK_GPHY_ID_MT7981:
++ /* We add some calibration to efuse values
++ * due to board level influence.
++ * GBE: +7, TBT: +1, HBT: +4, TST: +7
++ */
++ memcpy(bias, (const void *)vals_9461, sizeof(bias));
++ break;
++ case MTK_GPHY_ID_MT7988:
++ memcpy(bias, (const void *)vals_9481, sizeof(bias));
++ break;
++ }
++
++ /* Prevent overflow */
++ for (i = 0; i < 12; i++) {
++ if (buf[i >> 2] + bias[i] > 63) {
++ buf[i >> 2] = 63;
++ bias[i] = 0;
++ }
++ }
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
++ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
++ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
++ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
++ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
++ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
++ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
++ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
++ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
++ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
++ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
++ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
++ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
++ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
++ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
++ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
++ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
++
++ return 0;
++}
++
++static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
++{
++ u16 tx_amp_cal_val[4];
++
++ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
++ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
++ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
++ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
++ tx_amp_fill_result(phydev, tx_amp_cal_val);
++
++ return 0;
++}
++
++static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
++ u8 txg_calen_x)
++{
++ int bias = 0;
++ u16 reg, val;
++
++ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
++ bias = -2;
++
++ val = clamp_val(bias + tx_r50_cal_val, 0, 63);
++
++ switch (txg_calen_x) {
++ case PAIR_A:
++ reg = MTK_PHY_DA_TX_R50_PAIR_A;
++ break;
++ case PAIR_B:
++ reg = MTK_PHY_DA_TX_R50_PAIR_B;
++ break;
++ case PAIR_C:
++ reg = MTK_PHY_DA_TX_R50_PAIR_C;
++ break;
++ case PAIR_D:
++ reg = MTK_PHY_DA_TX_R50_PAIR_D;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
++
++ return 0;
++}
++
++static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
++ u8 txg_calen_x)
++{
++ u16 tx_r50_cal_val;
++
++ switch (txg_calen_x) {
++ case PAIR_A:
++ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
++ break;
++ case PAIR_B:
++ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
++ break;
++ case PAIR_C:
++ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
++ break;
++ case PAIR_D:
++ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
++ break;
++ default:
++ return -EINVAL;
++ }
++ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
++
++ return 0;
++}
++
++static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
++{
++ u8 lower_idx, upper_idx, txreserve_val;
++ u8 lower_ret, upper_ret;
++ int ret;
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ANA_CALEN);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_CAL_CKINV);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_TXVOS_CALEN);
++
++ switch (rg_txreserve_x) {
++ case PAIR_A:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_A,
++ MTK_PHY_DASN_DAC_IN0_A_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_A,
++ MTK_PHY_DASN_DAC_IN1_A_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ZCALEN_A);
++ break;
++ case PAIR_B:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_B,
++ MTK_PHY_DASN_DAC_IN0_B_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_B,
++ MTK_PHY_DASN_DAC_IN1_B_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_B);
++ break;
++ case PAIR_C:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_C,
++ MTK_PHY_DASN_DAC_IN0_C_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_C,
++ MTK_PHY_DASN_DAC_IN1_C_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_C);
++ break;
++ case PAIR_D:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN0_D,
++ MTK_PHY_DASN_DAC_IN0_D_MASK);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DASN_DAC_IN1_D,
++ MTK_PHY_DASN_DAC_IN1_D_MASK);
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_D);
++ break;
++ default:
++ ret = -EINVAL;
++ goto restore;
++ }
++
++ lower_idx = TXRESERVE_MIN;
++ upper_idx = TXRESERVE_MAX;
++
++ phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
++ while ((upper_idx - lower_idx) > 1) {
++ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
++ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ txreserve_val << 12 | txreserve_val << 8 |
++ txreserve_val << 4 | txreserve_val);
++ if (ret == 1) {
++ upper_idx = txreserve_val;
++ upper_ret = ret;
++ } else if (ret == 0) {
++ lower_idx = txreserve_val;
++ lower_ret = ret;
++ } else {
++ goto restore;
++ }
++ }
++
++ if (lower_idx == TXRESERVE_MIN) {
++ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ lower_idx << 12 | lower_idx << 8 |
++ lower_idx << 4 | lower_idx);
++ ret = lower_ret;
++ } else if (upper_idx == TXRESERVE_MAX) {
++ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ upper_idx << 12 | upper_idx << 8 |
++ upper_idx << 4 | upper_idx);
++ ret = upper_ret;
++ }
++ if (ret < 0)
++ goto restore;
++
++ /* We calibrate TX-VCM in different logic. Check upper index and then
++ * lower index. If this calibration is valid, apply lower index's result.
++ */
++ ret = upper_ret - lower_ret;
++ if (ret == 1) {
++ ret = 0;
++ /* Make sure we use upper_idx in our calibration system */
++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ upper_idx << 12 | upper_idx << 8 |
++ upper_idx << 4 | upper_idx);
++ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
++ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
++ lower_ret == 1) {
++ ret = 0;
++ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
++ MTK_PHY_DA_RX_PSBN_TBT_MASK |
++ MTK_PHY_DA_RX_PSBN_HBT_MASK |
++ MTK_PHY_DA_RX_PSBN_GBE_MASK |
++ MTK_PHY_DA_RX_PSBN_LP_MASK,
++ lower_idx << 12 | lower_idx << 8 |
++ lower_idx << 4 | lower_idx);
++ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
++ lower_idx);
++ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
++ lower_ret == 0) {
++ ret = 0;
++ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
++ upper_idx);
++ } else {
++ ret = -EINVAL;
++ }
++
++restore:
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ANA_CALEN);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_TXVOS_CALEN);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
++ MTK_PHY_RG_ZCALEN_A);
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
++ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
++ MTK_PHY_RG_ZCALEN_D);
++
++ return ret;
++}
++
++static void mt798x_phy_common_finetune(struct phy_device *phydev)
++{
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* EnabRandUpdTrig = 1 */
++ __phy_write(phydev, 0x11, 0x2f00);
++ __phy_write(phydev, 0x12, 0xe);
++ __phy_write(phydev, 0x10, 0x8fb0);
++
++ /* NormMseLoThresh = 85 */
++ __phy_write(phydev, 0x11, 0x55a0);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x83aa);
++
++ /* TrFreeze = 0 */
++ __phy_write(phydev, 0x11, 0x0);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x9686);
++
++ /* SSTrKp1000Slv = 5 */
++ __phy_write(phydev, 0x11, 0xbaef);
++ __phy_write(phydev, 0x12, 0x2e);
++ __phy_write(phydev, 0x10, 0x968c);
++
++ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
++ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
++ */
++ __phy_write(phydev, 0x11, 0xd10a);
++ __phy_write(phydev, 0x12, 0x34);
++ __phy_write(phydev, 0x10, 0x8f82);
++
++ /* VcoSlicerThreshBitsHigh */
++ __phy_write(phydev, 0x11, 0x5555);
++ __phy_write(phydev, 0x12, 0x55);
++ __phy_write(phydev, 0x10, 0x8ec0);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
++ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
++ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
++
++ /* rg_tr_lpf_cnt_val = 512 */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
++
++ /* IIR2 related */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
++
++ /* FFE peaking */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
++ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
++ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
++
++ /* Disable LDO pump */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
++ /* Adjust LDO output voltage */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
++}
++
++static void mt7981_phy_finetune(struct phy_device *phydev)
++{
++ u16 val[8] = { 0x01ce, 0x01c1,
++ 0x020f, 0x0202,
++ 0x03d0, 0x03c0,
++ 0x0013, 0x0005 };
++ int i, k;
++
++ /* 100M eye finetune:
++ * Keep middle level of TX MLT3 shapper as default.
++ * Only change TX MLT3 overshoot level here.
++ */
++ for (k = 0, i = 1; i < 12; i++) {
++ if (i % 3 == 0)
++ continue;
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
++ }
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
++ __phy_write(phydev, 0x11, 0xc71);
++ __phy_write(phydev, 0x12, 0xc);
++ __phy_write(phydev, 0x10, 0x8fae);
++
++ /* ResetSyncOffset = 6 */
++ __phy_write(phydev, 0x11, 0x600);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x8fc0);
++
++ /* VgaDecRate = 1 */
++ __phy_write(phydev, 0x11, 0x4c2a);
++ __phy_write(phydev, 0x12, 0x3e);
++ __phy_write(phydev, 0x10, 0x8fa4);
++
++ /* FfeUpdGainForce = 4 */
++ __phy_write(phydev, 0x11, 0x240);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x9680);
++
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++}
++
++static void mt7988_phy_finetune(struct phy_device *phydev)
++{
++ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
++ 0x020d, 0x0206, 0x0384, 0x03d0,
++ 0x03c6, 0x030a, 0x0011, 0x0005 };
++ int i;
++
++ /* Set default MLT3 shaper first */
++ for (i = 0; i < 12; i++)
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
++
++ /* TCT finetune */
++ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
++
++ /* Disable TX power saving */
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
++ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++
++ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
++ __phy_write(phydev, 0x11, 0x671);
++ __phy_write(phydev, 0x12, 0xc);
++ __phy_write(phydev, 0x10, 0x8fae);
++
++ /* ResetSyncOffset = 5 */
++ __phy_write(phydev, 0x11, 0x500);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x8fc0);
++
++ /* VgaDecRate is 1 at default on mt7988 */
++
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
++ /* TxClkOffset = 2 */
++ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
++ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++}
++
++static void mt798x_phy_eee(struct phy_device *phydev)
++{
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
++ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
++ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
++ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ 0xff));
++
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_TESTMUX_ADC_CTRL,
++ MTK_PHY_RG_TXEN_DIG_MASK);
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
++
++ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
++ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
++ MTK_PHY_LPI_SLV_SEND_TX_EN,
++ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
++ MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
++ MTK_PHY_LPI_TXPCS_LOC_RCV,
++ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
++ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
++ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
++ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
++ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
++ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
++ 0x33) |
++ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
++ MTK_PHY_LPI_VCO_EEE_STG0_EN);
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
++ MTK_PHY_EEE_WAKE_MAS_INT_DC |
++ MTK_PHY_EEE_WAKE_SLV_INT_DC);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
++ MTK_PHY_SMI_DETCNT_MAX_MASK,
++ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
++ MTK_PHY_SMI_DET_MAX_EN);
++
++ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
++ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
++ MTK_PHY_TREC_UPDATE_ENAB_CLR |
++ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
++ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
++ /* Regsigdet_sel_1000 = 0 */
++ __phy_write(phydev, 0x11, 0xb);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x9690);
++
++ /* REG_EEE_st2TrKf1000 = 3 */
++ __phy_write(phydev, 0x11, 0x114f);
++ __phy_write(phydev, 0x12, 0x2);
++ __phy_write(phydev, 0x10, 0x969a);
++
++ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
++ __phy_write(phydev, 0x11, 0x3028);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x969e);
++
++ /* RegEEE_slv_wake_int_timer_tar = 8 */
++ __phy_write(phydev, 0x11, 0x5010);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96a0);
++
++ /* RegEEE_trfreeze_timer2 = 586 */
++ __phy_write(phydev, 0x11, 0x24a);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96a8);
++
++ /* RegEEE100Stg1_tar = 16 */
++ __phy_write(phydev, 0x11, 0x3210);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96b8);
++
++ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
++ __phy_write(phydev, 0x11, 0x1463);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x96ca);
++
++ /* DfeTailEnableVgaThresh1000 = 27 */
++ __phy_write(phydev, 0x11, 0x36);
++ __phy_write(phydev, 0x12, 0x0);
++ __phy_write(phydev, 0x10, 0x8f80);
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
++ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
++
++ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
++ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
++ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
++
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
++ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
++ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
++ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
++}
++
++static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
++ u8 start_pair, u8 end_pair)
++{
++ u8 pair_n;
++ int ret;
++
++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
++ /* TX_OFFSET & TX_AMP have no SW calibration. */
++ switch (cal_item) {
++ case TX_VCM:
++ ret = tx_vcm_cal_sw(phydev, pair_n);
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (ret)
++ return ret;
++ }
++ return 0;
++}
++
++static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
++ u8 start_pair, u8 end_pair, u32 *buf)
++{
++ u8 pair_n;
++ int ret;
++
++ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
++ /* TX_VCM has no efuse calibration. */
++ switch (cal_item) {
++ case REXT:
++ ret = rext_cal_efuse(phydev, buf);
++ break;
++ case TX_OFFSET:
++ ret = tx_offset_cal_efuse(phydev, buf);
++ break;
++ case TX_AMP:
++ ret = tx_amp_cal_efuse(phydev, buf);
++ break;
++ case TX_R50:
++ ret = tx_r50_cal_efuse(phydev, buf, pair_n);
++ break;
++ default:
++ return -EINVAL;
++ }
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
++ enum CAL_MODE cal_mode, u8 start_pair,
++ u8 end_pair, u32 *buf)
++{
++ int ret;
++
++ switch (cal_mode) {
++ case EFUSE_M:
++ ret = cal_efuse(phydev, cal_item, start_pair,
++ end_pair, buf);
++ break;
++ case SW_M:
++ ret = cal_sw(phydev, cal_item, start_pair, end_pair);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (ret) {
++ phydev_err(phydev, "cal %d failed\n", cal_item);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int mt798x_phy_calibration(struct phy_device *phydev)
++{
++ int ret = 0;
++ u32 *buf;
++ size_t len;
++ struct nvmem_cell *cell;
++
++ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
++ if (IS_ERR(cell)) {
++ if (PTR_ERR(cell) == -EPROBE_DEFER)
++ return PTR_ERR(cell);
++ return 0;
++ }
++
++ buf = (u32 *)nvmem_cell_read(cell, &len);
++ if (IS_ERR(buf))
++ return PTR_ERR(buf);
++ nvmem_cell_put(cell);
++
++ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
++ phydev_err(phydev, "invalid efuse data\n");
++ ret = -EINVAL;
++ goto out;
++ }
++
++ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
++ if (ret)
++ goto out;
++ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
++ if (ret)
++ goto out;
++
++out:
++ kfree(buf);
++ return ret;
++}
++
++static int mt798x_phy_config_init(struct phy_device *phydev)
++{
++ switch (phydev->drv->phy_id) {
++ case MTK_GPHY_ID_MT7981:
++ mt7981_phy_finetune(phydev);
++ break;
++ case MTK_GPHY_ID_MT7988:
++ mt7988_phy_finetune(phydev);
++ break;
++ }
++
++ mt798x_phy_common_finetune(phydev);
++ mt798x_phy_eee(phydev);
++
++ return mt798x_phy_calibration(phydev);
++}
++
++static struct phy_driver mtk_socphy_driver[] = {
++ {
++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
++ .name = "MediaTek MT7981 PHY",
++ .config_init = mt798x_phy_config_init,
++ .config_intr = genphy_no_config_intr,
++ .handle_interrupt = genphy_handle_interrupt_no_ack,
++ .probe = mt798x_phy_calibration,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_socphy_read_page,
++ .write_page = mtk_socphy_write_page,
++ },
++ {
++ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
++ .name = "MediaTek MT7988 PHY",
++ .config_init = mt798x_phy_config_init,
++ .config_intr = genphy_no_config_intr,
++ .handle_interrupt = genphy_handle_interrupt_no_ack,
++ .probe = mt798x_phy_calibration,
++ .suspend = genphy_suspend,
++ .resume = genphy_resume,
++ .read_page = mtk_socphy_read_page,
++ .write_page = mtk_socphy_write_page,
++ },
++};
++
++module_phy_driver(mtk_socphy_driver);
++
++static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
++ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
++ { }
++};
++
++MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
++MODULE_LICENSE("GPL");
++
++MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
+--- a/drivers/net/phy/mediatek-ge.c
++++ b/drivers/net/phy/mediatek-ge.c
+@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
+ module_phy_driver(mtk_gephy_driver);
+
+ static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
+- { PHY_ID_MATCH_VENDOR(0x03a29400) },
++ { PHY_ID_MATCH_EXACT(0x03a29441) },
++ { PHY_ID_MATCH_EXACT(0x03a29412) },
+ { }
+ };
+
+++ /dev/null
---- a/drivers/net/phy/mxl-gpy.c
-+++ b/drivers/net/phy/mxl-gpy.c
-@@ -126,6 +126,12 @@ static int gpy_config_init(struct phy_de
- if (ret < 0)
- return ret;
-
-+ /* Disable SGMII auto-negotiation */
-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+ VSPEC1_SGMII_CTRL_ANEN, 0);
-+ if (ret < 0)
-+ return ret;
-+
- return gpy_led_write(phydev);
- }
-
-@@ -151,65 +157,6 @@ static int gpy_probe(struct phy_device *
- return 0;
- }
-
--static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
--{
-- int fw_ver, fw_type, fw_minor;
-- size_t i;
--
-- fw_ver = phy_read(phydev, PHY_FWV);
-- if (fw_ver < 0)
-- return true;
--
-- fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_ver);
-- fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_ver);
--
-- for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
-- if (fw_type != ver_need_sgmii_reaneg[i].type)
-- continue;
-- if (fw_minor < ver_need_sgmii_reaneg[i].minor)
-- return true;
-- break;
-- }
--
-- return false;
--}
--
--static bool gpy_2500basex_chk(struct phy_device *phydev)
--{
-- int ret;
--
-- ret = phy_read(phydev, PHY_MIISTAT);
-- if (ret < 0) {
-- phydev_err(phydev, "Error: MDIO register access failed: %d\n",
-- ret);
-- return false;
-- }
--
-- if (!(ret & PHY_MIISTAT_LS) ||
-- FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
-- return false;
--
-- phydev->speed = SPEED_2500;
-- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-- VSPEC1_SGMII_CTRL_ANEN, 0);
-- return true;
--}
--
--static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
--{
-- int ret;
--
-- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
-- if (ret < 0) {
-- phydev_err(phydev, "Error: MMD register access failed: %d\n",
-- ret);
-- return true;
-- }
--
-- return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
--}
--
- static int gpy_config_aneg(struct phy_device *phydev)
- {
- bool changed = false;
-@@ -248,53 +195,11 @@ static int gpy_config_aneg(struct phy_de
- phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
- return 0;
-
-- /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
-- * disabled.
-- */
-- if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
-- !gpy_sgmii_aneg_en(phydev))
-- return 0;
--
-- /* There is a design constraint in GPY2xx device where SGMII AN is
-- * only triggered when there is change of speed. If, PHY link
-- * partner`s speed is still same even after PHY TPI is down and up
-- * again, SGMII AN is not triggered and hence no new in-band message
-- * from GPY to MAC side SGMII.
-- * This could cause an issue during power up, when PHY is up prior to
-- * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
-- * wouldn`t receive new in-band message from GPY with correct link
-- * status, speed and duplex info.
-- *
-- * 1) If PHY is already up and TPI link status is still down (such as
-- * hard reboot), TPI link status is polled for 4 seconds before
-- * retriggerring SGMII AN.
-- * 2) If PHY is already up and TPI link status is also up (such as soft
-- * reboot), polling of TPI link status is not needed and SGMII AN is
-- * immediately retriggered.
-- * 3) Other conditions such as PHY is down, speed change etc, skip
-- * retriggering SGMII AN. Note: in case of speed change, GPY FW will
-- * initiate SGMII AN.
-- */
--
-- if (phydev->state != PHY_UP)
-- return 0;
--
-- ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
-- 20000, 4000000, false);
-- if (ret == -ETIMEDOUT)
-- return 0;
-- else if (ret < 0)
-- return ret;
--
-- /* Trigger SGMII AN. */
-- return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-- VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
-+ return 0;
- }
-
- static void gpy_update_interface(struct phy_device *phydev)
- {
-- int ret;
--
- /* Interface mode is fixed for USXGMII and integrated PHY */
- if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
- phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
-@@ -306,29 +211,11 @@ static void gpy_update_interface(struct
- switch (phydev->speed) {
- case SPEED_2500:
- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-- VSPEC1_SGMII_CTRL_ANEN, 0);
-- if (ret < 0)
-- phydev_err(phydev,
-- "Error: Disable of SGMII ANEG failed: %d\n",
-- ret);
- break;
- case SPEED_1000:
- case SPEED_100:
- case SPEED_10:
- phydev->interface = PHY_INTERFACE_MODE_SGMII;
-- if (gpy_sgmii_aneg_en(phydev))
-- break;
-- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
-- * if ANEG is disabled (in 2500-BaseX mode).
-- */
-- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-- VSPEC1_SGMII_ANEN_ANRS,
-- VSPEC1_SGMII_ANEN_ANRS);
-- if (ret < 0)
-- phydev_err(phydev,
-- "Error: Enable of SGMII ANEG failed: %d\n",
-- ret);
- break;
- }
- }
--- /dev/null
+From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 13 Jun 2023 03:27:14 +0100
+Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default
+ state
+
+Initialize LEDs and set sane default values.
+Read boottrap register and apply LED polarities accordingly to get
+uniform behavior from all LEDs on MT7988.
+Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
+which should point to the syscon holding the boottrap register.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++--
+ 1 file changed, 136 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/phy/mediatek-ge-soc.c
++++ b/drivers/net/phy/mediatek-ge-soc.c
+@@ -1,11 +1,13 @@
+ // SPDX-License-Identifier: GPL-2.0+
+ #include <linux/bitfield.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/nvmem-consumer.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/phy.h>
++#include <linux/regmap.h>
+
+ #define MTK_GPHY_ID_MT7981 0x03a29461
+ #define MTK_GPHY_ID_MT7988 0x03a29481
+@@ -208,9 +210,40 @@
+ #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
+ #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
+
++/* Registers on MDIO_MMD_VEND2 */
++#define MTK_PHY_LED0_ON_CTRL 0x24
++#define MTK_PHY_LED1_ON_CTRL 0x26
++#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
++#define MTK_PHY_LED_ON_LINK1000 BIT(0)
++#define MTK_PHY_LED_ON_LINK100 BIT(1)
++#define MTK_PHY_LED_ON_LINK10 BIT(2)
++#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
++#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
++#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
++#define MTK_PHY_LED_FORCE_ON BIT(6)
++#define MTK_PHY_LED_POLARITY BIT(14)
++#define MTK_PHY_LED_ENABLE BIT(15)
++
++#define MTK_PHY_LED0_BLINK_CTRL 0x25
++#define MTK_PHY_LED1_BLINK_CTRL 0x27
++#define MTK_PHY_LED_1000TX BIT(0)
++#define MTK_PHY_LED_1000RX BIT(1)
++#define MTK_PHY_LED_100TX BIT(2)
++#define MTK_PHY_LED_100RX BIT(3)
++#define MTK_PHY_LED_10TX BIT(4)
++#define MTK_PHY_LED_10RX BIT(5)
++#define MTK_PHY_LED_COLLISION BIT(6)
++#define MTK_PHY_LED_RX_CRC_ERR BIT(7)
++#define MTK_PHY_LED_RX_IDLE_ERR BIT(8)
++#define MTK_PHY_LED_FORCE_BLINK BIT(9)
++
+ #define MTK_PHY_RG_BG_RASEL 0x115
+ #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
+
++/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */
++#define RG_GPIO_MISC_TPBANK0 0x6f0
++#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
++
+ /* These macro privides efuse parsing for internal phy. */
+ #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
+ #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
+@@ -238,13 +271,6 @@ enum {
+ PAIR_D,
+ };
+
+-enum {
+- GPHY_PORT0,
+- GPHY_PORT1,
+- GPHY_PORT2,
+- GPHY_PORT3,
+-};
+-
+ enum calibration_mode {
+ EFUSE_K,
+ SW_K
+@@ -263,6 +289,10 @@ enum CAL_MODE {
+ SW_M
+ };
+
++struct mtk_socphy_shared {
++ u32 boottrap;
++};
++
+ static int mtk_socphy_read_page(struct phy_device *phydev)
+ {
+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct
+ return mt798x_phy_calibration(phydev);
+ }
+
++static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted)
++{
++ struct pinctrl *pinctrl;
++ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE |
++ MTK_PHY_LED_ON_LINK1000 |
++ MTK_PHY_LED_ON_LINK100 |
++ MTK_PHY_LED_ON_LINK10;
++ const u16 led_blink_defaults = MTK_PHY_LED_1000TX |
++ MTK_PHY_LED_1000RX |
++ MTK_PHY_LED_100TX |
++ MTK_PHY_LED_100RX |
++ MTK_PHY_LED_10TX |
++ MTK_PHY_LED_10RX;
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
++ led_on_ctrl_defaults ^
++ (inverted ? MTK_PHY_LED_POLARITY : 0));
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
++ led_on_ctrl_defaults);
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
++ led_blink_defaults);
++
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
++ led_blink_defaults);
++
++ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
++ if (IS_ERR(pinctrl))
++ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n");
++
++ return 0;
++}
++
++static int mt7988_phy_probe_shared(struct phy_device *phydev)
++{
++ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
++ struct mtk_socphy_shared *priv = phydev->shared->priv;
++ struct regmap *regmap;
++ u32 reg;
++ int ret;
++
++ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
++ * LED_C and LED_D respectively. At the same time those pins are used to
++ * bootstrap configuration of the reference clock source (LED_A),
++ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
++ * In practise this is done using a LED and a resistor pulling the pin
++ * either to GND or to VIO.
++ * The detected value at boot time is accessible at run-time using the
++ * TPBANK0 register located in the gpio base of the pinctrl, in order
++ * to read it here it needs to be referenced by a phandle called
++ * 'mediatek,pio' in the MDIO bus hosting the PHY.
++ * The 4 bits in TPBANK0 are kept as package shared data and are used to
++ * set LED polarity for each of the LED0.
++ */
++ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
++ if (IS_ERR(regmap))
++ return PTR_ERR(regmap);
++
++ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®);
++ if (ret)
++ return ret;
++
++ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
++
++ return 0;
++}
++
++static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev)
++{
++ struct mtk_socphy_shared *priv = phydev->shared->priv;
++
++ if (priv->boottrap & BIT(phydev->mdio.addr))
++ return false;
++
++ return true;
++}
++
++static int mt7988_phy_probe(struct phy_device *phydev)
++{
++ int err;
++
++ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
++ sizeof(struct mtk_socphy_shared));
++ if (err)
++ return err;
++
++ if (phy_package_probe_once(phydev)) {
++ err = mt7988_phy_probe_shared(phydev);
++ if (err)
++ return err;
++ }
++
++ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
++
++ return mt798x_phy_calibration(phydev);
++}
++
+ static struct phy_driver mtk_socphy_driver[] = {
+ {
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
+@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv
+ .config_init = mt798x_phy_config_init,
+ .config_intr = genphy_no_config_intr,
+ .handle_interrupt = genphy_handle_interrupt_no_ack,
+- .probe = mt798x_phy_calibration,
++ .probe = mt7988_phy_probe,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .read_page = mtk_socphy_read_page,
+++ /dev/null
-From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 28 Feb 2023 17:53:37 +0000
-Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig | 7 ++
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
- 3 files changed, 226 insertions(+)
- create mode 100644 drivers/net/phy/mediatek-2p5ge.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -305,6 +305,13 @@ config MEDIATEK_GE_SOC_PHY
- present in the SoCs efuse and will dynamically calibrate VCM
- (common-mode voltage) during startup.
-
-+config MEDIATEK_2P5G_PHY
-+ tristate "MediaTek 2.5G Ethernet PHY"
-+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+ default NET_MEDIATEK_SOC
-+ help
-+ Supports the MediaTek 2.5G Ethernet PHY.
-+
- config MICREL_PHY
- tristate "Micrel PHYs"
- help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
- obj-$(CONFIG_MARVELL_PHY) += marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
-+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o
- obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
- obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
--- /dev/null
+From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 6 Apr 2023 23:36:50 +0100
+Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
+
+MAC drivers using phylink expect SGMII in-band-status to be switched off
+when attached to a PHY. Make sure this is the case also for mxl-gpy which
+keeps SGMII in-band-status in case of SGMII interface mode is used.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
+ 1 file changed, 16 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/mxl-gpy.c
++++ b/drivers/net/phy/mxl-gpy.c
+@@ -367,8 +367,11 @@ static bool gpy_2500basex_chk(struct phy
+
+ phydev->speed = SPEED_2500;
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+- VSPEC1_SGMII_CTRL_ANEN, 0);
++
++ if (!phydev->phylink)
++ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
++ VSPEC1_SGMII_CTRL_ANEN, 0);
++
+ return true;
+ }
+
+@@ -392,6 +395,14 @@ static int gpy_config_aneg(struct phy_de
+ u32 adv;
+ int ret;
+
++ /* Disable SGMII auto-negotiation if using phylink */
++ if (phydev->phylink) {
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
++ VSPEC1_SGMII_CTRL_ANEN, 0);
++ if (ret < 0)
++ return ret;
++ }
++
+ if (phydev->autoneg == AUTONEG_DISABLE) {
+ /* Configure half duplex with genphy_setup_forced,
+ * because genphy_c45_pma_setup_forced does not support.
+@@ -482,6 +493,8 @@ static void gpy_update_interface(struct
+ switch (phydev->speed) {
+ case SPEED_2500:
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++ if (phydev->phylink)
++ break;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
+ VSPEC1_SGMII_CTRL_ANEN, 0);
+ if (ret < 0)
+@@ -493,7 +506,7 @@ static void gpy_update_interface(struct
+ case SPEED_100:
+ case SPEED_10:
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
+- if (gpy_sgmii_aneg_en(phydev))
++ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
+ break;
+ /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
+ * if ANEG is disabled (in 2500-BaseX mode).
--- /dev/null
+From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 28 Feb 2023 17:53:37 +0000
+Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/Kconfig | 7 ++
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
+ 3 files changed, 226 insertions(+)
+ create mode 100644 drivers/net/phy/mediatek-2p5ge.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -319,6 +319,13 @@ config MEDIATEK_GE_SOC_PHY
+ present in the SoCs efuse and will dynamically calibrate VCM
+ (common-mode voltage) during startup.
+
++config MEDIATEK_2P5G_PHY
++ tristate "MediaTek 2.5G Ethernet PHY"
++ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
++ default NET_MEDIATEK_SOC
++ help
++ Supports the MediaTek 2.5G Ethernet PHY.
++
+ config MICREL_PHY
+ tristate "Micrel PHYs"
+ depends on PTP_1588_CLOCK_OPTIONAL
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -83,6 +83,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
+ obj-$(CONFIG_MARVELL_PHY) += marvell.o
+ obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
+ obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
++obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o
+ obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
+ obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
+ obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
+++ /dev/null
-From 41ffe32e7ec23f592e21c508b5108899ad393059 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Tue, 25 Jan 2022 16:50:47 +0800
-Subject: [PATCH 4/5] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support
-
-Add PCIe 2 lane efuse support in tphy driver.
-
-Signed-off-by: Jie Yang <jieyy.yang@mediatek.com>
-Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 140 ++++++++++++++++++++++++++++
- 1 file changed, 140 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -44,6 +44,15 @@
- #define SSUSB_SIFSLV_V2_U3PHYD 0x200
- #define SSUSB_SIFSLV_V2_U3PHYA 0x400
-
-+/* version V4 sub-banks offset base address */
-+/* pcie phy banks */
-+#define SSUSB_SIFSLV_V4_SPLLC 0x000
-+#define SSUSB_SIFSLV_V4_CHIP 0x100
-+#define SSUSB_SIFSLV_V4_U3PHYD 0x900
-+#define SSUSB_SIFSLV_V4_U3PHYA 0xb00
-+
-+#define SSUSB_LN1_OFFSET 0x10000
-+
- #define U3P_MISC_REG1 0x04
- #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6)
-
-@@ -320,6 +329,7 @@ enum mtk_phy_version {
- MTK_PHY_V1 = 1,
- MTK_PHY_V2,
- MTK_PHY_V3,
-+ MTK_PHY_V4,
- };
-
- struct mtk_phy_pdata {
-@@ -369,6 +379,9 @@ struct mtk_phy_instance {
- u32 efuse_intr;
- u32 efuse_tx_imp;
- u32 efuse_rx_imp;
-+ u32 efuse_intr_ln1;
-+ u32 efuse_tx_imp_ln1;
-+ u32 efuse_rx_imp_ln1;
- int eye_src;
- int eye_vrt;
- int eye_term;
-@@ -946,6 +959,36 @@ static void phy_v2_banks_init(struct mtk
- }
- }
-
-+static void phy_v4_banks_init(struct mtk_tphy *tphy,
-+ struct mtk_phy_instance *instance)
-+{
-+ struct u2phy_banks *u2_banks = &instance->u2_banks;
-+ struct u3phy_banks *u3_banks = &instance->u3_banks;
-+
-+ switch (instance->type) {
-+ case PHY_TYPE_USB2:
-+ u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
-+ u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
-+ u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
-+ break;
-+ case PHY_TYPE_USB3:
-+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
-+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
-+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
-+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
-+ break;
-+ case PHY_TYPE_PCIE:
-+ u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC;
-+ u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP;
-+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD;
-+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA;
-+ break;
-+ default:
-+ dev_err(tphy->dev, "incompatible PHY type\n");
-+ return;
-+ }
-+}
-+
- static void phy_parse_property(struct mtk_tphy *tphy,
- struct mtk_phy_instance *instance)
- {
-@@ -1144,6 +1187,40 @@ static int phy_efuse_get(struct mtk_tphy
-
- dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
- instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
-+
-+ if (tphy->pdata->version != MTK_PHY_V4)
-+ break;
-+
-+ ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
-+ if (ret) {
-+ dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-+ break;
-+ }
-+
-+ ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1);
-+ if (ret) {
-+ dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret);
-+ break;
-+ }
-+
-+ ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1);
-+ if (ret) {
-+ dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret);
-+ break;
-+ }
-+
-+ /* no efuse, ignore it */
-+ if (!instance->efuse_intr_ln1 &&
-+ !instance->efuse_rx_imp_ln1 &&
-+ !instance->efuse_tx_imp_ln1) {
-+ dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n");
-+ instance->efuse_sw_en = 0;
-+ break;
-+ }
-+
-+ dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n",
-+ instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1,
-+ instance->efuse_tx_imp_ln1);
- break;
- default:
- dev_err(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1175,6 +1252,31 @@ static void phy_efuse_set(struct mtk_phy
- writel(tmp, u2_banks->com + U3P_USBPHYACR1);
- break;
- case PHY_TYPE_USB3:
-+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
-+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-+
-+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
-+ tmp &= ~P3D_RG_TX_IMPEL;
-+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp);
-+ tmp |= P3D_RG_FORCE_TX_IMPEL;
-+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
-+
-+ tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
-+ tmp &= ~P3D_RG_RX_IMPEL;
-+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp);
-+ tmp |= P3D_RG_FORCE_RX_IMPEL;
-+ writel(tmp, u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
-+
-+ tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
-+ tmp &= ~P3A_RG_IEXT_INTR;
-+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
-+ writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-+ pr_err("%s set efuse, tx_imp %x, rx_imp %x intr %x\n",
-+ __func__, instance->efuse_tx_imp,
-+ instance->efuse_rx_imp, instance->efuse_intr);
-+
-+ break;
- case PHY_TYPE_PCIE:
- tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-@@ -1196,6 +1298,34 @@ static void phy_efuse_set(struct mtk_phy
- tmp &= ~P3A_RG_IEXT_INTR;
- tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
- writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-+ if (!instance->efuse_intr_ln1 &&
-+ !instance->efuse_rx_imp_ln1 &&
-+ !instance->efuse_tx_imp_ln1)
-+ break;
-+
-+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
-+ tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
-+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
-+
-+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
-+ tmp &= ~P3D_RG_TX_IMPEL;
-+ tmp |= P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp_ln1);
-+ tmp |= P3D_RG_FORCE_TX_IMPEL;
-+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0);
-+
-+ tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
-+ tmp &= ~P3D_RG_RX_IMPEL;
-+ tmp |= P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp_ln1);
-+ tmp |= P3D_RG_FORCE_RX_IMPEL;
-+ writel(tmp, u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1);
-+
-+ tmp = readl(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
-+ tmp &= ~P3A_RG_IEXT_INTR;
-+ tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr_ln1);
-+ writel(tmp, u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0);
-+ dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n",
-+ __func__, instance->efuse_tx_imp_ln1,
-+ instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1);
- break;
- default:
- dev_warn(dev, "no sw efuse for type %d\n", instance->type);
-@@ -1335,6 +1465,9 @@ static struct phy *mtk_phy_xlate(struct
- case MTK_PHY_V3:
- phy_v2_banks_init(tphy, instance);
- break;
-+ case MTK_PHY_V4:
-+ phy_v4_banks_init(tphy, instance);
-+ break;
- default:
- dev_err(dev, "phy version is not supported\n");
- return ERR_PTR(-EINVAL);
-@@ -1375,6 +1508,12 @@ static const struct mtk_phy_pdata tphy_v
- .version = MTK_PHY_V3,
- };
-
-+static const struct mtk_phy_pdata tphy_v4_pdata = {
-+ .avoid_rx_sen_degradation = false,
-+ .sw_efuse_supported = true,
-+ .version = MTK_PHY_V4,
-+};
-+
- static const struct mtk_phy_pdata mt8173_pdata = {
- .avoid_rx_sen_degradation = true,
- .version = MTK_PHY_V1,
-@@ -1394,6 +1533,7 @@ static const struct of_device_id mtk_tph
- { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
- { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
- { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
-+ { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata },
- { },
- };
- MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
+++ /dev/null
-From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
-From: Zhanyong Wang <zhanyong.wang@mediatek.com>
-Date: Tue, 25 Jan 2022 19:03:34 +0800
-Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
- support
-
-add auto-load-valid check mechanism support
-
-Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
- 1 file changed, 64 insertions(+), 3 deletions(-)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -376,9 +376,13 @@ struct mtk_phy_instance {
- u32 type_sw_reg;
- u32 type_sw_index;
- u32 efuse_sw_en;
-+ bool efuse_alv_en;
-+ u32 efuse_autoloadvalid;
- u32 efuse_intr;
- u32 efuse_tx_imp;
- u32 efuse_rx_imp;
-+ bool efuse_alv_ln1_en;
-+ u32 efuse_ln1_autoloadvalid;
- u32 efuse_intr_ln1;
- u32 efuse_tx_imp_ln1;
- u32 efuse_rx_imp_ln1;
-@@ -1126,6 +1130,7 @@ static int phy_efuse_get(struct mtk_tphy
- {
- struct device *dev = &instance->phy->dev;
- int ret = 0;
-+ bool alv = false;
-
- /* tphy v1 doesn't support sw efuse, skip it */
- if (!tphy->pdata->sw_efuse_supported) {
-@@ -1140,6 +1145,20 @@ static int phy_efuse_get(struct mtk_tphy
-
- switch (instance->type) {
- case PHY_TYPE_USB2:
-+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
-+ if (alv) {
-+ instance->efuse_alv_en = alv;
-+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
-+ &instance->efuse_autoloadvalid);
-+ if (ret) {
-+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
-+ break;
-+ }
-+ dev_info(dev,
-+ "u2 auto load valid efuse: ENABLE with value: %u\n",
-+ instance->efuse_autoloadvalid);
-+ }
-+
- ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
- if (ret) {
- dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
-@@ -1158,6 +1177,20 @@ static int phy_efuse_get(struct mtk_tphy
-
- case PHY_TYPE_USB3:
- case PHY_TYPE_PCIE:
-+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
-+ if (alv) {
-+ instance->efuse_alv_en = alv;
-+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
-+ &instance->efuse_autoloadvalid);
-+ if (ret) {
-+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
-+ break;
-+ }
-+ dev_info(dev,
-+ "u3 auto load valid efuse: ENABLE with value: %u\n",
-+ instance->efuse_autoloadvalid);
-+ }
-+
- ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
- if (ret) {
- dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
-@@ -1191,6 +1224,20 @@ static int phy_efuse_get(struct mtk_tphy
- if (tphy->pdata->version != MTK_PHY_V4)
- break;
-
-+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
-+ if (alv) {
-+ instance->efuse_alv_ln1_en = alv;
-+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
-+ &instance->efuse_ln1_autoloadvalid);
-+ if (ret) {
-+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
-+ break;
-+ }
-+ dev_info(dev,
-+ "pcie auto load valid efuse: ENABLE with value: %u\n",
-+ instance->efuse_ln1_autoloadvalid);
-+ }
-+
- ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
- if (ret) {
- dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
-@@ -1242,6 +1289,10 @@ static void phy_efuse_set(struct mtk_phy
-
- switch (instance->type) {
- case PHY_TYPE_USB2:
-+ if (instance->efuse_alv_en &&
-+ instance->efuse_autoloadvalid == 1)
-+ break;
-+
- tmp = readl(u2_banks->misc + U3P_MISC_REG1);
- tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
- writel(tmp, u2_banks->misc + U3P_MISC_REG1);
-@@ -1252,6 +1303,10 @@ static void phy_efuse_set(struct mtk_phy
- writel(tmp, u2_banks->com + U3P_USBPHYACR1);
- break;
- case PHY_TYPE_USB3:
-+ if (instance->efuse_alv_en &&
-+ instance->efuse_autoloadvalid == 1)
-+ break;
-+
- tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
- writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1278,6 +1333,10 @@ static void phy_efuse_set(struct mtk_phy
-
- break;
- case PHY_TYPE_PCIE:
-+ if (instance->efuse_alv_en &&
-+ instance->efuse_autoloadvalid == 1)
-+ break;
-+
- tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
- tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
- writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
-@@ -1298,9 +1357,12 @@ static void phy_efuse_set(struct mtk_phy
- tmp &= ~P3A_RG_IEXT_INTR;
- tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
- writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
-- if (!instance->efuse_intr_ln1 &&
-- !instance->efuse_rx_imp_ln1 &&
-- !instance->efuse_tx_imp_ln1)
-+
-+ if ((!instance->efuse_intr_ln1 &&
-+ !instance->efuse_rx_imp_ln1 &&
-+ !instance->efuse_tx_imp_ln1) ||
-+ (instance->efuse_alv_ln1_en &&
-+ instance->efuse_ln1_autoloadvalid == 1))
- break;
-
- tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
-@@ -302,6 +302,12 @@ static const struct pwm_mediatek_of_data
+@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data
.has_ck_26m_sel = true,
};
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = false,
-@@ -314,6 +320,7 @@ static const struct of_device_id pwm_med
+@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med
{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
+ { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
- { },
/*
* The first read of a sensor often contains very high bogus
-@@ -1085,6 +1083,11 @@ static int mtk_thermal_probe(struct plat
+@@ -1075,6 +1073,11 @@ static int mtk_thermal_probe(struct plat
mtk_thermal_release_periodic_ts(mt, auxadc_base);
}
.compatible = "mediatek,mt8183-thermal",
.data = (void *)&mt8183_thermal_data,
}, {
-@@ -1078,15 +1196,24 @@ static int mtk_thermal_probe(struct plat
+@@ -1068,15 +1186,24 @@ static int mtk_thermal_probe(struct plat
goto err_disable_clk_auxadc;
}
+++ /dev/null
-From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:25:51 +0100
-Subject: [PATCH] pwm: mediatek: Add support for MT7981
-
-The PWM unit on MT7981 uses different register offsets than previous
-MediaTek PWM units. Add support for these new offsets and add support
-for PWM on MT7981 which has 3 PWM channels, one of them is typically
-used for a temperature controlled fan.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
- 1 file changed, 33 insertions(+), 8 deletions(-)
-
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
- unsigned int num_pwms;
- bool pwm45_fixup;
- bool has_ck_26m_sel;
-+ const unsigned int *reg_offset;
- };
-
- /**
-@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
- const struct pwm_mediatek_of_data *soc;
- };
-
--static const unsigned int pwm_mediatek_reg_offset[] = {
-+static const unsigned int mtk_pwm_reg_offset_v1[] = {
- 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
- };
-
-+static const unsigned int mtk_pwm_reg_offset_v2[] = {
-+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
-+};
-+
- static inline struct pwm_mediatek_chip *
- to_pwm_mediatek_chip(struct pwm_chip *chip)
- {
-@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
- unsigned int num, unsigned int offset,
- u32 value)
- {
-- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
-+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
- }
-
- static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
-@@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
- .num_pwms = 8,
- .pwm45_fixup = false,
- .has_ck_26m_sel = false,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct pwm_mediatek_of_data mt7622_pwm_data = {
- .num_pwms = 6,
- .pwm45_fixup = false,
- .has_ck_26m_sel = true,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct pwm_mediatek_of_data mt7623_pwm_data = {
- .num_pwms = 5,
- .pwm45_fixup = true,
- .has_ck_26m_sel = false,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct pwm_mediatek_of_data mt7628_pwm_data = {
- .num_pwms = 4,
- .pwm45_fixup = true,
- .has_ck_26m_sel = false,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct pwm_mediatek_of_data mt7629_pwm_data = {
- .num_pwms = 1,
- .pwm45_fixup = false,
- .has_ck_26m_sel = false,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- .num_pwms = 4,
- .pwm45_fixup = false,
- .has_ck_26m_sel = true,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
-+};
-+
-+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
-+ .num_pwms = 3,
-+ .pwm45_fixup = false,
-+ .has_ck_26m_sel = true,
-+ .reg_offset = mtk_pwm_reg_offset_v2,
- };
-
- static const struct pwm_mediatek_of_data mt7986_pwm_data = {
- .num_pwms = 2,
- .pwm45_fixup = false,
- .has_ck_26m_sel = true,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- .num_pwms = 5,
- .pwm45_fixup = false,
- .has_ck_26m_sel = true,
-+ .reg_offset = mtk_pwm_reg_offset_v1,
- };
-
- static const struct of_device_id pwm_mediatek_of_match[] = {
-@@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
- { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
- { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
+++ /dev/null
-From 26564c44357e19d03c124550bbd0b5851e6638c2 Mon Sep 17 00:00:00 2001
-From: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Date: Fri, 24 Sep 2021 16:06:28 +0800
-Subject: [PATCH] dt-bindings: pinctrl: mt8195: add rsel define
-
-This patch adds rsel define for mt8195.
-
-Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20210924080632.28410-2-zhiyong.tao@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- include/dt-bindings/pinctrl/mt65xx.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/include/dt-bindings/pinctrl/mt65xx.h
-+++ b/include/dt-bindings/pinctrl/mt65xx.h
-@@ -16,6 +16,15 @@
- #define MTK_PUPD_SET_R1R0_10 102
- #define MTK_PUPD_SET_R1R0_11 103
-
-+#define MTK_PULL_SET_RSEL_000 200
-+#define MTK_PULL_SET_RSEL_001 201
-+#define MTK_PULL_SET_RSEL_010 202
-+#define MTK_PULL_SET_RSEL_011 203
-+#define MTK_PULL_SET_RSEL_100 204
-+#define MTK_PULL_SET_RSEL_101 205
-+#define MTK_PULL_SET_RSEL_110 206
-+#define MTK_PULL_SET_RSEL_111 207
-+
- #define MTK_DRIVE_2mA 2
- #define MTK_DRIVE_4mA 4
- #define MTK_DRIVE_6mA 6
+++ /dev/null
-From d8b94c9ff96c2024a527086d850eb0b314337ff9 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 14 Sep 2021 16:51:32 +0800
-Subject: [PATCH] pinctrl: mediatek: moore: check if pin_desc is valid before
- use
-
-Certain SoC are missing the middle part gpios in consecutive pins,
-it's better to check if mtk_pin_desc is a valid pin for the extensibility
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Acked-by: Sean Wang <sean.wang@mediatek.com>
-Link: https://lore.kernel.org/r/20210914085137.31761-5-sam.shih@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pin
- int pin = grp->pins[i];
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- pin_modes[i]);
-@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enabl
- const struct mtk_pin_desc *desc;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
- hw->soc->gpio_m);
-@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction
- const struct mtk_pin_desc *desc;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- /* hardware would take 0 as input direction */
- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
-@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctr
- const struct mtk_pin_desc *desc;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
-@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctr
- int cfg, err = 0;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- for (cfg = 0; cfg < num_configs; cfg++) {
- param = pinconf_to_config_param(configs[cfg]);
-@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip
- int value, err;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
- if (err)
-@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chi
- const struct mtk_pin_desc *desc;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
-+ if (!desc->name) {
-+ dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
-+ return;
-+ }
-
- mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
- }
-@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gp
- u32 debounce;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
-+ if (!desc->name)
-+ return -ENOTSUPP;
-
- if (!hw->eint ||
- pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
+++ /dev/null
-From fb34a9ae383ae26326d4889fd2513e49f1019b88 Mon Sep 17 00:00:00 2001
-From: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Date: Fri, 24 Sep 2021 16:06:31 +0800
-Subject: [PATCH] pinctrl: mediatek: support rsel feature
-
-This patch supports rsel(resistance selection) feature for I2C pins.
-It provides more resistance selection solution in different ICs.
-It provides rsel define and si unit solution by identifying
-"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node.
-
-Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Link: https://lore.kernel.org/r/20210924080632.28410-5-zhiyong.tao@mediatek.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 231 +++++++++++++++---
- .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 46 ++++
- drivers/pinctrl/mediatek/pinctrl-paris.c | 60 +++--
- 3 files changed, 289 insertions(+), 48 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -665,6 +665,181 @@ out:
- return err;
- }
-
-+static int mtk_hw_pin_rsel_lookup(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg, u32 *rsel_val)
-+{
-+ const struct mtk_pin_rsel *rsel;
-+ int check;
-+ bool found = false;
-+
-+ rsel = hw->soc->pin_rsel;
-+
-+ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
-+ if (desc->number >= rsel[check].s_pin &&
-+ desc->number <= rsel[check].e_pin) {
-+ if (pullup) {
-+ if (rsel[check].up_rsel == arg) {
-+ found = true;
-+ *rsel_val = rsel[check].rsel_index;
-+ break;
-+ }
-+ } else {
-+ if (rsel[check].down_rsel == arg) {
-+ found = true;
-+ *rsel_val = rsel[check].rsel_index;
-+ break;
-+ }
-+ }
-+ }
-+ }
-+
-+ if (!found) {
-+ dev_err(hw->dev, "Not support rsel value %d Ohm for pin = %d (%s)\n",
-+ arg, desc->number, desc->name);
-+ return -ENOTSUPP;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_pinconf_bias_set_rsel(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg)
-+{
-+ int err, rsel_val;
-+
-+ if (hw->rsel_si_unit) {
-+ /* find pin rsel_index from pin_rsel array*/
-+ err = mtk_hw_pin_rsel_lookup(hw, desc, pullup, arg, &rsel_val);
-+ if (err)
-+ goto out;
-+ } else {
-+ if (arg < MTK_PULL_SET_RSEL_000 ||
-+ arg > MTK_PULL_SET_RSEL_111) {
-+ err = -EINVAL;
-+ goto out;
-+ }
-+
-+ rsel_val = arg - MTK_PULL_SET_RSEL_000;
-+ }
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_RSEL, rsel_val);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, MTK_ENABLE);
-+
-+out:
-+ return err;
-+}
-+
-+int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg)
-+{
-+ int err = -ENOTSUPP;
-+ u32 try_all_type;
-+
-+ if (hw->soc->pull_type)
-+ try_all_type = hw->soc->pull_type[desc->number];
-+ else
-+ try_all_type = MTK_PULL_TYPE_MASK;
-+
-+ if (try_all_type & MTK_PULL_RSEL_TYPE) {
-+ err = mtk_pinconf_bias_set_rsel(hw, desc, pullup, arg);
-+ if (!err)
-+ return err;
-+ }
-+
-+ if (try_all_type & MTK_PULL_PU_PD_TYPE) {
-+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
-+ if (!err)
-+ return err;
-+ }
-+
-+ if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
-+ err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc,
-+ pullup, arg);
-+ if (!err)
-+ return err;
-+ }
-+
-+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
-+ err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
-+
-+ if (err)
-+ dev_err(hw->dev, "Invalid pull argument\n");
-+
-+ return err;
-+}
-+EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
-+
-+static int mtk_rsel_get_si_unit(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 rsel_val, u32 *si_unit)
-+{
-+ const struct mtk_pin_rsel *rsel;
-+ int check;
-+
-+ rsel = hw->soc->pin_rsel;
-+
-+ for (check = 0; check <= hw->soc->npin_rsel - 1; check++) {
-+ if (desc->number >= rsel[check].s_pin &&
-+ desc->number <= rsel[check].e_pin) {
-+ if (rsel_val == rsel[check].rsel_index) {
-+ if (pullup)
-+ *si_unit = rsel[check].up_rsel;
-+ else
-+ *si_unit = rsel[check].down_rsel;
-+ break;
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_pinconf_bias_get_rsel(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 *pullup, u32 *enable)
-+{
-+ int pu, pd, rsel, err;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_RSEL, &rsel);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
-+ if (err)
-+ goto out;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+
-+ if (pu == 0 && pd == 0) {
-+ *pullup = 0;
-+ *enable = MTK_DISABLE;
-+ } else if (pu == 1 && pd == 0) {
-+ *pullup = 1;
-+ if (hw->rsel_si_unit)
-+ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
-+ else
-+ *enable = rsel + MTK_PULL_SET_RSEL_000;
-+ } else if (pu == 0 && pd == 1) {
-+ *pullup = 0;
-+ if (hw->rsel_si_unit)
-+ mtk_rsel_get_si_unit(hw, desc, *pullup, rsel, enable);
-+ else
-+ *enable = rsel + MTK_PULL_SET_RSEL_000;
-+ } else {
-+ err = -EINVAL;
-+ goto out;
-+ }
-+
-+out:
-+ return err;
-+}
-+
- static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc,
- u32 *pullup, u32 *enable)
-@@ -746,44 +921,40 @@ out:
- return err;
- }
-
--int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
-- const struct mtk_pin_desc *desc,
-- u32 pullup, u32 arg)
--{
-- int err;
--
-- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
-- if (!err)
-- goto out;
--
-- err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
-- if (!err)
-- goto out;
--
-- err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
--
--out:
-- return err;
--}
--EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
--
- int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc,
- u32 *pullup, u32 *enable)
- {
-- int err;
-+ int err = -ENOTSUPP;
-+ u32 try_all_type;
-
-- err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
-- if (!err)
-- goto out;
-+ if (hw->soc->pull_type)
-+ try_all_type = hw->soc->pull_type[desc->number];
-+ else
-+ try_all_type = MTK_PULL_TYPE_MASK;
-
-- err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
-- if (!err)
-- goto out;
-+ if (try_all_type & MTK_PULL_RSEL_TYPE) {
-+ err = mtk_pinconf_bias_get_rsel(hw, desc, pullup, enable);
-+ if (!err)
-+ return err;
-+ }
-+
-+ if (try_all_type & MTK_PULL_PU_PD_TYPE) {
-+ err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
-+ if (!err)
-+ return err;
-+ }
-+
-+ if (try_all_type & MTK_PULL_PULLSEL_TYPE) {
-+ err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc,
-+ pullup, enable);
-+ if (!err)
-+ return err;
-+ }
-
-- err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
-+ if (try_all_type & MTK_PULL_PUPD_R1R0_TYPE)
-+ err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
-
--out:
- return err;
- }
- EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-@@ -17,6 +17,22 @@
- #define MTK_ENABLE 1
- #define MTK_PULLDOWN 0
- #define MTK_PULLUP 1
-+#define MTK_PULL_PU_PD_TYPE BIT(0)
-+#define MTK_PULL_PULLSEL_TYPE BIT(1)
-+#define MTK_PULL_PUPD_R1R0_TYPE BIT(2)
-+/* MTK_PULL_RSEL_TYPE can select resistance and can be
-+ * turned on/off itself. But it can't be selected pull up/down
-+ */
-+#define MTK_PULL_RSEL_TYPE BIT(3)
-+/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
-+ * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
-+ */
-+#define MTK_PULL_PU_PD_RSEL_TYPE (MTK_PULL_PU_PD_TYPE \
-+ | MTK_PULL_RSEL_TYPE)
-+#define MTK_PULL_TYPE_MASK (MTK_PULL_PU_PD_TYPE |\
-+ MTK_PULL_PULLSEL_TYPE |\
-+ MTK_PULL_PUPD_R1R0_TYPE |\
-+ MTK_PULL_RSEL_TYPE)
-
- #define EINT_NA U16_MAX
- #define NO_EINT_SUPPORT EINT_NA
-@@ -42,6 +58,14 @@
- PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
- _x_bits, 32, 1)
-
-+#define PIN_RSEL(_s_pin, _e_pin, _rsel_index, _up_resl, _down_rsel) { \
-+ .s_pin = _s_pin, \
-+ .e_pin = _e_pin, \
-+ .rsel_index = _rsel_index, \
-+ .up_rsel = _up_resl, \
-+ .down_rsel = _down_rsel, \
-+ }
-+
- /* List these attributes which could be modified for the pin */
- enum {
- PINCTRL_PIN_REG_MODE,
-@@ -67,6 +91,7 @@ enum {
- PINCTRL_PIN_REG_DRV_E0,
- PINCTRL_PIN_REG_DRV_E1,
- PINCTRL_PIN_REG_DRV_ADV,
-+ PINCTRL_PIN_REG_RSEL,
- PINCTRL_PIN_REG_MAX,
- };
-
-@@ -129,6 +154,22 @@ struct mtk_pin_field_calc {
- u8 fixed;
- };
-
-+/**
-+ * struct mtk_pin_rsel - the structure that provides bias resistance selection.
-+ * @s_pin: the start pin within the rsel range
-+ * @e_pin: the end pin within the rsel range
-+ * @rsel_index: the rsel bias resistance index
-+ * @up_rsel: the pullup rsel bias resistance value
-+ * @down_rsel: the pulldown rsel bias resistance value
-+ */
-+struct mtk_pin_rsel {
-+ u16 s_pin;
-+ u16 e_pin;
-+ u16 rsel_index;
-+ u32 up_rsel;
-+ u32 down_rsel;
-+};
-+
- /* struct mtk_pin_reg_calc - the structure that holds all ranges used to
- * determine which register the pin would make use of
- * for certain pin attribute.
-@@ -206,6 +247,9 @@ struct mtk_pin_soc {
- bool ies_present;
- const char * const *base_names;
- unsigned int nbase_names;
-+ const unsigned int *pull_type;
-+ const struct mtk_pin_rsel *pin_rsel;
-+ unsigned int npin_rsel;
-
- /* Specific pinconfig operations */
- int (*bias_disable_set)(struct mtk_pinctrl *hw,
-@@ -254,6 +298,8 @@ struct mtk_pinctrl {
- const char **grp_names;
- /* lock pin's register resource to avoid multiple threads issue*/
- spinlock_t lock;
-+ /* identify rsel setting by si unit or rsel define in dts node */
-+ bool rsel_si_unit;
- };
-
- void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
---- a/drivers/pinctrl/mediatek/pinctrl-paris.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
-@@ -574,8 +574,9 @@ static int mtk_hw_get_value_wrap(struct
- ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
- unsigned int gpio, char *buf, unsigned int buf_len)
- {
-- int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1;
-+ int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
- const struct mtk_pin_desc *desc;
-+ u32 try_all_type;
-
- if (gpio >= hw->soc->npins)
- return -EINVAL;
-@@ -589,24 +590,39 @@ ssize_t mtk_pctrl_show_one_pin(struct mt
- pinmux -= hw->soc->nfuncs;
-
- mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
-- if (pullen == MTK_PUPD_SET_R1R0_00) {
-- pullen = 0;
-- r1 = 0;
-- r0 = 0;
-- } else if (pullen == MTK_PUPD_SET_R1R0_01) {
-- pullen = 1;
-- r1 = 0;
-- r0 = 1;
-- } else if (pullen == MTK_PUPD_SET_R1R0_10) {
-- pullen = 1;
-- r1 = 1;
-- r0 = 0;
-- } else if (pullen == MTK_PUPD_SET_R1R0_11) {
-+
-+ if (hw->soc->pull_type)
-+ try_all_type = hw->soc->pull_type[desc->number];
-+
-+ if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
-+ rsel = pullen;
- pullen = 1;
-- r1 = 1;
-- r0 = 1;
-- } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
-- pullen = 0;
-+ } else {
-+ /* Case for: R1R0 */
-+ if (pullen == MTK_PUPD_SET_R1R0_00) {
-+ pullen = 0;
-+ r1 = 0;
-+ r0 = 0;
-+ } else if (pullen == MTK_PUPD_SET_R1R0_01) {
-+ pullen = 1;
-+ r1 = 0;
-+ r0 = 1;
-+ } else if (pullen == MTK_PUPD_SET_R1R0_10) {
-+ pullen = 1;
-+ r1 = 1;
-+ r0 = 0;
-+ } else if (pullen == MTK_PUPD_SET_R1R0_11) {
-+ pullen = 1;
-+ r1 = 1;
-+ r0 = 1;
-+ }
-+
-+ /* Case for: RSEL */
-+ if (pullen >= MTK_PULL_SET_RSEL_000 &&
-+ pullen <= MTK_PULL_SET_RSEL_111) {
-+ rsel = pullen - MTK_PULL_SET_RSEL_000;
-+ pullen = 1;
-+ }
- }
- len += scnprintf(buf + len, buf_len - len,
- "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
-@@ -624,6 +640,8 @@ ssize_t mtk_pctrl_show_one_pin(struct mt
- if (r1 != -1) {
- len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n",
- r1, r0);
-+ } else if (rsel != -1) {
-+ len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel);
- } else {
- len += scnprintf(buf + len, buf_len - len, "\n");
- }
-@@ -966,6 +984,12 @@ int mtk_paris_pinctrl_probe(struct platf
-
- hw->nbase = hw->soc->nbase_names;
-
-+ if (of_find_property(hw->dev->of_node,
-+ "mediatek,rsel_resistance_in_si_unit", NULL))
-+ hw->rsel_si_unit = true;
-+ else
-+ hw->rsel_si_unit = false;
-+
- spin_lock_init(&hw->lock);
-
- err = mtk_pctrl_build_state(pdev);
+++ /dev/null
-From 9f9d17c228c89e38ed612500126daf626270be9a Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Sat, 27 Nov 2021 17:08:36 +0300
-Subject: [PATCH] pinctrl: mediatek: add a check for error in
- mtk_pinconf_bias_get_rsel()
-
-All the other mtk_hw_get_value() calls have a check for "if (err)" so
-we can add one here as well. This silences a Smatch warning:
-
- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c:819 mtk_pinconf_bias_get_rsel()
- error: uninitialized symbol 'pd'.
-
-Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Link: https://lore.kernel.org/r/20211127140836.GB24002@kili
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -815,6 +815,8 @@ static int mtk_pinconf_bias_get_rsel(str
- goto out;
-
- err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+ if (err)
-+ goto out;
-
- if (pu == 0 && pd == 0) {
- *pullup = 0;
+++ /dev/null
-From e1ff91f9d2303cd4e706cc908bfca21cd17b9927 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 11 Nov 2022 10:41:06 +0100
-Subject: [PATCH] pinctrl: mediatek: Fix EINT pins input debounce time
- configuration
-
-The External Interrupt Controller (EINTC) on all of the supported
-MediaTek SoCs does support input debouncing, but not all of them
-index the debounce time values (DBNC_SETTING registers) the same way.
-
-Before this change, in some cases, as an example, requesting a debounce
-time of 16 milliseconds would mistakenly set the relative DBNC_SETTING
-register to 0x2, resulting in a way shorter debounce time of 500uS.
-
-To fix the aforementioned issue, define three different debounce_time
-arrays, reflecting the correct register index for each value and for
-each register index variant, and make sure that each SoC pinctrl
-driver uses the right one.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/mtk-eint.c | 31 +++++++++++++++++++----
- drivers/pinctrl/mediatek/mtk-eint.h | 6 +++++
- drivers/pinctrl/mediatek/pinctrl-mt2701.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt2712.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt6765.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt6779.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt7629.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8127.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8135.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8167.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8173.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8183.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8192.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt8516.c | 1 +
- 22 files changed, 53 insertions(+), 5 deletions(-)
-
---- a/drivers/pinctrl/mediatek/mtk-eint.c
-+++ b/drivers/pinctrl/mediatek/mtk-eint.c
-@@ -24,6 +24,7 @@
- #define MTK_EINT_EDGE_SENSITIVE 0
- #define MTK_EINT_LEVEL_SENSITIVE 1
- #define MTK_EINT_DBNC_SET_DBNC_BITS 4
-+#define MTK_EINT_DBNC_MAX 16
- #define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
- #define MTK_EINT_DBNC_SET_EN (0x1 << 0)
-
-@@ -48,6 +49,18 @@ static const struct mtk_eint_regs mtk_ge
- .dbnc_clr = 0x700,
- };
-
-+const unsigned int debounce_time_mt2701[] = {
-+ 500, 1000, 16000, 32000, 64000, 128000, 256000, 0
-+};
-+
-+const unsigned int debounce_time_mt6765[] = {
-+ 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
-+};
-+
-+const unsigned int debounce_time_mt6795[] = {
-+ 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
-+};
-+
- static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
- unsigned int eint_num,
- unsigned int offset)
-@@ -407,10 +420,11 @@ int mtk_eint_set_debounce(struct mtk_ein
- int virq, eint_offset;
- unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
- dbnc;
-- static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
-- 64000, 128000, 256000};
- struct irq_data *d;
-
-+ if (!eint->hw->db_time)
-+ return -EOPNOTSUPP;
-+
- virq = irq_find_mapping(eint->domain, eint_num);
- eint_offset = (eint_num % 4) * 8;
- d = irq_get_irq_data(virq);
-@@ -421,9 +435,9 @@ int mtk_eint_set_debounce(struct mtk_ein
- if (!mtk_eint_can_en_debounce(eint, eint_num))
- return -EINVAL;
-
-- dbnc = ARRAY_SIZE(debounce_time);
-- for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
-- if (debounce <= debounce_time[i]) {
-+ dbnc = eint->num_db_time;
-+ for (i = 0; i < eint->num_db_time; i++) {
-+ if (debounce <= eint->hw->db_time[i]) {
- dbnc = i;
- break;
- }
-@@ -497,6 +511,13 @@ int mtk_eint_do_init(struct mtk_eint *ei
- if (!eint->domain)
- return -ENOMEM;
-
-+ if (eint->hw->db_time) {
-+ for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
-+ if (eint->hw->db_time[i] == 0)
-+ break;
-+ eint->num_db_time = i;
-+ }
-+
- mtk_eint_hw_init(eint);
- for (i = 0; i < eint->hw->ap_num; i++) {
- int virq = irq_create_mapping(eint->domain, i);
---- a/drivers/pinctrl/mediatek/mtk-eint.h
-+++ b/drivers/pinctrl/mediatek/mtk-eint.h
-@@ -37,8 +37,13 @@ struct mtk_eint_hw {
- u8 ports;
- unsigned int ap_num;
- unsigned int db_cnt;
-+ const unsigned int *db_time;
- };
-
-+extern const unsigned int debounce_time_mt2701[];
-+extern const unsigned int debounce_time_mt6765[];
-+extern const unsigned int debounce_time_mt6795[];
-+
- struct mtk_eint;
-
- struct mtk_eint_xt {
-@@ -62,6 +67,7 @@ struct mtk_eint {
- /* Used to fit into various EINT device */
- const struct mtk_eint_hw *hw;
- const struct mtk_eint_regs *regs;
-+ u16 num_db_time;
-
- /* Used to fit into various pinctrl device */
- void *pctl;
---- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
-@@ -531,6 +531,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 16,
-+ .db_time = debounce_time_mt2701,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
-@@ -584,6 +584,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 8,
- .ap_num = 229,
- .db_cnt = 40,
-+ .db_time = debounce_time_mt2701,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
-@@ -1062,6 +1062,7 @@ static const struct mtk_eint_hw mt6765_e
- .ports = 6,
- .ap_num = 160,
- .db_cnt = 13,
-+ .db_time = debounce_time_mt6765,
- };
-
- static const struct mtk_pin_soc mt6765_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
-@@ -737,6 +737,7 @@ static const struct mtk_eint_hw mt6779_e
- .ports = 6,
- .ap_num = 195,
- .db_cnt = 13,
-+ .db_time = debounce_time_mt2701,
- };
-
- static const struct mtk_pin_soc mt6779_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
-@@ -846,6 +846,7 @@ static const struct mtk_eint_hw mt7622_e
- .ports = 7,
- .ap_num = ARRAY_SIZE(mt7622_pins),
- .db_cnt = 20,
-+ .db_time = debounce_time_mt6765,
- };
-
- static const struct mtk_pin_soc mt7622_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
-@@ -1369,6 +1369,7 @@ static const struct mtk_eint_hw mt7623_e
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 20,
-+ .db_time = debounce_time_mt2701,
- };
-
- static struct mtk_pin_soc mt7623_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
-@@ -402,6 +402,7 @@ static const struct mtk_eint_hw mt7629_e
- .ports = 7,
- .ap_num = ARRAY_SIZE(mt7629_pins),
- .db_cnt = 16,
-+ .db_time = debounce_time_mt2701,
- };
-
- static struct mtk_pin_soc mt7629_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
-@@ -300,6 +300,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 6,
- .ap_num = 143,
- .db_cnt = 16,
-+ .db_time = debounce_time_mt2701,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
-@@ -313,6 +313,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 6,
- .ap_num = 192,
- .db_cnt = 16,
-+ .db_time = debounce_time_mt2701,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
-@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 64,
-+ .db_time = debounce_time_mt6795,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
-@@ -340,6 +340,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 6,
- .ap_num = 224,
- .db_cnt = 16,
-+ .db_time = debounce_time_mt2701,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
-@@ -545,6 +545,7 @@ static const struct mtk_eint_hw mt8183_e
- .ports = 6,
- .ap_num = 212,
- .db_cnt = 13,
-+ .db_time = debounce_time_mt6765,
- };
-
- static const struct mtk_pin_soc mt8183_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c
-@@ -1339,6 +1339,7 @@ static const struct mtk_eint_hw mt8192_e
- .ports = 7,
- .ap_num = 224,
- .db_cnt = 32,
-+ .db_time = debounce_time_mt6765,
- };
-
- static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c
-@@ -805,6 +805,7 @@ static const struct mtk_eint_hw mt8195_e
- .ports = 7,
- .ap_num = 225,
- .db_cnt = 32,
-+ .db_time = debounce_time_mt6765,
- };
-
- static const struct mtk_pin_soc mt8195_data = {
---- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c
-@@ -466,6 +466,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 5,
- .ap_num = 160,
- .db_cnt = 160,
-+ .db_time = debounce_time_mt6765,
- },
- };
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
-@@ -332,6 +332,7 @@ static const struct mtk_pinctrl_devdata
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 64,
-+ .db_time = debounce_time_mt6795,
- },
- };
-
+++ /dev/null
-From 2e35b25dd8e666b8619355fc3defb1b246a5dc02 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Tue, 15 Nov 2022 09:11:07 +0100
-Subject: [PATCH] pinctrl: mediatek: Export debounce time tables
-
-The kernel test robot complains that in certain combinations
-when building the Mediatek drivers as modules we lack some
-debounce table symbols, so export them.
-
-Reported-by: kernel test robot <lkp@intel.com>
-Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration")
-Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/mtk-eint.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/pinctrl/mediatek/mtk-eint.c
-+++ b/drivers/pinctrl/mediatek/mtk-eint.c
-@@ -52,14 +52,17 @@ static const struct mtk_eint_regs mtk_ge
- const unsigned int debounce_time_mt2701[] = {
- 500, 1000, 16000, 32000, 64000, 128000, 256000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt2701);
-
- const unsigned int debounce_time_mt6765[] = {
- 125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt6765);
-
- const unsigned int debounce_time_mt6795[] = {
- 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
- };
-+EXPORT_SYMBOL_GPL(debounce_time_mt6795);
-
- static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
- unsigned int eint_num,
+++ /dev/null
-From b77e70f6b8f2cc62fba847f3008a430a09ef275d Mon Sep 17 00:00:00 2001
-From: ChiYuan Huang <cy_huang@richtek.com>
-Date: Wed, 9 Mar 2022 16:01:42 +0800
-Subject: [PATCH 1/2] regulator: Add bindings for Richtek RT5190A PMIC
-
-Add bindings for Richtek RT5190A PMIC.
-
-Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
-Link: https://lore.kernel.org/r/1646812903-32496-2-git-send-email-u0084500@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../regulator/richtek,rt5190a-regulator.yaml | 141 ++++++++++++++++++
- .../regulator/richtek,rt5190a-regulator.h | 15 ++
- 2 files changed, 156 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
- create mode 100644 include/dt-bindings/regulator/richtek,rt5190a-regulator.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
-@@ -0,0 +1,141 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/richtek,rt5190a-regulator.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Richtek RT5190A PMIC Regulator
-+
-+maintainers:
-+ - ChiYuan Huang <cy_huang@richtek.com>
-+
-+description: |
-+ The RT5190A integrates 1 channel buck controller, 3 channels high efficiency
-+ synchronous buck converters, 1 LDO, I2C control interface and peripherial
-+ logical control.
-+
-+ It also supports mute AC OFF depop sound and quick setting storage while
-+ input power is removed.
-+
-+properties:
-+ compatible:
-+ enum:
-+ - richtek,rt5190a
-+
-+ reg:
-+ maxItems: 1
-+
-+ interrupts:
-+ maxItems: 1
-+
-+ vin2-supply:
-+ description: phandle to buck2 input voltage.
-+
-+ vin3-supply:
-+ description: phandle to buck3 input voltage.
-+
-+ vin4-supply:
-+ description: phandle to buck4 input voltage.
-+
-+ vinldo-supply:
-+ description: phandle to ldo input voltage
-+
-+ richtek,mute-enable:
-+ description: |
-+ The mute function uses 'mutein', 'muteout', and 'vdet' pins as the control
-+ signal. When enabled, The normal behavior is to bypass the 'mutein' signal
-+ 'muteout'. But if the power source removal is detected from 'vdet',
-+ whatever the 'mutein' signal is, it will pull down the 'muteout' to force
-+ speakers mute. this function is commonly used to prevent the speaker pop
-+ noise during AC power turned off in the modern TV system design.
-+ type: boolean
-+
-+ regulators:
-+ type: object
-+
-+ patternProperties:
-+ "^buck[1-4]$|^ldo$":
-+ type: object
-+ $ref: regulator.yaml#
-+ description: |
-+ regulator description for buck1 and buck4.
-+
-+ properties:
-+ regulator-allowed-modes:
-+ description: |
-+ buck operating mode, only buck1/4 support mode operating.
-+ 0: auto mode
-+ 1: force pwm mode
-+ items:
-+ enum: [0, 1]
-+
-+ richtek,latchup-enable:
-+ type: boolean
-+ description: |
-+ If specified, undervolt protection mode changes from the default
-+ hiccup to latchup.
-+
-+ unevaluatedProperties: false
-+
-+ additionalProperties: false
-+
-+required:
-+ - compatible
-+ - reg
-+ - regulators
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/interrupt-controller/irq.h>
-+ #include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-+
-+ i2c {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pmic@64 {
-+ compatible = "richtek,rt5190a";
-+ reg = <0x64>;
-+ interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
-+ vin2-supply = <&rt5190_buck1>;
-+ vin3-supply = <&rt5190_buck1>;
-+ vin4-supply = <&rt5190_buck1>;
-+
-+ regulators {
-+ rt5190_buck1: buck1 {
-+ regulator-name = "rt5190a-buck1";
-+ regulator-min-microvolt = <5090000>;
-+ regulator-max-microvolt = <5090000>;
-+ regulator-allowed-modes = <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-+ regulator-boot-on;
-+ };
-+ buck2 {
-+ regulator-name = "rt5190a-buck2";
-+ regulator-min-microvolt = <600000>;
-+ regulator-max-microvolt = <1400000>;
-+ regulator-boot-on;
-+ };
-+ buck3 {
-+ regulator-name = "rt5190a-buck3";
-+ regulator-min-microvolt = <600000>;
-+ regulator-max-microvolt = <1400000>;
-+ regulator-boot-on;
-+ };
-+ buck4 {
-+ regulator-name = "rt5190a-buck4";
-+ regulator-min-microvolt = <850000>;
-+ regulator-max-microvolt = <850000>;
-+ regulator-allowed-modes = <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
-+ regulator-boot-on;
-+ };
-+ ldo {
-+ regulator-name = "rt5190a-ldo";
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-boot-on;
-+ };
-+ };
-+ };
-+ };
---- /dev/null
-+++ b/include/dt-bindings/regulator/richtek,rt5190a-regulator.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+
-+#ifndef __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__
-+#define __DT_BINDINGS_RICHTEK_RT5190A_REGULATOR_H__
-+
-+/*
-+ * BUCK/LDO mode constants which may be used in devicetree properties
-+ * (eg. regulator-allowed-modes).
-+ * See the manufacturer's datasheet for more information on these modes.
-+ */
-+
-+#define RT5190A_OPMODE_AUTO 0
-+#define RT5190A_OPMODE_FPWM 1
-+
-+#endif
+++ /dev/null
-From 760423dfad53877b468490758fe7ea968ded9402 Mon Sep 17 00:00:00 2001
-From: ChiYuan Huang <cy_huang@richtek.com>
-Date: Wed, 9 Mar 2022 16:01:43 +0800
-Subject: [PATCH 2/2] regulator: rt5190a: Add support for Richtek RT5190A PMIC
-
-Add support for Richtek RT5190A PMIC.
-
-Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
-Link: https://lore.kernel.org/r/1646812903-32496-3-git-send-email-u0084500@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/Kconfig | 10 +
- drivers/regulator/Makefile | 1 +
- drivers/regulator/rt5190a-regulator.c | 513 ++++++++++++++++++++++++++
- 3 files changed, 524 insertions(+)
- create mode 100644 drivers/regulator/rt5190a-regulator.c
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1037,6 +1037,16 @@ config REGULATOR_RT5033
- RT5033 PMIC. The device supports multiple regulators like
- current source, LDO and Buck.
-
-+config REGULATOR_RT5190A
-+ tristate "Richtek RT5190A PMIC"
-+ depends on I2C
-+ select REGMAP_I2C
-+ help
-+ This adds support for voltage regulator in Richtek RT5190A PMIC.
-+ It integratas 1 channel buck controller, 3 channels high efficiency
-+ buck converters, 1 LDO, mute AC OFF depop function, with the general
-+ I2C control interface.
-+
- config REGULATOR_RT6160
- tristate "Richtek RT6160 BuckBoost voltage regulator"
- depends on I2C
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -125,6 +125,7 @@ obj-$(CONFIG_REGULATOR_ROHM) += rohm-reg
- obj-$(CONFIG_REGULATOR_RT4801) += rt4801-regulator.o
- obj-$(CONFIG_REGULATOR_RT4831) += rt4831-regulator.o
- obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o
-+obj-$(CONFIG_REGULATOR_RT5190A) += rt5190a-regulator.o
- obj-$(CONFIG_REGULATOR_RT6160) += rt6160-regulator.o
- obj-$(CONFIG_REGULATOR_RT6245) += rt6245-regulator.o
- obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o
---- /dev/null
-+++ b/drivers/regulator/rt5190a-regulator.c
-@@ -0,0 +1,513 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-+#include <linux/bits.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/property.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/of_regulator.h>
-+
-+#define RT5190A_REG_MANUFACTURE 0x00
-+#define RT5190A_REG_BUCK2VSEL 0x04
-+#define RT5190A_REG_BUCK3VSEL 0x05
-+#define RT5190A_REG_DCDCCNTL 0x06
-+#define RT5190A_REG_ENABLE 0x07
-+#define RT5190A_REG_DISCHARGE 0x09
-+#define RT5190A_REG_PROTMODE 0x0A
-+#define RT5190A_REG_MUTECNTL 0x0B
-+#define RT5190A_REG_PGSTAT 0x0F
-+#define RT5190A_REG_OVINT 0x10
-+#define RT5190A_REG_HOTDIEMASK 0x17
-+
-+#define RT5190A_VSEL_MASK GENMASK(6, 0)
-+#define RT5190A_RID_BITMASK(rid) BIT(rid + 1)
-+#define RT5190A_BUCK1_DISCHG_MASK GENMASK(1, 0)
-+#define RT5190A_BUCK1_DISCHG_ONVAL 0x01
-+#define RT5190A_OVERVOLT_MASK GENMASK(7, 0)
-+#define RT5190A_UNDERVOLT_MASK GENMASK(15, 8)
-+#define RT5190A_CH234OT_MASK BIT(29)
-+#define RT5190A_CHIPOT_MASK BIT(28)
-+
-+#define RT5190A_BUCK23_MINUV 600000
-+#define RT5190A_BUCK23_MAXUV 1400000
-+#define RT5190A_BUCK23_STEPUV 10000
-+#define RT5190A_BUCK23_STEPNUM ((1400000 - 600000) / 10000 + 1)
-+
-+enum {
-+ RT5190A_IDX_BUCK1 = 0,
-+ RT5190A_IDX_BUCK2,
-+ RT5190A_IDX_BUCK3,
-+ RT5190A_IDX_BUCK4,
-+ RT5190A_IDX_LDO,
-+ RT5190A_MAX_IDX
-+};
-+
-+struct rt5190a_priv {
-+ struct device *dev;
-+ struct regmap *regmap;
-+ struct regulator_desc rdesc[RT5190A_MAX_IDX];
-+ struct regulator_dev *rdev[RT5190A_MAX_IDX];
-+};
-+
-+static int rt5190a_get_error_flags(struct regulator_dev *rdev,
-+ unsigned int *flags)
-+{
-+ struct regmap *regmap = rdev_get_regmap(rdev);
-+ int rid = rdev_get_id(rdev);
-+ unsigned int pgood_stat;
-+ int ret;
-+
-+ ret = regmap_read(regmap, RT5190A_REG_PGSTAT, &pgood_stat);
-+ if (ret)
-+ return ret;
-+
-+ if (!(pgood_stat & RT5190A_RID_BITMASK(rid)))
-+ *flags = REGULATOR_ERROR_FAIL;
-+ else
-+ *flags = 0;
-+
-+ return 0;
-+}
-+
-+static int rt5190a_fixed_buck_set_mode(struct regulator_dev *rdev,
-+ unsigned int mode)
-+{
-+ struct regmap *regmap = rdev_get_regmap(rdev);
-+ int rid = rdev_get_id(rdev);
-+ unsigned int mask = RT5190A_RID_BITMASK(rid), val;
-+
-+ switch (mode) {
-+ case REGULATOR_MODE_FAST:
-+ val = mask;
-+ break;
-+ case REGULATOR_MODE_NORMAL:
-+ val = 0;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return regmap_update_bits(regmap, RT5190A_REG_DCDCCNTL, mask, val);
-+}
-+
-+static unsigned int rt5190a_fixed_buck_get_mode(struct regulator_dev *rdev)
-+{
-+ struct regmap *regmap = rdev_get_regmap(rdev);
-+ int rid = rdev_get_id(rdev);
-+ unsigned int val;
-+ int ret;
-+
-+ ret = regmap_read(regmap, RT5190A_REG_DCDCCNTL, &val);
-+ if (ret) {
-+ dev_err(&rdev->dev, "Failed to get mode [%d]\n", ret);
-+ return ret;
-+ }
-+
-+ if (val & RT5190A_RID_BITMASK(rid))
-+ return REGULATOR_MODE_FAST;
-+
-+ return REGULATOR_MODE_NORMAL;
-+}
-+
-+static const struct regulator_ops rt5190a_ranged_buck_ops = {
-+ .enable = regulator_enable_regmap,
-+ .disable = regulator_disable_regmap,
-+ .is_enabled = regulator_is_enabled_regmap,
-+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
-+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
-+ .list_voltage = regulator_list_voltage_linear,
-+ .set_active_discharge = regulator_set_active_discharge_regmap,
-+ .get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static const struct regulator_ops rt5190a_fixed_buck_ops = {
-+ .enable = regulator_enable_regmap,
-+ .disable = regulator_disable_regmap,
-+ .is_enabled = regulator_is_enabled_regmap,
-+ .set_active_discharge = regulator_set_active_discharge_regmap,
-+ .set_mode = rt5190a_fixed_buck_set_mode,
-+ .get_mode = rt5190a_fixed_buck_get_mode,
-+ .get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static const struct regulator_ops rt5190a_fixed_ldo_ops = {
-+ .enable = regulator_enable_regmap,
-+ .disable = regulator_disable_regmap,
-+ .is_enabled = regulator_is_enabled_regmap,
-+ .set_active_discharge = regulator_set_active_discharge_regmap,
-+ .get_error_flags = rt5190a_get_error_flags,
-+};
-+
-+static irqreturn_t rt5190a_irq_handler(int irq, void *data)
-+{
-+ struct rt5190a_priv *priv = data;
-+ __le32 raws;
-+ unsigned int events, fields;
-+ static const struct {
-+ unsigned int bitmask;
-+ unsigned int report;
-+ } event_tbl[] = {
-+ { RT5190A_OVERVOLT_MASK, REGULATOR_ERROR_REGULATION_OUT },
-+ { RT5190A_UNDERVOLT_MASK, REGULATOR_ERROR_UNDER_VOLTAGE }
-+ };
-+ int i, j, ret;
-+
-+ ret = regmap_raw_read(priv->regmap, RT5190A_REG_OVINT, &raws,
-+ sizeof(raws));
-+ if (ret) {
-+ dev_err(priv->dev, "Failed to read events\n");
-+ return IRQ_NONE;
-+ }
-+
-+ events = le32_to_cpu(raws);
-+
-+ ret = regmap_raw_write(priv->regmap, RT5190A_REG_OVINT, &raws,
-+ sizeof(raws));
-+ if (ret)
-+ dev_err(priv->dev, "Failed to write-clear events\n");
-+
-+ /* Handle OV,UV events */
-+ for (i = 0; i < ARRAY_SIZE(event_tbl); i++) {
-+ fields = events & event_tbl[i].bitmask;
-+ fields >>= ffs(event_tbl[i].bitmask) - 1;
-+
-+ for (j = 0; j < RT5190A_MAX_IDX; j++) {
-+ if (!(fields & RT5190A_RID_BITMASK(j)))
-+ continue;
-+
-+ regulator_notifier_call_chain(priv->rdev[j],
-+ event_tbl[i].report,
-+ NULL);
-+ }
-+ }
-+
-+ /* Handle CH234 OT event */
-+ if (events & RT5190A_CH234OT_MASK) {
-+ for (j = RT5190A_IDX_BUCK2; j < RT5190A_IDX_LDO; j++) {
-+ regulator_notifier_call_chain(priv->rdev[j],
-+ REGULATOR_ERROR_OVER_TEMP,
-+ NULL);
-+ }
-+ }
-+
-+ /* Warning if CHIP OT occur */
-+ if (events & RT5190A_CHIPOT_MASK)
-+ dev_warn(priv->dev, "CHIP overheat\n");
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static unsigned int rt5190a_of_map_mode(unsigned int mode)
-+{
-+ switch (mode) {
-+ case RT5190A_OPMODE_AUTO:
-+ return REGULATOR_MODE_NORMAL;
-+ case RT5190A_OPMODE_FPWM:
-+ return REGULATOR_MODE_FAST;
-+ default:
-+ return REGULATOR_MODE_INVALID;
-+ }
-+}
-+
-+static int rt5190a_of_parse_cb(struct rt5190a_priv *priv, int rid,
-+ struct of_regulator_match *match)
-+{
-+ struct regulator_desc *desc = priv->rdesc + rid;
-+ struct regulator_init_data *init_data = match->init_data;
-+ struct device_node *np = match->of_node;
-+ bool latchup_enable;
-+ unsigned int mask = RT5190A_RID_BITMASK(rid), val;
-+
-+ switch (rid) {
-+ case RT5190A_IDX_BUCK1:
-+ case RT5190A_IDX_BUCK4:
-+ case RT5190A_IDX_LDO:
-+ init_data->constraints.apply_uV = 0;
-+
-+ if (init_data->constraints.min_uV ==
-+ init_data->constraints.max_uV)
-+ desc->fixed_uV = init_data->constraints.min_uV;
-+ else {
-+ dev_err(priv->dev,
-+ "Variable voltage for fixed regulator\n");
-+ return -EINVAL;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ latchup_enable = of_property_read_bool(np, "richtek,latchup-enable");
-+
-+ /* latchup: 0, default hiccup: 1 */
-+ val = !latchup_enable ? mask : 0;
-+
-+ return regmap_update_bits(priv->regmap, RT5190A_REG_PROTMODE, mask, val);
-+}
-+
-+static void rt5190a_fillin_regulator_desc(struct regulator_desc *desc, int rid)
-+{
-+ static const char * const regu_name[] = { "buck1", "buck2",
-+ "buck3", "buck4",
-+ "ldo" };
-+ static const char * const supply[] = { NULL, "vin2", "vin3", "vin4",
-+ "vinldo" };
-+
-+ desc->name = regu_name[rid];
-+ desc->supply_name = supply[rid];
-+ desc->owner = THIS_MODULE;
-+ desc->type = REGULATOR_VOLTAGE;
-+ desc->id = rid;
-+ desc->enable_reg = RT5190A_REG_ENABLE;
-+ desc->enable_mask = RT5190A_RID_BITMASK(rid);
-+ desc->active_discharge_reg = RT5190A_REG_DISCHARGE;
-+ desc->active_discharge_mask = RT5190A_RID_BITMASK(rid);
-+ desc->active_discharge_on = RT5190A_RID_BITMASK(rid);
-+
-+ switch (rid) {
-+ case RT5190A_IDX_BUCK1:
-+ desc->active_discharge_mask = RT5190A_BUCK1_DISCHG_MASK;
-+ desc->active_discharge_on = RT5190A_BUCK1_DISCHG_ONVAL;
-+ desc->n_voltages = 1;
-+ desc->ops = &rt5190a_fixed_buck_ops;
-+ desc->of_map_mode = rt5190a_of_map_mode;
-+ break;
-+ case RT5190A_IDX_BUCK2:
-+ desc->vsel_reg = RT5190A_REG_BUCK2VSEL;
-+ desc->vsel_mask = RT5190A_VSEL_MASK;
-+ desc->min_uV = RT5190A_BUCK23_MINUV;
-+ desc->uV_step = RT5190A_BUCK23_STEPUV;
-+ desc->n_voltages = RT5190A_BUCK23_STEPNUM;
-+ desc->ops = &rt5190a_ranged_buck_ops;
-+ break;
-+ case RT5190A_IDX_BUCK3:
-+ desc->vsel_reg = RT5190A_REG_BUCK3VSEL;
-+ desc->vsel_mask = RT5190A_VSEL_MASK;
-+ desc->min_uV = RT5190A_BUCK23_MINUV;
-+ desc->uV_step = RT5190A_BUCK23_STEPUV;
-+ desc->n_voltages = RT5190A_BUCK23_STEPNUM;
-+ desc->ops = &rt5190a_ranged_buck_ops;
-+ break;
-+ case RT5190A_IDX_BUCK4:
-+ desc->n_voltages = 1;
-+ desc->ops = &rt5190a_fixed_buck_ops;
-+ desc->of_map_mode = rt5190a_of_map_mode;
-+ break;
-+ case RT5190A_IDX_LDO:
-+ desc->n_voltages = 1;
-+ desc->ops = &rt5190a_fixed_ldo_ops;
-+ break;
-+ }
-+}
-+
-+static struct of_regulator_match rt5190a_regulator_match[] = {
-+ { .name = "buck1", },
-+ { .name = "buck2", },
-+ { .name = "buck3", },
-+ { .name = "buck4", },
-+ { .name = "ldo", }
-+};
-+
-+static int rt5190a_parse_regulator_dt_data(struct rt5190a_priv *priv)
-+{
-+ struct device_node *regulator_np;
-+ struct regulator_desc *reg_desc;
-+ struct of_regulator_match *match;
-+ int i, ret;
-+
-+ for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+ reg_desc = priv->rdesc + i;
-+ match = rt5190a_regulator_match + i;
-+
-+ rt5190a_fillin_regulator_desc(reg_desc, i);
-+
-+ match->desc = reg_desc;
-+ }
-+
-+ regulator_np = of_get_child_by_name(priv->dev->of_node, "regulators");
-+ if (!regulator_np) {
-+ dev_err(priv->dev, "Could not find 'regulators' node\n");
-+ return -ENODEV;
-+ }
-+
-+ ret = of_regulator_match(priv->dev, regulator_np,
-+ rt5190a_regulator_match,
-+ ARRAY_SIZE(rt5190a_regulator_match));
-+
-+ of_node_put(regulator_np);
-+
-+ if (ret < 0) {
-+ dev_err(priv->dev,
-+ "Error parsing regulator init data: %d\n", ret);
-+ return ret;
-+ }
-+
-+ for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+ match = rt5190a_regulator_match + i;
-+
-+ ret = rt5190a_of_parse_cb(priv, i, match);
-+ if (ret) {
-+ dev_err(priv->dev, "Failed in [%d] of_parse_cb\n", i);
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct reg_sequence rt5190a_init_patch[] = {
-+ { 0x09, 0x3d, },
-+ { 0x0a, 0x3e, },
-+ { 0x0b, 0x01, },
-+ { 0x10, 0xff, },
-+ { 0x11, 0xff, },
-+ { 0x12, 0xff, },
-+ { 0x13, 0xff, },
-+ { 0x14, 0, },
-+ { 0x15, 0, },
-+ { 0x16, 0x3e, },
-+ { 0x17, 0, }
-+};
-+
-+static int rt5190a_device_initialize(struct rt5190a_priv *priv)
-+{
-+ bool mute_enable;
-+ int ret;
-+
-+ ret = regmap_register_patch(priv->regmap, rt5190a_init_patch,
-+ ARRAY_SIZE(rt5190a_init_patch));
-+ if (ret) {
-+ dev_err(priv->dev, "Failed to do register patch\n");
-+ return ret;
-+ }
-+
-+ mute_enable = device_property_read_bool(priv->dev,
-+ "richtek,mute-enable");
-+
-+ if (mute_enable) {
-+ ret = regmap_write(priv->regmap, RT5190A_REG_MUTECNTL, 0x00);
-+ if (ret) {
-+ dev_err(priv->dev, "Failed to enable mute function\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int rt5190a_device_check(struct rt5190a_priv *priv)
-+{
-+ u16 devid;
-+ int ret;
-+
-+ ret = regmap_raw_read(priv->regmap, RT5190A_REG_MANUFACTURE, &devid,
-+ sizeof(devid));
-+ if (ret)
-+ return ret;
-+
-+ if (devid) {
-+ dev_err(priv->dev, "Incorrect device id 0x%04x\n", devid);
-+ return -ENODEV;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct regmap_config rt5190a_regmap_config = {
-+ .reg_bits = 8,
-+ .val_bits = 8,
-+ .max_register = RT5190A_REG_HOTDIEMASK,
-+};
-+
-+static int rt5190a_probe(struct i2c_client *i2c)
-+{
-+ struct rt5190a_priv *priv;
-+ struct regulator_config cfg = {};
-+ int i, ret;
-+
-+ priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->dev = &i2c->dev;
-+
-+ priv->regmap = devm_regmap_init_i2c(i2c, &rt5190a_regmap_config);
-+ if (IS_ERR(priv->regmap)) {
-+ dev_err(&i2c->dev, "Failed to allocate regmap\n");
-+ return PTR_ERR(priv->regmap);
-+ }
-+
-+ ret = rt5190a_device_check(priv);
-+ if (ret) {
-+ dev_err(&i2c->dev, "Failed to check device %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = rt5190a_device_initialize(priv);
-+ if (ret) {
-+ dev_err(&i2c->dev, "Failed to initialize the device\n");
-+ return ret;
-+ }
-+
-+ ret = rt5190a_parse_regulator_dt_data(priv);
-+ if (ret) {
-+ dev_err(&i2c->dev, "Failed to parse regulator dt\n");
-+ return ret;
-+ }
-+
-+ cfg.dev = &i2c->dev;
-+ cfg.regmap = priv->regmap;
-+
-+ for (i = 0; i < RT5190A_MAX_IDX; i++) {
-+ struct regulator_desc *desc = priv->rdesc + i;
-+ struct of_regulator_match *match = rt5190a_regulator_match + i;
-+
-+ cfg.init_data = match->init_data;
-+ cfg.of_node = match->of_node;
-+
-+ priv->rdev[i] = devm_regulator_register(&i2c->dev, desc, &cfg);
-+ if (IS_ERR(priv->rdev[i])) {
-+ dev_err(&i2c->dev, "Failed to register regulator %s\n",
-+ desc->name);
-+ return PTR_ERR(priv->rdev[i]);
-+ }
-+ }
-+
-+ if (i2c->irq) {
-+ ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
-+ rt5190a_irq_handler,
-+ IRQF_ONESHOT,
-+ dev_name(&i2c->dev), priv);
-+ if (ret) {
-+ dev_err(&i2c->dev, "Failed to register interrupt\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id __maybe_unused rt5190a_device_table[] = {
-+ { .compatible = "richtek,rt5190a", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, rt5190a_device_table);
-+
-+static struct i2c_driver rt5190a_driver = {
-+ .driver = {
-+ .name = "rt5190a",
-+ .of_match_table = rt5190a_device_table,
-+ },
-+ .probe_new = rt5190a_probe,
-+};
-+module_i2c_driver(rt5190a_driver);
-+
-+MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
-+MODULE_DESCRIPTION("Richtek RT5190A Regulator Driver");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sun, 10 Oct 2021 15:05:12 +0800
-Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c
- and dma
-
-Due to changes in the hardware design of the handshaking signal
-between i2c and dma, it is necessary to reset the handshaking
-signal before each transfer to ensure that the multi-msgs can
-be transferred correctly.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -15,6 +15,7 @@
- #include <linux/init.h>
- #include <linux/interrupt.h>
- #include <linux/io.h>
-+#include <linux/iopoll.h>
- #include <linux/kernel.h>
- #include <linux/mm.h>
- #include <linux/module.h>
-@@ -49,6 +50,8 @@
- #define I2C_RD_TRANAC_VALUE 0x0001
- #define I2C_SCL_MIS_COMP_VALUE 0x0000
- #define I2C_CHN_CLR_FLAG 0x0000
-+#define I2C_RELIABILITY 0x0010
-+#define I2C_DMAACK_ENABLE 0x0008
-
- #define I2C_DMA_CON_TX 0x0000
- #define I2C_DMA_CON_RX 0x0001
-@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt
- u16 restart_flag = 0;
- u16 dma_sync = 0;
- u32 reg_4g_mode;
-+ u32 reg_dma_reset;
- u8 *dma_rd_buf = NULL;
- u8 *dma_wr_buf = NULL;
- dma_addr_t rpaddr = 0;
-@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt
-
- reinit_completion(&i2c->msg_complete);
-
-+ if (i2c->dev_comp->apdma_sync &&
-+ i2c->op != I2C_MASTER_WRRD && num > 1) {
-+ mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
-+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
-+ i2c->pdmabase + OFFSET_RST);
-+
-+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
-+ reg_dma_reset,
-+ !(reg_dma_reset & I2C_DMA_WARM_RST),
-+ 0, 100);
-+ if (ret) {
-+ dev_err(i2c->dev, "DMA warm reset timeout\n");
-+ return -ETIMEDOUT;
-+ }
-+
-+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
-+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
-+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
-+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
-+ OFFSET_DEBUGCTRL);
-+ }
-+
- control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
- ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
- if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
+++ /dev/null
-From 5b8e29e566e086ef9b5b9ea0d054370a295e1d05 Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sun, 10 Oct 2021 15:05:13 +0800
-Subject: [PATCH 02/16] i2c: mediatek: Dump i2c/dma register when a timeout
- occurs
-
-When a timeout error occurs in i2c transter, it is usually related
-to the i2c/dma IP hardware configuration. Therefore, the purpose of
-this patch is to dump the key register values of i2c/dma when a
-timeout occurs in i2c for debugging.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 54 +++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -130,6 +130,7 @@ enum I2C_REGS_OFFSET {
- OFFSET_HS,
- OFFSET_SOFTRESET,
- OFFSET_DCM_EN,
-+ OFFSET_MULTI_DMA,
- OFFSET_PATH_DIR,
- OFFSET_DEBUGSTAT,
- OFFSET_DEBUGCTRL,
-@@ -197,6 +198,7 @@ static const u16 mt_i2c_regs_v2[] = {
- [OFFSET_TRANSFER_LEN_AUX] = 0x44,
- [OFFSET_CLOCK_DIV] = 0x48,
- [OFFSET_SOFTRESET] = 0x50,
-+ [OFFSET_MULTI_DMA] = 0x8c,
- [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
- [OFFSET_DEBUGSTAT] = 0xe4,
- [OFFSET_DEBUGCTRL] = 0xe8,
-@@ -845,6 +847,57 @@ static int mtk_i2c_set_speed(struct mtk_
- return 0;
- }
-
-+static void i2c_dump_register(struct mtk_i2c *i2c)
-+{
-+ dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
-+ mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
-+ dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
-+ mtk_i2c_readw(i2c, OFFSET_CONTROL));
-+ dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
-+ mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
-+ dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
-+ mtk_i2c_readw(i2c, OFFSET_TIMING));
-+ dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_START),
-+ mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
-+ dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_HS),
-+ mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
-+ dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_DCM_EN),
-+ mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
-+ dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
-+ mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
-+ dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
-+ mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
-+ if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
-+ dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
-+ mtk_i2c_readw(i2c, OFFSET_LTIMING),
-+ mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
-+ }
-+ dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
-+ readl(i2c->pdmabase + OFFSET_INT_FLAG),
-+ readl(i2c->pdmabase + OFFSET_INT_EN));
-+ dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
-+ readl(i2c->pdmabase + OFFSET_EN),
-+ readl(i2c->pdmabase + OFFSET_CON));
-+ dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
-+ readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
-+ readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
-+ dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
-+ readl(i2c->pdmabase + OFFSET_TX_LEN),
-+ readl(i2c->pdmabase + OFFSET_RX_LEN));
-+ dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
-+ readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
-+ readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
-+}
-+
- static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
- int num, int left_num)
- {
-@@ -1075,6 +1128,7 @@ static int mtk_i2c_do_transfer(struct mt
-
- if (ret == 0) {
- dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
-+ i2c_dump_register(i2c);
- mtk_i2c_init_hw(i2c);
- return -ETIMEDOUT;
- }
+++ /dev/null
-From 83630e3c6147bf7bb18a18f3d5a99462464f450b Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Tue, 25 Jan 2022 19:04:13 +0800
-Subject: [PATCH 03/16] i2c: mediatek: Add i2c compatible for Mediatek MT8186
-
-Add i2c compatible for MT8186. Compare to MT8192 i2c controller,
-MT8186 doesn't need handshake signal witch apdma.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -397,6 +397,19 @@ static const struct mtk_i2c_compatible m
- .max_dma_support = 33,
- };
-
-+static const struct mtk_i2c_compatible mt8186_compat = {
-+ .regs = mt_i2c_regs_v2,
-+ .pmic_i2c = 0,
-+ .dcm = 0,
-+ .auto_restart = 1,
-+ .aux_len_reg = 1,
-+ .timing_adjust = 1,
-+ .dma_sync = 0,
-+ .ltiming_adjust = 1,
-+ .apdma_sync = 0,
-+ .max_dma_support = 36,
-+};
-+
- static const struct mtk_i2c_compatible mt8192_compat = {
- .quirks = &mt8183_i2c_quirks,
- .regs = mt_i2c_regs_v2,
-@@ -418,6 +431,7 @@ static const struct of_device_id mtk_i2c
- { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
- { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
-+ { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
- { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
- {}
- };
+++ /dev/null
-From f606aab3f1a49d723d66e14e545f6ca45005bda6 Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Thu, 17 Feb 2022 20:22:43 +0800
-Subject: [PATCH 04/16] i2c: mediatek: modify bus speed calculation formula
-
-When clock-div is 0 or greater than 1, the bus speed
-calculated by the old speed calculation formula will be
-larger than the target speed. So we update the formula.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 51 ++++++++++++++++++++++++++-------
- 1 file changed, 41 insertions(+), 10 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -67,11 +67,12 @@
-
- #define MAX_SAMPLE_CNT_DIV 8
- #define MAX_STEP_CNT_DIV 64
--#define MAX_CLOCK_DIV 256
-+#define MAX_CLOCK_DIV_8BITS 256
-+#define MAX_CLOCK_DIV_5BITS 32
- #define MAX_HS_STEP_CNT_DIV 8
--#define I2C_STANDARD_MODE_BUFFER (1000 / 2)
--#define I2C_FAST_MODE_BUFFER (300 / 2)
--#define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
-+#define I2C_STANDARD_MODE_BUFFER (1000 / 3)
-+#define I2C_FAST_MODE_BUFFER (300 / 3)
-+#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3)
-
- #define I2C_CONTROL_RS (0x1 << 1)
- #define I2C_CONTROL_DMA_EN (0x1 << 2)
-@@ -604,6 +605,31 @@ static int mtk_i2c_max_step_cnt(unsigned
- return MAX_STEP_CNT_DIV;
- }
-
-+static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
-+ unsigned int sample_cnt)
-+{
-+ int clk_div_restri = 0;
-+
-+ if (i2c->dev_comp->ltiming_adjust == 0)
-+ return 0;
-+
-+ if (sample_cnt == 1) {
-+ if (i2c->ac_timing.inter_clk_div == 0)
-+ clk_div_restri = 0;
-+ else
-+ clk_div_restri = 1;
-+ } else {
-+ if (i2c->ac_timing.inter_clk_div == 0)
-+ clk_div_restri = -1;
-+ else if (i2c->ac_timing.inter_clk_div == 1)
-+ clk_div_restri = 0;
-+ else
-+ clk_div_restri = 1;
-+ }
-+
-+ return clk_div_restri;
-+}
-+
- /*
- * Check and Calculate i2c ac-timing
- *
-@@ -732,6 +758,7 @@ static int mtk_i2c_calculate_speed(struc
- unsigned int best_mul;
- unsigned int cnt_mul;
- int ret = -EINVAL;
-+ int clk_div_restri = 0;
-
- if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
- target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
-@@ -749,7 +776,8 @@ static int mtk_i2c_calculate_speed(struc
- * optimizing for sample_cnt * step_cnt being minimal
- */
- for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
-- step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
-+ clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
-+ step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
- cnt_mul = step_cnt * sample_cnt;
- if (step_cnt > max_step_cnt)
- continue;
-@@ -763,7 +791,7 @@ static int mtk_i2c_calculate_speed(struc
- best_mul = cnt_mul;
- base_sample_cnt = sample_cnt;
- base_step_cnt = step_cnt;
-- if (best_mul == opt_div)
-+ if (best_mul == (opt_div + clk_div_restri))
- break;
- }
- }
-@@ -774,7 +802,8 @@ static int mtk_i2c_calculate_speed(struc
- sample_cnt = base_sample_cnt;
- step_cnt = base_step_cnt;
-
-- if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
-+ if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
-+ target_speed) {
- /* In this case, hardware can't support such
- * low i2c_bus_freq
- */
-@@ -803,13 +832,16 @@ static int mtk_i2c_set_speed(struct mtk_
- target_speed = i2c->speed_hz;
- parent_clk /= i2c->clk_src_div;
-
-- if (i2c->dev_comp->timing_adjust)
-- max_clk_div = MAX_CLOCK_DIV;
-+ if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
-+ max_clk_div = MAX_CLOCK_DIV_5BITS;
-+ else if (i2c->dev_comp->timing_adjust)
-+ max_clk_div = MAX_CLOCK_DIV_8BITS;
- else
- max_clk_div = 1;
-
- for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
- clk_src = parent_clk / clk_div;
-+ i2c->ac_timing.inter_clk_div = clk_div - 1;
-
- if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
- /* Set master code speed register */
-@@ -856,7 +888,6 @@ static int mtk_i2c_set_speed(struct mtk_
- break;
- }
-
-- i2c->ac_timing.inter_clk_div = clk_div - 1;
-
- return 0;
- }
+++ /dev/null
-From eb4a2ae019815946f574cd9f8209e12bdcd8fd34 Mon Sep 17 00:00:00 2001
-From: Xu Wang <vulab@iscas.ac.cn>
-Date: Wed, 30 Sep 2020 08:42:33 +0000
-Subject: [PATCH 05/16] i2c: mediatek: remove redundant null check
-
-Because clk_disable_unprepare already checked NULL clock parameter,
-so the additional checks are unnecessary, just remove it
-
-Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -476,8 +476,7 @@ static int mtk_i2c_clock_enable(struct m
- return 0;
-
- err_arb:
-- if (i2c->have_pmic)
-- clk_disable_unprepare(i2c->clk_pmic);
-+ clk_disable_unprepare(i2c->clk_pmic);
- err_pmic:
- clk_disable_unprepare(i2c->clk_main);
- err_main:
-@@ -488,11 +487,9 @@ err_main:
-
- static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
- {
-- if (i2c->clk_arb)
-- clk_disable_unprepare(i2c->clk_arb);
-+ clk_disable_unprepare(i2c->clk_arb);
-
-- if (i2c->have_pmic)
-- clk_disable_unprepare(i2c->clk_pmic);
-+ clk_disable_unprepare(i2c->clk_pmic);
-
- clk_disable_unprepare(i2c->clk_main);
- clk_disable_unprepare(i2c->clk_dma);
+++ /dev/null
-From cc6faa5e0772296d815fd298c231277d47308a6a Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Thu, 3 Mar 2022 10:15:47 +0100
-Subject: [PATCH 06/16] i2c: mt65xx: Simplify with clk-bulk
-
-Since depending on the SoC or specific bus functionality some clocks
-may be optional, we cannot get the benefit of using devm_clk_bulk_get()
-but, by migrating to clk-bulk, we are able to remove the custom functions
-mtk_i2c_clock_enable() and mtk_i2c_clock_disable(), increasing common
-APIs usage, hence (lightly) decreasing kernel footprint.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 124 +++++++++++++-------------------
- 1 file changed, 51 insertions(+), 73 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -86,6 +86,27 @@
-
- #define I2C_DRV_NAME "i2c-mt65xx"
-
-+/**
-+ * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
-+ *
-+ * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
-+ * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
-+ * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
-+ * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
-+ * @I2C_MT65XX_CLK_MAX: Number of supported clocks
-+ */
-+enum i2c_mt65xx_clks {
-+ I2C_MT65XX_CLK_MAIN = 0,
-+ I2C_MT65XX_CLK_DMA,
-+ I2C_MT65XX_CLK_PMIC,
-+ I2C_MT65XX_CLK_ARB,
-+ I2C_MT65XX_CLK_MAX
-+};
-+
-+static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
-+ "main", "dma", "pmic", "arb"
-+};
-+
- enum DMA_REGS_OFFSET {
- OFFSET_INT_FLAG = 0x0,
- OFFSET_INT_EN = 0x04,
-@@ -244,10 +265,7 @@ struct mtk_i2c {
- /* set in i2c probe */
- void __iomem *base; /* i2c base addr */
- void __iomem *pdmabase; /* dma base address*/
-- struct clk *clk_main; /* main clock for i2c bus */
-- struct clk *clk_dma; /* DMA clock for i2c via DMA */
-- struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
-- struct clk *clk_arb; /* Arbitrator clock for i2c */
-+ struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
- bool have_pmic; /* can use i2c pins from PMIC */
- bool use_push_pull; /* IO config push-pull mode */
-
-@@ -449,52 +467,6 @@ static void mtk_i2c_writew(struct mtk_i2
- writew(val, i2c->base + i2c->dev_comp->regs[reg]);
- }
-
--static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
--{
-- int ret;
--
-- ret = clk_prepare_enable(i2c->clk_dma);
-- if (ret)
-- return ret;
--
-- ret = clk_prepare_enable(i2c->clk_main);
-- if (ret)
-- goto err_main;
--
-- if (i2c->have_pmic) {
-- ret = clk_prepare_enable(i2c->clk_pmic);
-- if (ret)
-- goto err_pmic;
-- }
--
-- if (i2c->clk_arb) {
-- ret = clk_prepare_enable(i2c->clk_arb);
-- if (ret)
-- goto err_arb;
-- }
--
-- return 0;
--
--err_arb:
-- clk_disable_unprepare(i2c->clk_pmic);
--err_pmic:
-- clk_disable_unprepare(i2c->clk_main);
--err_main:
-- clk_disable_unprepare(i2c->clk_dma);
--
-- return ret;
--}
--
--static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
--{
-- clk_disable_unprepare(i2c->clk_arb);
--
-- clk_disable_unprepare(i2c->clk_pmic);
--
-- clk_disable_unprepare(i2c->clk_main);
-- clk_disable_unprepare(i2c->clk_dma);
--}
--
- static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
- {
- u16 control_reg;
-@@ -1191,7 +1163,7 @@ static int mtk_i2c_transfer(struct i2c_a
- int left_num = num;
- struct mtk_i2c *i2c = i2c_get_adapdata(adap);
-
-- ret = mtk_i2c_clock_enable(i2c);
-+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- if (ret)
- return ret;
-
-@@ -1245,7 +1217,7 @@ static int mtk_i2c_transfer(struct i2c_a
- ret = num;
-
- err_exit:
-- mtk_i2c_clock_disable(i2c);
-+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
- return ret;
- }
-
-@@ -1323,9 +1295,8 @@ static int mtk_i2c_probe(struct platform
- {
- int ret = 0;
- struct mtk_i2c *i2c;
-- struct clk *clk;
- struct resource *res;
-- int irq;
-+ int i, irq, speed_clk;
-
- i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- if (!i2c)
-@@ -1371,35 +1342,42 @@ static int mtk_i2c_probe(struct platform
- if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
- return -EINVAL;
-
-- i2c->clk_main = devm_clk_get(&pdev->dev, "main");
-- if (IS_ERR(i2c->clk_main)) {
-+ /* Fill in clk-bulk IDs */
-+ for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
-+ i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
-+
-+ /* Get clocks one by one, some may be optional */
-+ i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
-+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
- dev_err(&pdev->dev, "cannot get main clock\n");
-- return PTR_ERR(i2c->clk_main);
-+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
- }
-
-- i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
-- if (IS_ERR(i2c->clk_dma)) {
-+ i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
-+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
- dev_err(&pdev->dev, "cannot get dma clock\n");
-- return PTR_ERR(i2c->clk_dma);
-+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
- }
-
-- i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
-- if (IS_ERR(i2c->clk_arb))
-- i2c->clk_arb = NULL;
-+ i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
-+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
-+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
-
-- clk = i2c->clk_main;
- if (i2c->have_pmic) {
-- i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
-- if (IS_ERR(i2c->clk_pmic)) {
-+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
-+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
- dev_err(&pdev->dev, "cannot get pmic clock\n");
-- return PTR_ERR(i2c->clk_pmic);
-+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
- }
-- clk = i2c->clk_pmic;
-+ speed_clk = I2C_MT65XX_CLK_PMIC;
-+ } else {
-+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
-+ speed_clk = I2C_MT65XX_CLK_MAIN;
- }
-
- strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
-
-- ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
-+ ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
- if (ret) {
- dev_err(&pdev->dev, "Failed to set the speed.\n");
- return -EINVAL;
-@@ -1414,13 +1392,13 @@ static int mtk_i2c_probe(struct platform
- }
- }
-
-- ret = mtk_i2c_clock_enable(i2c);
-+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- if (ret) {
- dev_err(&pdev->dev, "clock enable failed!\n");
- return ret;
- }
- mtk_i2c_init_hw(i2c);
-- mtk_i2c_clock_disable(i2c);
-+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-
- ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
-@@ -1465,7 +1443,7 @@ static int mtk_i2c_resume_noirq(struct d
- int ret;
- struct mtk_i2c *i2c = dev_get_drvdata(dev);
-
-- ret = mtk_i2c_clock_enable(i2c);
-+ ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- if (ret) {
- dev_err(dev, "clock enable failed!\n");
- return ret;
-@@ -1473,7 +1451,7 @@ static int mtk_i2c_resume_noirq(struct d
-
- mtk_i2c_init_hw(i2c);
-
-- mtk_i2c_clock_disable(i2c);
-+ clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-
- i2c_mark_adapter_resumed(&i2c->adap);
-
+++ /dev/null
-From de054c03f90b3ea22bc346fbf78ac716df192b2d Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Mon, 7 Mar 2022 11:36:49 +0800
-Subject: [PATCH 07/16] i2c: mediatek: Add i2c compatible for Mediatek MT8168
-
-Add i2c compatible for MT8168. Compare to MT2712 i2c controller,
-MT8168 need to synchronize signal with dma.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -389,6 +389,19 @@ static const struct mtk_i2c_compatible m
- .max_dma_support = 32,
- };
-
-+static const struct mtk_i2c_compatible mt8168_compat = {
-+ .regs = mt_i2c_regs_v1,
-+ .pmic_i2c = 0,
-+ .dcm = 1,
-+ .auto_restart = 1,
-+ .aux_len_reg = 1,
-+ .timing_adjust = 1,
-+ .dma_sync = 1,
-+ .ltiming_adjust = 0,
-+ .apdma_sync = 0,
-+ .max_dma_support = 33,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- .regs = mt_i2c_regs_v1,
- .pmic_i2c = 0,
-@@ -448,6 +461,7 @@ static const struct of_device_id mtk_i2c
- { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+ { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
- { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
+++ /dev/null
-From 2831f9a53ec3a16012d2d23590e3ebad6084b763 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Mon, 11 Apr 2022 15:21:07 +0200
-Subject: [PATCH 08/16] i2c: mediatek: Optimize master_xfer() and avoid
- circular locking
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Especially (but not only) during probe, it may happen that multiple
-devices are communicating via i2c (or multiple i2c busses) and
-sometimes while others are probing asynchronously.
-For example, a Cr50 TPM may be filling entropy (or userspace may be
-reading random data) while the rt5682 (i2c) codec driver reads/sets
-some registers, like while getting/setting a clock's rate, which
-happens both during probe and during system operation.
-
-In this driver, the mtk_i2c_transfer() function (which is the i2c
-.master_xfer() callback) was granularly managing the clocks by
-performing a clk_bulk_prepare_enable() to start them and its inverse.
-This is not only creating possible circular locking dependencies in
-the some cases (like former explanation), but it's also suboptimal,
-as clk_core prepare/unprepare operations are using mutex locking,
-which creates a bit of unwanted overhead (for example, i2c trackpads
-will call master_xfer() every few milliseconds!).
-
-With this commit, we avoid both the circular locking and additional
-overhead by changing how we handle the clocks in this driver:
-- Prepare the clocks during probe (and PM resume)
-- Enable/disable clocks in mtk_i2c_transfer()
-- Unprepare the clocks only for driver removal (and PM suspend)
-
-For the sake of providing a full explanation: during probe, the
-clocks are not only prepared but also enabled, as this is needed
-for some hardware initialization but, after that, we are disabling
-but not unpreparing them, leaving an expected state for the
-aforementioned clock handling strategy.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 11 +++++++----
- 1 file changed, 7 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1177,7 +1177,7 @@ static int mtk_i2c_transfer(struct i2c_a
- int left_num = num;
- struct mtk_i2c *i2c = i2c_get_adapdata(adap);
-
-- ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+ ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- if (ret)
- return ret;
-
-@@ -1231,7 +1231,7 @@ static int mtk_i2c_transfer(struct i2c_a
- ret = num;
-
- err_exit:
-- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
- return ret;
- }
-
-@@ -1412,7 +1412,7 @@ static int mtk_i2c_probe(struct platform
- return ret;
- }
- mtk_i2c_init_hw(i2c);
-- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
-
- ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
- IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
-@@ -1439,6 +1439,8 @@ static int mtk_i2c_remove(struct platfor
-
- i2c_del_adapter(&i2c->adap);
-
-+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+
- return 0;
- }
-
-@@ -1448,6 +1450,7 @@ static int mtk_i2c_suspend_noirq(struct
- struct mtk_i2c *i2c = dev_get_drvdata(dev);
-
- i2c_mark_adapter_suspended(&i2c->adap);
-+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-
- return 0;
- }
-@@ -1465,7 +1468,7 @@ static int mtk_i2c_resume_noirq(struct d
-
- mtk_i2c_init_hw(i2c);
-
-- clk_bulk_disable_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+ clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
-
- i2c_mark_adapter_resumed(&i2c->adap);
-
+++ /dev/null
-From 6f3a5814c7aaea4176e0ac8b1ec6dc0a65aa2808 Mon Sep 17 00:00:00 2001
-From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Date: Sun, 22 May 2022 14:22:07 +0200
-Subject: [PATCH 09/16] i2c: mediatek: Fix an error handling path in
- mtk_i2c_probe()
-
-The clsk are prepared, enabled, then disabled. So if an error occurs after
-the disable step, they are still prepared.
-
-Add an error handling path to unprepare the clks in such a case, as already
-done in the .remove function.
-
-Fixes: 8b4fc246c3ff ("i2c: mediatek: Optimize master_xfer() and avoid circular locking")
-Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1420,17 +1420,22 @@ static int mtk_i2c_probe(struct platform
- if (ret < 0) {
- dev_err(&pdev->dev,
- "Request I2C IRQ %d fail\n", irq);
-- return ret;
-+ goto err_bulk_unprepare;
- }
-
- i2c_set_adapdata(&i2c->adap, i2c);
- ret = i2c_add_adapter(&i2c->adap);
- if (ret)
-- return ret;
-+ goto err_bulk_unprepare;
-
- platform_set_drvdata(pdev, i2c);
-
- return 0;
-+
-+err_bulk_unprepare:
-+ clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
-+
-+ return ret;
- }
-
- static int mtk_i2c_remove(struct platform_device *pdev)
+++ /dev/null
-From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001
-From: Kewei Xu <kewei.xu@mediatek.com>
-Date: Sat, 6 Aug 2022 18:02:49 +0800
-Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188
-
-Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since
-MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94.
-
-Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Qii Wang <qii.wang@mediatek.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = {
- [OFFSET_DCM_EN] = 0xf88,
- };
-
-+static const u16 mt_i2c_regs_v3[] = {
-+ [OFFSET_DATA_PORT] = 0x0,
-+ [OFFSET_INTR_MASK] = 0x8,
-+ [OFFSET_INTR_STAT] = 0xc,
-+ [OFFSET_CONTROL] = 0x10,
-+ [OFFSET_TRANSFER_LEN] = 0x14,
-+ [OFFSET_TRANSAC_LEN] = 0x18,
-+ [OFFSET_DELAY_LEN] = 0x1c,
-+ [OFFSET_TIMING] = 0x20,
-+ [OFFSET_START] = 0x24,
-+ [OFFSET_EXT_CONF] = 0x28,
-+ [OFFSET_LTIMING] = 0x2c,
-+ [OFFSET_HS] = 0x30,
-+ [OFFSET_IO_CONFIG] = 0x34,
-+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
-+ [OFFSET_SDA_TIMING] = 0x3c,
-+ [OFFSET_TRANSFER_LEN_AUX] = 0x44,
-+ [OFFSET_CLOCK_DIV] = 0x48,
-+ [OFFSET_SOFTRESET] = 0x50,
-+ [OFFSET_MULTI_DMA] = 0x8c,
-+ [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
-+ [OFFSET_SLAVE_ADDR] = 0x94,
-+ [OFFSET_DEBUGSTAT] = 0xe4,
-+ [OFFSET_DEBUGCTRL] = 0xe8,
-+ [OFFSET_FIFO_STAT] = 0xf4,
-+ [OFFSET_FIFO_THRESH] = 0xf8,
-+ [OFFSET_DCM_EN] = 0xf88,
-+};
-+
- struct mtk_i2c_compatible {
- const struct i2c_adapter_quirks *quirks;
- const u16 *regs;
-@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m
- .max_dma_support = 36,
- };
-
-+static const struct mtk_i2c_compatible mt8188_compat = {
-+ .regs = mt_i2c_regs_v3,
-+ .pmic_i2c = 0,
-+ .dcm = 0,
-+ .auto_restart = 1,
-+ .aux_len_reg = 1,
-+ .timing_adjust = 1,
-+ .dma_sync = 0,
-+ .ltiming_adjust = 1,
-+ .apdma_sync = 1,
-+ .max_dma_support = 36,
-+};
-+
- static const struct mtk_i2c_compatible mt8192_compat = {
- .quirks = &mt8183_i2c_quirks,
- .regs = mt_i2c_regs_v2,
-@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c
- { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
- { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
-+ { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
- { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
- {}
- };
+++ /dev/null
-From 2f4ca256a98cc19787b7c861109dd1150a21b0bf Mon Sep 17 00:00:00 2001
-From: Wolfram Sang <wsa+renesas@sang-engineering.com>
-Date: Thu, 11 Aug 2022 09:10:30 +0200
-Subject: [PATCH 11/16] i2c: move drivers from strlcpy to strscpy
-
-Follow the advice of the below link and prefer 'strscpy'. Conversion is
-easy because no driver used the return value and has been done with a
-simple sed invocation.
-
-Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/
-Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-altera.c | 2 +-
- drivers/i2c/busses/i2c-aspeed.c | 2 +-
- drivers/i2c/busses/i2c-au1550.c | 2 +-
- drivers/i2c/busses/i2c-axxia.c | 2 +-
- drivers/i2c/busses/i2c-bcm-kona.c | 2 +-
- drivers/i2c/busses/i2c-cbus-gpio.c | 2 +-
- drivers/i2c/busses/i2c-cht-wc.c | 2 +-
- drivers/i2c/busses/i2c-cros-ec-tunnel.c | 2 +-
- drivers/i2c/busses/i2c-davinci.c | 2 +-
- drivers/i2c/busses/i2c-digicolor.c | 2 +-
- drivers/i2c/busses/i2c-eg20t.c | 2 +-
- drivers/i2c/busses/i2c-emev2.c | 2 +-
- drivers/i2c/busses/i2c-exynos5.c | 2 +-
- drivers/i2c/busses/i2c-gpio.c | 2 +-
- drivers/i2c/busses/i2c-highlander.c | 2 +-
- drivers/i2c/busses/i2c-hix5hd2.c | 2 +-
- drivers/i2c/busses/i2c-i801.c | 4 ++--
- drivers/i2c/busses/i2c-ibm_iic.c | 2 +-
- drivers/i2c/busses/i2c-icy.c | 2 +-
- drivers/i2c/busses/i2c-imx-lpi2c.c | 2 +-
- drivers/i2c/busses/i2c-lpc2k.c | 2 +-
- drivers/i2c/busses/i2c-meson.c | 2 +-
- drivers/i2c/busses/i2c-mt65xx.c | 2 +-
- drivers/i2c/busses/i2c-mt7621.c | 2 +-
- drivers/i2c/busses/i2c-mv64xxx.c | 2 +-
- drivers/i2c/busses/i2c-mxs.c | 2 +-
- drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +-
- drivers/i2c/busses/i2c-omap.c | 2 +-
- drivers/i2c/busses/i2c-opal.c | 4 ++--
- drivers/i2c/busses/i2c-parport.c | 2 +-
- drivers/i2c/busses/i2c-pxa.c | 2 +-
- drivers/i2c/busses/i2c-qcom-geni.c | 2 +-
- drivers/i2c/busses/i2c-qup.c | 2 +-
- drivers/i2c/busses/i2c-rcar.c | 2 +-
- drivers/i2c/busses/i2c-riic.c | 2 +-
- drivers/i2c/busses/i2c-rk3x.c | 2 +-
- drivers/i2c/busses/i2c-s3c2410.c | 2 +-
- drivers/i2c/busses/i2c-sh_mobile.c | 2 +-
- drivers/i2c/busses/i2c-simtec.c | 2 +-
- drivers/i2c/busses/i2c-taos-evm.c | 2 +-
- drivers/i2c/busses/i2c-tegra-bpmp.c | 2 +-
- drivers/i2c/busses/i2c-tegra.c | 2 +-
- drivers/i2c/busses/i2c-uniphier-f.c | 2 +-
- drivers/i2c/busses/i2c-uniphier.c | 2 +-
- drivers/i2c/busses/i2c-versatile.c | 2 +-
- drivers/i2c/busses/i2c-wmt.c | 2 +-
- 46 files changed, 48 insertions(+), 48 deletions(-)
-
---- a/drivers/i2c/busses/i2c-altera.c
-+++ b/drivers/i2c/busses/i2c-altera.c
-@@ -447,7 +447,7 @@ static int altr_i2c_probe(struct platfor
- mutex_unlock(&idev->isr_mutex);
-
- i2c_set_adapdata(&idev->adapter, idev);
-- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
-+ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
- idev->adapter.owner = THIS_MODULE;
- idev->adapter.algo = &altr_i2c_algo;
- idev->adapter.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-aspeed.c
-+++ b/drivers/i2c/busses/i2c-aspeed.c
-@@ -1024,7 +1024,7 @@ static int aspeed_i2c_probe_bus(struct p
- bus->adap.algo = &aspeed_i2c_algo;
- bus->adap.dev.parent = &pdev->dev;
- bus->adap.dev.of_node = pdev->dev.of_node;
-- strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
-+ strscpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
- i2c_set_adapdata(&bus->adap, bus);
-
- bus->dev = &pdev->dev;
---- a/drivers/i2c/busses/i2c-au1550.c
-+++ b/drivers/i2c/busses/i2c-au1550.c
-@@ -321,7 +321,7 @@ i2c_au1550_probe(struct platform_device
- priv->adap.algo = &au1550_algo;
- priv->adap.algo_data = priv;
- priv->adap.dev.parent = &pdev->dev;
-- strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
-+ strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
-
- /* Now, set up the PSC for SMBus PIO mode. */
- i2c_au1550_setup(priv);
---- a/drivers/i2c/busses/i2c-axxia.c
-+++ b/drivers/i2c/busses/i2c-axxia.c
-@@ -783,7 +783,7 @@ static int axxia_i2c_probe(struct platfo
- }
-
- i2c_set_adapdata(&idev->adapter, idev);
-- strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
-+ strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
- idev->adapter.owner = THIS_MODULE;
- idev->adapter.algo = &axxia_i2c_algo;
- idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
---- a/drivers/i2c/busses/i2c-bcm-kona.c
-+++ b/drivers/i2c/busses/i2c-bcm-kona.c
-@@ -849,7 +849,7 @@ static int bcm_kona_i2c_probe(struct pla
- adap = &dev->adapter;
- i2c_set_adapdata(adap, dev);
- adap->owner = THIS_MODULE;
-- strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
-+ strscpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
- adap->algo = &bcm_algo;
- adap->dev.parent = &pdev->dev;
- adap->dev.of_node = pdev->dev.of_node;
---- a/drivers/i2c/busses/i2c-cbus-gpio.c
-+++ b/drivers/i2c/busses/i2c-cbus-gpio.c
-@@ -245,7 +245,7 @@ static int cbus_i2c_probe(struct platfor
- adapter->nr = pdev->id;
- adapter->timeout = HZ;
- adapter->algo = &cbus_i2c_algo;
-- strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
-+ strscpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
-
- spin_lock_init(&chost->lock);
- chost->dev = &pdev->dev;
---- a/drivers/i2c/busses/i2c-cht-wc.c
-+++ b/drivers/i2c/busses/i2c-cht-wc.c
-@@ -334,7 +334,7 @@ static int cht_wc_i2c_adap_i2c_probe(str
- adap->adapter.class = I2C_CLASS_HWMON;
- adap->adapter.algo = &cht_wc_i2c_adap_algo;
- adap->adapter.lock_ops = &cht_wc_i2c_adap_lock_ops;
-- strlcpy(adap->adapter.name, "PMIC I2C Adapter",
-+ strscpy(adap->adapter.name, "PMIC I2C Adapter",
- sizeof(adap->adapter.name));
- adap->adapter.dev.parent = &pdev->dev;
-
---- a/drivers/i2c/busses/i2c-cros-ec-tunnel.c
-+++ b/drivers/i2c/busses/i2c-cros-ec-tunnel.c
-@@ -267,7 +267,7 @@ static int ec_i2c_probe(struct platform_
- bus->dev = dev;
-
- bus->adap.owner = THIS_MODULE;
-- strlcpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
-+ strscpy(bus->adap.name, "cros-ec-i2c-tunnel", sizeof(bus->adap.name));
- bus->adap.algo = &ec_i2c_algorithm;
- bus->adap.algo_data = bus;
- bus->adap.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-davinci.c
-+++ b/drivers/i2c/busses/i2c-davinci.c
-@@ -847,7 +847,7 @@ static int davinci_i2c_probe(struct plat
- i2c_set_adapdata(adap, dev);
- adap->owner = THIS_MODULE;
- adap->class = I2C_CLASS_DEPRECATED;
-- strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
-+ strscpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
- adap->algo = &i2c_davinci_algo;
- adap->dev.parent = &pdev->dev;
- adap->timeout = DAVINCI_I2C_TIMEOUT;
---- a/drivers/i2c/busses/i2c-digicolor.c
-+++ b/drivers/i2c/busses/i2c-digicolor.c
-@@ -322,7 +322,7 @@ static int dc_i2c_probe(struct platform_
- if (ret < 0)
- return ret;
-
-- strlcpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
-+ strscpy(i2c->adap.name, "Conexant Digicolor I2C adapter",
- sizeof(i2c->adap.name));
- i2c->adap.owner = THIS_MODULE;
- i2c->adap.algo = &dc_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-eg20t.c
-+++ b/drivers/i2c/busses/i2c-eg20t.c
-@@ -773,7 +773,7 @@ static int pch_i2c_probe(struct pci_dev
-
- pch_adap->owner = THIS_MODULE;
- pch_adap->class = I2C_CLASS_HWMON;
-- strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
-+ strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
- pch_adap->algo = &pch_algorithm;
- pch_adap->algo_data = &adap_info->pch_data[i];
-
---- a/drivers/i2c/busses/i2c-emev2.c
-+++ b/drivers/i2c/busses/i2c-emev2.c
-@@ -371,7 +371,7 @@ static int em_i2c_probe(struct platform_
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
-
-- strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
-+ strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
-
- priv->sclk = devm_clk_get(&pdev->dev, "sclk");
- if (IS_ERR(priv->sclk))
---- a/drivers/i2c/busses/i2c-exynos5.c
-+++ b/drivers/i2c/busses/i2c-exynos5.c
-@@ -751,7 +751,7 @@ static int exynos5_i2c_probe(struct plat
- if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
- i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
-
-- strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
- i2c->adap.owner = THIS_MODULE;
- i2c->adap.algo = &exynos5_i2c_algorithm;
- i2c->adap.retries = 3;
---- a/drivers/i2c/busses/i2c-gpio.c
-+++ b/drivers/i2c/busses/i2c-gpio.c
-@@ -436,7 +436,7 @@ static int i2c_gpio_probe(struct platfor
-
- adap->owner = THIS_MODULE;
- if (np)
-- strlcpy(adap->name, dev_name(dev), sizeof(adap->name));
-+ strscpy(adap->name, dev_name(dev), sizeof(adap->name));
- else
- snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id);
-
---- a/drivers/i2c/busses/i2c-highlander.c
-+++ b/drivers/i2c/busses/i2c-highlander.c
-@@ -402,7 +402,7 @@ static int highlander_i2c_probe(struct p
- i2c_set_adapdata(adap, dev);
- adap->owner = THIS_MODULE;
- adap->class = I2C_CLASS_HWMON;
-- strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
-+ strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
- adap->algo = &highlander_i2c_algo;
- adap->dev.parent = &pdev->dev;
- adap->nr = pdev->id;
---- a/drivers/i2c/busses/i2c-hix5hd2.c
-+++ b/drivers/i2c/busses/i2c-hix5hd2.c
-@@ -423,7 +423,7 @@ static int hix5hd2_i2c_probe(struct plat
- }
- clk_prepare_enable(priv->clk);
-
-- strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
-+ strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
- priv->dev = &pdev->dev;
- priv->adap.owner = THIS_MODULE;
- priv->adap.algo = &hix5hd2_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-i801.c
-+++ b/drivers/i2c/busses/i2c-i801.c
-@@ -1111,7 +1111,7 @@ static void dmi_check_onboard_device(u8
-
- memset(&info, 0, sizeof(struct i2c_board_info));
- info.addr = dmi_devices[i].i2c_addr;
-- strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
-+ strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
- i2c_new_client_device(adap, &info);
- break;
- }
-@@ -1267,7 +1267,7 @@ static void register_dell_lis3lv02d_i2c_
-
- memset(&info, 0, sizeof(struct i2c_board_info));
- info.addr = dell_lis3lv02d_devices[i].i2c_addr;
-- strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
-+ strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
- i2c_new_client_device(&priv->adapter, &info);
- }
-
---- a/drivers/i2c/busses/i2c-ibm_iic.c
-+++ b/drivers/i2c/busses/i2c-ibm_iic.c
-@@ -738,7 +738,7 @@ static int iic_probe(struct platform_dev
- adap = &dev->adap;
- adap->dev.parent = &ofdev->dev;
- adap->dev.of_node = of_node_get(np);
-- strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
-+ strscpy(adap->name, "IBM IIC", sizeof(adap->name));
- i2c_set_adapdata(adap, dev);
- adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
- adap->algo = &iic_algo;
---- a/drivers/i2c/busses/i2c-icy.c
-+++ b/drivers/i2c/busses/i2c-icy.c
-@@ -141,7 +141,7 @@ static int icy_probe(struct zorro_dev *z
- i2c->adapter.owner = THIS_MODULE;
- /* i2c->adapter.algo assigned by i2c_pcf_add_bus() */
- i2c->adapter.algo_data = algo_data;
-- strlcpy(i2c->adapter.name, "ICY I2C Zorro adapter",
-+ strscpy(i2c->adapter.name, "ICY I2C Zorro adapter",
- sizeof(i2c->adapter.name));
-
- if (!devm_request_mem_region(&z->dev,
---- a/drivers/i2c/busses/i2c-imx-lpi2c.c
-+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c
-@@ -564,7 +564,7 @@ static int lpi2c_imx_probe(struct platfo
- lpi2c_imx->adapter.algo = &lpi2c_imx_algo;
- lpi2c_imx->adapter.dev.parent = &pdev->dev;
- lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node;
-- strlcpy(lpi2c_imx->adapter.name, pdev->name,
-+ strscpy(lpi2c_imx->adapter.name, pdev->name,
- sizeof(lpi2c_imx->adapter.name));
-
- lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
---- a/drivers/i2c/busses/i2c-lpc2k.c
-+++ b/drivers/i2c/busses/i2c-lpc2k.c
-@@ -417,7 +417,7 @@ static int i2c_lpc2k_probe(struct platfo
-
- i2c_set_adapdata(&i2c->adap, i2c);
- i2c->adap.owner = THIS_MODULE;
-- strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
- i2c->adap.algo = &i2c_lpc2k_algorithm;
- i2c->adap.dev.parent = &pdev->dev;
- i2c->adap.dev.of_node = pdev->dev.of_node;
---- a/drivers/i2c/busses/i2c-meson.c
-+++ b/drivers/i2c/busses/i2c-meson.c
-@@ -451,7 +451,7 @@ static int meson_i2c_probe(struct platfo
- return ret;
- }
-
-- strlcpy(i2c->adap.name, "Meson I2C adapter",
-+ strscpy(i2c->adap.name, "Meson I2C adapter",
- sizeof(i2c->adap.name));
- i2c->adap.owner = THIS_MODULE;
- i2c->adap.algo = &meson_i2c_algorithm;
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1432,7 +1432,7 @@ static int mtk_i2c_probe(struct platform
- speed_clk = I2C_MT65XX_CLK_MAIN;
- }
-
-- strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
-
- ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
- if (ret) {
---- a/drivers/i2c/busses/i2c-mt7621.c
-+++ b/drivers/i2c/busses/i2c-mt7621.c
-@@ -315,7 +315,7 @@ static int mtk_i2c_probe(struct platform
- adap->dev.parent = &pdev->dev;
- i2c_set_adapdata(adap, i2c);
- adap->dev.of_node = pdev->dev.of_node;
-- strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+ strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-
- platform_set_drvdata(pdev, i2c);
-
---- a/drivers/i2c/busses/i2c-mv64xxx.c
-+++ b/drivers/i2c/busses/i2c-mv64xxx.c
-@@ -1000,7 +1000,7 @@ mv64xxx_i2c_probe(struct platform_device
- if (IS_ERR(drv_data->reg_base))
- return PTR_ERR(drv_data->reg_base);
-
-- strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
-+ strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
- sizeof(drv_data->adapter.name));
-
- init_waitqueue_head(&drv_data->waitq);
---- a/drivers/i2c/busses/i2c-mxs.c
-+++ b/drivers/i2c/busses/i2c-mxs.c
-@@ -838,7 +838,7 @@ static int mxs_i2c_probe(struct platform
- return err;
-
- adap = &i2c->adapter;
-- strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
-+ strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
- adap->owner = THIS_MODULE;
- adap->algo = &mxs_i2c_algo;
- adap->quirks = &mxs_i2c_quirks;
---- a/drivers/i2c/busses/i2c-nvidia-gpu.c
-+++ b/drivers/i2c/busses/i2c-nvidia-gpu.c
-@@ -319,7 +319,7 @@ static int gpu_i2c_probe(struct pci_dev
-
- i2c_set_adapdata(&i2cd->adapter, i2cd);
- i2cd->adapter.owner = THIS_MODULE;
-- strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
-+ strscpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
- sizeof(i2cd->adapter.name));
- i2cd->adapter.algo = &gpu_i2c_algorithm;
- i2cd->adapter.quirks = &gpu_i2c_quirks;
---- a/drivers/i2c/busses/i2c-omap.c
-+++ b/drivers/i2c/busses/i2c-omap.c
-@@ -1488,7 +1488,7 @@ omap_i2c_probe(struct platform_device *p
- i2c_set_adapdata(adap, omap);
- adap->owner = THIS_MODULE;
- adap->class = I2C_CLASS_DEPRECATED;
-- strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
-+ strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
- adap->algo = &omap_i2c_algo;
- adap->quirks = &omap_i2c_quirks;
- adap->dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-opal.c
-+++ b/drivers/i2c/busses/i2c-opal.c
-@@ -220,9 +220,9 @@ static int i2c_opal_probe(struct platfor
- adapter->dev.of_node = of_node_get(pdev->dev.of_node);
- pname = of_get_property(pdev->dev.of_node, "ibm,port-name", NULL);
- if (pname)
-- strlcpy(adapter->name, pname, sizeof(adapter->name));
-+ strscpy(adapter->name, pname, sizeof(adapter->name));
- else
-- strlcpy(adapter->name, "opal", sizeof(adapter->name));
-+ strscpy(adapter->name, "opal", sizeof(adapter->name));
-
- platform_set_drvdata(pdev, adapter);
- rc = i2c_add_adapter(adapter);
---- a/drivers/i2c/busses/i2c-parport.c
-+++ b/drivers/i2c/busses/i2c-parport.c
-@@ -308,7 +308,7 @@ static void i2c_parport_attach(struct pa
- /* Fill the rest of the structure */
- adapter->adapter.owner = THIS_MODULE;
- adapter->adapter.class = I2C_CLASS_HWMON;
-- strlcpy(adapter->adapter.name, "Parallel port adapter",
-+ strscpy(adapter->adapter.name, "Parallel port adapter",
- sizeof(adapter->adapter.name));
- adapter->algo_data = parport_algo_data;
- /* Slow down if we can't sense SCL */
---- a/drivers/i2c/busses/i2c-pxa.c
-+++ b/drivers/i2c/busses/i2c-pxa.c
-@@ -1403,7 +1403,7 @@ static int i2c_pxa_probe(struct platform
- spin_lock_init(&i2c->lock);
- init_waitqueue_head(&i2c->wait);
-
-- strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
-
- i2c->clk = devm_clk_get(&dev->dev, NULL);
- if (IS_ERR(i2c->clk)) {
---- a/drivers/i2c/busses/i2c-qcom-geni.c
-+++ b/drivers/i2c/busses/i2c-qcom-geni.c
-@@ -577,7 +577,7 @@ static int geni_i2c_probe(struct platfor
- i2c_set_adapdata(&gi2c->adap, gi2c);
- gi2c->adap.dev.parent = dev;
- gi2c->adap.dev.of_node = dev->of_node;
-- strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
-+ strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
-
- ret = geni_icc_get(&gi2c->se, "qup-memory");
- if (ret)
---- a/drivers/i2c/busses/i2c-qup.c
-+++ b/drivers/i2c/busses/i2c-qup.c
-@@ -1878,7 +1878,7 @@ nodma:
- qup->adap.dev.of_node = pdev->dev.of_node;
- qup->is_last = true;
-
-- strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
-+ strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
-
- pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
- pm_runtime_use_autosuspend(qup->dev);
---- a/drivers/i2c/busses/i2c-rcar.c
-+++ b/drivers/i2c/busses/i2c-rcar.c
-@@ -1059,7 +1059,7 @@ static int rcar_i2c_probe(struct platfor
- adap->bus_recovery_info = &rcar_i2c_bri;
- adap->quirks = &rcar_i2c_quirks;
- i2c_set_adapdata(adap, priv);
-- strlcpy(adap->name, pdev->name, sizeof(adap->name));
-+ strscpy(adap->name, pdev->name, sizeof(adap->name));
-
- /* Init DMA */
- sg_init_table(&priv->sg, 1);
---- a/drivers/i2c/busses/i2c-riic.c
-+++ b/drivers/i2c/busses/i2c-riic.c
-@@ -447,7 +447,7 @@ static int riic_i2c_probe(struct platfor
-
- adap = &riic->adapter;
- i2c_set_adapdata(adap, riic);
-- strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
-+ strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
- adap->owner = THIS_MODULE;
- adap->algo = &riic_algo;
- adap->dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-rk3x.c
-+++ b/drivers/i2c/busses/i2c-rk3x.c
-@@ -1240,7 +1240,7 @@ static int rk3x_i2c_probe(struct platfor
- /* use common interface to get I2C timing properties */
- i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
-
-- strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
- i2c->adap.owner = THIS_MODULE;
- i2c->adap.algo = &rk3x_i2c_algorithm;
- i2c->adap.retries = 3;
---- a/drivers/i2c/busses/i2c-s3c2410.c
-+++ b/drivers/i2c/busses/i2c-s3c2410.c
-@@ -1076,7 +1076,7 @@ static int s3c24xx_i2c_probe(struct plat
- else
- s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
-
-- strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
- i2c->adap.owner = THIS_MODULE;
- i2c->adap.algo = &s3c24xx_i2c_algorithm;
- i2c->adap.retries = 2;
---- a/drivers/i2c/busses/i2c-sh_mobile.c
-+++ b/drivers/i2c/busses/i2c-sh_mobile.c
-@@ -930,7 +930,7 @@ static int sh_mobile_i2c_probe(struct pl
- adap->nr = dev->id;
- adap->dev.of_node = dev->dev.of_node;
-
-- strlcpy(adap->name, dev->name, sizeof(adap->name));
-+ strscpy(adap->name, dev->name, sizeof(adap->name));
-
- spin_lock_init(&pd->lock);
- init_waitqueue_head(&pd->wait);
---- a/drivers/i2c/busses/i2c-simtec.c
-+++ b/drivers/i2c/busses/i2c-simtec.c
-@@ -99,7 +99,7 @@ static int simtec_i2c_probe(struct platf
- pd->adap.algo_data = &pd->bit;
- pd->adap.dev.parent = &dev->dev;
-
-- strlcpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name));
-+ strscpy(pd->adap.name, "Simtec I2C", sizeof(pd->adap.name));
-
- pd->bit.data = pd;
- pd->bit.setsda = simtec_i2c_setsda;
---- a/drivers/i2c/busses/i2c-taos-evm.c
-+++ b/drivers/i2c/busses/i2c-taos-evm.c
-@@ -239,7 +239,7 @@ static int taos_connect(struct serio *se
- dev_err(&serio->dev, "TAOS EVM identification failed\n");
- goto exit_close;
- }
-- strlcpy(adapter->name, name, sizeof(adapter->name));
-+ strscpy(adapter->name, name, sizeof(adapter->name));
-
- /* Turn echo off for better performance */
- taos->state = TAOS_STATE_EOFF;
---- a/drivers/i2c/busses/i2c-tegra-bpmp.c
-+++ b/drivers/i2c/busses/i2c-tegra-bpmp.c
-@@ -305,7 +305,7 @@ static int tegra_bpmp_i2c_probe(struct p
-
- i2c_set_adapdata(&i2c->adapter, i2c);
- i2c->adapter.owner = THIS_MODULE;
-- strlcpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
-+ strscpy(i2c->adapter.name, "Tegra BPMP I2C adapter",
- sizeof(i2c->adapter.name));
- i2c->adapter.algo = &tegra_bpmp_i2c_algo;
- i2c->adapter.dev.parent = &pdev->dev;
---- a/drivers/i2c/busses/i2c-tegra.c
-+++ b/drivers/i2c/busses/i2c-tegra.c
-@@ -1799,7 +1799,7 @@ static int tegra_i2c_probe(struct platfo
- if (i2c_dev->hw->supports_bus_clear)
- i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
-
-- strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
-+ strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
- sizeof(i2c_dev->adapter.name));
-
- err = i2c_add_numbered_adapter(&i2c_dev->adapter);
---- a/drivers/i2c/busses/i2c-uniphier-f.c
-+++ b/drivers/i2c/busses/i2c-uniphier-f.c
-@@ -564,7 +564,7 @@ static int uniphier_fi2c_probe(struct pl
- priv->adap.algo = &uniphier_fi2c_algo;
- priv->adap.dev.parent = dev;
- priv->adap.dev.of_node = dev->of_node;
-- strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
-+ strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
- priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
- i2c_set_adapdata(&priv->adap, priv);
- platform_set_drvdata(pdev, priv);
---- a/drivers/i2c/busses/i2c-uniphier.c
-+++ b/drivers/i2c/busses/i2c-uniphier.c
-@@ -358,7 +358,7 @@ static int uniphier_i2c_probe(struct pla
- priv->adap.algo = &uniphier_i2c_algo;
- priv->adap.dev.parent = dev;
- priv->adap.dev.of_node = dev->of_node;
-- strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
-+ strscpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
- priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
- i2c_set_adapdata(&priv->adap, priv);
- platform_set_drvdata(pdev, priv);
---- a/drivers/i2c/busses/i2c-versatile.c
-+++ b/drivers/i2c/busses/i2c-versatile.c
-@@ -79,7 +79,7 @@ static int i2c_versatile_probe(struct pl
- writel(SCL | SDA, i2c->base + I2C_CONTROLS);
-
- i2c->adap.owner = THIS_MODULE;
-- strlcpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name));
-+ strscpy(i2c->adap.name, "Versatile I2C adapter", sizeof(i2c->adap.name));
- i2c->adap.algo_data = &i2c->algo;
- i2c->adap.dev.parent = &dev->dev;
- i2c->adap.dev.of_node = dev->dev.of_node;
---- a/drivers/i2c/busses/i2c-wmt.c
-+++ b/drivers/i2c/busses/i2c-wmt.c
-@@ -413,7 +413,7 @@ static int wmt_i2c_probe(struct platform
-
- adap = &i2c_dev->adapter;
- i2c_set_adapdata(adap, i2c_dev);
-- strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
-+ strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
- adap->owner = THIS_MODULE;
- adap->algo = &wmt_i2c_algo;
- adap->dev.parent = &pdev->dev;
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -318,7 +318,7 @@
+@@ -314,7 +314,7 @@
/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
* SATA functions. i.e. output-high: PCIe, output-low: SATA
*/
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
-@@ -1729,6 +1729,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+@@ -1588,6 +1588,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
endchoice
default ""
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
-@@ -1162,6 +1162,17 @@ int __init early_init_dt_scan_chosen(uns
+@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
if (p != NULL && l > 0)
- strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
+ strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
-+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+ * device tree option of chosen/bootargs-override. This is
-+ * helpful on boards where u-boot sets bootargs, and is unable
-+ * to be modified.
-+ */
++ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++ * device tree option of chosen/bootargs-override. This is
++ * helpful on boards where u-boot sets bootargs, and is unable
++ * to be modified.
++ */
+#ifdef CONFIG_CMDLINE_OVERRIDE
+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
+ if (p != NULL && l > 0)
-+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));
++ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
+#endif
+
+ handle_cmdline:
/*
* CONFIG_CMDLINE is meant to be a default in case nothing else
- * managed to set the command line, unless CONFIG_CMDLINE_FORCE
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
-@@ -1942,6 +1942,14 @@ config CMDLINE_FORCE
+@@ -2202,6 +2202,14 @@ config CMDLINE_FORCE
endchoice
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -645,5 +645,28 @@
+@@ -641,5 +641,28 @@
};
&wmac {
+++ /dev/null
-From 59b0f51335644ee603260faaa4298c0115fb7187 Mon Sep 17 00:00:00 2001
-From: Fengquan Chen <Fengquan.Chen@mediatek.com>
-Date: Tue, 14 Sep 2021 20:34:54 +0800
-Subject: [PATCH] watchdog: mtk: add disable_wdt_extrst support
-
-In some cases, we may need watchdog just to trigger an
-internal soc reset without sending any output signal.
-
-Provide a disable_wdt_extrst parameter for configuration.
-We can disable or enable it just by configuring dts.
-
-Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20210914123454.32603-3-Fengquan.Chen@mediatek.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -65,6 +65,7 @@ struct mtk_wdt_dev {
- void __iomem *wdt_base;
- spinlock_t lock; /* protects WDT_SWSYSRST reg */
- struct reset_controller_dev rcdev;
-+ bool disable_wdt_extrst;
- };
-
- struct mtk_wdt_data {
-@@ -256,6 +257,8 @@ static int mtk_wdt_start(struct watchdog
- reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
- else
- reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
-+ if (mtk_wdt->disable_wdt_extrst)
-+ reg &= ~WDT_MODE_EXRST_EN;
- reg |= (WDT_MODE_EN | WDT_MODE_KEY);
- iowrite32(reg, wdt_base + WDT_MODE);
-
-@@ -381,6 +384,10 @@ static int mtk_wdt_probe(struct platform
- if (err)
- return err;
- }
-+
-+ mtk_wdt->disable_wdt_extrst =
-+ of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
-+
- return 0;
- }
-
+++ /dev/null
-From 711a5b25bac95dcd1111521ed71693330e74a926 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Wed, 5 Jan 2022 18:04:56 +0800
-Subject: [PATCH] watchdog: mtk_wdt: mt7986: Add toprgu reset controller
- support
-
-Besides watchdog, the mt7986 toprgu module also provides software reset
-functionality for various peripheral subsystems
-(eg, ethernet, pcie, and connectivity)
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220105100456.7126-3-sam.shih@mediatek.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -10,6 +10,7 @@
- */
-
- #include <dt-bindings/reset-controller/mt2712-resets.h>
-+#include <dt-bindings/reset/mt7986-resets.h>
- #include <dt-bindings/reset-controller/mt8183-resets.h>
- #include <dt-bindings/reset-controller/mt8192-resets.h>
- #include <dt-bindings/reset/mt8195-resets.h>
-@@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt2712_
- .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
- };
-
-+static const struct mtk_wdt_data mt7986_data = {
-+ .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
-+};
-+
- static const struct mtk_wdt_data mt8183_data = {
- .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
- };
-@@ -418,6 +423,7 @@ static int mtk_wdt_resume(struct device
- static const struct of_device_id mtk_wdt_dt_ids[] = {
- { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
- { .compatible = "mediatek,mt6589-wdt" },
-+ { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
- { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
- { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
- { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 4 May 2022 12:03:42 +0200
-Subject: [PATCH] PCI: mediatek-gen3: change driver name to mtk-pcie-gen3
-
-This allows it to coexist with the other mtk pcie driver in the same kernel
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d
- .probe = mtk_pcie_probe,
- .remove = mtk_pcie_remove,
- .driver = {
-- .name = "mtk-pcie",
-+ .name = "mtk-pcie-gen3",
- .of_match_table = mtk_pcie_of_match,
- .pm = &mtk_pcie_pm_ops,
- },
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
-@@ -1231,10 +1231,16 @@ static int mtk_spi_probe(struct platform
- goto err_disable_spi_hclk;
- }
+@@ -1225,8 +1225,15 @@ static int mtk_spi_probe(struct platform
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to enable hclk\n");
+ ret = clk_prepare_enable(mdata->sel_clk);
+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to enable sel_clk (%d)\n", ret);
-+ goto err_disable_spi_clk;
++ clk_disable_unprepare(mdata->spi_hclk);
++ return dev_err_probe(dev, ret, "failed to enable sel_clk\n");
+ }
+
- ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
+ ret = clk_prepare_enable(mdata->spi_clk);
if (ret < 0) {
- dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
-- goto err_disable_spi_clk;
-+ goto err_disable_spi_sel_clk;
++ clk_disable_unprepare(mdata->sel_clk);
+ clk_disable_unprepare(mdata->spi_hclk);
+ return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
}
-
- mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
-@@ -1285,6 +1291,8 @@ static int mtk_spi_probe(struct platform
-
- err_disable_runtime_pm:
- pm_runtime_disable(&pdev->dev);
-+err_disable_spi_sel_clk:
-+ clk_disable_unprepare(mdata->sel_clk);
- err_disable_spi_clk:
- clk_disable_unprepare(mdata->spi_clk);
- err_disable_spi_hclk:
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -813,6 +813,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -806,6 +806,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
-@@ -829,6 +847,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -822,6 +840,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;
projects / openwrt / staging / jow.git / commitdiff