ARM: dts: sun9i: a80-optimus: Order nodes by alphabetical order

Move the mmc nodes above the ohci nodes for proper ordering by name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 78fddd9152a5dc583f44a9d69630791362c86e29..7fd22e888602c7e7bc7897a96e25e90d7ace1d80 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -119,6 +119,31 @@
        status = "okay";
 };
 
+&mmc0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
+       vmmc-supply = <&reg_dcdc1>;
+       bus-width = <4>;
+       cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
+       cd-inverted;
+       status = "okay";
+};
+
+&mmc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc2_8bit_pins>;
+       vmmc-supply = <&reg_dcdc1>;
+       bus-width = <8>;
+       non-removable;
+       cap-mmc-hw-reset;
+       status = "okay";
+};
+
+&mmc2_8bit_pins {
+       /* Increase drive strength for DDR modes */
+       allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &ohci0 {
        status = "okay";
 };
@@ -157,31 +182,6 @@
        };
 };
 
-&mmc0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
-       vmmc-supply = <&reg_dcdc1>;
-       bus-width = <4>;
-       cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
-       cd-inverted;
-       status = "okay";
-};
-
-&mmc2 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&mmc2_8bit_pins>;
-       vmmc-supply = <&reg_dcdc1>;
-       bus-width = <8>;
-       non-removable;
-       cap-mmc-hw-reset;
-       status = "okay";
-};
-
-&mmc2_8bit_pins {
-       /* Increase drive strength for DDR modes */
-       allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-};
-
 &r_ir {
        status = "okay";
 };