model = "D-Link DIR-860L B1";
memory@0 {
+ device_type = "memory";
reg = <0x0 0x8000000>;
};
model = "Firefly FireWRT";
memory@0 {
+ device_type = "memory";
reg = <0x0 0x10000000>;
};
model = "Mediatek MT7621 evaluation board";
memory@0 {
+ device_type = "memory";
reg = <0x0 0x2000000>;
};
model = "Mediatek MT7628AN evaluation board";
memory@0 {
+ device_type = "memory";
reg = <0x0 0x2000000>;
};
model = "Buffalo WSR-1166DHP";
memory@0 {
+ device_type = "memory";
reg = <0x0 0x8000000>;
};
model = "Buffalo WSR-600DHP";
memory@0 {
+ device_type = "memory";
reg = <0x0 0x4000000>;
};
#reset-cells = <1>;
};
- usbphy {
+ usbphy: usbphy {
compatible = "ralink,mt7620a-usbphy";
+ #phy-cells = <1>;
resets = <&rstctrl 22 &rstctrl 25>;
reset-names = "host", "device";
interrupt-parent = <&intc>;
interrupts = <18>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
status = "disabled";
};
interrupt-parent = <&intc>;
interrupts = <18>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
status = "disabled";
};
#reset-cells = <1>;
};
- usbphy {
+ usbphy: usbphy {
compatible = "ralink,mt7620a-usbphy";
+ #phy-cells = <1>;
resets = <&rstctrl 22 &rstctrl 25>;
reset-names = "host", "device";
interrupt-parent = <&intc>;
interrupts = <18>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
status = "disabled";
};
compatible = "ralink,rt3xxx-ohci";
reg = <0x101c1000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
#reset-cells = <1>;
};
- usbphy {
+ usbphy: usbphy {
compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
+ #phy-cells = <1>;
resets = <&rstctrl 22>;
reset-names = "host";
compatible = "ralink,rt3xxx-ehci";
reg = <0x101c0000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
};
compatible = "ralink,rt3xxx-ohci";
reg = <0x101c1000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
};
};
};
- usbphy {
+ usbphy: usbphy {
compatible = "ralink,rt3xxx-usbphy";
+ #phy-cells = <1>;
resets = <&rstctrl 22 &rstctrl 25>;
reset-names = "host", "device";
compatible = "ralink,rt3xxx-ehci", "ehci-platform";
reg = <0x101c0000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
compatible = "ralink,rt3xxx-ohci", "ohci-platform";
reg = <0x101c1000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
#reset-cells = <1>;
};
- usbphy {
+ usbphy: usbphy {
compatible = "ralink,rt3xxx-usbphy";
+ #phy-cells = <1>;
resets = <&rstctrl 22 &rstctrl 25>;
reset-names = "host", "device";
compatible = "ralink,rt3xxx-ehci", "ehci-platform";
reg = <0x101c0000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
};
compatible = "ralink,rt3xxx-ohci", "ohci-platform";
reg = <0x101c1000 0x1000>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+
interrupt-parent = <&intc>;
interrupts = <18>;
};
do {
data_src = &hwstats->tx_bytes;
data_dst = data;
- start = u64_stats_fetch_begin_bh(&hwstats->syncp);
+ start = u64_stats_fetch_begin_irq(&hwstats->syncp);
for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
*data_dst++ = *data_src++;
- } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
+ } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
}
static struct ethtool_ops fe_ethtool_ops = {
}
do {
- start = u64_stats_fetch_begin_bh(&hwstats->syncp);
+ start = u64_stats_fetch_begin_irq(&hwstats->syncp);
storage->rx_packets = hwstats->rx_packets;
storage->tx_packets = hwstats->tx_packets;
storage->rx_bytes = hwstats->rx_bytes;
storage->rx_crc_errors = hwstats->rx_fcs_errors;
storage->rx_errors = hwstats->rx_checksum_errors;
storage->tx_aborted_errors = hwstats->tx_skip;
- } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
+ } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
storage->tx_errors = priv->netdev->stats.tx_errors;
storage->rx_dropped = priv->netdev->stats.rx_dropped;
else
soc->reg_table = fe_reg_table;
- fe_base = devm_request_and_ioremap(&pdev->dev, res);
+ fe_base = devm_ioremap_resource(&pdev->dev, res);
if (!fe_base) {
err = -EADDRNOTAVAIL;
goto err_out;
#include <linux/dma-mapping.h>
#include <linux/phy.h>
#include <linux/ethtool.h>
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
+#define u64_stats_fetch_retry_irq u64_stats_fetch_retry_bh
+#define u64_stats_fetch_begin_irq u64_stats_fetch_begin_bh
+#endif
enum fe_reg {
FE_REG_PDMA_GLO_CFG = 0,
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_MT7628AN_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-# CONFIG_GPIO_MT7621 is not set
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INET_LRO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_O32_FP64_SUPPORT is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MT7621_WDT is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MT7620=y
-# CONFIG_NET_RALINK_RT305X is not set
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+# CONFIG_GPIO_MT7621 is not set
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INET_LRO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_WORK=y
+CONFIG_KERNFS=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT7621_WDT is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_MT7620=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SUPPORT=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_GSW_MT7620=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MT7620=y
+# CONFIG_NET_RALINK_RT305X is not set
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+CONFIG_RALINK_WDT=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_CEVT_GIC is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7621_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_GIC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-CONFIG_MIPS_CMP=y
-CONFIG_MIPS_CPU_SCACHE=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=6
-CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT=y
-# CONFIG_MIPS_MT_DISABLED is not set
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_O32_FP64_SUPPORT is not set
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TRX_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MT7620=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SCHED_SMT=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SLUB_CPU_PARTIAL=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-# CONFIG_SOC_MT7620 is not set
-CONFIG_SOC_MT7621=y
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_STOP_MACHINE=y
-CONFIG_SWCONFIG=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS_CMP=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TREE_RCU=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_MT7621_XHCI_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_XPS=y
-CONFIG_ZONE_DMA_FLAG=0
-# CONFIG_MTK_MTD_NAND is not set
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_CEVT_GIC is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7621_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_GIC=y
+CONFIG_IRQ_WORK=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+CONFIG_MIPS_CMP=y
+CONFIG_MIPS_CPU_SCACHE=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_DISABLED is not set
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+# CONFIG_MIPS_VPE_LOADER is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TRX_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_GSW_MT7620=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MT7620=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PINCONF is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_SCHED_SMT=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SLUB_CPU_PARTIAL=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+# CONFIG_SOC_MT7620 is not set
+CONFIG_SOC_MT7621=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_SWCONFIG=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS_CMP=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_MT7621_XHCI_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_ZONE_DMA_FLAG=0
+# CONFIG_MTK_MTD_NAND is not set
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_AT803X_PHY=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_MT7628AN_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INET_LRO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_O32_FP64_SUPPORT is not set
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND_MT7620=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_ESW_RT3052=y
-# CONFIG_NET_RALINK_MT7620 is not set
-CONFIG_NET_RALINK_RT305X=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INET_LRO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_WORK=y
+CONFIG_KERNFS=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_MT7620=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SUPPORT=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_ESW_RT3052=y
+# CONFIG_NET_RALINK_MT7620 is not set
+CONFIG_NET_RALINK_RT305X=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+# CONFIG_RALINK_WDT is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+From 453850d315070678245f61202ae343153589e5a6 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:16:50 +0100
+Subject: [PATCH 01/57] MIPS: ralink: add verbose pmu info
+
+Print the PMU and LDO settings on boot.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -20,6 +20,22 @@
+
+ #include "common.h"
+
++/* analog */
++#define PMU0_CFG 0x88
++#define PMU_SW_SET BIT(28)
++#define A_DCDC_EN BIT(24)
++#define A_SSC_PERI BIT(19)
++#define A_SSC_GEN BIT(18)
++#define A_SSC_M 0x3
++#define A_SSC_S 16
++#define A_DLY_M 0x7
++#define A_DLY_S 8
++#define A_VTUNE_M 0xff
++
++/* digital */
++#define PMU1_CFG 0x8C
++#define DIG_SW_SEL BIT(25)
++
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+@@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_inf
+ u32 n1;
+ u32 rev;
+ u32 cfg0;
++ u32 pmu0;
++ u32 pmu1;
+
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+@@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_inf
+ BUG();
+ }
+ soc_info->mem_base = MT7620_DRAM_BASE;
++
++ pmu0 = __raw_readl(sysc + PMU0_CFG);
++ pmu1 = __raw_readl(sysc + PMU1_CFG);
++
++ pr_info("Analog PMU set to %s control\n",
++ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
++ pr_info("Digital PMU set to %s control\n",
++ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+ }
--- /dev/null
+From 1751f28d4779df83cc793c9d7ff75485c0ceaa23 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:53:02 +0000
+Subject: [PATCH 02/57] MIPS: ralink: add a helper for reading the ECO version
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -105,4 +105,9 @@
+ #define MT7620_GPIO_MODE_EPHY BIT(15)
+ #define MT7620_GPIO_MODE_WDT BIT(22)
+
++static inline int mt7620_get_eco(void)
++{
++ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
++}
++
+ #endif
--- /dev/null
+From 0f0f041cd6a05eb865e391155d3299bb55ff00e3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 19 May 2013 00:42:23 +0200
+Subject: [PATCH 03/57] MIPS: ralink: add rt_sysc_m32 helper
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/ralink_regs.h | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned r
+ return __raw_readl(rt_sysc_membase + reg);
+ }
+
++static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
++{
++ u32 val = rt_sysc_r32(reg) & ~clr;
++
++ __raw_writel(val | set, rt_sysc_membase + reg);
++}
++
+ static inline void rt_memc_w32(u32 val, unsigned reg)
+ {
+ __raw_writel(val, rt_memc_membase + reg);
--- /dev/null
+From af03898c74172ab16d610f3eeaa65f66401eb7db Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 21 May 2013 15:50:31 +0200
+Subject: [PATCH 04/57] MIPS: ralink: adds a bootrom dumper module
+
+This patch adds a trivial driver that allows userland to extract the bootrom of
+a SoC via debugfs.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile | 2 ++
+ arch/mips/ralink/bootrom.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 50 insertions(+)
+ create mode 100644 arch/mips/ralink/bootrom.c
+
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -16,3 +16,5 @@ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+ obj-$(CONFIG_SOC_MT7620) += mt7620.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++
++obj-$(CONFIG_DEBUG_FS) += bootrom.o
+--- /dev/null
++++ b/arch/mips/ralink/bootrom.c
+@@ -0,0 +1,48 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++
++#define BOOTROM_OFFSET 0x10118000
++#define BOOTROM_SIZE 0x8000
++
++static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
++
++static int bootrom_show(struct seq_file *s, void *unused)
++{
++ seq_write(s, membase, BOOTROM_SIZE);
++
++ return 0;
++}
++
++static int bootrom_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, bootrom_show, NULL);
++}
++
++static const struct file_operations bootrom_file_ops = {
++ .open = bootrom_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int bootrom_setup(void)
++{
++ if (!debugfs_create_file("bootrom", 0444,
++ NULL, NULL, &bootrom_file_ops)) {
++ pr_err("Failed to create bootrom debugfs file\n");
++
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++postcore_initcall(bootrom_setup);
--- /dev/null
+From 60999174904c731e55992a4087999bbd4e5f2051 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 16 May 2013 23:28:23 +0200
+Subject: [PATCH 05/57] MIPS: ralink: add illegal access driver
+
+these SoCs have a special irq that fires upon an illegal memmory access.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile | 2 +
+ arch/mips/ralink/ill_acc.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 89 insertions(+)
+ create mode 100644 arch/mips/ralink/ill_acc.c
+
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o
+
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+
++obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
++
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+--- /dev/null
++++ b/arch/mips/ralink/ill_acc.c
+@@ -0,0 +1,87 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define REG_ILL_ACC_ADDR 0x10
++#define REG_ILL_ACC_TYPE 0x14
++
++#define ILL_INT_STATUS BIT(31)
++#define ILL_ACC_WRITE BIT(30)
++#define ILL_ACC_LEN_M 0xff
++#define ILL_ACC_OFF_M 0xf
++#define ILL_ACC_OFF_S 16
++#define ILL_ACC_ID_M 0x7
++#define ILL_ACC_ID_S 8
++
++#define DRV_NAME "ill_acc"
++
++static const char *ill_acc_ids[] = {
++ "cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
++};
++
++static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
++{
++ struct device *dev = (struct device *) _priv;
++ u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
++ u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
++
++ dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
++ (type & ILL_ACC_WRITE) ? ("write") : ("read"),
++ ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
++ addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
++ type & ILL_ACC_LEN_M);
++
++ rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
++
++ return IRQ_HANDLED;
++}
++
++static int __init ill_acc_of_setup(void)
++{
++ struct platform_device *pdev;
++ struct device_node *np;
++ int irq;
++
++ /* somehow this driver breaks on RT5350 */
++ if (of_machine_is_compatible("ralink,rt5350-soc"))
++ return -EINVAL;
++
++ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
++ if (!np)
++ return -EINVAL;
++
++ pdev = of_find_device_by_node(np);
++ if (!pdev) {
++ pr_err("%s: failed to lookup pdev\n", np->name);
++ return -EINVAL;
++ }
++
++ irq = irq_of_parse_and_map(np, 0);
++ if (!irq) {
++ dev_err(&pdev->dev, "failed to get irq\n");
++ return -EINVAL;
++ }
++
++ if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
++ dev_err(&pdev->dev, "failed to request irq\n");
++ return -EINVAL;
++ }
++
++ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
++
++ dev_info(&pdev->dev, "irq registered\n");
++
++ return 0;
++}
++
++arch_initcall(ill_acc_of_setup);
--- /dev/null
+From 979ad9f0324ad8fa5eb4a00b57d9feb061aa3200 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:38:07 +0000
+Subject: [PATCH 06/57] MIPS: ralink: add missing clk_set_rate() to clk.c
+
+This function was missing causing allmod to fail.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/clk.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c
+ }
+ EXPORT_SYMBOL_GPL(clk_get_rate);
+
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ return -1;
++}
++EXPORT_SYMBOL_GPL(clk_set_rate);
++
+ void __init plat_time_init(void)
+ {
+ struct clk *clk;
--- /dev/null
+From efc0f99cebcab21dbabcc634b9dbb963bbbbcab8 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:23:36 +0100
+Subject: [PATCH 07/57] MIPS: ralink: add support for MT7620n
+
+This is the small version of MT7620a.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
+ arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
+ 2 files changed, 14 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -25,11 +25,8 @@
+ #define SYSC_REG_CPLL_CONFIG0 0x54
+ #define SYSC_REG_CPLL_CONFIG1 0x58
+
+-#define MT7620N_CHIP_NAME0 0x33365452
+-#define MT7620N_CHIP_NAME1 0x20203235
+-
+-#define MT7620A_CHIP_NAME0 0x3637544d
+-#define MT7620A_CHIP_NAME1 0x20203032
++#define MT7620_CHIP_NAME0 0x3637544d
++#define MT7620_CHIP_NAME1 0x20203032
+
+ #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -357,22 +357,27 @@ void prom_soc_init(struct ralink_soc_inf
+ u32 cfg0;
+ u32 pmu0;
+ u32 pmu1;
++ u32 bga;
+
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
++ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
+
+- if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
+- name = "MT7620N";
+- soc_info->compatible = "ralink,mt7620n-soc";
+- } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
++ if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
++ panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++
++ if (bga) {
+ name = "MT7620A";
+ soc_info->compatible = "ralink,mt7620a-soc";
+ } else {
+- panic("mt7620: unknown SoC, n0:%08x n1:%08x", n0, n1);
++ name = "MT7620N";
++ soc_info->compatible = "ralink,mt7620n-soc";
++#ifdef CONFIG_PCI
++ panic("mt7620n is only supported for non pci kernels");
++#endif
+ }
+
+- rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
+-
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+ "Ralink %s ver:%u eco:%u",
+ name,
--- /dev/null
+From 071e97587a291d3a5bbd614a425f46b7f90310aa Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:40:48 +0000
+Subject: [PATCH 08/57] MIPS: ralink: allow manual memory override
+
+RT5350 relies on the bootloader setting up the memc correctly.
+On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range
+.
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c | 16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -53,6 +53,17 @@ void __init device_tree_init(void)
+ unflatten_and_copy_device_tree();
+ }
+
++static int memory_dtb;
++
++static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
++ int depth, void *data)
++{
++ if (depth == 1 && !strcmp(uname, "memory@0"))
++ memory_dtb = 1;
++
++ return 0;
++}
++
+ void __init plat_mem_setup(void)
+ {
+ set_io_port_base(KSEG1);
+@@ -63,7 +74,10 @@ void __init plat_mem_setup(void)
+ */
+ __dt_setup_arch(__dtb_start);
+
+- if (soc_info.mem_size)
++ of_scan_flat_dt(early_init_dt_find_memory, NULL);
++ if (memory_dtb)
++ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
++ else if (soc_info.mem_size)
+ add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
+ BOOT_MEM_RAM);
+ else
--- /dev/null
+From 1cb19fe02c830e278b91498edea09fbda37c4a21 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 10:13:43 +0100
+Subject: [PATCH 09/57] MIPS: ralink: define the wmac clock on mt7620
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -336,6 +336,7 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("10000500.uart", periph_rate);
+ ralink_clk_add("10000b00.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", periph_rate);
++ ralink_clk_add("10180000.wmac", xtal_rate);
+ }
+
+ void __init ralink_of_remap(void)
--- /dev/null
+From 1f17cf131fc2ae7fa2651dbe6a622dd125939718 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 10:14:30 +0100
+Subject: [PATCH 10/57] MIPS: ralink: define the wmac clock on rt3883
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/rt3883.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -204,6 +204,7 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("10000b00.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", 40000000);
+ ralink_clk_add("10100000.ethernet", sys_rate);
++ ralink_clk_add("10180000.wmac", 40000000);
+ }
+
+ void __init ralink_of_remap(void)
--- /dev/null
+From bf4f5250117cd65a78903b8ce302499806416ed1 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Aug 2014 09:52:22 +0200
+Subject: [PATCH 11/57] MIPS: ralink: add rt2880 wmac clock
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/rt288x.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -76,7 +76,7 @@ struct ralink_pinmux rt_gpio_pinmux = {
+
+ void __init ralink_clk_init(void)
+ {
+- unsigned long cpu_rate;
++ unsigned long cpu_rate, wmac_rate = 40000000;
+ u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
+ t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
+
+@@ -101,6 +101,7 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("300500.uart", cpu_rate / 2);
+ ralink_clk_add("300c00.uartlite", cpu_rate / 2);
+ ralink_clk_add("400000.ethernet", cpu_rate / 2);
++ ralink_clk_add("480000.wmac", wmac_rate);
+ }
+
+ void __init ralink_of_remap(void)
--- /dev/null
+From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 10:57:40 +0100
+Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/gic.h | 4 +
+ arch/mips/include/asm/mach-ralink/irq.h | 9 +
+ arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
+ arch/mips/kernel/vmlinux.lds.S | 1 +
+ arch/mips/ralink/Kconfig | 18 ++
+ arch/mips/ralink/Makefile | 7 +-
+ arch/mips/ralink/Platform | 5 +
+ arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
+ arch/mips/ralink/malta-amon.c | 81 +++++++++
+ arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
+ 10 files changed, 617 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
+ create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
+ create mode 100644 arch/mips/ralink/irq-gic.c
+ create mode 100644 arch/mips/ralink/malta-amon.c
+ create mode 100644 arch/mips/ralink/mt7621.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/irq.h
+@@ -0,0 +1,9 @@
++#ifndef __ASM_MACH_RALINK_IRQ_H
++#define __ASM_MACH_RALINK_IRQ_H
++
++#define GIC_NUM_INTRS 64
++#define NR_IRQS 256
++
++#include_next <irq.h>
++
++#endif
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/mt7621.h
+@@ -0,0 +1,39 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _MT7621_REGS_H_
++#define _MT7621_REGS_H_
++
++#define MT7621_SYSC_BASE 0x1E000000
++
++#define SYSC_REG_CHIP_NAME0 0x00
++#define SYSC_REG_CHIP_NAME1 0x04
++#define SYSC_REG_CHIP_REV 0x0c
++#define SYSC_REG_SYSTEM_CONFIG0 0x10
++#define SYSC_REG_SYSTEM_CONFIG1 0x14
++
++#define CHIP_REV_PKG_MASK 0x1
++#define CHIP_REV_PKG_SHIFT 16
++#define CHIP_REV_VER_MASK 0xf
++#define CHIP_REV_VER_SHIFT 8
++#define CHIP_REV_ECO_MASK 0xf
++
++#define MT7621_DRAM_BASE 0x0
++#define MT7621_DDR2_SIZE_MIN 32
++#define MT7621_DDR2_SIZE_MAX 256
++
++#define MT7621_CHIP_NAME0 0x3637544D
++#define MT7621_CHIP_NAME1 0x20203132
++
++#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
++
++#endif
+--- a/arch/mips/kernel/vmlinux.lds.S
++++ b/arch/mips/kernel/vmlinux.lds.S
+@@ -51,6 +51,7 @@ SECTIONS
+ /* read-only */
+ _text = .; /* Text and read-only data */
+ .text : {
++ /*. = . + 0x8000; */
+ TEXT_TEXT
+ SCHED_TEXT
+ LOCK_TEXT
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -7,6 +7,11 @@ config CLKEVT_RT3352
+ select CLKSRC_OF
+ select CLKSRC_MMIO
+
++config IRQ_INTC
++ bool
++ default y
++ depends on !SOC_MT7621
++
+ choice
+ prompt "Ralink SoC selection"
+ default SOC_RT305X
+@@ -28,6 +33,15 @@ choice
+ config SOC_MT7620
+ bool "MT7620"
+
++ config SOC_MT7621
++ bool "MT7621"
++ select MIPS_CPU_SCACHE
++ select SYS_SUPPORTS_MULTITHREADING
++ select SYS_SUPPORTS_SMP
++ select SYS_SUPPORTS_MIPS_CMP
++ select IRQ_GIC
++ select HW_HAS_PCI
++
+ endchoice
+
+ choice
+@@ -59,6 +73,10 @@ choice
+ depends on SOC_MT7620
+ select BUILTIN_DTB
+
++ config DTB_MT7621_EVAL
++ bool "MT7621 eval kit"
++ depends on SOC_MT7621
++
+ endchoice
+
+ endif
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -6,16 +6,21 @@
+ # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
+ # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+
+-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
++obj-y := prom.o of.o reset.o clk.o timer.o
+
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+
+ obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
+
++obj-$(CONFIG_IRQ_INTC) += irq.o
++obj-$(CONFIG_IRQ_GIC) += irq-gic.o
++obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
++
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+ obj-$(CONFIG_SOC_MT7620) += mt7620.o
++obj-$(CONFIG_SOC_MT7621) += mt7621.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
+--- a/arch/mips/ralink/Platform
++++ b/arch/mips/ralink/Platform
+@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
+ #
+ load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
+ cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
++
++# Ralink MT7621
++#
++load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
++cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
+--- /dev/null
++++ b/arch/mips/ralink/irq-gic.c
+@@ -0,0 +1,271 @@
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/hardirq.h>
++#include <linux/preempt.h>
++#include <linux/irqdomain.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++
++#include <asm/irq_cpu.h>
++#include <asm/mipsregs.h>
++
++#include <asm/irq.h>
++#include <asm/setup.h>
++
++#include <asm/gic.h>
++#include <asm/gcmpregs.h>
++
++#include <asm/mach-ralink/mt7621.h>
++
++unsigned long _gcmp_base;
++static int gic_resched_int_base = 56;
++static int gic_call_int_base = 60;
++static struct irq_chip *irq_gic;
++static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
++
++#if defined(CONFIG_MIPS_MT_SMP)
++static int gic_resched_int_base;
++static int gic_call_int_base;
++
++#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
++#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
++
++static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
++{
++ scheduler_ipi();
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t
++ipi_call_interrupt(int irq, void *dev_id)
++{
++ smp_call_function_interrupt();
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction irq_resched = {
++ .handler = ipi_resched_interrupt,
++ .flags = IRQF_DISABLED|IRQF_PERCPU,
++ .name = "ipi resched"
++};
++
++static struct irqaction irq_call = {
++ .handler = ipi_call_interrupt,
++ .flags = IRQF_DISABLED|IRQF_PERCPU,
++ .name = "ipi call"
++};
++
++#endif
++
++static void __init
++gic_fill_map(void)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
++ gic_intr_map[i].cpunum = 0;
++ gic_intr_map[i].pin = GIC_CPU_INT0;
++ gic_intr_map[i].polarity = GIC_POL_POS;
++ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
++ gic_intr_map[i].flags = GIC_FLAG_IPI;
++ }
++
++#if defined(CONFIG_MIPS_MT_SMP)
++ {
++ int cpu;
++
++ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
++ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
++
++ i = gic_resched_int_base;
++
++ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
++ gic_intr_map[i + cpu].cpunum = cpu;
++ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
++ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
++
++ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
++ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
++ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
++ }
++ }
++#endif
++}
++
++void
++gic_irq_ack(struct irq_data *d)
++{
++ int irq = (d->irq - gic_irq_base);
++
++ GIC_CLR_INTR_MASK(irq);
++
++ if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
++ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
++}
++
++void
++gic_finish_irq(struct irq_data *d)
++{
++ GIC_SET_INTR_MASK(d->irq - gic_irq_base);
++}
++
++void __init
++gic_platform_init(int irqs, struct irq_chip *irq_controller)
++{
++ irq_gic = irq_controller;
++}
++
++static void
++gic_irqdispatch(void)
++{
++ unsigned int irq = gic_get_int();
++
++ if (likely(irq < GIC_NUM_INTRS))
++ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
++ else {
++ pr_debug("Spurious GIC Interrupt!\n");
++ spurious_interrupt();
++ }
++
++}
++
++static void
++vi_timer_irqdispatch(void)
++{
++ do_IRQ(cp0_compare_irq);
++}
++
++#if defined(CONFIG_MIPS_MT_SMP)
++unsigned int
++plat_ipi_call_int_xlate(unsigned int cpu)
++{
++ return GIC_CALL_INT(cpu);
++}
++
++unsigned int
++plat_ipi_resched_int_xlate(unsigned int cpu)
++{
++ return GIC_RESCHED_INT(cpu);
++}
++#endif
++
++asmlinkage void
++plat_irq_dispatch(void)
++{
++ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
++
++ if (unlikely(!pending)) {
++ pr_err("Spurious CP0 Interrupt!\n");
++ spurious_interrupt();
++ } else {
++ if (pending & CAUSEF_IP7)
++ do_IRQ(cp0_compare_irq);
++
++ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
++ gic_irqdispatch();
++ }
++}
++
++unsigned int __cpuinit
++get_c0_compare_int(void)
++{
++ return CP0_LEGACY_COMPARE_IRQ;
++}
++
++static int
++gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, irq_gic,
++#if defined(CONFIG_MIPS_MT_SMP)
++ (hw >= gic_resched_int_base) ?
++ handle_percpu_irq :
++#endif
++ handle_level_irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = gic_map,
++};
++
++static int __init
++of_gic_init(struct device_node *node,
++ struct device_node *parent)
++{
++ struct irq_domain *domain;
++ struct resource gcmp = { 0 }, gic = { 0 };
++ unsigned int gic_rev;
++ int i;
++
++ if (of_address_to_resource(node, 0, &gic))
++ panic("Failed to get gic memory range");
++ if (request_mem_region(gic.start, resource_size(&gic),
++ gic.name) < 0)
++ panic("Failed to request gic memory");
++ if (of_address_to_resource(node, 2, &gcmp))
++ panic("Failed to get gic memory range");
++ if (request_mem_region(gcmp.start, resource_size(&gcmp),
++ gcmp.name) < 0)
++ panic("Failed to request gcmp memory");
++
++ _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
++ if (!_gcmp_base)
++ panic("Failed to remap gcmp memory\n");
++
++ if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
++ panic("Failed to find gcmp core\n");
++
++ /* tell the gcmp where to find the gic */
++ GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
++ gic_present = 1;
++ if (cpu_has_vint) {
++ set_vi_handler(2, gic_irqdispatch);
++ set_vi_handler(3, gic_irqdispatch);
++ set_vi_handler(4, gic_irqdispatch);
++ set_vi_handler(7, vi_timer_irqdispatch);
++ }
++
++ gic_fill_map();
++
++ gic_init(gic.start, resource_size(&gic), gic_intr_map,
++ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
++
++ GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
++ pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
++
++ domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
++ 0, &irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add irqdomain");
++
++#if defined(CONFIG_MIPS_MT_SMP)
++ for (i = 0; i < nr_cpu_ids; i++) {
++ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
++ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
++ }
++#endif
++
++ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
++ STATUSF_IP2);
++ return 0;
++}
++
++static struct of_device_id __initdata of_irq_ids[] = {
++ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
++ { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
++ {},
++};
++
++void __init
++arch_init_irq(void)
++{
++ of_irq_init(of_irq_ids);
++}
+--- /dev/null
++++ b/arch/mips/ralink/malta-amon.c
+@@ -0,0 +1,81 @@
++/*
++ * Copyright (C) 2007 MIPS Technologies, Inc.
++ * All rights reserved.
++
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Arbitrary Monitor interface
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/smp.h>
++
++#include <asm/addrspace.h>
++#include <asm/mips-boards/launch.h>
++#include <asm/mipsmtregs.h>
++
++int amon_cpu_avail(int cpu)
++{
++ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
++
++ if (cpu < 0 || cpu >= NCPULAUNCH) {
++ pr_debug("avail: cpu%d is out of range\n", cpu);
++ return 0;
++ }
++
++ launch += cpu;
++ if (!(launch->flags & LAUNCH_FREADY)) {
++ pr_debug("avail: cpu%d is not ready\n", cpu);
++ return 0;
++ }
++ if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
++ pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
++ return 0;
++ }
++
++ return 1;
++}
++
++void amon_cpu_start(int cpu,
++ unsigned long pc, unsigned long sp,
++ unsigned long gp, unsigned long a0)
++{
++ volatile struct cpulaunch *launch =
++ (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
++
++ if (!amon_cpu_avail(cpu))
++ return;
++ if (cpu == smp_processor_id()) {
++ pr_debug("launch: I am cpu%d!\n", cpu);
++ return;
++ }
++ launch += cpu;
++
++ pr_debug("launch: starting cpu%d\n", cpu);
++
++ launch->pc = pc;
++ launch->gp = gp;
++ launch->sp = sp;
++ launch->a0 = a0;
++
++ smp_wmb(); /* Target must see parameters before go */
++ launch->flags |= LAUNCH_FGO;
++ smp_wmb(); /* Target must see go before we poll */
++
++ while ((launch->flags & LAUNCH_FGONE) == 0)
++ ;
++ smp_rmb(); /* Target will be updating flags soon */
++ pr_debug("launch: cpu%d gone!\n", cpu);
++}
+--- /dev/null
++++ b/arch/mips/ralink/mt7621.c
+@@ -0,0 +1,183 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <asm/gcmpregs.h>
++
++#include <asm/mipsregs.h>
++#include <asm/smp-ops.h>
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/mt7621.h>
++
++#include <pinmux.h>
++
++#include "common.h"
++
++#define SYSC_REG_SYSCFG 0x10
++#define SYSC_REG_CPLL_CLKCFG0 0x2c
++#define SYSC_REG_CUR_CLK_STS 0x44
++#define CPU_CLK_SEL (BIT(30) | BIT(31))
++
++#define MT7621_GPIO_MODE_UART1 1
++#define MT7621_GPIO_MODE_I2C 2
++#define MT7621_GPIO_MODE_UART2 3
++#define MT7621_GPIO_MODE_UART3 5
++#define MT7621_GPIO_MODE_JTAG 7
++#define MT7621_GPIO_MODE_WDT_MASK 0x3
++#define MT7621_GPIO_MODE_WDT_SHIFT 8
++#define MT7621_GPIO_MODE_WDT_GPIO 1
++#define MT7621_GPIO_MODE_PCIE_RST 0
++#define MT7621_GPIO_MODE_PCIE_REF 2
++#define MT7621_GPIO_MODE_PCIE_MASK 0x3
++#define MT7621_GPIO_MODE_PCIE_SHIFT 10
++#define MT7621_GPIO_MODE_PCIE_GPIO 1
++#define MT7621_GPIO_MODE_MDIO 12
++#define MT7621_GPIO_MODE_RGMII1 14
++#define MT7621_GPIO_MODE_RGMII2 15
++#define MT7621_GPIO_MODE_SPI_MASK 0x3
++#define MT7621_GPIO_MODE_SPI_SHIFT 16
++#define MT7621_GPIO_MODE_SPI_GPIO 1
++#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
++#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
++#define MT7621_GPIO_MODE_SDHCI_GPIO 1
++
++static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) };
++static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
++static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
++static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
++static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
++static struct rt2880_pmx_func wdt_grp[] = {
++ FUNC("wdt rst", 0, 18, 1),
++ FUNC("wdt refclk", 2, 18, 1),
++};
++static struct rt2880_pmx_func pcie_rst_grp[] = {
++ FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
++ FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
++};
++static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
++static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
++static struct rt2880_pmx_func spi_grp[] = {
++ FUNC("spi", 0, 34, 7),
++ FUNC("nand", 2, 34, 8),
++};
++static struct rt2880_pmx_func sdhci_grp[] = {
++ FUNC("sdhci", 0, 41, 8),
++ FUNC("nand", 2, 41, 8),
++};
++static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) };
++
++static struct rt2880_pmx_group mt7621_pinmux_data[] = {
++ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
++ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
++ GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
++ GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
++ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
++ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
++ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
++ GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
++ MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
++ GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
++ GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
++ GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
++ MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
++ GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
++ MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
++ GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
++ { 0 }
++};
++
++void __init ralink_clk_init(void)
++{
++ int cpu_fdiv = 0;
++ int cpu_ffrac = 0;
++ int fbdiv = 0;
++ u32 clk_sts, syscfg;
++ u8 clk_sel = 0, xtal_mode;
++ u32 cpu_clk;
++
++ if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
++ clk_sel = 1;
++
++ switch (clk_sel) {
++ case 0:
++ clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
++ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
++ cpu_ffrac = (clk_sts & 0x1F);
++ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
++ break;
++
++ case 1:
++ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
++ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
++ xtal_mode = (syscfg >> 6) & 0x7;
++ if(xtal_mode >= 6) { //25Mhz Xtal
++ cpu_clk = 25 * fbdiv * 1000 * 1000;
++ } else if(xtal_mode >=3) { //40Mhz Xtal
++ cpu_clk = 40 * fbdiv * 1000 * 1000;
++ } else { // 20Mhz Xtal
++ cpu_clk = 20 * fbdiv * 1000 * 1000;
++ }
++ break;
++ }
++ cpu_clk = 880000000;
++ ralink_clk_add("cpu", cpu_clk);
++ ralink_clk_add("1e000b00.spi", 50000000);
++ ralink_clk_add("1e000c00.uartlite", 50000000);
++ ralink_clk_add("1e000d00.uart", 50000000);
++}
++
++void __init ralink_of_remap(void)
++{
++ rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
++ rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
++
++ if (!rt_sysc_membase || !rt_memc_membase)
++ panic("Failed to remap core resources");
++}
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
++ unsigned char *name = NULL;
++ u32 n0;
++ u32 n1;
++ u32 rev;
++
++ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
++ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++
++ if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
++ name = "MT7621";
++ soc_info->compatible = "mtk,mt7621-soc";
++ } else {
++ panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++ }
++
++ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
++
++ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
++ "Mediatek %s ver:%u eco:%u",
++ name,
++ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
++ (rev & CHIP_REV_ECO_MASK));
++
++ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
++ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
++ soc_info->mem_base = MT7621_DRAM_BASE;
++
++ rt2880_pinmux_data = mt7621_pinmux_data;
++
++ if (register_cmp_smp_ops())
++ panic("failed to register_vsmp_smp_ops()");
++}
--- /dev/null
+From 8f92eac5ace0f834ec069b4bb8e9ad38f162de0e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 27 Jan 2014 13:12:41 +0000
+Subject: [PATCH 13/57] MIPS: ralink: add MT7621 defconfig
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/configs/mt7621_defconfig | 197 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 197 insertions(+)
+ create mode 100644 arch/mips/configs/mt7621_defconfig
+
+--- /dev/null
++++ b/arch/mips/configs/mt7621_defconfig
+@@ -0,0 +1,197 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SYSVIPC=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_RCU_FANOUT=32
++CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/root-ramips /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
++CONFIG_INITRAMFS_ROOT_UID=1000
++CONFIG_INITRAMFS_ROOT_GID=1000
++# CONFIG_RD_GZIP is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_AIO is not set
++CONFIG_EMBEDDED=y
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_SMP=y
++CONFIG_NR_CPUS=4
++CONFIG_SCHED_SMT=y
++# CONFIG_COMPACTION is not set
++# CONFIG_CROSS_MEMORY_ATTACH is not set
++# CONFIG_SECCOMP is not set
++CONFIG_HZ_100=y
++CONFIG_CMDLINE_BOOL=y
++CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_ARPD=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++# CONFIG_INET_DIAG is not set
++CONFIG_TCP_CONG_ADVANCED=y
++# CONFIG_TCP_CONG_BIC is not set
++# CONFIG_TCP_CONG_WESTWOOD is not set
++# CONFIG_TCP_CONG_HTCP is not set
++CONFIG_IPV6_PRIVACY=y
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_NETFILTER=y
++# CONFIG_BRIDGE_NETFILTER is not set
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NF_CONNTRACK_IPV4=m
++# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_NF_NAT_IPV4=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_RAW=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_BRIDGE=m
++# CONFIG_BRIDGE_IGMP_SNOOPING is not set
++CONFIG_VLAN_8021Q=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_HAMRADIO=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++# CONFIG_FIRMWARE_IN_KERNEL is not set
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_COMPLEX_MAPPINGS=y
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_M25P80=y
++CONFIG_EEPROM_93CX6=m
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_NETDEVICES=y
++# CONFIG_NET_PACKET_ENGINE is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWCONFIG=y
++CONFIG_PPP=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPPOE=m
++CONFIG_PPP_ASYNC=m
++CONFIG_ISDN=y
++# CONFIG_INPUT is not set
++# CONFIG_SERIO is not set
++# CONFIG_VT is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++# CONFIG_SERIAL_8250_PCI is not set
++CONFIG_SERIAL_8250_RUNTIME_UARTS=2
++CONFIG_SPI=y
++CONFIG_GPIOLIB=y
++CONFIG_GPIO_SYSFS=y
++# CONFIG_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_CORE=y
++# CONFIG_VGA_ARB is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++CONFIG_USB_MT7621_XHCI_PLATFORM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_PHY=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=m
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_STAGING=y
++CONFIG_USB_DWC2=m
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_PROC_PAGE_MONITOR is not set
++CONFIG_TMPFS=y
++CONFIG_TMPFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_JFFS2_FS_XATTR=y
++# CONFIG_JFFS2_FS_POSIX_ACL is not set
++# CONFIG_JFFS2_FS_SECURITY is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++# CONFIG_JFFS2_ZLIB is not set
++CONFIG_SQUASHFS=y
++# CONFIG_SQUASHFS_ZLIB is not set
++CONFIG_SQUASHFS_XZ=y
++CONFIG_PRINTK_TIME=y
++# CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_STRIP_ASM_SYMS=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_SCHED_DEBUG is not set
++CONFIG_DEBUG_INFO=y
++CONFIG_DEBUG_INFO_REDUCED=y
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_FTRACE is not set
++CONFIG_CRYPTO_ARC4=m
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_VIRTUALIZATION is not set
++CONFIG_CRC_ITU_T=m
++CONFIG_CRC32_SARWATE=y
++# CONFIG_XZ_DEC_X86 is not set
++CONFIG_AVERAGE=y
--- /dev/null
+From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 24 Jan 2014 17:01:17 +0100
+Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk
+
+Add support for the new MT7621/8 SoC and kill ifdefs.
+Cleanup some whitespace error while we are at it.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/early_printk.c | 45 ++++++++++++++++++++++++++-------------
+ 1 file changed, 30 insertions(+), 15 deletions(-)
+
+--- a/arch/mips/ralink/early_printk.c
++++ b/arch/mips/ralink/early_printk.c
+@@ -12,21 +12,24 @@
+ #include <asm/addrspace.h>
+
+ #ifdef CONFIG_SOC_RT288X
+-#define EARLY_UART_BASE 0x300c00
++#define EARLY_UART_BASE 0x300c00
++#define CHIPID_BASE 0x300004
++#elif defined(CONFIG_SOC_MT7621)
++#define EARLY_UART_BASE 0x1E000c00
++#define CHIPID_BASE 0x1E000004
+ #else
+-#define EARLY_UART_BASE 0x10000c00
++#define EARLY_UART_BASE 0x10000c00
++#define CHIPID_BASE 0x10000004
+ #endif
+
+-#define UART_REG_RX 0x00
+-#define UART_REG_TX 0x04
+-#define UART_REG_IER 0x08
+-#define UART_REG_IIR 0x0c
+-#define UART_REG_FCR 0x10
+-#define UART_REG_LCR 0x14
+-#define UART_REG_MCR 0x18
+-#define UART_REG_LSR 0x1c
++#define MT7628_CHIP_NAME1 0x20203832
++
++#define UART_REG_TX 0x04
++#define UART_REG_LSR 0x14
++#define UART_REG_LSR_RT2880 0x1c
+
+ static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
++static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
+
+ static inline void uart_w32(u32 val, unsigned reg)
+ {
+@@ -38,11 +41,23 @@ static inline u32 uart_r32(unsigned reg)
+ return __raw_readl(uart_membase + reg);
+ }
+
++static inline int soc_is_mt7628(void)
++{
++ return IS_ENABLED(CONFIG_SOC_MT7620) &&
++ (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
++}
++
+ void prom_putchar(unsigned char ch)
+ {
+- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+- ;
+- uart_w32(ch, UART_REG_TX);
+- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+- ;
++ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
++ uart_w32(ch, UART_TX);
++ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
++ ;
++ } else {
++ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
++ ;
++ uart_w32(ch, UART_REG_TX);
++ while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
++ ;
++ }
+ }
--- /dev/null
+From 95d7eb13a864ef666cea7f0e86349e86d80d28ce Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 05:22:39 +0000
+Subject: [PATCH 16/57] MIPS: ralink: add MT7621 pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-mt7621.c | 797 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 798 insertions(+)
+ create mode 100644 arch/mips/pci/pci-mt7621.c
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -42,6 +42,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
+ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
+ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
++obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
+--- /dev/null
++++ b/arch/mips/pci/pci-mt7621.c
+@@ -0,0 +1,813 @@
++/**************************************************************************
++ *
++ * BRIEF MODULE DESCRIPTION
++ * PCI init for Ralink RT2880 solution
++ *
++ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ * May 2007 Bruce Chang
++ * Initial Release
++ *
++ * May 2009 Bruce Chang
++ * support RT2880/RT3883 PCIe
++ *
++ * May 2011 Bruce Chang
++ * support RT6855/MT7620 PCIe
++ *
++ **************************************************************************
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/version.h>
++#include <asm/pci.h>
++#include <asm/io.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/of_pci.h>
++#include <linux/platform_device.h>
++
++#include <ralink_regs.h>
++
++extern void pcie_phy_init(void);
++extern void chk_phy_pll(void);
++
++/*
++ * These functions and structures provide the BIOS scan and mapping of the PCI
++ * devices.
++ */
++
++#define CONFIG_PCIE_PORT0
++#define CONFIG_PCIE_PORT1
++#define CONFIG_PCIE_PORT2
++#define RALINK_PCIE0_CLK_EN (1<<24)
++#define RALINK_PCIE1_CLK_EN (1<<25)
++#define RALINK_PCIE2_CLK_EN (1<<26)
++
++#define RALINK_PCI_CONFIG_ADDR 0x20
++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
++#define SURFBOARDINT_PCIE0 12 /* PCIE0 */
++#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
++#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
++#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
++#define SURFBOARDINT_PCIE1 32 /* PCIE1 */
++#define SURFBOARDINT_PCIE2 33 /* PCIE2 */
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCIE0_RST (1<<24)
++#define RALINK_PCIE1_RST (1<<25)
++#define RALINK_PCIE2_RST (1<<26)
++#define RALINK_SYSCTL_BASE 0xBE000000
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_BASE 0xBE140000
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
++#define RT6855_PCIE0_OFFSET 0x2000
++#define RT6855_PCIE1_OFFSET 0x3000
++#define RT6855_PCIE2_OFFSET 0x4000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
++#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
++#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
++
++#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
++#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
++#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
++#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
++#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
++#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
++#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
++#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
++#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
++
++
++#define MV_WRITE(ofs, data) \
++ *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
++#define MV_READ(ofs, data) \
++ *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++#define MV_READ_DATA(ofs) \
++ le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_16(ofs, data) \
++ *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
++#define MV_READ_16(ofs, data) \
++ *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_8(ofs, data) \
++ *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
++#define MV_READ_8(ofs, data) \
++ *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
++
++
++
++#define RALINK_PCI_MM_MAP_BASE 0x60000000
++#define RALINK_PCI_IO_MAP_BASE 0x1e160000
++
++#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
++#define GPIO_PERST
++#define ASSERT_SYSRST_PCIE(val) do { \
++ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
++ RALINK_RSTCTRL |= val; \
++ else \
++ RALINK_RSTCTRL &= ~val; \
++ } while(0)
++#define DEASSERT_SYSRST_PCIE(val) do { \
++ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
++ RALINK_RSTCTRL &= ~val; \
++ else \
++ RALINK_RSTCTRL |= val; \
++ } while(0)
++#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
++#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
++#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
++#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
++#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
++#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
++#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
++#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
++//RALINK_SYSCFG1 bit
++#define RALINK_PCI_HOST_MODE_EN (1<<7)
++#define RALINK_PCIE_RC_MODE_EN (1<<8)
++//RALINK_RSTCTRL bit
++#define RALINK_PCIE_RST (1<<23)
++#define RALINK_PCI_RST (1<<24)
++//RALINK_CLKCFG1 bit
++#define RALINK_PCI_CLK_EN (1<<19)
++#define RALINK_PCIE_CLK_EN (1<<21)
++//RALINK_GPIOMODE bit
++#define PCI_SLOTx2 (1<<11)
++#define PCI_SLOTx1 (2<<11)
++//MTK PCIE PLL bit
++#define PDRV_SW_SET (1<<31)
++#define LC_CKDRVPD_ (1<<19)
++
++#define MEMORY_BASE 0x0
++static int pcie_link_status = 0;
++
++#define PCI_ACCESS_READ_1 0
++#define PCI_ACCESS_READ_2 1
++#define PCI_ACCESS_READ_4 2
++#define PCI_ACCESS_WRITE_1 3
++#define PCI_ACCESS_WRITE_2 4
++#define PCI_ACCESS_WRITE_4 5
++
++static int config_access(unsigned char access_type, struct pci_bus *bus,
++ unsigned int devfn, unsigned int where, u32 * data)
++{
++ unsigned int slot = PCI_SLOT(devfn);
++ u8 func = PCI_FUNC(devfn);
++ uint32_t address_reg, data_reg;
++ unsigned int address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++ address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++ MV_WRITE(address_reg, address);
++
++ switch(access_type) {
++ case PCI_ACCESS_WRITE_1:
++ MV_WRITE_8(data_reg+(where&0x3), *data);
++ break;
++ case PCI_ACCESS_WRITE_2:
++ MV_WRITE_16(data_reg+(where&0x3), *data);
++ break;
++ case PCI_ACCESS_WRITE_4:
++ MV_WRITE(data_reg, *data);
++ break;
++ case PCI_ACCESS_READ_1:
++ MV_READ_8( data_reg+(where&0x3), data);
++ break;
++ case PCI_ACCESS_READ_2:
++ MV_READ_16(data_reg+(where&0x3), data);
++ break;
++ case PCI_ACCESS_READ_4:
++ MV_READ(data_reg, data);
++ break;
++ default:
++ printk("no specify access type\n");
++ break;
++ }
++ return 0;
++}
++
++static int
++read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
++{
++ return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
++{
++ return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
++{
++ return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
++{
++ if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
++{
++ if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
++{
++ if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
++ return -1;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++
++static int
++pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
++{
++ switch (size) {
++ case 1:
++ return read_config_byte(bus, devfn, where, (u8 *) val);
++ case 2:
++ return read_config_word(bus, devfn, where, (u16 *) val);
++ default:
++ return read_config_dword(bus, devfn, where, val);
++ }
++}
++
++static int
++pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
++{
++ switch (size) {
++ case 1:
++ return write_config_byte(bus, devfn, where, (u8) val);
++ case 2:
++ return write_config_word(bus, devfn, where, (u16) val);
++ default:
++ return write_config_dword(bus, devfn, where, val);
++ }
++}
++
++struct pci_ops mt7621_pci_ops= {
++ .read = pci_config_read,
++ .write = pci_config_write,
++};
++
++static struct resource mt7621_res_pci_mem1 = {
++ .name = "PCI MEM1",
++ .start = RALINK_PCI_MM_MAP_BASE,
++ .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
++ .flags = IORESOURCE_MEM,
++};
++static struct resource mt7621_res_pci_io1 = {
++ .name = "PCI I/O1",
++ .start = RALINK_PCI_IO_MAP_BASE,
++ .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
++ .flags = IORESOURCE_IO,
++};
++
++static struct pci_controller mt7621_controller = {
++ .pci_ops = &mt7621_pci_ops,
++ .mem_resource = &mt7621_res_pci_mem1,
++ .io_resource = &mt7621_res_pci_io1,
++ .mem_offset = 0x00000000UL,
++ .io_offset = 0x00000000UL,
++ .io_map_base = 0xa0000000,
++};
++
++static void
++read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
++{
++ unsigned int address_reg, data_reg, address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++ address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++ MV_WRITE(address_reg, address);
++ MV_READ(data_reg, val);
++ return;
++}
++
++static void
++write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
++{
++ unsigned int address_reg, data_reg, address;
++
++ address_reg = RALINK_PCI_CONFIG_ADDR;
++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++ address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++ MV_WRITE(address_reg, address);
++ MV_WRITE(data_reg, val);
++ return;
++}
++
++
++int __init
++pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ u16 cmd;
++ u32 val;
++ int irq = 0;
++
++ if ((dev->bus->number == 0) && (slot == 0)) {
++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++ printk("BAR0 at slot 0 = %x\n", val);
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ } else if((dev->bus->number == 0) && (slot == 0x1)) {
++ write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++ printk("BAR0 at slot 1 = %x\n", val);
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ } else if((dev->bus->number == 0) && (slot == 0x2)) {
++ write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++ read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++ printk("BAR0 at slot 2 = %x\n", val);
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
++ switch (pcie_link_status) {
++ case 2:
++ case 6:
++ irq = RALINK_INT_PCIE1;
++ break;
++ case 4:
++ irq = RALINK_INT_PCIE2;
++ break;
++ default:
++ irq = RALINK_INT_PCIE0;
++ }
++ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++ } else if ((dev->bus->number == 2) && (slot == 0x0)) {
++ switch (pcie_link_status) {
++ case 5:
++ case 6:
++ irq = RALINK_INT_PCIE2;
++ break;
++ default:
++ irq = RALINK_INT_PCIE1;
++ }
++ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++ } else if ((dev->bus->number == 2) && (slot == 0x1)) {
++ switch (pcie_link_status) {
++ case 5:
++ case 6:
++ irq = RALINK_INT_PCIE2;
++ break;
++ default:
++ irq = RALINK_INT_PCIE1;
++ }
++ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++ } else if ((dev->bus->number ==3) && (slot == 0x0)) {
++ irq = RALINK_INT_PCIE2;
++ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++ } else if ((dev->bus->number ==3) && (slot == 0x1)) {
++ irq = RALINK_INT_PCIE2;
++ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++ } else if ((dev->bus->number ==3) && (slot == 0x2)) {
++ irq = RALINK_INT_PCIE2;
++ printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++ } else {
++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++ return 0;
++ }
++
++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
++ pci_read_config_word(dev, PCI_COMMAND, &cmd);
++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
++ pci_write_config_word(dev, PCI_COMMAND, cmd);
++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
++ return irq;
++}
++
++void
++set_pcie_phy(u32 *addr, int start_b, int bits, int val)
++{
++// printk("0x%p:", addr);
++// printk(" %x", *addr);
++ *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
++ *(unsigned int *)(addr) |= val << start_b;
++// printk(" -> %x\n", *addr);
++}
++
++void
++bypass_pipe_rst(void)
++{
++#if defined (CONFIG_PCIE_PORT0)
++ /* PCIe Port 0 */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++ /* PCIe Port 1 */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ /* PCIe Port 2 */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
++#endif
++}
++
++void
++set_phy_for_ssc(void)
++{
++ unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
++
++ reg = (reg >> 6) & 0x7;
++#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
++ /* Set PCIe Port0 & Port1 PHY to disable SSC */
++ /* Debug Xtal Type */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
++ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
++ printk("***** Xtal 40MHz *****\n");
++ } else { // 25MHz | 20MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
++ if (reg >= 6) {
++ printk("***** Xtal 25MHz *****\n");
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
++ } else {
++ printk("***** Xtal 20MHz *****\n");
++ }
++ }
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
++ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
++ }
++ /* Enable PHY and disable force mode */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ /* Set PCIe Port2 PHY to disable SSC */
++ /* Debug Xtal Type */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
++ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
++ } else { // 25MHz | 20MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
++ if (reg >= 6) { // 25MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
++ }
++ }
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
++ if(reg <= 5 && reg >= 3) { // 40MHz Xtal
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
++ }
++ /* Enable PHY and disable force mode */
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
++ set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
++#endif
++}
++
++static int mt7621_pci_probe(struct platform_device *pdev)
++{
++ unsigned long val = 0;
++
++ iomem_resource.start = 0;
++ iomem_resource.end= ~0;
++ ioport_resource.start= 0;
++ ioport_resource.end = ~0;
++
++#if defined (CONFIG_PCIE_PORT0)
++ val = RALINK_PCIE0_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++ val |= RALINK_PCIE1_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ val |= RALINK_PCIE2_RST;
++#endif
++ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
++ printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
++ *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
++ *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
++ mdelay(100);
++ *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
++ mdelay(100);
++ *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
++
++ mdelay(100);
++#else
++ *(unsigned int *)(0xbe000060) &= ~0x00000c00;
++#endif
++#if defined (CONFIG_PCIE_PORT0)
++ val = RALINK_PCIE0_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++ val |= RALINK_PCIE1_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ val |= RALINK_PCIE2_RST;
++#endif
++ DEASSERT_SYSRST_PCIE(val);
++ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++
++ if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
++ bypass_pipe_rst();
++ set_phy_for_ssc();
++ printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++
++#if defined (CONFIG_PCIE_PORT0)
++ read_config(0, 0, 0, 0x70c, &val);
++ printk("Port 0 N_FTS = %x\n", (unsigned int)val);
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++ read_config(0, 1, 0, 0x70c, &val);
++ printk("Port 1 N_FTS = %x\n", (unsigned int)val);
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ read_config(0, 2, 0, 0x70c, &val);
++ printk("Port 2 N_FTS = %x\n", (unsigned int)val);
++#endif
++
++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
++ RALINK_SYSCFG1 &= ~(0x30);
++ RALINK_SYSCFG1 |= (2<<4);
++ RALINK_PCIE_CLK_GEN &= 0x7fffffff;
++ RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
++ RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
++ RALINK_PCIE_CLK_GEN |= 0x80000000;
++ mdelay(50);
++ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
++
++
++#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
++ *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
++ mdelay(100);
++#else
++ RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
++#endif
++ mdelay(500);
++
++
++ mdelay(500);
++#if defined (CONFIG_PCIE_PORT0)
++ if(( RALINK_PCI0_STATUS & 0x1) == 0)
++ {
++ printk("PCIE0 no card, disable it(RST&CLK)\n");
++ ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
++ pcie_link_status &= ~(1<<0);
++ } else {
++ pcie_link_status |= 1<<0;
++ RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
++ }
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++ if(( RALINK_PCI1_STATUS & 0x1) == 0)
++ {
++ printk("PCIE1 no card, disable it(RST&CLK)\n");
++ ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
++ pcie_link_status &= ~(1<<1);
++ } else {
++ pcie_link_status |= 1<<1;
++ RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
++ }
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ if (( RALINK_PCI2_STATUS & 0x1) == 0) {
++ printk("PCIE2 no card, disable it(RST&CLK)\n");
++ ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
++ pcie_link_status &= ~(1<<2);
++ } else {
++ pcie_link_status |= 1<<2;
++ RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
++ }
++#endif
++ if (pcie_link_status == 0)
++ return 0;
++
++/*
++pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
++3'b000 x x x
++3'b001 x x 0
++3'b010 x 0 x
++3'b011 x 1 0
++3'b100 0 x x
++3'b101 1 x 0
++3'b110 1 0 x
++3'b111 2 1 0
++*/
++ switch(pcie_link_status) {
++ case 2:
++ RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
++ RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
++ RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
++ break;
++ case 4:
++ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
++ RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
++ RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
++ RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
++ break;
++ case 5:
++ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
++ RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
++ RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
++ RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
++ break;
++ case 6:
++ RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
++ RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
++ RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
++ RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
++ break;
++ }
++ printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
++ //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
++
++/*
++ ioport_resource.start = mt7621_res_pci_io1.start;
++ ioport_resource.end = mt7621_res_pci_io1.end;
++*/
++
++ RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
++ RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
++
++#if defined (CONFIG_PCIE_PORT0)
++ //PCIe0
++ if((pcie_link_status & 0x1) != 0) {
++ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
++ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI0_CLASS = 0x06040001;
++ printk("PCIE0 enabled\n");
++ }
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++ //PCIe1
++ if ((pcie_link_status & 0x2) != 0) {
++ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
++ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI1_CLASS = 0x06040001;
++ printk("PCIE1 enabled\n");
++ }
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++ //PCIe2
++ if ((pcie_link_status & 0x4) != 0) {
++ RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
++ RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
++ RALINK_PCI2_CLASS = 0x06040001;
++ printk("PCIE2 enabled\n");
++ }
++#endif
++
++
++ switch(pcie_link_status) {
++ case 7:
++ read_config(0, 2, 0, 0x4, &val);
++ write_config(0, 2, 0, 0x4, val|0x4);
++ // write_config(0, 1, 0, 0x4, val|0x7);
++ read_config(0, 2, 0, 0x70c, &val);
++ val &= ~(0xff)<<8;
++ val |= 0x50<<8;
++ write_config(0, 2, 0, 0x70c, val);
++ case 3:
++ case 5:
++ case 6:
++ read_config(0, 1, 0, 0x4, &val);
++ write_config(0, 1, 0, 0x4, val|0x4);
++ // write_config(0, 1, 0, 0x4, val|0x7);
++ read_config(0, 1, 0, 0x70c, &val);
++ val &= ~(0xff)<<8;
++ val |= 0x50<<8;
++ write_config(0, 1, 0, 0x70c, val);
++ default:
++ read_config(0, 0, 0, 0x4, &val);
++ write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
++ // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
++ read_config(0, 0, 0, 0x70c, &val);
++ val &= ~(0xff)<<8;
++ val |= 0x50<<8;
++ write_config(0, 0, 0, 0x70c, val);
++ }
++
++ pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
++ register_pci_controller(&mt7621_controller);
++ return 0;
++
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ return 0;
++}
++
++static const struct of_device_id mt7621_pci_ids[] = {
++ { .compatible = "mediatek,mt7621-pci" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
++
++static struct platform_driver mt7621_pci_driver = {
++ .probe = mt7621_pci_probe,
++ .driver = {
++ .name = "mt7621-pci",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(mt7621_pci_ids),
++ },
++};
++
++static int __init mt7621_pci_init(void)
++{
++ return platform_driver_register(&mt7621_pci_driver);
++}
++
++arch_initcall(mt7621_pci_init);
--- /dev/null
+From f8da5caf65926d44581d4e7914b28ceab3d28a7c Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:08:11 +0200
+Subject: [PATCH 17/57] MIPS: use set_mode() to enable/disable the cevt-r4k
+ irq
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/cevt-r4k.c | 37 +++++++++++++++++++++++++++++++------
+ 1 file changed, 31 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -29,12 +29,6 @@ static int mips_next_event(unsigned long
+ return res;
+ }
+
+-void mips_set_clock_mode(enum clock_event_mode mode,
+- struct clock_event_device *evt)
+-{
+- /* Nothing to do ... */
+-}
+-
+ DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+ int cp0_timer_irq_installed;
+
+@@ -75,9 +69,38 @@ struct irqaction c0_compare_irqaction =
+ .name = "timer",
+ };
+
++void mips_set_clock_mode(enum clock_event_mode mode,
++ struct clock_event_device *evt)
++{
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
++ switch (mode) {
++ case CLOCK_EVT_MODE_ONESHOT:
++ if (cp0_timer_irq_installed)
++ break;
++
++ cp0_timer_irq_installed = 1;
++
++ setup_irq(evt->irq, &c0_compare_irqaction);
++ break;
++
++ case CLOCK_EVT_MODE_SHUTDOWN:
++ if (!cp0_timer_irq_installed)
++ break;
++
++ cp0_timer_irq_installed = 0;
++ free_irq(evt->irq, &c0_compare_irqaction);
++ break;
++
++ default:
++ pr_err("Unhandeled mips clock_mode\n");
++ break;
++ }
++#endif
++}
+
+ void mips_event_handler(struct clock_event_device *dev)
+ {
++
+ }
+
+ /*
+@@ -198,12 +221,14 @@ int r4k_clockevent_init(void)
+
+ clockevents_register_device(cd);
+
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+ if (cp0_timer_irq_installed)
+ return 0;
+
+ cp0_timer_irq_installed = 1;
+
+ setup_irq(irq, &c0_compare_irqaction);
++#endif
+
+ return 0;
+ }
--- /dev/null
+From 9de00286e20a5f5edc419698373010f1cb6ff0ce Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:25:02 +0100
+Subject: [PATCH 19/57] MIPS: ralink: add pseudo pwm led trigger based on
+ timer0
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/timer.c | 213 ++++++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 197 insertions(+), 16 deletions(-)
+
+--- a/arch/mips/ralink/timer.c
++++ b/arch/mips/ralink/timer.c
+@@ -12,6 +12,8 @@
+ #include <linux/timer.h>
+ #include <linux/of_gpio.h>
+ #include <linux/clk.h>
++#include <linux/leds.h>
++#include <linux/slab.h>
+
+ #include <asm/mach-ralink/ralink_regs.h>
+
+@@ -23,16 +25,34 @@
+
+ #define TMR0CTL_ENABLE BIT(7)
+ #define TMR0CTL_MODE_PERIODIC BIT(4)
+-#define TMR0CTL_PRESCALER 1
++#define TMR0CTL_PRESCALER 2
+ #define TMR0CTL_PRESCALE_VAL (0xf - TMR0CTL_PRESCALER)
+ #define TMR0CTL_PRESCALE_DIV (65536 / BIT(TMR0CTL_PRESCALER))
+
++struct rt_timer_gpio {
++ struct list_head list;
++ struct led_classdev *led;
++};
++
+ struct rt_timer {
+- struct device *dev;
+- void __iomem *membase;
+- int irq;
+- unsigned long timer_freq;
+- unsigned long timer_div;
++ struct device *dev;
++ void __iomem *membase;
++ int irq;
++
++ unsigned long timer_freq;
++ unsigned long timer_div;
++
++ struct list_head gpios;
++ struct led_trigger led_trigger;
++ unsigned int duty_cycle;
++ unsigned int duty;
++
++ unsigned int fade;
++ unsigned int fade_min;
++ unsigned int fade_max;
++ unsigned int fade_speed;
++ unsigned int fade_dir;
++ unsigned int fade_count;
+ };
+
+ static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
+@@ -48,8 +68,37 @@ static inline u32 rt_timer_r32(struct rt
+ static irqreturn_t rt_timer_irq(int irq, void *_rt)
+ {
+ struct rt_timer *rt = (struct rt_timer *) _rt;
++ struct rt_timer_gpio *gpio;
++ unsigned int val;
+
+- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
++ if (rt->fade && (rt->fade_count++ > rt->fade_speed)) {
++ rt->fade_count = 0;
++ if (rt->duty_cycle <= rt->fade_min)
++ rt->fade_dir = 1;
++ else if (rt->duty_cycle >= rt->fade_max)
++ rt->fade_dir = 0;
++
++ if (rt->fade_dir)
++ rt->duty_cycle += 1;
++ else
++ rt->duty_cycle -= 1;
++
++ }
++
++ val = rt->timer_freq / rt->timer_div;
++ if (rt->duty)
++ val *= rt->duty_cycle;
++ else
++ val *= (100 - rt->duty_cycle);
++ val /= 100;
++
++ if (!list_empty(&rt->gpios))
++ list_for_each_entry(gpio, &rt->gpios, list)
++ led_set_brightness(gpio->led, !!rt->duty);
++
++ rt->duty = !rt->duty;
++
++ rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1);
+ rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
+
+ return IRQ_HANDLED;
+@@ -58,8 +107,8 @@ static irqreturn_t rt_timer_irq(int irq,
+
+ static int rt_timer_request(struct rt_timer *rt)
+ {
+- int err = request_irq(rt->irq, rt_timer_irq, 0,
+- dev_name(rt->dev), rt);
++ int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq,
++ 0, dev_name(rt->dev), rt);
+ if (err) {
+ dev_err(rt->dev, "failed to request irq\n");
+ } else {
+@@ -81,8 +130,6 @@ static int rt_timer_config(struct rt_tim
+ else
+ rt->timer_div = divisor;
+
+- rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
+-
+ return 0;
+ }
+
+@@ -108,11 +155,128 @@ static void rt_timer_disable(struct rt_t
+ rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
+ }
+
++static ssize_t led_fade_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct led_classdev *led_cdev = dev_get_drvdata(dev);
++ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++
++ return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max);
++}
++
++static ssize_t led_fade_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t size)
++{
++ struct led_classdev *led_cdev = dev_get_drvdata(dev);
++ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++ unsigned int speed = 0, min = 0, max = 0;
++ ssize_t ret = -EINVAL;
++
++ ret = sscanf(buf, "%u %u %u", &speed, &min, &max);
++
++ if (ret == 3) {
++ rt->fade_speed = speed;
++ rt->fade_min = min;
++ rt->fade_max = max;
++ rt->fade = 1;
++ } else {
++ rt->fade = 0;
++ }
++
++ return size;
++}
++
++static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store);
++
++static ssize_t led_duty_cycle_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct led_classdev *led_cdev = dev_get_drvdata(dev);
++ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++
++ return sprintf(buf, "%u\n", rt->duty_cycle);
++}
++
++static ssize_t led_duty_cycle_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t size)
++{
++ struct led_classdev *led_cdev = dev_get_drvdata(dev);
++ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++ unsigned long state;
++ ssize_t ret = -EINVAL;
++
++ ret = kstrtoul(buf, 10, &state);
++ if (ret)
++ return ret;
++
++ if (state <= 100)
++ rt->duty_cycle = state;
++ else
++ rt->duty_cycle = 100;
++
++ rt->fade = 0;
++
++ return size;
++}
++
++static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store);
++
++static void rt_timer_trig_activate(struct led_classdev *led_cdev)
++{
++ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++ struct rt_timer_gpio *gpio_data;
++ int rc;
++
++ led_cdev->trigger_data = NULL;
++ gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL);
++ if (!gpio_data)
++ return;
++
++ rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle);
++ if (rc)
++ goto err_gpio;
++ rc = device_create_file(led_cdev->dev, &dev_attr_fade);
++ if (rc)
++ goto err_out_duty_cycle;
++
++ led_cdev->activated = true;
++ led_cdev->trigger_data = gpio_data;
++ gpio_data->led = led_cdev;
++ list_add(&gpio_data->list, &rt->gpios);
++ led_cdev->trigger_data = gpio_data;
++ rt_timer_enable(rt);
++ return;
++
++err_out_duty_cycle:
++ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
++
++err_gpio:
++ kfree(gpio_data);
++}
++
++static void rt_timer_trig_deactivate(struct led_classdev *led_cdev)
++{
++ struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++ struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data;
++
++ if (led_cdev->activated) {
++ device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
++ device_remove_file(led_cdev->dev, &dev_attr_fade);
++ led_cdev->activated = false;
++ }
++
++ list_del(&gpio_data->list);
++ rt_timer_disable(rt);
++ led_set_brightness(led_cdev, LED_OFF);
++}
++
+ static int rt_timer_probe(struct platform_device *pdev)
+ {
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ const __be32 *divisor;
+ struct rt_timer *rt;
+ struct clk *clk;
++ int ret;
+
+ rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
+ if (!rt) {
+@@ -140,12 +304,29 @@ static int rt_timer_probe(struct platfor
+ if (!rt->timer_freq)
+ return -EINVAL;
+
++ rt->duty_cycle = 100;
+ rt->dev = &pdev->dev;
+ platform_set_drvdata(pdev, rt);
+
+- rt_timer_request(rt);
+- rt_timer_config(rt, 2);
+- rt_timer_enable(rt);
++ ret = rt_timer_request(rt);
++ if (ret)
++ return ret;
++
++ divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL);
++ if (divisor)
++ rt_timer_config(rt, be32_to_cpu(*divisor));
++ else
++ rt_timer_config(rt, 200);
++
++ rt->led_trigger.name = "pwmtimer",
++ rt->led_trigger.activate = rt_timer_trig_activate,
++ rt->led_trigger.deactivate = rt_timer_trig_deactivate,
++
++ ret = led_trigger_register(&rt->led_trigger);
++ if (ret)
++ return ret;
++
++ INIT_LIST_HEAD(&rt->gpios);
+
+ dev_info(&pdev->dev, "maximum frequency is %luHz\n", rt->timer_freq);
+
+@@ -156,6 +337,7 @@ static int rt_timer_remove(struct platfo
+ {
+ struct rt_timer *rt = platform_get_drvdata(pdev);
+
++ led_trigger_unregister(&rt->led_trigger);
+ rt_timer_disable(rt);
+ rt_timer_free(rt);
+
+@@ -180,6 +362,6 @@ static struct platform_driver rt_timer_d
+
+ module_platform_driver(rt_timer_driver);
+
+-MODULE_DESCRIPTION("Ralink RT2880 timer");
++MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm");
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
+ MODULE_LICENSE("GPL");
--- /dev/null
+From e76ecd496c9b074ab21b17f12494d823a407e89a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 16:26:41 +0200
+Subject: [PATCH 21/57] MIPS: ralink: add cpu frequency scaling
+
+This feature will break udelay() and cause the delay loop to have longer delays
+when the frequency is scaled causing a performance hit.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/cevt-rt3352.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/arch/mips/ralink/cevt-rt3352.c
++++ b/arch/mips/ralink/cevt-rt3352.c
+@@ -29,6 +29,10 @@
+ /* enable the counter */
+ #define CFG_CNT_EN 0x1
+
++/* mt7620 frequency scaling defines */
++#define CLK_LUT_CFG 0x40
++#define SLEEP_EN BIT(31)
++
+ struct systick_device {
+ void __iomem *membase;
+ struct clock_event_device dev;
+@@ -36,6 +40,8 @@ struct systick_device {
+ int freq_scale;
+ };
+
++static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
++
+ static void systick_set_clock_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt);
+
+@@ -87,6 +93,21 @@ static struct irqaction systick_irqactio
+ .dev_id = &systick.dev,
+ };
+
++static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
++{
++ if (sdev->freq_scale == status)
++ return;
++
++ sdev->freq_scale = status;
++
++ pr_info("%s: %s autosleep mode\n", systick.dev.name,
++ (status) ? ("enable") : ("disable"));
++ if (status)
++ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
++ else
++ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
++}
++
+ static void systick_set_clock_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+ {
+@@ -101,9 +122,13 @@ static void systick_set_clock_mode(enum
+ sdev->irq_requested = 1;
+ iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
+ systick.membase + SYSTICK_CONFIG);
++ if (systick_freq_scaling)
++ systick_freq_scaling(sdev, 1);
+ break;
+
+ case CLOCK_EVT_MODE_SHUTDOWN:
++ if (systick_freq_scaling)
++ systick_freq_scaling(sdev, 0);
+ if (sdev->irq_requested)
+ free_irq(systick.dev.irq, &systick_irqaction);
+ sdev->irq_requested = 0;
+@@ -116,12 +141,23 @@ static void systick_set_clock_mode(enum
+ }
+ }
+
++static const struct of_device_id systick_match[] = {
++ { .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
++ {},
++};
++
+ static void __init ralink_systick_init(struct device_node *np)
+ {
++ const struct of_device_id *match;
++
+ systick.membase = of_iomap(np, 0);
+ if (!systick.membase)
+ return;
+
++ match = of_match_node(systick_match, np);
++ if (match)
++ systick_freq_scaling = match->data;
++
+ systick_irqaction.name = np->name;
+ systick.dev.name = np->name;
+ clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
--- /dev/null
+From ec26251ea980b1ee88733f178a4e86e3c70fd244 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Aug 2014 18:46:02 +0200
+Subject: [PATCH 22/57] MIPS: ralink: copy the commandline from the devicetree
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -74,6 +74,8 @@ void __init plat_mem_setup(void)
+ */
+ __dt_setup_arch(__dtb_start);
+
++ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
++
+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
+ if (memory_dtb)
+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
--- /dev/null
+From 1f1c12e85defba9459b41ec95b86f23b4791f1ab Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Aug 2014 20:43:25 +0200
+Subject: [PATCH 23/57] MIPS: ralink: mt7620: fix usb issue during frequency
+ scaling
+
+ If the USB HCD is running and the cpu is scaled too low, then the USB stops
+ working. Increase the idle speed of the core to fix this if the kernel is
+ built with USB support.
+
+ The values are taken from the Ralink SDK Kernel.
+
+ Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -36,6 +36,12 @@
+ #define PMU1_CFG 0x8C
+ #define DIG_SW_SEL BIT(25)
+
++/* clock scaling */
++#define CLKCFG_FDIV_MASK 0x1f00
++#define CLKCFG_FDIV_USB_VAL 0x0300
++#define CLKCFG_FFRAC_MASK 0x001f
++#define CLKCFG_FFRAC_USB_VAL 0x0003
++
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+@@ -337,6 +343,19 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("10000b00.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", periph_rate);
+ ralink_clk_add("10180000.wmac", xtal_rate);
++
++ if (IS_ENABLED(CONFIG_USB)) {
++ /*
++ * When the CPU goes into sleep mode, the BUS clock will be too low for
++ * USB to function properly
++ */
++ u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
++
++ val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
++ val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
++
++ rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
++ }
+ }
+
+ void __init ralink_of_remap(void)
--- /dev/null
+From b1cc9a15f6ead8dbd849257e42d69a5799fb7597 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 6 Aug 2014 18:24:36 +0200
+Subject: [PATCH 25/57] MIPS: ralink: allow loading irq registers from the
+ devicetree
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/irq.c | 33 +++++++++++++++++++++++----------
+ 1 file changed, 23 insertions(+), 10 deletions(-)
+
+--- a/arch/mips/ralink/irq.c
++++ b/arch/mips/ralink/irq.c
+@@ -20,14 +20,6 @@
+
+ #include "common.h"
+
+-/* INTC register offsets */
+-#define INTC_REG_STATUS0 0x00
+-#define INTC_REG_STATUS1 0x04
+-#define INTC_REG_TYPE 0x20
+-#define INTC_REG_RAW_STATUS 0x30
+-#define INTC_REG_ENABLE 0x34
+-#define INTC_REG_DISABLE 0x38
+-
+ #define INTC_INT_GLOBAL BIT(31)
+
+ #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
+@@ -44,16 +36,34 @@
+
+ #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
+
++enum rt_intc_regs_enum {
++ INTC_REG_STATUS0 = 0,
++ INTC_REG_STATUS1,
++ INTC_REG_TYPE,
++ INTC_REG_RAW_STATUS,
++ INTC_REG_ENABLE,
++ INTC_REG_DISABLE,
++};
++
++static u32 rt_intc_regs[] = {
++ [INTC_REG_STATUS0] = 0x00,
++ [INTC_REG_STATUS1] = 0x04,
++ [INTC_REG_TYPE] = 0x20,
++ [INTC_REG_RAW_STATUS] = 0x30,
++ [INTC_REG_ENABLE] = 0x34,
++ [INTC_REG_DISABLE] = 0x38,
++};
++
+ static void __iomem *rt_intc_membase;
+
+ static inline void rt_intc_w32(u32 val, unsigned reg)
+ {
+- __raw_writel(val, rt_intc_membase + reg);
++ __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
+ }
+
+ static inline u32 rt_intc_r32(unsigned reg)
+ {
+- return __raw_readl(rt_intc_membase + reg);
++ return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
+ }
+
+ static void ralink_intc_irq_unmask(struct irq_data *d)
+@@ -134,6 +144,9 @@ static int __init intc_of_init(struct de
+ struct irq_domain *domain;
+ int irq;
+
++ if (!of_property_read_u32_array(node, "ralink,intc-registers", rt_intc_regs, 6))
++ pr_info("intc: using register map from devicetree\n");
++
+ irq = irq_of_parse_and_map(node, 0);
+ if (!irq)
+ panic("Failed to get INTC IRQ");
--- /dev/null
+From a375beba066516ecafddebc765454ac6ec599f3d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 6 Aug 2014 18:26:08 +0200
+Subject: [PATCH 26/57] MIPS: ralink: add mt7628an support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 11 ++
+ arch/mips/ralink/Kconfig | 2 +-
+ arch/mips/ralink/mt7620.c | 266 +++++++++++++++++++++++-----
+ 3 files changed, 232 insertions(+), 47 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -13,6 +13,13 @@
+ #ifndef _MT7620_REGS_H_
+ #define _MT7620_REGS_H_
+
++enum mt762x_soc_type {
++ MT762X_SOC_UNKNOWN = 0,
++ MT762X_SOC_MT7620A,
++ MT762X_SOC_MT7620N,
++ MT762X_SOC_MT7628AN,
++};
++
+ #define MT7620_SYSC_BASE 0x10000000
+
+ #define SYSC_REG_CHIP_NAME0 0x00
+@@ -27,6 +34,7 @@
+
+ #define MT7620_CHIP_NAME0 0x3637544d
+ #define MT7620_CHIP_NAME1 0x20203032
++#define MT7628_CHIP_NAME1 0x20203832
+
+ #define SYSCFG0_XTAL_FREQ_SEL BIT(6)
+
+@@ -71,6 +79,9 @@
+ #define SYSCFG0_DRAM_TYPE_DDR1 1
+ #define SYSCFG0_DRAM_TYPE_DDR2 2
+
++#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
++#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
++
+ #define MT7620_DRAM_BASE 0x0
+ #define MT7620_SDRAM_SIZE_MIN 2
+ #define MT7620_SDRAM_SIZE_MAX 64
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -31,7 +31,7 @@ choice
+ select HW_HAS_PCI
+
+ config SOC_MT7620
+- bool "MT7620"
++ bool "MT7620/8"
+
+ config SOC_MT7621
+ bool "MT7621"
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -42,6 +42,8 @@
+ #define CLKCFG_FFRAC_MASK 0x001f
+ #define CLKCFG_FFRAC_USB_VAL 0x0003
+
++enum mt762x_soc_type mt762x_soc;
++
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+@@ -159,6 +161,125 @@ struct ralink_pinmux rt_gpio_pinmux = {
+ .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
+ };
+
++static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
++ FUNC("sdcx", 3, 19, 1),
++ FUNC("utif", 2, 19, 1),
++ FUNC("gpio", 1, 19, 1),
++ FUNC("pwm", 0, 19, 1),
++};
++
++static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
++ FUNC("sdcx", 3, 18, 1),
++ FUNC("utif", 2, 18, 1),
++ FUNC("gpio", 1, 18, 1),
++ FUNC("pwm", 0, 18, 1),
++};
++
++static struct rt2880_pmx_func uart2_grp_mt7628[] = {
++ FUNC("sdcx", 3, 20, 2),
++ FUNC("pwm", 2, 20, 2),
++ FUNC("gpio", 1, 20, 2),
++ FUNC("uart", 0, 20, 2),
++};
++
++static struct rt2880_pmx_func uart1_grp_mt7628[] = {
++ FUNC("sdcx", 3, 45, 2),
++ FUNC("pwm", 2, 45, 2),
++ FUNC("gpio", 1, 45, 2),
++ FUNC("uart", 0, 45, 2),
++};
++
++static struct rt2880_pmx_func i2c_grp_mt7628[] = {
++ FUNC("-", 3, 4, 2),
++ FUNC("debug", 2, 4, 2),
++ FUNC("gpio", 1, 4, 2),
++ FUNC("i2c", 0, 4, 2),
++};
++
++static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
++static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
++static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
++static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
++
++static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
++ FUNC("jtag", 3, 22, 8),
++ FUNC("utif", 2, 22, 8),
++ FUNC("gpio", 1, 22, 8),
++ FUNC("sdcx", 0, 22, 8),
++};
++
++static struct rt2880_pmx_func uart0_grp_mt7628[] = {
++ FUNC("-", 3, 12, 2),
++ FUNC("-", 2, 12, 2),
++ FUNC("gpio", 1, 12, 2),
++ FUNC("uart", 0, 12, 2),
++};
++
++static struct rt2880_pmx_func i2s_grp_mt7628[] = {
++ FUNC("antenna", 3, 0, 4),
++ FUNC("pcm", 2, 0, 4),
++ FUNC("gpio", 1, 0, 4),
++ FUNC("i2s", 0, 0, 4),
++};
++
++static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
++ FUNC("-", 3, 6, 1),
++ FUNC("refclk", 2, 6, 1),
++ FUNC("gpio", 1, 6, 1),
++ FUNC("spi", 0, 6, 1),
++};
++
++static struct rt2880_pmx_func spis_grp_mt7628[] = {
++ FUNC("pwm", 3, 14, 4),
++ FUNC("util", 2, 14, 4),
++ FUNC("gpio", 1, 14, 4),
++ FUNC("spis", 0, 14, 4),
++};
++
++static struct rt2880_pmx_func gpio_grp_mt7628[] = {
++ FUNC("pcie", 3, 11, 1),
++ FUNC("refclk", 2, 11, 1),
++ FUNC("gpio", 1, 11, 1),
++ FUNC("gpio", 0, 11, 1),
++};
++
++#define MT7628_GPIO_MODE_MASK 0x3
++
++#define MT7628_GPIO_MODE_PWM1 30
++#define MT7628_GPIO_MODE_PWM0 28
++#define MT7628_GPIO_MODE_UART2 26
++#define MT7628_GPIO_MODE_UART1 24
++#define MT7628_GPIO_MODE_I2C 20
++#define MT7628_GPIO_MODE_REFCLK 18
++#define MT7628_GPIO_MODE_PERST 16
++#define MT7628_GPIO_MODE_WDT 14
++#define MT7628_GPIO_MODE_SPI 12
++#define MT7628_GPIO_MODE_SDMODE 10
++#define MT7628_GPIO_MODE_UART0 8
++#define MT7628_GPIO_MODE_I2S 6
++#define MT7628_GPIO_MODE_CS1 4
++#define MT7628_GPIO_MODE_SPIS 2
++#define MT7628_GPIO_MODE_GPIO 0
++
++static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
++ GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM1),
++ GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_PWM0),
++ GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART2),
++ GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART1),
++ GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2C),
++ GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
++ GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
++ GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
++ GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
++ GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SDMODE),
++ GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_UART0),
++ GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_I2S),
++ GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_CS1),
++ GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_SPIS),
++ GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, 1, MT7628_GPIO_MODE_GPIO),
++ { 0 }
++};
++
+ static __init u32
+ mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
+ {
+@@ -309,29 +430,42 @@ void __init ralink_clk_init(void)
+
+ xtal_rate = mt7620_get_xtal_rate();
+
+- cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
+- pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
+-
+- cpu_rate = mt7620_get_cpu_rate(pll_rate);
+- dram_rate = mt7620_get_dram_rate(pll_rate);
+- sys_rate = mt7620_get_sys_rate(cpu_rate);
+- periph_rate = mt7620_get_periph_rate(xtal_rate);
+-
+ #define RFMT(label) label ":%lu.%03luMHz "
+ #define RINT(x) ((x) / 1000000)
+ #define RFRAC(x) (((x) / 1000) % 1000)
+
+- pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
+- RINT(xtal_rate), RFRAC(xtal_rate),
+- RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
+- RINT(pll_rate), RFRAC(pll_rate));
++ if (mt762x_soc == MT762X_SOC_MT7628AN) {
++ if (xtal_rate == MHZ(40))
++ cpu_rate = MHZ(580);
++ else
++ cpu_rate = MHZ(575);
++ dram_rate = sys_rate = cpu_rate / 3;
++ periph_rate = MHZ(40);
++
++ ralink_clk_add("10000d00.uartlite", periph_rate);
++ ralink_clk_add("10000e00.uartlite", periph_rate);
++ } else {
++ cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
++ pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
++
++ cpu_rate = mt7620_get_cpu_rate(pll_rate);
++ dram_rate = mt7620_get_dram_rate(pll_rate);
++ sys_rate = mt7620_get_sys_rate(cpu_rate);
++ periph_rate = mt7620_get_periph_rate(xtal_rate);
++
++ pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
++ RINT(xtal_rate), RFRAC(xtal_rate),
++ RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
++ RINT(pll_rate), RFRAC(pll_rate));
++
++ ralink_clk_add("10000500.uart", periph_rate);
++ }
+
+ pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
+ RINT(cpu_rate), RFRAC(cpu_rate),
+ RINT(dram_rate), RFRAC(dram_rate),
+ RINT(sys_rate), RFRAC(sys_rate),
+ RINT(periph_rate), RFRAC(periph_rate));
+-
+ #undef RFRAC
+ #undef RINT
+ #undef RFMT
+@@ -339,12 +473,11 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("cpu", cpu_rate);
+ ralink_clk_add("10000100.timer", periph_rate);
+ ralink_clk_add("10000120.watchdog", periph_rate);
+- ralink_clk_add("10000500.uart", periph_rate);
+ ralink_clk_add("10000b00.spi", sys_rate);
+ ralink_clk_add("10000c00.uartlite", periph_rate);
+ ralink_clk_add("10180000.wmac", xtal_rate);
+
+- if (IS_ENABLED(CONFIG_USB)) {
++ if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
+ /*
+ * When the CPU goes into sleep mode, the BUS clock will be too low for
+ * USB to function properly
+@@ -367,6 +500,52 @@ void __init ralink_of_remap(void)
+ panic("Failed to remap core resources");
+ }
+
++static __init void
++mt7620_dram_init(struct ralink_soc_info *soc_info)
++{
++ switch (dram_type) {
++ case SYSCFG0_DRAM_TYPE_SDRAM:
++ pr_info("Board has SDRAM\n");
++ soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
++ soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
++ break;
++
++ case SYSCFG0_DRAM_TYPE_DDR1:
++ pr_info("Board has DDR1\n");
++ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
++ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
++ break;
++
++ case SYSCFG0_DRAM_TYPE_DDR2:
++ pr_info("Board has DDR2\n");
++ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
++ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
++ break;
++ default:
++ BUG();
++ }
++}
++
++static __init void
++mt7628_dram_init(struct ralink_soc_info *soc_info)
++{
++ switch (dram_type) {
++ case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
++ pr_info("Board has DDR1\n");
++ soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
++ soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
++ break;
++
++ case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
++ pr_info("Board has DDR2\n");
++ soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
++ soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
++ break;
++ default:
++ BUG();
++ }
++}
++
+ void prom_soc_init(struct ralink_soc_info *soc_info)
+ {
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
+@@ -384,18 +563,25 @@ void prom_soc_init(struct ralink_soc_inf
+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
+ bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
+
+- if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
+- panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
+-
+- if (bga) {
+- name = "MT7620A";
+- soc_info->compatible = "ralink,mt7620a-soc";
+- } else {
+- name = "MT7620N";
+- soc_info->compatible = "ralink,mt7620n-soc";
++ if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
++ if (bga) {
++ mt762x_soc = MT762X_SOC_MT7620A;
++ name = "MT7620A";
++ soc_info->compatible = "ralink,mt7620a-soc";
++ } else {
++ mt762x_soc = MT762X_SOC_MT7620N;
++ name = "MT7620N";
++ soc_info->compatible = "ralink,mt7620n-soc";
+ #ifdef CONFIG_PCI
+- panic("mt7620n is only supported for non pci kernels");
++ panic("mt7620n is only supported for non pci kernels");
+ #endif
++ }
++ } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
++ mt762x_soc = MT762X_SOC_MT7628AN;
++ name = "MT7628AN";
++ soc_info->compatible = "ralink,mt7628an-soc";
++ } else {
++ panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
+ }
+
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
+@@ -407,28 +593,11 @@ void prom_soc_init(struct ralink_soc_inf
+ cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
+ dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
+
+- switch (dram_type) {
+- case SYSCFG0_DRAM_TYPE_SDRAM:
+- pr_info("Board has SDRAM\n");
+- soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+- soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+- break;
+-
+- case SYSCFG0_DRAM_TYPE_DDR1:
+- pr_info("Board has DDR1\n");
+- soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+- soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+- break;
+-
+- case SYSCFG0_DRAM_TYPE_DDR2:
+- pr_info("Board has DDR2\n");
+- soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+- soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+- break;
+- default:
+- BUG();
+- }
+ soc_info->mem_base = MT7620_DRAM_BASE;
++ if (mt762x_soc == MT762X_SOC_MT7628AN)
++ mt7628_dram_init(soc_info);
++ else
++ mt7620_dram_init(soc_info);
+
+ pmu0 = __raw_readl(sysc + PMU0_CFG);
+ pmu1 = __raw_readl(sysc + PMU1_CFG);
+@@ -437,4 +606,9 @@ void prom_soc_init(struct ralink_soc_inf
+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
+ pr_info("Digital PMU set to %s control\n",
+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
++
++ if (mt762x_soc == MT762X_SOC_MT7628AN)
++ rt2880_pinmux_data = mt7628an_pinmux_data;
++ else
++ rt2880_pinmux_data = mt7620a_pinmux_data;
+ }
--- /dev/null
+From 0b24e0e6bf2d9a1ca5f95446bc025dafc226998c Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 15 Mar 2013 18:16:01 +0100
+Subject: [PATCH 27/57] serial: ralink: adds mt7620 serial
+
+Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/8250/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/8250/Kconfig
++++ b/drivers/tty/serial/8250/Kconfig
+@@ -297,7 +297,7 @@ config SERIAL_8250_EM
+
+ config SERIAL_8250_RT288X
+ bool "Ralink RT288x/RT305x/RT3662/RT3883 serial port support"
+- depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883)
++ depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
+ help
+ If you have a Ralink RT288x/RT305x SoC based board and want to use the
+ serial port, say Y to this option. The driver can handle up to 2 serial
--- /dev/null
+From b9ba09038dab4d824176ea2c2f2b73f49b567217 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:52:01 +0000
+Subject: [PATCH 28/57] serial: ralink: the core has a size of 0x100 and not
+ 0x1000
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/8250/8250_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/8250/8250_core.c
++++ b/drivers/tty/serial/8250/8250_core.c
+@@ -2635,7 +2635,7 @@ serial8250_pm(struct uart_port *port, un
+ static unsigned int serial8250_port_size(struct uart_8250_port *pt)
+ {
+ if (pt->port.iotype == UPIO_AU)
+- return 0x1000;
++ return 0x100;
+ if (is_omap1_8250(pt))
+ return 0x16 << pt->port.regshift;
+
--- /dev/null
+From 49b47dfcef1353cd28eac8f64170e75d28ce4311 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:18:57 +0200
+Subject: [PATCH 29/57] serial: of: allow au1x00 and rt288x to load from OF
+
+In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
+to default the iotype to UPIO_AU.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/of_serial.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/of_serial.c
++++ b/drivers/tty/serial/of_serial.c
+@@ -102,7 +102,10 @@ static int of_platform_serial_setup(stru
+ port->fifosize = prop;
+
+ port->irq = irq_of_parse_and_map(np, 0);
+- port->iotype = UPIO_MEM;
++ if (of_device_is_compatible(np, "ralink,rt2880-uart"))
++ port->iotype = UPIO_AU;
++ else
++ port->iotype = UPIO_MEM;
+ if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
+ switch (prop) {
+ case 1:
--- /dev/null
+From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 12 Aug 2014 20:49:27 +0200
+Subject: [PATCH 30/36] GPIO: add named gpio exports
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++
+ drivers/gpio/gpiolib.c | 11 +++++--
+ include/asm-generic/gpio.h | 5 +++
+ include/linux/gpio/consumer.h | 8 +++++
+ 4 files changed, 90 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -22,6 +22,8 @@
+ #include <linux/of_gpio.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
+
+ #include "gpiolib.h"
+
+@@ -315,3 +317,69 @@ void of_gpiochip_remove(struct gpio_chip
+ gpiochip_remove_pin_ranges(chip);
+ of_node_put(chip->of_node);
+ }
++
++static struct of_device_id gpio_export_ids[] = {
++ { .compatible = "gpio-export" },
++ { /* sentinel */ }
++};
++
++static int __init of_gpio_export_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *cnp;
++ u32 val;
++ int nb = 0;
++
++ for_each_child_of_node(np, cnp) {
++ const char *name = NULL;
++ int gpio;
++ bool dmc;
++ int max_gpio = 1;
++ int i;
++
++ of_property_read_string(cnp, "gpio-export,name", &name);
++
++ if (!name)
++ max_gpio = of_gpio_count(cnp);
++
++ for (i = 0; i < max_gpio; i++) {
++ unsigned flags = 0;
++ enum of_gpio_flags of_flags;
++
++ gpio = of_get_gpio_flags(cnp, i, &of_flags);
++
++ if (of_flags == OF_GPIO_ACTIVE_LOW)
++ flags |= GPIOF_ACTIVE_LOW;
++
++ if (!of_property_read_u32(cnp, "gpio-export,output", &val))
++ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++ else
++ flags |= GPIOF_IN;
++
++ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
++ continue;
++
++ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
++ gpio_export_with_name(gpio, dmc, name);
++ nb++;
++ }
++ }
++
++ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
++
++ return 0;
++}
++
++static struct platform_driver gpio_export_driver = {
++ .driver = {
++ .name = "gpio-export",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(gpio_export_ids),
++ },
++};
++
++static int __init of_gpio_export_init(void)
++{
++ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
++}
++device_initcall(of_gpio_export_init);
+--- a/include/asm-generic/gpio.h
++++ b/include/asm-generic/gpio.h
+@@ -123,6 +123,12 @@ static inline int gpio_export(unsigned g
+ return gpiod_export(gpio_to_desc(gpio), direction_may_change);
+ }
+
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
++static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
++{
++ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
++}
++
+ static inline int gpio_export_link(struct device *dev, const char *name,
+ unsigned gpio)
+ {
+--- a/include/linux/gpio/consumer.h
++++ b/include/linux/gpio/consumer.h
+@@ -323,6 +323,7 @@ static inline int desc_to_gpio(const str
+
+ #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
+
++int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+ int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
+ int gpiod_export_link(struct device *dev, const char *name,
+ struct gpio_desc *desc);
+@@ -331,6 +332,13 @@ void gpiod_unexport(struct gpio_desc *de
+
+ #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
+
++static inline int _gpiod_export(struct gpio_desc *desc,
++ bool direction_may_change,
++ const char *name)
++{
++ return -ENOSYS;
++}
++
+ static inline int gpiod_export(struct gpio_desc *desc,
+ bool direction_may_change)
+ {
+--- a/drivers/gpio/gpiolib-sysfs.c
++++ b/drivers/gpio/gpiolib-sysfs.c
+@@ -517,7 +517,7 @@ static struct class gpio_class = {
+ *
+ * Returns zero on success, else an error.
+ */
+-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
+ {
+ unsigned long flags;
+ int status;
+@@ -557,6 +557,8 @@ int gpiod_export(struct gpio_desc *desc,
+ offset = gpio_chip_hwgpio(desc);
+ if (desc->chip->names && desc->chip->names[offset])
+ ioname = desc->chip->names[offset];
++ if (name)
++ ioname = name;
+
+ dev = device_create_with_groups(&gpio_class, desc->chip->dev,
+ MKDEV(0, 0), desc, gpio_groups,
+@@ -593,6 +595,12 @@ fail_unlock:
+ gpiod_dbg(desc, "%s: status %d\n", __func__, status);
+ return status;
+ }
++EXPORT_SYMBOL_GPL(__gpiod_export);
++
++int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++{
++ return __gpiod_export(desc, direction_may_change, NULL);
++}
+ EXPORT_SYMBOL_GPL(gpiod_export);
+
+ static int match_export(struct device *dev, const void *data)
--- /dev/null
+From 675c6ddd9432c39f508f9d6bdda17d9c675788cf Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:34:05 +0100
+Subject: [PATCH 30/57] pinctrl: ralink: add pinctrl driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/Kconfig | 2 +
+ arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
+ arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
+ arch/mips/include/asm/mach-ralink/rt305x.h | 35 ++-
+ arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
+ arch/mips/ralink/common.h | 19 --
+ arch/mips/ralink/mt7620.c | 159 +++-------
+ arch/mips/ralink/rt288x.c | 62 ++--
+ arch/mips/ralink/rt305x.c | 151 ++++-----
+ arch/mips/ralink/rt3883.c | 173 +++--------
+ drivers/pinctrl/Kconfig | 5 +
+ drivers/pinctrl/Makefile | 1 +
+ drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
+ 13 files changed, 764 insertions(+), 420 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
+ create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -453,6 +453,8 @@ config RALINK
+ select CLKDEV_LOOKUP
+ select ARCH_HAS_RESET_CONTROLLER
+ select RESET_CONTROLLER
++ select PINCTRL
++ select PINCTRL_RT2880
+
+ config SGI_IP22
+ bool "SGI IP22 (Indy/Indigo2)"
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -90,7 +90,6 @@ enum mt762x_soc_type {
+ #define MT7620_DDR2_SIZE_MIN 32
+ #define MT7620_DDR2_SIZE_MAX 256
+
+-#define MT7620_GPIO_MODE_I2C BIT(0)
+ #define MT7620_GPIO_MODE_UART0_SHIFT 2
+ #define MT7620_GPIO_MODE_UART0_MASK 0x7
+ #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
+@@ -102,16 +101,36 @@ enum mt762x_soc_type {
+ #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
+ #define MT7620_GPIO_MODE_GPIO_I2S 0x6
+ #define MT7620_GPIO_MODE_GPIO 0x7
+-#define MT7620_GPIO_MODE_UART1 BIT(5)
+-#define MT7620_GPIO_MODE_MDIO BIT(8)
+-#define MT7620_GPIO_MODE_RGMII1 BIT(9)
+-#define MT7620_GPIO_MODE_RGMII2 BIT(10)
+-#define MT7620_GPIO_MODE_SPI BIT(11)
+-#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
+-#define MT7620_GPIO_MODE_WLED BIT(13)
+-#define MT7620_GPIO_MODE_JTAG BIT(15)
+-#define MT7620_GPIO_MODE_EPHY BIT(15)
+-#define MT7620_GPIO_MODE_WDT BIT(22)
++
++#define MT7620_GPIO_MODE_NAND 0
++#define MT7620_GPIO_MODE_SD 1
++#define MT7620_GPIO_MODE_ND_SD_GPIO 2
++#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
++#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
++
++#define MT7620_GPIO_MODE_PCIE_RST 0
++#define MT7620_GPIO_MODE_PCIE_REF 1
++#define MT7620_GPIO_MODE_PCIE_GPIO 2
++#define MT7620_GPIO_MODE_PCIE_MASK 0x3
++#define MT7620_GPIO_MODE_PCIE_SHIFT 16
++
++#define MT7620_GPIO_MODE_WDT_RST 0
++#define MT7620_GPIO_MODE_WDT_REF 1
++#define MT7620_GPIO_MODE_WDT_GPIO 2
++#define MT7620_GPIO_MODE_WDT_MASK 0x3
++#define MT7620_GPIO_MODE_WDT_SHIFT 21
++
++#define MT7620_GPIO_MODE_I2C 0
++#define MT7620_GPIO_MODE_UART1 5
++#define MT7620_GPIO_MODE_MDIO 8
++#define MT7620_GPIO_MODE_RGMII1 9
++#define MT7620_GPIO_MODE_RGMII2 10
++#define MT7620_GPIO_MODE_SPI 11
++#define MT7620_GPIO_MODE_SPI_REF_CLK 12
++#define MT7620_GPIO_MODE_WLED 13
++#define MT7620_GPIO_MODE_JTAG 15
++#define MT7620_GPIO_MODE_EPHY 15
++#define MT7620_GPIO_MODE_PA 20
+
+ static inline int mt7620_get_eco(void)
+ {
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/pinmux.h
+@@ -0,0 +1,53 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * publishhed by the Free Software Foundation.
++ *
++ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RT288X_PINMUX_H__
++#define _RT288X_PINMUX_H__
++
++#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
++#define GRP(_name, _func, _mask, _shift) \
++ { .name = _name, .mask = _mask, .shift = _shift, \
++ .func = _func, .gpio = _mask, \
++ .func_count = ARRAY_SIZE(_func) }
++
++#define GRP_G(_name, _func, _mask, _gpio, _shift) \
++ { .name = _name, .mask = _mask, .shift = _shift, \
++ .func = _func, .gpio = _gpio, \
++ .func_count = ARRAY_SIZE(_func) }
++
++struct rt2880_pmx_group;
++
++struct rt2880_pmx_func {
++ const char *name;
++ const char value;
++
++ int pin_first;
++ int pin_count;
++ int *pins;
++
++ int *groups;
++ int group_count;
++
++ int enabled;
++};
++
++struct rt2880_pmx_group {
++ const char *name;
++ int enabled;
++
++ const u32 shift;
++ const char mask;
++ const char gpio;
++
++ struct rt2880_pmx_func *func;
++ int func_count;
++};
++
++extern struct rt2880_pmx_group *rt2880_pinmux_data;
++
++#endif
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -125,24 +125,29 @@ static inline int soc_is_rt5350(void)
+ #define RT305X_GPIO_GE0_TXD0 40
+ #define RT305X_GPIO_GE0_RXCLK 51
+
+-#define RT305X_GPIO_MODE_I2C BIT(0)
+-#define RT305X_GPIO_MODE_SPI BIT(1)
+ #define RT305X_GPIO_MODE_UART0_SHIFT 2
+ #define RT305X_GPIO_MODE_UART0_MASK 0x7
+ #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+-#define RT305X_GPIO_MODE_UARTF 0x0
+-#define RT305X_GPIO_MODE_PCM_UARTF 0x1
+-#define RT305X_GPIO_MODE_PCM_I2S 0x2
+-#define RT305X_GPIO_MODE_I2S_UARTF 0x3
+-#define RT305X_GPIO_MODE_PCM_GPIO 0x4
+-#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
+-#define RT305X_GPIO_MODE_GPIO_I2S 0x6
+-#define RT305X_GPIO_MODE_GPIO 0x7
+-#define RT305X_GPIO_MODE_UART1 BIT(5)
+-#define RT305X_GPIO_MODE_JTAG BIT(6)
+-#define RT305X_GPIO_MODE_MDIO BIT(7)
+-#define RT305X_GPIO_MODE_SDRAM BIT(8)
+-#define RT305X_GPIO_MODE_RGMII BIT(9)
++#define RT305X_GPIO_MODE_UARTF 0
++#define RT305X_GPIO_MODE_PCM_UARTF 1
++#define RT305X_GPIO_MODE_PCM_I2S 2
++#define RT305X_GPIO_MODE_I2S_UARTF 3
++#define RT305X_GPIO_MODE_PCM_GPIO 4
++#define RT305X_GPIO_MODE_GPIO_UARTF 5
++#define RT305X_GPIO_MODE_GPIO_I2S 6
++#define RT305X_GPIO_MODE_GPIO 7
++
++#define RT305X_GPIO_MODE_I2C 0
++#define RT305X_GPIO_MODE_SPI 1
++#define RT305X_GPIO_MODE_UART1 5
++#define RT305X_GPIO_MODE_JTAG 6
++#define RT305X_GPIO_MODE_MDIO 7
++#define RT305X_GPIO_MODE_SDRAM 8
++#define RT305X_GPIO_MODE_RGMII 9
++#define RT5350_GPIO_MODE_PHY_LED 14
++#define RT5350_GPIO_MODE_SPI_CS1 21
++#define RT3352_GPIO_MODE_LNA 18
++#define RT3352_GPIO_MODE_PA 20
+
+ #define RT3352_SYSC_REG_SYSCFG0 0x010
+ #define RT3352_SYSC_REG_SYSCFG1 0x014
+--- a/arch/mips/include/asm/mach-ralink/rt3883.h
++++ b/arch/mips/include/asm/mach-ralink/rt3883.h
+@@ -112,8 +112,6 @@
+ #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
+ #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
+
+-#define RT3883_GPIO_MODE_I2C BIT(0)
+-#define RT3883_GPIO_MODE_SPI BIT(1)
+ #define RT3883_GPIO_MODE_UART0_SHIFT 2
+ #define RT3883_GPIO_MODE_UART0_MASK 0x7
+ #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
+@@ -125,11 +123,15 @@
+ #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
+ #define RT3883_GPIO_MODE_GPIO_I2S 0x6
+ #define RT3883_GPIO_MODE_GPIO 0x7
+-#define RT3883_GPIO_MODE_UART1 BIT(5)
+-#define RT3883_GPIO_MODE_JTAG BIT(6)
+-#define RT3883_GPIO_MODE_MDIO BIT(7)
+-#define RT3883_GPIO_MODE_GE1 BIT(9)
+-#define RT3883_GPIO_MODE_GE2 BIT(10)
++
++#define RT3883_GPIO_MODE_I2C 0
++#define RT3883_GPIO_MODE_SPI 1
++#define RT3883_GPIO_MODE_UART1 5
++#define RT3883_GPIO_MODE_JTAG 6
++#define RT3883_GPIO_MODE_MDIO 7
++#define RT3883_GPIO_MODE_GE1 9
++#define RT3883_GPIO_MODE_GE2 10
++
+ #define RT3883_GPIO_MODE_PCI_SHIFT 11
+ #define RT3883_GPIO_MODE_PCI_MASK 0x7
+ #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -11,25 +11,6 @@
+
+ #define RAMIPS_SYS_TYPE_LEN 32
+
+-struct ralink_pinmux_grp {
+- const char *name;
+- u32 mask;
+- int gpio_first;
+- int gpio_last;
+-};
+-
+-struct ralink_pinmux {
+- struct ralink_pinmux_grp *mode;
+- struct ralink_pinmux_grp *uart;
+- int uart_shift;
+- u32 uart_mask;
+- void (*wdt_reset)(void);
+- struct ralink_pinmux_grp *pci;
+- int pci_shift;
+- u32 pci_mask;
+-};
+-extern struct ralink_pinmux rt_gpio_pinmux;
+-
+ struct ralink_soc_info {
+ unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
+ unsigned char *compatible;
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -17,6 +17,7 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/mt7620.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+@@ -47,118 +48,58 @@ enum mt762x_soc_type mt762x_soc;
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = MT7620_GPIO_MODE_I2C,
+- .gpio_first = 1,
+- .gpio_last = 2,
+- }, {
+- .name = "spi",
+- .mask = MT7620_GPIO_MODE_SPI,
+- .gpio_first = 3,
+- .gpio_last = 6,
+- }, {
+- .name = "uartlite",
+- .mask = MT7620_GPIO_MODE_UART1,
+- .gpio_first = 15,
+- .gpio_last = 16,
+- }, {
+- .name = "wdt",
+- .mask = MT7620_GPIO_MODE_WDT,
+- .gpio_first = 17,
+- .gpio_last = 17,
+- }, {
+- .name = "mdio",
+- .mask = MT7620_GPIO_MODE_MDIO,
+- .gpio_first = 22,
+- .gpio_last = 23,
+- }, {
+- .name = "rgmii1",
+- .mask = MT7620_GPIO_MODE_RGMII1,
+- .gpio_first = 24,
+- .gpio_last = 35,
+- }, {
+- .name = "spi refclk",
+- .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
+- .gpio_first = 37,
+- .gpio_last = 39,
+- }, {
+- .name = "jtag",
+- .mask = MT7620_GPIO_MODE_JTAG,
+- .gpio_first = 40,
+- .gpio_last = 44,
+- }, {
+- /* shared lines with jtag */
+- .name = "ephy",
+- .mask = MT7620_GPIO_MODE_EPHY,
+- .gpio_first = 40,
+- .gpio_last = 44,
+- }, {
+- .name = "nand",
+- .mask = MT7620_GPIO_MODE_JTAG,
+- .gpio_first = 45,
+- .gpio_last = 59,
+- }, {
+- .name = "rgmii2",
+- .mask = MT7620_GPIO_MODE_RGMII2,
+- .gpio_first = 60,
+- .gpio_last = 71,
+- }, {
+- .name = "wled",
+- .mask = MT7620_GPIO_MODE_WLED,
+- .gpio_first = 72,
+- .gpio_last = 72,
+- }, {0}
++static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
++static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
++static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
++static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
++static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
++static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
++static struct rt2880_pmx_func uartf_grp[] = {
++ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
++ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
++ FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
++ FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
++ FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
++ FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
++ FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
+ };
+-
+-static struct ralink_pinmux_grp uart_mux[] = {
+- {
+- .name = "uartf",
+- .mask = MT7620_GPIO_MODE_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "pcm uartf",
+- .mask = MT7620_GPIO_MODE_PCM_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "pcm i2s",
+- .mask = MT7620_GPIO_MODE_PCM_I2S,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "i2s uartf",
+- .mask = MT7620_GPIO_MODE_I2S_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "pcm gpio",
+- .mask = MT7620_GPIO_MODE_PCM_GPIO,
+- .gpio_first = 11,
+- .gpio_last = 14,
+- }, {
+- .name = "gpio uartf",
+- .mask = MT7620_GPIO_MODE_GPIO_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 10,
+- }, {
+- .name = "gpio i2s",
+- .mask = MT7620_GPIO_MODE_GPIO_I2S,
+- .gpio_first = 7,
+- .gpio_last = 10,
+- }, {
+- .name = "gpio",
+- .mask = MT7620_GPIO_MODE_GPIO,
+- }, {0}
++static struct rt2880_pmx_func wdt_grp[] = {
++ FUNC("wdt rst", 0, 17, 1),
++ FUNC("wdt refclk", 0, 17, 1),
++ };
++static struct rt2880_pmx_func pcie_rst_grp[] = {
++ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
++ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
++};
++static struct rt2880_pmx_func nd_sd_grp[] = {
++ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
++ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
+ };
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .uart = uart_mux,
+- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
+- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
++static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
++ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
++ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
++ MT7620_GPIO_MODE_UART0_SHIFT),
++ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
++ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
++ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
++ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
++ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
++ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
++ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
++ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
++ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
++ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
++ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
++ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
++ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
++ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
++ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
++ { 0 }
+ };
+
+ static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
+--- a/arch/mips/ralink/rt288x.c
++++ b/arch/mips/ralink/rt288x.c
+@@ -17,46 +17,27 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt288x.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = RT2880_GPIO_MODE_I2C,
+- .gpio_first = 1,
+- .gpio_last = 2,
+- }, {
+- .name = "spi",
+- .mask = RT2880_GPIO_MODE_SPI,
+- .gpio_first = 3,
+- .gpio_last = 6,
+- }, {
+- .name = "uartlite",
+- .mask = RT2880_GPIO_MODE_UART0,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "jtag",
+- .mask = RT2880_GPIO_MODE_JTAG,
+- .gpio_first = 17,
+- .gpio_last = 21,
+- }, {
+- .name = "mdio",
+- .mask = RT2880_GPIO_MODE_MDIO,
+- .gpio_first = 22,
+- .gpio_last = 23,
+- }, {
+- .name = "sdram",
+- .mask = RT2880_GPIO_MODE_SDRAM,
+- .gpio_first = 24,
+- .gpio_last = 39,
+- }, {
+- .name = "pci",
+- .mask = RT2880_GPIO_MODE_PCI,
+- .gpio_first = 40,
+- .gpio_last = 71,
+- }, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
++static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
++
++static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
++ GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
++ GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
++ GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
++ GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
++ GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
++ { 0 }
+ };
+
+ static void rt288x_wdt_reset(void)
+@@ -69,11 +50,6 @@ static void rt288x_wdt_reset(void)
+ rt_sysc_w32(t, SYSC_REG_CLKCFG);
+ }
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .wdt_reset = rt288x_wdt_reset,
+-};
+-
+ void __init ralink_clk_init(void)
+ {
+ unsigned long cpu_rate, wmac_rate = 40000000;
+@@ -141,4 +117,6 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_base = RT2880_SDRAM_BASE;
+ soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
++
++ rt2880_pinmux_data = rt2880_pinmux_data_act;
+ }
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -17,90 +17,76 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt305x.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+ enum rt305x_soc_type rt305x_soc;
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = RT305X_GPIO_MODE_I2C,
+- .gpio_first = RT305X_GPIO_I2C_SD,
+- .gpio_last = RT305X_GPIO_I2C_SCLK,
+- }, {
+- .name = "spi",
+- .mask = RT305X_GPIO_MODE_SPI,
+- .gpio_first = RT305X_GPIO_SPI_EN,
+- .gpio_last = RT305X_GPIO_SPI_CLK,
+- }, {
+- .name = "uartlite",
+- .mask = RT305X_GPIO_MODE_UART1,
+- .gpio_first = RT305X_GPIO_UART1_TXD,
+- .gpio_last = RT305X_GPIO_UART1_RXD,
+- }, {
+- .name = "jtag",
+- .mask = RT305X_GPIO_MODE_JTAG,
+- .gpio_first = RT305X_GPIO_JTAG_TDO,
+- .gpio_last = RT305X_GPIO_JTAG_TDI,
+- }, {
+- .name = "mdio",
+- .mask = RT305X_GPIO_MODE_MDIO,
+- .gpio_first = RT305X_GPIO_MDIO_MDC,
+- .gpio_last = RT305X_GPIO_MDIO_MDIO,
+- }, {
+- .name = "sdram",
+- .mask = RT305X_GPIO_MODE_SDRAM,
+- .gpio_first = RT305X_GPIO_SDRAM_MD16,
+- .gpio_last = RT305X_GPIO_SDRAM_MD31,
+- }, {
+- .name = "rgmii",
+- .mask = RT305X_GPIO_MODE_RGMII,
+- .gpio_first = RT305X_GPIO_GE0_TXD0,
+- .gpio_last = RT305X_GPIO_GE0_RXCLK,
+- }, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartf_func[] = {
++ FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
++ FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
++ FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
++ FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
++ FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
++ FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
++ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
++};
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
++static struct rt2880_pmx_func rt5350_cs1_func[] = {
++ FUNC("spi_cs1", 0, 27, 1),
++ FUNC("wdg_cs1", 1, 27, 1),
++};
++static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
++static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
++static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
++static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
++static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
++static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
++
++static struct rt2880_pmx_group rt3050_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
++ RT305X_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
++ GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
++ GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
++ { 0 }
++};
++
++static struct rt2880_pmx_group rt3352_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
++ RT305X_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
++ GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
++ GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
++ GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
++ GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
++ { 0 }
+ };
+
+-static struct ralink_pinmux_grp uart_mux[] = {
+- {
+- .name = "uartf",
+- .mask = RT305X_GPIO_MODE_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "pcm uartf",
+- .mask = RT305X_GPIO_MODE_PCM_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "pcm i2s",
+- .mask = RT305X_GPIO_MODE_PCM_I2S,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "i2s uartf",
+- .mask = RT305X_GPIO_MODE_I2S_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "pcm gpio",
+- .mask = RT305X_GPIO_MODE_PCM_GPIO,
+- .gpio_first = RT305X_GPIO_10,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "gpio uartf",
+- .mask = RT305X_GPIO_MODE_GPIO_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_10,
+- }, {
+- .name = "gpio i2s",
+- .mask = RT305X_GPIO_MODE_GPIO_I2S,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_10,
+- }, {
+- .name = "gpio",
+- .mask = RT305X_GPIO_MODE_GPIO,
+- }, {0}
++static struct rt2880_pmx_group rt5350_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
++ RT305X_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
++ GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
++ GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
++ { 0 }
+ };
+
+ static void rt305x_wdt_reset(void)
+@@ -114,14 +100,6 @@ static void rt305x_wdt_reset(void)
+ rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
+ }
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .uart = uart_mux,
+- .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
+- .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
+- .wdt_reset = rt305x_wdt_reset,
+-};
+-
+ static unsigned long rt5350_get_mem_size(void)
+ {
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+@@ -290,11 +268,14 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_base = RT305X_SDRAM_BASE;
+ if (soc_is_rt5350()) {
+ soc_info->mem_size = rt5350_get_mem_size();
++ rt2880_pinmux_data = rt5350_pinmux_data;
+ } else if (soc_is_rt305x() || soc_is_rt3350()) {
+ soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
++ rt2880_pinmux_data = rt3050_pinmux_data;
+ } else if (soc_is_rt3352()) {
+ soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
++ rt2880_pinmux_data = rt3352_pinmux_data;
+ }
+ }
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -17,132 +17,50 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt3883.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = RT3883_GPIO_MODE_I2C,
+- .gpio_first = RT3883_GPIO_I2C_SD,
+- .gpio_last = RT3883_GPIO_I2C_SCLK,
+- }, {
+- .name = "spi",
+- .mask = RT3883_GPIO_MODE_SPI,
+- .gpio_first = RT3883_GPIO_SPI_CS0,
+- .gpio_last = RT3883_GPIO_SPI_MISO,
+- }, {
+- .name = "uartlite",
+- .mask = RT3883_GPIO_MODE_UART1,
+- .gpio_first = RT3883_GPIO_UART1_TXD,
+- .gpio_last = RT3883_GPIO_UART1_RXD,
+- }, {
+- .name = "jtag",
+- .mask = RT3883_GPIO_MODE_JTAG,
+- .gpio_first = RT3883_GPIO_JTAG_TDO,
+- .gpio_last = RT3883_GPIO_JTAG_TCLK,
+- }, {
+- .name = "mdio",
+- .mask = RT3883_GPIO_MODE_MDIO,
+- .gpio_first = RT3883_GPIO_MDIO_MDC,
+- .gpio_last = RT3883_GPIO_MDIO_MDIO,
+- }, {
+- .name = "ge1",
+- .mask = RT3883_GPIO_MODE_GE1,
+- .gpio_first = RT3883_GPIO_GE1_TXD0,
+- .gpio_last = RT3883_GPIO_GE1_RXCLK,
+- }, {
+- .name = "ge2",
+- .mask = RT3883_GPIO_MODE_GE2,
+- .gpio_first = RT3883_GPIO_GE2_TXD0,
+- .gpio_last = RT3883_GPIO_GE2_RXCLK,
+- }, {
+- .name = "pci",
+- .mask = RT3883_GPIO_MODE_PCI,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "lna a",
+- .mask = RT3883_GPIO_MODE_LNA_A,
+- .gpio_first = RT3883_GPIO_LNA_PE_A0,
+- .gpio_last = RT3883_GPIO_LNA_PE_A2,
+- }, {
+- .name = "lna g",
+- .mask = RT3883_GPIO_MODE_LNA_G,
+- .gpio_first = RT3883_GPIO_LNA_PE_G0,
+- .gpio_last = RT3883_GPIO_LNA_PE_G2,
+- }, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartf_func[] = {
++ FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
++ FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
++ FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
++ FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
++ FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
++ FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
++ FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
+ };
+-
+-static struct ralink_pinmux_grp uart_mux[] = {
+- {
+- .name = "uartf",
+- .mask = RT3883_GPIO_MODE_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "pcm uartf",
+- .mask = RT3883_GPIO_MODE_PCM_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "pcm i2s",
+- .mask = RT3883_GPIO_MODE_PCM_I2S,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "i2s uartf",
+- .mask = RT3883_GPIO_MODE_I2S_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "pcm gpio",
+- .mask = RT3883_GPIO_MODE_PCM_GPIO,
+- .gpio_first = RT3883_GPIO_11,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "gpio uartf",
+- .mask = RT3883_GPIO_MODE_GPIO_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_10,
+- }, {
+- .name = "gpio i2s",
+- .mask = RT3883_GPIO_MODE_GPIO_I2S,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_10,
+- }, {
+- .name = "gpio",
+- .mask = RT3883_GPIO_MODE_GPIO,
+- }, {0}
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
++static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
++static struct rt2880_pmx_func pci_func[] = {
++ FUNC("pci-dev", 0, 40, 32),
++ FUNC("pci-host2", 1, 40, 32),
++ FUNC("pci-host1", 2, 40, 32),
++ FUNC("pci-fnc", 3, 40, 32)
+ };
++static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
++static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
+
+-static struct ralink_pinmux_grp pci_mux[] = {
+- {
+- .name = "pci-dev",
+- .mask = 0,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-host2",
+- .mask = 1,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-host1",
+- .mask = 2,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-fnc",
+- .mask = 3,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-gpio",
+- .mask = 7,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {0}
++static struct rt2880_pmx_group rt3883_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
++ RT3883_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
++ GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
++ GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
++ GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
++ RT3883_GPIO_MODE_PCI_SHIFT),
++ GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
++ GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
++ { 0 }
+ };
+
+ static void rt3883_wdt_reset(void)
+@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
+ rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
+ }
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .uart = uart_mux,
+- .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
+- .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
+- .wdt_reset = rt3883_wdt_reset,
+- .pci = pci_mux,
+- .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
+- .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
+-};
+-
+ void __init ralink_clk_init(void)
+ {
+ unsigned long cpu_rate, sys_rate;
+@@ -244,4 +151,6 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_base = RT3883_SDRAM_BASE;
+ soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
++
++ rt2880_pinmux_data = rt3883_pinmux_data;
+ }
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -103,6 +103,11 @@ config PINCTRL_LANTIQ
+ select PINMUX
+ select PINCONF
+
++config PINCTRL_RT2880
++ bool
++ depends on RALINK
++ select PINMUX
++
+ config PINCTRL_FALCON
+ bool
+ depends on SOC_FALCON
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctr
+ obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
+ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
+ obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
++obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
+ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
+ obj-$(CONFIG_PINCTRL_SIRF) += sirf/
+ obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
+--- /dev/null
++++ b/drivers/pinctrl/pinctrl-rt2880.c
+@@ -0,0 +1,467 @@
++/*
++ * linux/drivers/pinctrl/pinctrl-rt2880.c
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * publishhed by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/io.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/machine.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/pinmux.h>
++#include <asm/mach-ralink/mt7620.h>
++
++#include "core.h"
++
++#define SYSC_REG_GPIO_MODE 0x60
++
++struct rt2880_priv {
++ struct device *dev;
++
++ struct pinctrl_pin_desc *pads;
++ struct pinctrl_desc *desc;
++
++ struct rt2880_pmx_func **func;
++ int func_count;
++
++ struct rt2880_pmx_group *groups;
++ const char **group_names;
++ int group_count;
++
++ uint8_t *gpio;
++ int max_pins;
++};
++
++struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
++
++static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ return p->group_count;
++}
++
++static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
++ unsigned group)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ if (group >= p->group_count)
++ return NULL;
++
++ return p->group_names[group];
++}
++
++static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
++ unsigned group,
++ const unsigned **pins,
++ unsigned *num_pins)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ if (group >= p->group_count)
++ return -EINVAL;
++
++ *pins = p->groups[group].func[0].pins;
++ *num_pins = p->groups[group].func[0].pin_count;
++
++ return 0;
++}
++
++static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
++ struct pinctrl_map *map, unsigned num_maps)
++{
++ int i;
++
++ for (i = 0; i < num_maps; i++)
++ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
++ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
++ kfree(map[i].data.configs.configs);
++ kfree(map);
++}
++
++static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
++ struct seq_file *s,
++ unsigned offset)
++{
++ seq_printf(s, "ralink pio");
++}
++
++static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
++ struct device_node *np,
++ struct pinctrl_map **map)
++{
++ const char *function;
++ int func = of_property_read_string(np, "ralink,function", &function);
++ int grps = of_property_count_strings(np, "ralink,group");
++ int i;
++
++ if (func || !grps)
++ return;
++
++ for (i = 0; i < grps; i++) {
++ const char *group;
++
++ of_property_read_string_index(np, "ralink,group", i, &group);
++
++ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
++ (*map)->name = function;
++ (*map)->data.mux.group = group;
++ (*map)->data.mux.function = function;
++ (*map)++;
++ }
++}
++
++static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
++ struct device_node *np_config,
++ struct pinctrl_map **map,
++ unsigned *num_maps)
++{
++ int max_maps = 0;
++ struct pinctrl_map *tmp;
++ struct device_node *np;
++
++ for_each_child_of_node(np_config, np) {
++ int ret = of_property_count_strings(np, "ralink,group");
++
++ if (ret >= 0)
++ max_maps += ret;
++ }
++
++ if (!max_maps)
++ return max_maps;
++
++ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
++ if (!*map)
++ return -ENOMEM;
++
++ tmp = *map;
++
++ for_each_child_of_node(np_config, np)
++ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
++ *num_maps = max_maps;
++
++ return 0;
++}
++
++static const struct pinctrl_ops rt2880_pctrl_ops = {
++ .get_groups_count = rt2880_get_group_count,
++ .get_group_name = rt2880_get_group_name,
++ .get_group_pins = rt2880_get_group_pins,
++ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
++ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
++ .dt_free_map = rt2880_pinctrl_dt_free_map,
++};
++
++static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ return p->func_count;
++}
++
++static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
++ unsigned func)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ return p->func[func]->name;
++}
++
++static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
++ unsigned func,
++ const char * const **groups,
++ unsigned * const num_groups)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ if (p->func[func]->group_count == 1)
++ *groups = &p->group_names[p->func[func]->groups[0]];
++ else
++ *groups = p->group_names;
++
++ *num_groups = p->func[func]->group_count;
++
++ return 0;
++}
++
++static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
++ unsigned func,
++ unsigned group)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++ u32 mode = 0;
++ int i;
++
++ /* dont allow double use */
++ if (p->groups[group].enabled) {
++ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
++ return -EBUSY;
++ }
++
++ p->groups[group].enabled = 1;
++ p->func[func]->enabled = 1;
++
++ mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
++ mode &= ~(p->groups[group].mask << p->groups[group].shift);
++
++ /* mark the pins as gpio */
++ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
++ p->gpio[p->groups[group].func[0].pins[i]] = 1;
++
++ /* function 0 is gpio and needs special handling */
++ if (func == 0) {
++ mode |= p->groups[group].gpio << p->groups[group].shift;
++ } else {
++ for (i = 0; i < p->func[func]->pin_count; i++)
++ p->gpio[p->func[func]->pins[i]] = 0;
++ mode |= p->func[func]->value << p->groups[group].shift;
++ }
++ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
++
++
++ return 0;
++}
++
++static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
++ struct pinctrl_gpio_range *range,
++ unsigned pin)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ if (!p->gpio[pin]) {
++ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static const struct pinmux_ops rt2880_pmx_group_ops = {
++ .get_functions_count = rt2880_pmx_func_count,
++ .get_function_name = rt2880_pmx_func_name,
++ .get_function_groups = rt2880_pmx_group_get_groups,
++ .set_mux = rt2880_pmx_group_enable,
++ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
++};
++
++static struct pinctrl_desc rt2880_pctrl_desc = {
++ .owner = THIS_MODULE,
++ .name = "rt2880-pinmux",
++ .pctlops = &rt2880_pctrl_ops,
++ .pmxops = &rt2880_pmx_group_ops,
++};
++
++static struct rt2880_pmx_func gpio_func = {
++ .name = "gpio",
++};
++
++static int rt2880_pinmux_index(struct rt2880_priv *p)
++{
++ struct rt2880_pmx_func **f;
++ struct rt2880_pmx_group *mux = p->groups;
++ int i, j, c = 0;
++
++ /* count the mux functions */
++ while (mux->name) {
++ p->group_count++;
++ mux++;
++ }
++
++ /* allocate the group names array needed by the gpio function */
++ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
++ if (!p->group_names)
++ return -1;
++
++ for (i = 0; i < p->group_count; i++) {
++ p->group_names[i] = p->groups[i].name;
++ p->func_count += p->groups[i].func_count;
++ }
++
++ /* we have a dummy function[0] for gpio */
++ p->func_count++;
++
++ /* allocate our function and group mapping index buffers */
++ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
++ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
++ if (!f || !gpio_func.groups)
++ return -1;
++
++ /* add a backpointer to the function so it knows its group */
++ gpio_func.group_count = p->group_count;
++ for (i = 0; i < gpio_func.group_count; i++)
++ gpio_func.groups[i] = i;
++
++ f[c] = &gpio_func;
++ c++;
++
++ /* add remaining functions */
++ for (i = 0; i < p->group_count; i++) {
++ for (j = 0; j < p->groups[i].func_count; j++) {
++ f[c] = &p->groups[i].func[j];
++ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
++ f[c]->groups[0] = i;
++ f[c]->group_count = 1;
++ c++;
++ }
++ }
++ return 0;
++}
++
++static int rt2880_pinmux_pins(struct rt2880_priv *p)
++{
++ int i, j;
++
++ /* loop over the functions and initialize the pins array. also work out the highest pin used */
++ for (i = 0; i < p->func_count; i++) {
++ int pin;
++
++ if (!p->func[i]->pin_count)
++ continue;
++
++ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
++ for (j = 0; j < p->func[i]->pin_count; j++)
++ p->func[i]->pins[j] = p->func[i]->pin_first + j;
++
++ pin = p->func[i]->pin_first + p->func[i]->pin_count;
++ if (pin > p->max_pins)
++ p->max_pins = pin;
++ }
++
++ /* the buffer that tells us which pins are gpio */
++ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
++ GFP_KERNEL);
++ /* the pads needed to tell pinctrl about our pins */
++ p->pads = devm_kzalloc(p->dev,
++ sizeof(struct pinctrl_pin_desc) * p->max_pins,
++ GFP_KERNEL);
++ if (!p->pads || !p->gpio ) {
++ dev_err(p->dev, "Failed to allocate gpio data\n");
++ return -ENOMEM;
++ }
++
++ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
++ for (i = 0; i < p->func_count; i++) {
++ if (!p->func[i]->pin_count)
++ continue;
++
++ for (j = 0; j < p->func[i]->pin_count; j++)
++ p->gpio[p->func[i]->pins[j]] = 0;
++ }
++
++ /* pin 0 is always a gpio */
++ p->gpio[0] = 1;
++
++ /* set the pads */
++ for (i = 0; i < p->max_pins; i++) {
++ /* strlen("ioXY") + 1 = 5 */
++ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
++
++ if (!name) {
++ dev_err(p->dev, "Failed to allocate pad name\n");
++ return -ENOMEM;
++ }
++ snprintf(name, 5, "io%d", i);
++ p->pads[i].number = i;
++ p->pads[i].name = name;
++ }
++ p->desc->pins = p->pads;
++ p->desc->npins = p->max_pins;
++
++ return 0;
++}
++
++static int rt2880_pinmux_probe(struct platform_device *pdev)
++{
++ struct rt2880_priv *p;
++ struct pinctrl_dev *dev;
++ struct device_node *np;
++
++ if (!rt2880_pinmux_data)
++ return -ENOSYS;
++
++ /* setup the private data */
++ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
++ if (!p)
++ return -ENOMEM;
++
++ p->dev = &pdev->dev;
++ p->desc = &rt2880_pctrl_desc;
++ p->groups = rt2880_pinmux_data;
++ platform_set_drvdata(pdev, p);
++
++ /* init the device */
++ if (rt2880_pinmux_index(p)) {
++ dev_err(&pdev->dev, "failed to load index\n");
++ return -EINVAL;
++ }
++ if (rt2880_pinmux_pins(p)) {
++ dev_err(&pdev->dev, "failed to load pins\n");
++ return -EINVAL;
++ }
++ dev = pinctrl_register(p->desc, &pdev->dev, p);
++ if (IS_ERR(dev))
++ return PTR_ERR(dev);
++
++ /* finalize by adding gpio ranges for enables gpio controllers */
++ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
++ const __be32 *ngpio, *gpiobase;
++ struct pinctrl_gpio_range *range;
++ char *name;
++
++ if (!of_device_is_available(np))
++ continue;
++
++ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
++ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
++ if (!ngpio || !gpiobase) {
++ dev_err(&pdev->dev, "failed to load chip info\n");
++ return -EINVAL;
++ }
++
++ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
++ range->name = name = (char *) &range[1];
++ sprintf(name, "pio");
++ range->npins = __be32_to_cpu(*ngpio);
++ range->base = __be32_to_cpu(*gpiobase);
++ range->pin_base = range->base;
++ pinctrl_add_gpio_range(dev, range);
++ }
++
++ return 0;
++}
++
++static const struct of_device_id rt2880_pinmux_match[] = {
++ { .compatible = "ralink,rt2880-pinmux" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
++
++static struct platform_driver rt2880_pinmux_driver = {
++ .probe = rt2880_pinmux_probe,
++ .driver = {
++ .name = "rt2880-pinmux",
++ .owner = THIS_MODULE,
++ .of_match_table = rt2880_pinmux_match,
++ },
++};
++
++int __init rt2880_pinmux_init(void)
++{
++ return platform_driver_register(&rt2880_pinmux_driver);
++}
++
++core_initcall_sync(rt2880_pinmux_init);
--- /dev/null
+From 5b0bcc314005dd14eeae190948165a81eef7da1f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:36:02 +0100
+Subject: [PATCH 31/57] PCI: MIPS: adds rt2880 pci support
+
+Add support for the pci found on the rt2880 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-rt2880.c | 281 ++++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/Kconfig | 1 +
+ 3 files changed, 283 insertions(+)
+ create mode 100644 arch/mips/pci/pci-rt2880.c
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
+ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
++obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
+--- /dev/null
++++ b/arch/mips/pci/pci-rt2880.c
+@@ -0,0 +1,281 @@
++/*
++ * Ralink RT288x SoC PCI register definitions
++ *
++ * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++
++#include <asm/mach-ralink/rt288x.h>
++
++#define RT2880_PCI_BASE 0x00440000
++#define RT288X_CPU_IRQ_PCI 4
++
++#define RT2880_PCI_MEM_BASE 0x20000000
++#define RT2880_PCI_MEM_SIZE 0x10000000
++#define RT2880_PCI_IO_BASE 0x00460000
++#define RT2880_PCI_IO_SIZE 0x00010000
++
++#define RT2880_PCI_REG_PCICFG_ADDR 0x00
++#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
++#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
++#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
++#define RT2880_PCI_REG_CONFIG_ADDR 0x20
++#define RT2880_PCI_REG_CONFIG_DATA 0x24
++#define RT2880_PCI_REG_MEMBASE 0x28
++#define RT2880_PCI_REG_IOBASE 0x2c
++#define RT2880_PCI_REG_ID 0x30
++#define RT2880_PCI_REG_CLASS 0x34
++#define RT2880_PCI_REG_SUBID 0x38
++#define RT2880_PCI_REG_ARBCTL 0x80
++
++static void __iomem *rt2880_pci_base;
++static DEFINE_SPINLOCK(rt2880_pci_lock);
++
++static u32 rt2880_pci_reg_read(u32 reg)
++{
++ return readl(rt2880_pci_base + reg);
++}
++
++static void rt2880_pci_reg_write(u32 val, u32 reg)
++{
++ writel(val, rt2880_pci_base + reg);
++}
++
++static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
++ unsigned int func, unsigned int where)
++{
++ return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
++ 0x80000000);
++}
++
++static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 *val)
++{
++ unsigned long flags;
++ u32 address;
++ u32 data;
++
++ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
++ PCI_FUNC(devfn), where);
++
++ spin_lock_irqsave(&rt2880_pci_lock, flags);
++ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
++ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++
++ switch (size) {
++ case 1:
++ *val = (data >> ((where & 3) << 3)) & 0xff;
++ break;
++ case 2:
++ *val = (data >> ((where & 3) << 3)) & 0xffff;
++ break;
++ case 4:
++ *val = data;
++ break;
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 val)
++{
++ unsigned long flags;
++ u32 address;
++ u32 data;
++
++ address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
++ PCI_FUNC(devfn), where);
++
++ spin_lock_irqsave(&rt2880_pci_lock, flags);
++ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++ data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
++
++ switch (size) {
++ case 1:
++ data = (data & ~(0xff << ((where & 3) << 3))) |
++ (val << ((where & 3) << 3));
++ break;
++ case 2:
++ data = (data & ~(0xffff << ((where & 3) << 3))) |
++ (val << ((where & 3) << 3));
++ break;
++ case 4:
++ data = val;
++ break;
++ }
++
++ rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
++ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops rt2880_pci_ops = {
++ .read = rt2880_pci_config_read,
++ .write = rt2880_pci_config_write,
++};
++
++static struct resource rt2880_pci_mem_resource = {
++ .name = "PCI MEM space",
++ .start = RT2880_PCI_MEM_BASE,
++ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct resource rt2880_pci_io_resource = {
++ .name = "PCI IO space",
++ .start = RT2880_PCI_IO_BASE,
++ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
++ .flags = IORESOURCE_IO,
++};
++
++static struct pci_controller rt2880_pci_controller = {
++ .pci_ops = &rt2880_pci_ops,
++ .mem_resource = &rt2880_pci_mem_resource,
++ .io_resource = &rt2880_pci_io_resource,
++};
++
++static inline u32 rt2880_pci_read_u32(unsigned long reg)
++{
++ unsigned long flags;
++ u32 address;
++ u32 ret;
++
++ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
++
++ spin_lock_irqsave(&rt2880_pci_lock, flags);
++ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++ ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
++ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++
++ return ret;
++}
++
++static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
++{
++ unsigned long flags;
++ u32 address;
++
++ address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
++
++ spin_lock_irqsave(&rt2880_pci_lock, flags);
++ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++ rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
++ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ u16 cmd;
++ int irq = -1;
++
++ if (dev->bus->number != 0)
++ return irq;
++
++ switch (PCI_SLOT(dev->devfn)) {
++ case 0x00:
++ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
++ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
++ break;
++ case 0x11:
++ irq = RT288X_CPU_IRQ_PCI;
++ break;
++ default:
++ printk("%s:%s[%d] trying to alloc unknown pci irq\n",
++ __FILE__, __func__, __LINE__);
++ BUG();
++ break;
++ }
++
++ pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
++ pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
++ pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
++ PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
++ pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
++ pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
++ dev->irq);
++ return irq;
++}
++
++static int rt288x_pci_probe(struct platform_device *pdev)
++{
++ void __iomem *io_map_base;
++ int i;
++
++ rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
++
++ io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
++ rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
++ set_io_port_base((unsigned long) io_map_base);
++
++ ioport_resource.start = RT2880_PCI_IO_BASE;
++ ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
++
++ rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
++ for(i = 0; i < 0xfffff; i++) {}
++
++ rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
++ rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
++ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
++ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
++ rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
++ rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
++ rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
++ rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
++ rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
++
++ rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
++ (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
++
++ register_pci_controller(&rt2880_pci_controller);
++ return 0;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ return 0;
++}
++
++static const struct of_device_id rt288x_pci_match[] = {
++ { .compatible = "ralink,rt288x-pci" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt288x_pci_match);
++
++static struct platform_driver rt288x_pci_driver = {
++ .probe = rt288x_pci_probe,
++ .driver = {
++ .name = "rt288x-pci",
++ .owner = THIS_MODULE,
++ .of_match_table = rt288x_pci_match,
++ },
++};
++
++int __init pcibios_init(void)
++{
++ int ret = platform_driver_register(&rt288x_pci_driver);
++ if (ret)
++ pr_info("rt288x-pci: Error registering platform driver!");
++ return ret;
++}
++
++arch_initcall(pcibios_init);
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -21,6 +21,7 @@ choice
+ config SOC_RT288X
+ bool "RT288x"
+ select MIPS_L1_CACHE_SHIFT_4
++ select HW_HAS_PCI
+
+ config SOC_RT305X
+ bool "RT305x"
--- /dev/null
+From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 18 May 2013 22:06:15 +0200
+Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-mt7620.c | 363 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/Kconfig | 1 +
+ 3 files changed, 365 insertions(+)
+ create mode 100644 arch/mips/pci/pci-mt7620.c
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -43,6 +43,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
+ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
++obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
+ obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
+--- /dev/null
++++ b/arch/mips/pci/pci-mt7620.c
+@@ -0,0 +1,396 @@
++/*
++ * Ralink MT7620A SoC PCI support
++ *
++ * Copyright (C) 2007-2013 Bruce Chang
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++#include <linux/reset.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/mt7620.h>
++
++#define RALINK_PCI_MM_MAP_BASE 0x20000000
++#define RALINK_PCI_IO_MAP_BASE 0x10160000
++
++#define RALINK_INT_PCIE0 4
++#define RALINK_SYSCFG1 0x14
++#define RALINK_CLKCFG1 0x30
++#define RALINK_GPIOMODE 0x60
++#define RALINK_PCIE_CLK_GEN 0x7c
++#define RALINK_PCIE_CLK_GEN1 0x80
++#define PCIEPHY0_CFG 0x90
++#define PPLL_CFG1 0x9c
++#define PPLL_DRV 0xa0
++#define PDRV_SW_SET (1<<31)
++#define LC_CKDRVPD_ (1<<19)
++
++#define RALINK_PCI_CONFIG_ADDR 0x20
++#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
++#define MEMORY_BASE 0x0
++#define RALINK_PCIE0_RST (1<<26)
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_PCI_MEMBASE 0x28
++#define RALINK_PCI_IOBASE 0x2C
++
++#define RT6855_PCIE0_OFFSET 0x2000
++
++#define RALINK_PCI_PCICFG_ADDR 0x00
++#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
++#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
++#define RALINK_PCI0_ID 0x30
++#define RALINK_PCI0_CLASS 0x34
++#define RALINK_PCI0_SUBID 0x38
++#define RALINK_PCI0_STATUS 0x50
++#define RALINK_PCI_PCIMSK_ADDR 0x0C
++
++#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
++#define RALINK_PCIE0_CLK_EN (1 << 26)
++
++#define BUSY 0x80000000
++#define WAITRETRY_MAX 10
++#define WRITE_MODE (1UL << 23)
++#define DATA_SHIFT 0
++#define ADDR_SHIFT 8
++
++static void __iomem *bridge_base;
++static void __iomem *pcie_base;
++
++static struct reset_control *rstpcie0;
++
++static inline void bridge_w32(u32 val, unsigned reg)
++{
++ iowrite32(val, bridge_base + reg);
++}
++
++static inline u32 bridge_r32(unsigned reg)
++{
++ return ioread32(bridge_base + reg);
++}
++
++static inline void pcie_w32(u32 val, unsigned reg)
++{
++ iowrite32(val, pcie_base + reg);
++}
++
++static inline u32 pcie_r32(unsigned reg)
++{
++ return ioread32(pcie_base + reg);
++}
++
++static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
++{
++ u32 val = pcie_r32(reg);
++
++ val &= ~clr;
++ val |= set;
++ pcie_w32(val, reg);
++}
++
++static int wait_pciephy_busy(void)
++{
++ unsigned long reg_value = 0x0, retry = 0;
++
++ while (1) {
++ reg_value = pcie_r32(PCIEPHY0_CFG);
++
++ if (reg_value & BUSY)
++ mdelay(100);
++ else
++ break;
++ if (retry++ > WAITRETRY_MAX){
++ printk("PCIE-PHY retry failed.\n");
++ return -1;
++ }
++ }
++ return 0;
++}
++
++static void pcie_phy(unsigned long addr, unsigned long val)
++{
++ wait_pciephy_busy();
++ pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
++ mdelay(1);
++ wait_pciephy_busy();
++}
++
++static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
++{
++ unsigned int slot = PCI_SLOT(devfn);
++ u8 func = PCI_FUNC(devfn);
++ u32 address;
++ u32 data;
++ u32 num = 0;
++
++ if (bus)
++ num = bus->number;
++
++ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
++ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
++
++ switch (size) {
++ case 1:
++ *val = (data >> ((where & 3) << 3)) & 0xff;
++ break;
++ case 2:
++ *val = (data >> ((where & 3) << 3)) & 0xffff;
++ break;
++ case 4:
++ *val = data;
++ break;
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
++{
++ unsigned int slot = PCI_SLOT(devfn);
++ u8 func = PCI_FUNC(devfn);
++ u32 address;
++ u32 data;
++ u32 num = 0;
++
++ if (bus)
++ num = bus->number;
++
++ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++ bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
++ data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
++
++ switch (size) {
++ case 1:
++ data = (data & ~(0xff << ((where & 3) << 3))) |
++ (val << ((where & 3) << 3));
++ break;
++ case 2:
++ data = (data & ~(0xffff << ((where & 3) << 3))) |
++ (val << ((where & 3) << 3));
++ break;
++ case 4:
++ data = val;
++ break;
++ }
++
++ bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++struct pci_ops mt7620_pci_ops= {
++ .read = pci_config_read,
++ .write = pci_config_write,
++};
++
++static struct resource mt7620_res_pci_mem1;
++static struct resource mt7620_res_pci_io1;
++struct pci_controller mt7620_controller = {
++ .pci_ops = &mt7620_pci_ops,
++ .mem_resource = &mt7620_res_pci_mem1,
++ .mem_offset = 0x00000000UL,
++ .io_resource = &mt7620_res_pci_io1,
++ .io_offset = 0x00000000UL,
++ .io_map_base = 0xa0000000,
++};
++
++static int mt7620_pci_hw_init(struct platform_device *pdev) {
++ /* PCIE: bypass PCIe DLL */
++ pcie_phy(0x0, 0x80);
++ pcie_phy(0x1, 0x04);
++
++ /* PCIE: Elastic buffer control */
++ pcie_phy(0x68, 0xB4);
++
++ pcie_m32(0, BIT(1), RALINK_PCI_PCICFG_ADDR);
++
++ reset_control_assert(rstpcie0);
++
++ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
++ rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
++
++ reset_control_deassert(rstpcie0);
++ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
++
++ mdelay(100);
++
++ if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
++ dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
++ reset_control_assert(rstpcie0);
++ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
++ return -1;
++ }
++ rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
++
++ return 0;
++}
++
++static int mt7628_pci_hw_init(struct platform_device *pdev) {
++ u32 val = 0;
++
++ rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
++ reset_control_deassert(rstpcie0);
++ rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
++ mdelay(100);
++
++ pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
++
++ pci_config_read(NULL, 0, 0x70c, 4, &val);
++ val &= ~(0xff) << 8;
++ val |= 0x50 << 8;
++ pci_config_write(NULL, 0, 0x70c, 4, val);
++
++ pci_config_read(NULL, 0, 0x70c, 4, &val);
++ dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
++
++ return 0;
++}
++
++static int mt7620_pci_probe(struct platform_device *pdev)
++{
++ struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ u32 val = 0;
++
++ rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
++ if (IS_ERR(rstpcie0))
++ return PTR_ERR(rstpcie0);
++
++ bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
++ if (!bridge_base)
++ return -ENOMEM;
++
++ pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
++ if (!pcie_base)
++ return -ENOMEM;
++
++ iomem_resource.start = 0;
++ iomem_resource.end = ~0;
++ ioport_resource.start = 0;
++ ioport_resource.end = ~0;
++
++ /* bring up the pci core */
++ switch (ralink_soc) {
++ case MT762X_SOC_MT7620A:
++ if (mt7620_pci_hw_init(pdev))
++ return -1;
++ break;
++
++ case MT762X_SOC_MT7628AN:
++ if (mt7628_pci_hw_init(pdev))
++ return -1;
++ break;
++
++ default:
++ dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
++ return -1;
++ }
++ mdelay(50);
++
++ /* enable write access */
++ pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
++ mdelay(100);
++
++ /* check if there is a card present */
++ if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
++ reset_control_assert(rstpcie0);
++ rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
++ if (ralink_soc == MT762X_SOC_MT7620A)
++ rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
++ dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
++ return -1;
++ }
++
++ /* setup ranges */
++ bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
++ bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
++
++ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
++ pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
++ pcie_w32(0x06040001, RALINK_PCI0_CLASS);
++
++ /* enable interrupts */
++ pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
++
++ /* voodoo from the SDK driver */
++ pci_config_read(NULL, 0, 4, 4, &val);
++ pci_config_write(NULL, 0, 4, 4, val | 0x7);
++
++ pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
++ register_pci_controller(&mt7620_controller);
++
++ return 0;
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ u16 cmd;
++ u32 val;
++ int irq = 0;
++
++ if ((dev->bus->number == 0) && (slot == 0)) {
++ pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
++ pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
++ pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
++ } else if ((dev->bus->number == 1) && (slot == 0x0)) {
++ irq = RALINK_INT_PCIE0;
++ } else {
++ dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
++ return 0;
++ }
++ dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq);
++
++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
++ pci_read_config_word(dev, PCI_COMMAND, &cmd);
++
++ // FIXME
++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
++ pci_write_config_word(dev, PCI_COMMAND, cmd);
++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
++ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
++
++ return irq;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ return 0;
++}
++
++static const struct of_device_id mt7620_pci_ids[] = {
++ { .compatible = "mediatek,mt7620-pci" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
++
++static struct platform_driver mt7620_pci_driver = {
++ .probe = mt7620_pci_probe,
++ .driver = {
++ .name = "mt7620-pci",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(mt7620_pci_ids),
++ },
++};
++
++static int __init mt7620_pci_init(void)
++{
++ return platform_driver_register(&mt7620_pci_driver);
++}
++
++arch_initcall(mt7620_pci_init);
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -33,6 +33,7 @@ choice
+
+ config SOC_MT7620
+ bool "MT7620/8"
++ select HW_HAS_PCI
+
+ config SOC_MT7621
+ bool "MT7621"
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -19,6 +19,7 @@ enum mt762x_soc_type {
+ MT762X_SOC_MT7620N,
+ MT762X_SOC_MT7628AN,
+ };
++extern enum mt762x_soc_type mt762x_soc;
+
+ #define MT7620_SYSC_BASE 0x10000000
+
--- /dev/null
+From 9c34372c25519234add1cfdfe2b69c0847f2037e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:38:50 +0100
+Subject: [PATCH 33/57] NET: multi phy support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/phy.c | 9 ++++++---
+ include/linux/phy.h | 1 +
+ 2 files changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -819,7 +819,8 @@ void phy_state_machine(struct work_struc
+ /* If the link is down, give up on negotiation for now */
+ if (!phydev->link) {
+ phydev->state = PHY_NOLINK;
+- netif_carrier_off(phydev->attached_dev);
++ if (!phydev->no_auto_carrier_off)
++ netif_carrier_off(phydev->attached_dev);
+ phydev->adjust_link(phydev->attached_dev);
+ break;
+ }
+@@ -892,7 +893,8 @@ void phy_state_machine(struct work_struc
+ netif_carrier_on(phydev->attached_dev);
+ } else {
+ phydev->state = PHY_NOLINK;
+- netif_carrier_off(phydev->attached_dev);
++ if (!phydev->no_auto_carrier_off)
++ netif_carrier_off(phydev->attached_dev);
+ }
+
+ phydev->adjust_link(phydev->attached_dev);
+@@ -904,7 +906,8 @@ void phy_state_machine(struct work_struc
+ case PHY_HALTED:
+ if (phydev->link) {
+ phydev->link = 0;
+- netif_carrier_off(phydev->attached_dev);
++ if (!phydev->no_auto_carrier_off)
++ netif_carrier_off(phydev->attached_dev);
+ phydev->adjust_link(phydev->attached_dev);
+ do_suspend = true;
+ }
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -363,6 +363,7 @@ struct phy_device {
+ struct phy_c45_device_ids c45_ids;
+ bool is_c45;
+ bool is_internal;
++ bool no_auto_carrier_off;
+ bool has_fixups;
+
+ enum phy_state state;
--- /dev/null
+From 92f38460229a8816404408f036f0a374f1013d0e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:40:01 +0100
+Subject: [PATCH 34/57] NET: add of_get_mac_address_mtd()
+
+Many embedded devices have information such as mac addresses stored inside mtd
+devices. This patch allows us to add a property inside a node describing a
+network interface. The new property points at a mtd partition with an offset
+where the mac address can be found.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++
+ include/linux/of_net.h | 1 +
+ 2 files changed, 38 insertions(+)
+
+--- a/drivers/of/of_net.c
++++ b/drivers/of/of_net.c
+@@ -10,6 +10,7 @@
+ #include <linux/of_net.h>
+ #include <linux/phy.h>
+ #include <linux/export.h>
++#include <linux/mtd/mtd.h>
+
+ /**
+ * of_get_phy_mode - Get phy mode for given device_node
+@@ -75,3 +76,39 @@ const void *of_get_mac_address(struct de
+ return NULL;
+ }
+ EXPORT_SYMBOL(of_get_mac_address);
++
++int of_get_mac_address_mtd(struct device_node *np, void *mac)
++{
++ struct device_node *mtd_np = NULL;
++ size_t retlen;
++ int size, ret;
++ struct mtd_info *mtd;
++ const char *part;
++ const __be32 *list;
++ phandle phandle;
++
++ list = of_get_property(np, "mtd-mac-address", &size);
++ if (!list || (size != (2 * sizeof(*list))))
++ return -ENOENT;
++
++ phandle = be32_to_cpup(list++);
++ if (phandle)
++ mtd_np = of_find_node_by_phandle(phandle);
++
++ if (!mtd_np)
++ return -ENOENT;
++
++ part = of_get_property(mtd_np, "label", NULL);
++ if (!part)
++ part = mtd_np->name;
++
++ mtd = get_mtd_device_nm(part);
++ if (IS_ERR(mtd))
++ return PTR_ERR(mtd);
++
++ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, (u_char *) mac);
++ put_mtd_device(mtd);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(of_get_mac_address_mtd);
+--- a/include/linux/of_net.h
++++ b/include/linux/of_net.h
+@@ -11,6 +11,7 @@
+ #include <linux/of.h>
+ extern int of_get_phy_mode(struct device_node *np);
+ extern const void *of_get_mac_address(struct device_node *np);
++extern int of_get_mac_address_mtd(struct device_node *np, void *mac);
+ #else
+ static inline int of_get_phy_mode(struct device_node *np)
+ {
--- /dev/null
+From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Apr 2013 23:20:03 +0200
+Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
+
+Add support for Ralink FE and ESW.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -199,6 +199,7 @@ void __init ralink_clk_init(void)
+ }
+
+ ralink_clk_add("cpu", cpu_rate);
++ ralink_clk_add("sys", sys_rate);
+ ralink_clk_add("10000b00.spi", sys_rate);
+ ralink_clk_add("10000100.timer", wdt_rate);
+ ralink_clk_add("10000120.watchdog", wdt_rate);
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -152,6 +152,7 @@ source "drivers/net/ethernet/packetengin
+ source "drivers/net/ethernet/pasemi/Kconfig"
+ source "drivers/net/ethernet/qlogic/Kconfig"
+ source "drivers/net/ethernet/qualcomm/Kconfig"
++source "drivers/net/ethernet/ralink/Kconfig"
+ source "drivers/net/ethernet/realtek/Kconfig"
+ source "drivers/net/ethernet/renesas/Kconfig"
+ source "drivers/net/ethernet/rdc/Kconfig"
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -62,6 +62,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe
+ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
+ obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
+ obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
++obj-$(CONFIG_NET_RALINK) += ralink/
+ obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
+ obj-$(CONFIG_SH_ETH) += renesas/
+ obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
--- /dev/null
+--- a/drivers/phy/Kconfig
++++ b/drivers/phy/Kconfig
+@@ -239,6 +239,11 @@
+ help
+ This option enables support for APM X-Gene SoC multi-purpose PHY.
+
++config PHY_RALINK_USB
++ tristate "Ralink USB PHY driver"
++ select GENERIC_PHY
++ depends on RALINK
++
+ config PHY_STIH407_USB
+ tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
+ depends on RESET_CONTROLLER
+--- a/drivers/phy/Makefile
++++ b/drivers/phy/Makefile
+@@ -31,3 +31,4 @@
+ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
+ obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
+ obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
++obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
+--- /dev/null
++++ b/drivers/phy/phy-ralink-usb.c
+@@ -0,0 +1,177 @@
++/*
++ * Allwinner ralink USB phy driver
++ *
++ * Copyright (C) 2014 John Crispin <blogic@openwrt.org>
++ *
++ * Based on code from
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++#include <linux/of_platform.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define RT_SYSC_REG_SYSCFG1 0x014
++#define RT_SYSC_REG_CLKCFG1 0x030
++#define RT_SYSC_REG_USB_PHY_CFG 0x05c
++
++#define RT_RSTCTRL_UDEV BIT(25)
++#define RT_RSTCTRL_UHST BIT(22)
++#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
++
++#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
++#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
++#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
++#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
++
++#define USB_PHY_UTMI_8B60M BIT(1)
++#define UDEV_WAKEUP BIT(0)
++
++static atomic_t usb_pwr_ref = ATOMIC_INIT(0);
++static struct reset_control *rstdev;
++static struct reset_control *rsthost;
++static u32 phy_clk;
++static struct phy *rt_phy;
++
++static void usb_phy_enable(int state)
++{
++ if (state)
++ rt_sysc_m32(0, phy_clk, RT_SYSC_REG_CLKCFG1);
++ else
++ rt_sysc_m32(phy_clk, 0, RT_SYSC_REG_CLKCFG1);
++ mdelay(100);
++}
++
++static int ralink_usb_phy_init(struct phy *_phy)
++{
++ return 0;
++}
++
++static int ralink_usb_phy_exit(struct phy *_phy)
++{
++ return 0;
++}
++
++static int ralink_usb_phy_power_on(struct phy *_phy)
++{
++ if (atomic_inc_return(&usb_pwr_ref) == 1) {
++ int host = 1;
++ u32 t;
++
++ usb_phy_enable(1);
++
++ if (host) {
++ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
++ if (!IS_ERR(rsthost))
++ reset_control_deassert(rsthost);
++ if (!IS_ERR(rstdev))
++ reset_control_deassert(rstdev);
++ } else {
++ rt_sysc_m32(RT_SYSCFG1_USB0_HOST_MODE, 0, RT_SYSC_REG_SYSCFG1);
++ if (!IS_ERR(rstdev))
++ reset_control_deassert(rstdev);
++ }
++ mdelay(100);
++
++ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
++ dev_info(&_phy->dev, "remote usb device wakeup %s\n",
++ (t & UDEV_WAKEUP) ? ("enabbled") : ("disabled"));
++ if (t & USB_PHY_UTMI_8B60M)
++ dev_info(&_phy->dev, "UTMI 8bit 60MHz\n");
++ else
++ dev_info(&_phy->dev, "UTMI 16bit 30MHz\n");
++ }
++
++ return 0;
++}
++
++static int ralink_usb_phy_power_off(struct phy *_phy)
++{
++ if (atomic_dec_return(&usb_pwr_ref) == 0) {
++ usb_phy_enable(0);
++ if (!IS_ERR(rstdev))
++ reset_control_assert(rstdev);
++ if (!IS_ERR(rsthost))
++ reset_control_assert(rsthost);
++ }
++
++ return 0;
++}
++
++static struct phy_ops ralink_usb_phy_ops = {
++ .init = ralink_usb_phy_init,
++ .exit = ralink_usb_phy_exit,
++ .power_on = ralink_usb_phy_power_on,
++ .power_off = ralink_usb_phy_power_off,
++ .owner = THIS_MODULE,
++};
++
++static struct phy *ralink_usb_phy_xlate(struct device *dev,
++ struct of_phandle_args *args)
++{
++ return rt_phy;
++}
++
++static const struct of_device_id ralink_usb_phy_of_match[] = {
++ { .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
++ { .compatible = "ralink,mt7620a-usbphy", .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN | MT7620_CLKCFG1_UPHY0_CLK_EN) },
++ { },
++};
++MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
++
++static int ralink_usb_phy_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct phy_provider *phy_provider;
++ const struct of_device_id *match;
++
++ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++ match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
++ phy_clk = (int) match->data;
++
++ rsthost = devm_reset_control_get(&pdev->dev, "host");
++ rstdev = devm_reset_control_get(&pdev->dev, "device");
++
++ rt_phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops, NULL);
++ if (IS_ERR(rt_phy)) {
++ dev_err(dev, "failed to create PHY\n");
++ return PTR_ERR(rt_phy);
++ }
++
++ phy_provider = devm_of_phy_provider_register(dev, ralink_usb_phy_xlate);
++printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static struct platform_driver ralink_usb_phy_driver = {
++ .probe = ralink_usb_phy_probe,
++ .driver = {
++ .of_match_table = ralink_usb_phy_of_match,
++ .name = "ralink-usb-phy",
++ }
++};
++module_platform_driver(ralink_usb_phy_driver);
++
++MODULE_DESCRIPTION("Ralink USB phy driver");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_LICENSE("GPL v2");
--- /dev/null
+From ffb27de4760595c356ef619c97f25722c8db28e7 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:49:07 +0100
+Subject: [PATCH 38/57] USB: add OHCI/EHCI OF binding
+
+based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/usb/Makefile | 3 ++-
+ drivers/usb/host/ehci-platform.c | 21 +++++++++++++++++----
+ drivers/usb/host/ohci-platform.c | 37 +++++++++++++++++++++++++++++++------
+ 3 files changed, 50 insertions(+), 11 deletions(-)
+
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -359,6 +373,7 @@ static int ehci_platform_resume(struct d
+ static const struct of_device_id vt8500_ehci_ids[] = {
+ { .compatible = "via,vt8500-ehci", },
+ { .compatible = "wm,prizm-ehci", },
++ { .compatible = "ralink,rt3xxx-ehci", },
+ { .compatible = "generic-ehci", },
+ {}
+ };
+--- a/drivers/usb/host/ohci-platform.c
++++ b/drivers/usb/host/ohci-platform.c
+@@ -342,6 +358,7 @@ static int ohci_platform_resume(struct d
+ #endif /* CONFIG_PM */
+
+ static const struct of_device_id ohci_platform_ids[] = {
++ { .compatible = "ralink,rt3xxx-ohci", },
+ { .compatible = "generic-ohci", },
+ { }
+ };
--- /dev/null
+From f0df443ca7d5d0e4d31aa6769ea12a8cf24d2cd8 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:38:51 +0200
+Subject: [PATCH 41/57] mtd: fix cfi cmdset 0002 erase status check
+
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -2291,7 +2291,7 @@ static int __xipram do_erase_chip(struct
+ chip->erase_suspended = 0;
+ }
+
+- if (chip_ready(map, adr))
++ if (chip_good(map, adr, map_word_ff(map)))
+ break;
+
+ if (time_after(jiffies, timeo)) {
+@@ -2380,7 +2380,7 @@ static int __xipram do_erase_oneblock(st
+ chip->erase_suspended = 0;
+ }
+
+- if (chip_ready(map, adr)) {
++ if (chip_good(map, adr, map_word_ff(map))) {
+ xip_enable(map, chip, adr);
+ break;
+ }
--- /dev/null
+From 39010a26a34a56a7928f9217ac23e5138c5ea952 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:39:21 +0200
+Subject: [PATCH 42/57] mtd: cfi cmdset 0002 force word write
+
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -40,7 +40,7 @@
+ #include <linux/mtd/xip.h>
+
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+
+ #define MAX_WORD_RETRIES 3
+
+@@ -51,7 +51,9 @@
+
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m
+ }
+ #endif
+
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ struct map_info *map = mtd->priv;
+@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru
+ mtd->_write = cfi_amdstd_write_buffers;
+ }
+ }
++#endif /* !FORCE_WORD_WRITE */
+
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1789,6 +1793,7 @@ static int cfi_amdstd_write_words(struct
+ /*
+ * FIXME: interleaved mode not tested, and probably not supported!
+ */
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ unsigned long adr, const u_char *buf,
+ int len)
+@@ -1917,7 +1922,6 @@ static int __xipram do_write_buffer(stru
+ return ret;
+ }
+
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+ {
+@@ -1992,6 +1996,7 @@ static int cfi_amdstd_write_buffers(stru
+
+ return 0;
+ }
++#endif /* !FORCE_WORD_WRITE */
+
+ /*
+ * Wait for the flash chip to become ready to write data
--- /dev/null
+From b915fe7cd934160bfaf2cd52f03c118abcae2419 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 17 Nov 2013 17:41:46 +0100
+Subject: [PATCH 43/57] mtd: ralink: add mt7620 nand driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/maps/Kconfig | 4 +
+ drivers/mtd/maps/Makefile | 2 +
+ drivers/mtd/maps/ralink_nand.c | 2136 ++++++++++++++++++++++++++++++++++++++++
+ drivers/mtd/maps/ralink_nand.h | 232 +++++
+ 4 files changed, 2374 insertions(+)
+ create mode 100644 drivers/mtd/maps/ralink_nand.c
+ create mode 100644 drivers/mtd/maps/ralink_nand.h
+
+--- a/drivers/mtd/maps/Kconfig
++++ b/drivers/mtd/maps/Kconfig
+@@ -399,4 +399,8 @@ config MTD_LATCH_ADDR
+
+ If compiled as a module, it will be called latch-addr-flash.
+
++config MTD_NAND_MT7620
++ tristate "Support for NAND on Mediatek MT7620"
++ depends on RALINK && SOC_MT7620
++
+ endmenu
+--- a/drivers/mtd/maps/Makefile
++++ b/drivers/mtd/maps/Makefile
+@@ -43,3 +43,5 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o
+ obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
+ obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o
+ obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o
++obj-$(CONFIG_MTD_NAND_MT7620) += ralink_nand.o
++
+--- /dev/null
++++ b/drivers/mtd/maps/ralink_nand.c
+@@ -0,0 +1,2136 @@
++#define DEBUG
++#include <linux/device.h>
++#undef DEBUG
++#include <linux/slab.h>
++#include <linux/mtd/mtd.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/mtd/partitions.h>
++#include <asm/io.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++#include "ralink_nand.h"
++#ifdef RANDOM_GEN_BAD_BLOCK
++#include <linux/random.h>
++#endif
++
++#define LARGE_MTD_BOOT_PART_SIZE (CFG_BLOCKSIZE<<2)
++#define LARGE_MTD_CONFIG_PART_SIZE (CFG_BLOCKSIZE<<2)
++#define LARGE_MTD_FACTORY_PART_SIZE (CFG_BLOCKSIZE<<1)
++
++
++#define BLOCK_ALIGNED(a) ((a) & (CFG_BLOCKSIZE - 1))
++
++#define READ_STATUS_RETRY 1000
++
++struct mtd_info *ranfc_mtd = NULL;
++
++int skipbbt = 0;
++int ranfc_debug = 1;
++static int ranfc_bbt = 1;
++#if defined (WORKAROUND_RX_BUF_OV)
++static int ranfc_verify = 1;
++#endif
++static u32 nand_addrlen;
++
++#if 0
++module_param(ranfc_debug, int, 0644);
++module_param(ranfc_bbt, int, 0644);
++module_param(ranfc_verify, int, 0644);
++#endif
++
++#if 0
++#define ra_dbg(args...) do { if (ranfc_debug) printk(args); } while(0)
++#else
++#define ra_dbg(args...)
++#endif
++
++#define CLEAR_INT_STATUS() ra_outl(NFC_INT_ST, ra_inl(NFC_INT_ST))
++#define NFC_TRANS_DONE() (ra_inl(NFC_INT_ST) & INT_ST_ND_DONE)
++
++int is_nand_page_2048 = 0;
++const unsigned int nand_size_map[2][3] = {{25, 30, 30}, {20, 27, 30}};
++
++static int nfc_wait_ready(int snooze_ms);
++
++static const char * const mtk_probe_types[] = { "cmdlinepart", "ofpart", NULL };
++
++/**
++ * reset nand chip
++ */
++static int nfc_chip_reset(void)
++{
++ int status;
++
++ //ra_dbg("%s:\n", __func__);
++
++ // reset nand flash
++ ra_outl(NFC_CMD1, 0x0);
++ ra_outl(NFC_CMD2, 0xff);
++ ra_outl(NFC_ADDR, 0x0);
++ ra_outl(NFC_CONF, 0x0411);
++
++ status = nfc_wait_ready(5); //erase wait 5us
++ if (status & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ }
++
++ return (int)(status & NAND_STATUS_FAIL);
++
++}
++
++
++
++/**
++ * clear NFC and flash chip.
++ */
++static int nfc_all_reset(void)
++{
++ int retry;
++
++ ra_dbg("%s: \n", __func__);
++
++ // reset controller
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
++
++ CLEAR_INT_STATUS();
++
++ retry = READ_STATUS_RETRY;
++ while ((ra_inl(NFC_INT_ST) & 0x02) != 0x02 && retry--);
++ if (retry <= 0) {
++ printk("nfc_all_reset: clean buffer fail \n");
++ return -1;
++ }
++
++ retry = READ_STATUS_RETRY;
++ while ((ra_inl(NFC_STATUS) & 0x1) != 0x0 && retry--) { //fixme, controller is busy ?
++ udelay(1);
++ }
++
++ nfc_chip_reset();
++
++ return 0;
++}
++
++/** NOTICE: only called by nfc_wait_ready().
++ * @return -1, nfc can not get transction done
++ * @return 0, ok.
++ */
++static int _nfc_read_status(char *status)
++{
++ unsigned long cmd1, conf;
++ int int_st, nfc_st;
++ int retry;
++
++ cmd1 = 0x70;
++ conf = 0x000101 | (1 << 20);
++
++ //fixme, should we check nfc status?
++ CLEAR_INT_STATUS();
++
++ ra_outl(NFC_CMD1, cmd1);
++ ra_outl(NFC_CONF, conf);
++
++ /* FIXME,
++ * 1. since we have no wired ready signal, directly
++ * calling this function is not gurantee to read right status under ready state.
++ * 2. the other side, we can not determine how long to become ready, this timeout retry is nonsense.
++ * 3. SUGGESTION: call nfc_read_status() from nfc_wait_ready(),
++ * that is aware about caller (in sementics) and has snooze plused nfc ND_DONE.
++ */
++ retry = READ_STATUS_RETRY;
++ do {
++ nfc_st = ra_inl(NFC_STATUS);
++ int_st = ra_inl(NFC_INT_ST);
++
++ ndelay(10);
++ } while (!(int_st & INT_ST_RX_BUF_RDY) && retry--);
++
++ if (!(int_st & INT_ST_RX_BUF_RDY)) {
++ printk("nfc_read_status: NFC fail, int_st(%x), retry:%x. nfc:%x, reset nfc and flash. \n",
++ int_st, retry, nfc_st);
++ nfc_all_reset();
++ *status = NAND_STATUS_FAIL;
++ return -1;
++ }
++
++ *status = (char)(le32_to_cpu(ra_inl(NFC_DATA)) & 0x0ff);
++ return 0;
++}
++
++/**
++ * @return !0, chip protect.
++ * @return 0, chip not protected.
++ */
++static int nfc_check_wp(void)
++{
++ /* Check the WP bit */
++#if !defined CONFIG_NOT_SUPPORT_WP
++ return !!(ra_inl(NFC_CTRL) & 0x01);
++#else
++ char result = 0;
++ int ret;
++
++ ret = _nfc_read_status(&result);
++ //FIXME, if ret < 0
++
++ return !(result & NAND_STATUS_WP);
++#endif
++}
++
++#if !defined CONFIG_NOT_SUPPORT_RB
++/*
++ * @return !0, chip ready.
++ * @return 0, chip busy.
++ */
++static int nfc_device_ready(void)
++{
++ /* Check the ready */
++ return !!(ra_inl(NFC_STATUS) & 0x04);
++}
++#endif
++
++
++/**
++ * generic function to get data from flash.
++ * @return data length reading from flash.
++ */
++static int _ra_nand_pull_data(char *buf, int len, int use_gdma)
++{
++#ifdef RW_DATA_BY_BYTE
++ char *p = buf;
++#else
++ __u32 *p = (__u32 *)buf;
++#endif
++ int retry, int_st;
++ unsigned int ret_data;
++ int ret_size;
++
++ // receive data by use_gdma
++ if (use_gdma) {
++ //if (_ra_nand_dma_pull((unsigned long)p, len)) {
++ if (1) {
++ printk("%s: fail \n", __func__);
++ len = -1; //return error
++ }
++
++ return len;
++ }
++
++ //fixme: retry count size?
++ retry = READ_STATUS_RETRY;
++ // no gdma
++ while (len > 0) {
++ int_st = ra_inl(NFC_INT_ST);
++ if (int_st & INT_ST_RX_BUF_RDY) {
++
++ ret_data = ra_inl(NFC_DATA);
++ ra_outl(NFC_INT_ST, INT_ST_RX_BUF_RDY);
++#ifdef RW_DATA_BY_BYTE
++ ret_size = sizeof(unsigned int);
++ ret_size = min(ret_size, len);
++ len -= ret_size;
++ while (ret_size-- > 0) {
++ //nfc is little endian
++ *p++ = ret_data & 0x0ff;
++ ret_data >>= 8;
++ }
++#else
++ ret_size = min(len, 4);
++ len -= ret_size;
++ if (ret_size == 4)
++ *p++ = ret_data;
++ else {
++ __u8 *q = (__u8 *)p;
++ while (ret_size-- > 0) {
++ *q++ = ret_data & 0x0ff;
++ ret_data >>= 8;
++ }
++ p = (__u32 *)q;
++ }
++#endif
++ retry = READ_STATUS_RETRY;
++ }
++ else if (int_st & INT_ST_ND_DONE) {
++ break;
++ }
++ else {
++ udelay(1);
++ if (retry-- < 0)
++ break;
++ }
++ }
++
++#ifdef RW_DATA_BY_BYTE
++ return (int)(p - buf);
++#else
++ return ((int)p - (int)buf);
++#endif
++}
++
++/**
++ * generic function to put data into flash.
++ * @return data length writing into flash.
++ */
++static int _ra_nand_push_data(char *buf, int len, int use_gdma)
++{
++#ifdef RW_DATA_BY_BYTE
++ char *p = buf;
++#else
++ __u32 *p = (__u32 *)buf;
++#endif
++ int retry, int_st;
++ unsigned int tx_data = 0;
++ int tx_size, iter = 0;
++
++ // receive data by use_gdma
++ if (use_gdma) {
++ //if (_ra_nand_dma_push((unsigned long)p, len))
++ if (1)
++ len = 0;
++ printk("%s: fail \n", __func__);
++ return len;
++ }
++
++ // no gdma
++ retry = READ_STATUS_RETRY;
++ while (len > 0) {
++ int_st = ra_inl(NFC_INT_ST);
++ if (int_st & INT_ST_TX_BUF_RDY) {
++#ifdef RW_DATA_BY_BYTE
++ tx_size = min(len, (int)sizeof(unsigned long));
++ for (iter = 0; iter < tx_size; iter++) {
++ tx_data |= (*p++ << (8*iter));
++ }
++#else
++ tx_size = min(len, 4);
++ if (tx_size == 4)
++ tx_data = (*p++);
++ else {
++ __u8 *q = (__u8 *)p;
++ for (iter = 0; iter < tx_size; iter++)
++ tx_data |= (*q++ << (8*iter));
++ p = (__u32 *)q;
++ }
++#endif
++ ra_outl(NFC_INT_ST, INT_ST_TX_BUF_RDY);
++ ra_outl(NFC_DATA, tx_data);
++ len -= tx_size;
++ retry = READ_STATUS_RETRY;
++ }
++ else if (int_st & INT_ST_ND_DONE) {
++ break;
++ }
++ else {
++ udelay(1);
++ if (retry-- < 0) {
++ ra_dbg("%s p:%p buf:%p \n", __func__, p, buf);
++ break;
++ }
++ }
++ }
++
++
++#ifdef RW_DATA_BY_BYTE
++ return (int)(p - buf);
++#else
++ return ((int)p - (int)buf);
++#endif
++
++}
++
++static int nfc_select_chip(struct ra_nand_chip *ra, int chipnr)
++{
++#if (CONFIG_NUMCHIPS == 1)
++ if (!(chipnr < CONFIG_NUMCHIPS))
++ return -1;
++ return 0;
++#else
++ BUG();
++#endif
++}
++
++/** @return -1: chip_select fail
++ * 0 : both CE and WP==0 are OK
++ * 1 : CE OK and WP==1
++ */
++static int nfc_enable_chip(struct ra_nand_chip *ra, unsigned int offs, int read_only)
++{
++ int chipnr = offs >> ra->chip_shift;
++
++ ra_dbg("%s: offs:%x read_only:%x \n", __func__, offs, read_only);
++
++ chipnr = nfc_select_chip(ra, chipnr);
++ if (chipnr < 0) {
++ printk("%s: chip select error, offs(%x)\n", __func__, offs);
++ return -1;
++ }
++
++ if (!read_only)
++ return nfc_check_wp();
++
++ return 0;
++}
++
++/** wait nand chip becomeing ready and return queried status.
++ * @param snooze: sleep time in ms unit before polling device ready.
++ * @return status of nand chip
++ * @return NAN_STATUS_FAIL if something unexpected.
++ */
++static int nfc_wait_ready(int snooze_ms)
++{
++ int retry;
++ char status;
++
++ // wait nfc idle,
++ if (snooze_ms == 0)
++ snooze_ms = 1;
++ else
++ schedule_timeout(snooze_ms * HZ / 1000);
++
++ snooze_ms = retry = snooze_ms *1000000 / 100 ; // ndelay(100)
++
++ while (!NFC_TRANS_DONE() && retry--) {
++ if (!cond_resched())
++ ndelay(100);
++ }
++
++ if (!NFC_TRANS_DONE()) {
++ printk("nfc_wait_ready: no transaction done \n");
++ return NAND_STATUS_FAIL;
++ }
++
++#if !defined (CONFIG_NOT_SUPPORT_RB)
++ //fixme
++ while(!(status = nfc_device_ready()) && retry--) {
++ ndelay(100);
++ }
++
++ if (status == 0) {
++ printk("nfc_wait_ready: no device ready. \n");
++ return NAND_STATUS_FAIL;
++ }
++
++ _nfc_read_status(&status);
++ return status;
++#else
++
++ while(retry--) {
++ _nfc_read_status(&status);
++ if (status & NAND_STATUS_READY)
++ break;
++ ndelay(100);
++ }
++ if (retry<0)
++ printk("nfc_wait_ready 2: no device ready, status(%x). \n", status);
++
++ return status;
++#endif
++}
++
++/**
++ * return 0: erase OK
++ * return -EIO: fail
++ */
++int nfc_erase_block(struct ra_nand_chip *ra, int row_addr)
++{
++ unsigned long cmd1, cmd2, bus_addr, conf;
++ char status;
++
++ cmd1 = 0x60;
++ cmd2 = 0xd0;
++ bus_addr = row_addr;
++ conf = 0x00511 | ((CFG_ROW_ADDR_CYCLE)<<16);
++
++ // set NFC
++ ra_dbg("%s: cmd1: %lx, cmd2:%lx bus_addr: %lx, conf: %lx \n",
++ __func__, cmd1, cmd2, bus_addr, conf);
++
++ //fixme, should we check nfc status?
++ CLEAR_INT_STATUS();
++
++ ra_outl(NFC_CMD1, cmd1);
++ ra_outl(NFC_CMD2, cmd2);
++ ra_outl(NFC_ADDR, bus_addr);
++ ra_outl(NFC_CONF, conf);
++
++ status = nfc_wait_ready(3); //erase wait 3ms
++ if (status & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ return -EIO;
++ }
++
++ return 0;
++
++}
++
++static inline int _nfc_read_raw_data(int cmd1, int cmd2, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
++{
++ int ret;
++
++ CLEAR_INT_STATUS();
++ ra_outl(NFC_CMD1, cmd1);
++ ra_outl(NFC_CMD2, cmd2);
++ ra_outl(NFC_ADDR, bus_addr);
++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++ ra_outl(NFC_ADDR2, bus_addr2);
++#endif
++ ra_outl(NFC_CONF, conf);
++
++ ret = _ra_nand_pull_data(buf, len, 0);
++ if (ret != len) {
++ ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
++ return NAND_STATUS_FAIL;
++ }
++
++ //FIXME, this section is not necessary
++ ret = nfc_wait_ready(0); //wait ready
++ /* to prevent the DATA FIFO 's old data from next operation */
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
++
++ if (ret & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ return NAND_STATUS_FAIL;
++ }
++
++ return 0;
++}
++
++static inline int _nfc_write_raw_data(int cmd1, int cmd3, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
++{
++ int ret;
++
++ CLEAR_INT_STATUS();
++ ra_outl(NFC_CMD1, cmd1);
++ ra_outl(NFC_CMD3, cmd3);
++ ra_outl(NFC_ADDR, bus_addr);
++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++ ra_outl(NFC_ADDR2, bus_addr2);
++#endif
++ ra_outl(NFC_CONF, conf);
++
++ ret = _ra_nand_push_data(buf, len, 0);
++ if (ret != len) {
++ ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
++ return NAND_STATUS_FAIL;
++ }
++
++ ret = nfc_wait_ready(1); //write wait 1ms
++ /* to prevent the DATA FIFO 's old data from next operation */
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
++
++ if (ret & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ return NAND_STATUS_FAIL;
++ }
++
++ return 0;
++}
++
++/**
++ * @return !0: fail
++ * @return 0: OK
++ */
++int nfc_read_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
++{
++ unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
++ unsigned int bus_addr = 0, bus_addr2 = 0;
++ unsigned int ecc_en;
++ int use_gdma;
++ int status;
++
++ int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
++ // constrain of nfc read function
++
++#if defined (WORKAROUND_RX_BUF_OV)
++ BUG_ON (len > 60); //problem of rx-buffer overrun
++#endif
++ BUG_ON (offs >> ra->oob_shift); //page boundry
++ BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
++ ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
++
++ use_gdma = flags & FLAG_USE_GDMA;
++ ecc_en = flags & FLAG_ECC_EN;
++ bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
++
++ if (is_nand_page_2048) {
++ bus_addr += CFG_PAGESIZE;
++ bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
++ cmd1 = 0x0;
++ cmd2 = 0x30;
++ conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
++ }
++ else {
++ cmd1 = 0x50;
++ conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
++ }
++ if (ecc_en)
++ conf |= (1<<3);
++ if (use_gdma)
++ conf |= (1<<2);
++
++ ra_dbg("%s: cmd1:%x, bus_addr:%x, conf:%x, len:%x, flag:%x\n",
++ __func__, cmd1, bus_addr, conf, len, flags);
++
++ status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf, len, flags);
++ if (status & NAND_STATUS_FAIL) {
++ printk("%s: fail\n", __func__);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++/**
++ * @return !0: fail
++ * @return 0: OK
++ */
++int nfc_write_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
++{
++ unsigned int cmd1 = 0, cmd3=0, conf = 0;
++ unsigned int bus_addr = 0, bus_addr2 = 0;
++ int use_gdma;
++ int status;
++
++ int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
++ // constrain of nfc read function
++
++ BUG_ON (offs >> ra->oob_shift); //page boundry
++ BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
++ ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
++
++ use_gdma = flags & FLAG_USE_GDMA;
++ bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
++
++ if (is_nand_page_2048) {
++ cmd1 = 0x80;
++ cmd3 = 0x10;
++ bus_addr += CFG_PAGESIZE;
++ bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
++ conf = 0x001123 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
++ }
++ else {
++ cmd1 = 0x08050;
++ cmd3 = 0x10;
++ conf = 0x001223 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
++ }
++ if (use_gdma)
++ conf |= (1<<2);
++
++ // set NFC
++ ra_dbg("%s: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
++ __func__, cmd1, cmd3, bus_addr, conf, len);
++
++ status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, len, flags);
++ if (status & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++
++int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
++int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
++
++
++#if !defined (WORKAROUND_RX_BUF_OV)
++static int one_bit_correction(char *ecc, char *expected, int *bytes, int *bits);
++int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
++{
++ int ret, i;
++ char *p, *e;
++ int ecc;
++
++ //ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
++
++ if (mode == FL_WRITING) {
++ int len = CFG_PAGESIZE + CFG_PAGE_OOBSIZE;
++ int conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
++ conf |= (1<<3); //(ecc_en)
++ //conf |= (1<<2); // (use_gdma)
++
++ p = ra->readback_buffers;
++ ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
++ if (ret == 0)
++ goto ecc_check;
++
++ //FIXME, double comfirm
++ printk("%s: read back fail, try again \n",__func__);
++ ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
++ if (ret != 0) {
++ printk("\t%s: read back fail agian \n",__func__);
++ goto bad_block;
++ }
++ }
++ else if (mode == FL_READING) {
++ p = buf;
++ }
++ else
++ return -2;
++
++ecc_check:
++ p += CFG_PAGESIZE;
++ if (!is_nand_page_2048) {
++ ecc = ra_inl(NFC_ECC);
++ if (ecc == 0) //clean page.
++ return 0;
++ e = (char*)&ecc;
++ for (i=0; i<CONFIG_ECC_BYTES; i++) {
++ int eccpos = CONFIG_ECC_OFFSET + i;
++ if (*(p + eccpos) != (char)0xff)
++ break;
++ if (i == CONFIG_ECC_BYTES - 1) {
++ printk("skip ecc 0xff at page %x\n", page);
++ return 0;
++ }
++ }
++ for (i=0; i<CONFIG_ECC_BYTES; i++) {
++ int eccpos = CONFIG_ECC_OFFSET + i;
++ if (*(p + eccpos) != *(e + i)) {
++ printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
++ __func__, (mode == FL_READING)?"read":"write", page,
++ *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
++ return -1;
++ }
++ }
++ }
++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++ else {
++ int ecc2, ecc3, ecc4, qsz;
++ char *e2, *e3, *e4;
++ int correction_flag = 0;
++ ecc = ra_inl(NFC_ECC_P1);
++ ecc2 = ra_inl(NFC_ECC_P2);
++ ecc3 = ra_inl(NFC_ECC_P3);
++ ecc4 = ra_inl(NFC_ECC_P4);
++ e = (char*)&ecc;
++ e2 = (char*)&ecc2;
++ e3 = (char*)&ecc3;
++ e4 = (char*)&ecc4;
++ qsz = CFG_PAGE_OOBSIZE / 4;
++ if (ecc == 0 && ecc2 == 0 && ecc3 == 0 && ecc4 == 0)
++ return 0;
++ for (i=0; i<CONFIG_ECC_BYTES; i++) {
++ int eccpos = CONFIG_ECC_OFFSET + i;
++ if (*(p + eccpos) != (char)0xff)
++ break;
++ else if (*(p + eccpos + qsz) != (char)0xff)
++ break;
++ else if (*(p + eccpos + qsz*2) != (char)0xff)
++ break;
++ else if (*(p + eccpos + qsz*3) != (char)0xff)
++ break;
++ if (i == CONFIG_ECC_BYTES - 1) {
++ printk("skip ecc 0xff at page %x\n", page);
++ return 0;
++ }
++ }
++ for (i=0; i<CONFIG_ECC_BYTES; i++) {
++ int eccpos = CONFIG_ECC_OFFSET + i;
++ if (*(p + eccpos) != *(e + i)) {
++ printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
++ __func__, (mode == FL_READING)?"read":"write", page,
++ *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
++ correction_flag |= 0x1;
++ }
++ if (*(p + eccpos + qsz) != *(e2 + i)) {
++ printk("%s mode:%s, invalid ecc2, page: %x read:%x %x %x, ecc2:%x \n",
++ __func__, (mode == FL_READING)?"read":"write", page,
++ *(p+CONFIG_ECC_OFFSET+qsz), *(p+ CONFIG_ECC_OFFSET+1+qsz), *(p+ CONFIG_ECC_OFFSET+2+qsz), ecc2);
++ correction_flag |= 0x2;
++ }
++ if (*(p + eccpos + qsz*2) != *(e3 + i)) {
++ printk("%s mode:%s, invalid ecc3, page: %x read:%x %x %x, ecc3:%x \n",
++ __func__, (mode == FL_READING)?"read":"write", page,
++ *(p+CONFIG_ECC_OFFSET+qsz*2), *(p+ CONFIG_ECC_OFFSET+1+qsz*2), *(p+ CONFIG_ECC_OFFSET+2+qsz*2), ecc3);
++ correction_flag |= 0x4;
++ }
++ if (*(p + eccpos + qsz*3) != *(e4 + i)) {
++ printk("%s mode:%s, invalid ecc4, page: %x read:%x %x %x, ecc4:%x \n",
++ __func__, (mode == FL_READING)?"read":"write", page,
++ *(p+CONFIG_ECC_OFFSET+qsz*3), *(p+ CONFIG_ECC_OFFSET+1+qsz*3), *(p+ CONFIG_ECC_OFFSET+2+qsz*3), ecc4);
++ correction_flag |= 0x8;
++ }
++ }
++
++ if (correction_flag)
++ {
++ printk("trying to do correction!\n");
++ if (correction_flag & 0x1)
++ {
++ int bytes, bits;
++ char *pBuf = p - CFG_PAGESIZE;
++
++ if (one_bit_correction(p + CONFIG_ECC_OFFSET, e, &bytes, &bits) == 0)
++ {
++ pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
++ printk("1. correct byte %d, bit %d!\n", bytes, bits);
++ }
++ else
++ {
++ printk("failed to correct!\n");
++ return -1;
++ }
++ }
++
++ if (correction_flag & 0x2)
++ {
++ int bytes, bits;
++ char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/4;
++
++ if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz), e2, &bytes, &bits) == 0)
++ {
++ pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
++ printk("2. correct byte %d, bit %d!\n", bytes, bits);
++ }
++ else
++ {
++ printk("failed to correct!\n");
++ return -1;
++ }
++ }
++ if (correction_flag & 0x4)
++ {
++ int bytes, bits;
++ char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/2;
++
++ if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 2), e3, &bytes, &bits) == 0)
++ {
++ pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
++ printk("3. correct byte %d, bit %d!\n", bytes, bits);
++ }
++ else
++ {
++ printk("failed to correct!\n");
++ return -1;
++ }
++ }
++ if (correction_flag & 0x8)
++ {
++ int bytes, bits;
++ char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE*3/4;
++
++ if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 3), e4, &bytes, &bits) == 0)
++ {
++ pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
++ printk("4. correct byte %d, bit %d!\n", bytes, bits);
++ }
++ else
++ {
++ printk("failed to correct!\n");
++ return -1;
++ }
++ }
++ }
++
++ }
++#endif
++ return 0;
++
++bad_block:
++ return -1;
++}
++
++#else
++
++void ranfc_dump(void)
++{
++ int i;
++ for (i=0; i<11; i++) {
++ if (i==6)
++ continue;
++ printk("%x: %x \n", NFC_BASE + i*4, ra_inl(NFC_BASE + i*4));
++ }
++}
++
++/**
++ * @return 0, ecc OK or corrected.
++ * @return NAND_STATUS_FAIL, ecc fail.
++ */
++
++int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
++{
++ int ret, i;
++ char *p, *e;
++ int ecc;
++
++ if (ranfc_verify == 0)
++ return 0;
++
++ ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
++
++ if (mode == FL_WRITING) { // read back and memcmp
++ ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
++ if (ret != 0) //double comfirm
++ ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
++
++ if (ret != 0) {
++ printk("%s: mode:%x read back fail \n", __func__, mode);
++ return -1;
++ }
++ return memcmp(buf, ra->readback_buffers, 1<<ra->page_shift);
++ }
++
++ if (mode == FL_READING) {
++#if 0
++ if (ra->sandbox_page == 0)
++ return 0;
++
++ ret = nfc_write_page(ra, buf, ra->sandbox_page, FLAG_USE_GDMA | FLAG_ECC_EN);
++ if (ret != 0) {
++ printk("%s, fail write sandbox_page \n", __func__);
++ return -1;
++ }
++#else
++ /** @note:
++ * The following command is actually not 'write' command to drive NFC to write flash.
++ * However, it can make NFC to calculate ECC, that will be used to compare with original ones.
++ * --YT
++ */
++ unsigned int conf = 0x001223| (CFG_ADDR_CYCLE<<16) | (0x200 << 20) | (1<<3) | (1<<2);
++ _nfc_write_raw_data(0xff, 0xff, ra->sandbox_page<<ra->page_shift, conf, buf, 0x200, FLAG_USE_GDMA);
++#endif
++
++ ecc = ra_inl(NFC_ECC);
++ if (ecc == 0) //clean page.
++ return 0;
++ e = (char*)&ecc;
++ p = buf + (1<<ra->page_shift);
++ for (i=0; i<CONFIG_ECC_BYTES; i++) {
++ int eccpos = CONFIG_ECC_OFFSET + i;
++ if (*(p + eccpos) != *(e + i)) {
++ printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, write:%x \n",
++ __func__, (mode == FL_READING)?"read":"write", page,
++ *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
++
++ for (i=0; i<528; i++)
++ printk("%-2x \n", *(buf + i));
++ return -1;
++ }
++ }
++ return 0;
++ }
++
++ return -1;
++
++}
++
++#endif
++
++
++/**
++ * @return -EIO, writing size is less than a page
++ * @return 0, OK
++ */
++int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
++{
++ unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
++ unsigned int bus_addr = 0, bus_addr2 = 0;
++ unsigned int ecc_en;
++ int use_gdma;
++ int size, offs;
++ int status = 0;
++
++ use_gdma = flags & FLAG_USE_GDMA;
++ ecc_en = flags & FLAG_ECC_EN;
++
++ page = page & (CFG_CHIPSIZE - 1); // chip boundary
++ size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
++ offs = 0;
++
++ while (size > 0) {
++ int len;
++#if defined (WORKAROUND_RX_BUF_OV)
++ len = min(60, size);
++#else
++ len = size;
++#endif
++ bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8)-1));
++ if (is_nand_page_2048) {
++ bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
++ cmd1 = 0x0;
++ cmd2 = 0x30;
++ conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
++ }
++ else {
++ if (offs & ~(CFG_PAGESIZE-1))
++ cmd1 = 0x50;
++ else if (offs & ~((1<<CFG_COLUMN_ADDR_CYCLE*8)-1))
++ cmd1 = 0x01;
++ else
++ cmd1 = 0;
++
++ conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
++ }
++#if !defined (WORKAROUND_RX_BUF_OV)
++ if (ecc_en)
++ conf |= (1<<3);
++#endif
++ if (use_gdma)
++ conf |= (1<<2);
++
++ status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf+offs, len, flags);
++ if (status & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ return -EIO;
++ }
++
++ offs += len;
++ size -= len;
++ }
++
++ // verify and correct ecc
++ if ((flags & (FLAG_VERIFY | FLAG_ECC_EN)) == (FLAG_VERIFY | FLAG_ECC_EN)) {
++ status = nfc_ecc_verify(ra, buf, page, FL_READING);
++ if (status != 0) {
++ printk("%s: fail, buf:%x, page:%x, flag:%x\n",
++ __func__, (unsigned int)buf, page, flags);
++ return -EBADMSG;
++ }
++ }
++ else {
++ // fix,e not yet support
++ ra->buffers_page = -1; //cached
++ }
++
++ return 0;
++}
++
++
++/**
++ * @return -EIO, fail to write
++ * @return 0, OK
++ */
++int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
++{
++ unsigned int cmd1 = 0, cmd3, conf = 0;
++ unsigned int bus_addr = 0, bus_addr2 = 0;
++ unsigned int ecc_en;
++ int use_gdma;
++ int size;
++ char status;
++ uint8_t *oob = buf + (1<<ra->page_shift);
++
++ use_gdma = flags & FLAG_USE_GDMA;
++ ecc_en = flags & FLAG_ECC_EN;
++
++ oob[ra->badblockpos] = 0xff; //tag as good block.
++ ra->buffers_page = -1; //cached
++
++ page = page & (CFG_CHIPSIZE-1); //chip boundary
++ size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
++ bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)); //write_page always write from offset 0.
++
++ if (is_nand_page_2048) {
++ bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
++ cmd1 = 0x80;
++ cmd3 = 0x10;
++ conf = 0x001123| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
++ }
++ else {
++ cmd1 = 0x8000;
++ cmd3 = 0x10;
++ conf = 0x001223| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
++}
++ if (ecc_en)
++ conf |= (1<<3); //enable ecc
++ if (use_gdma)
++ conf |= (1<<2);
++
++ // set NFC
++ ra_dbg("nfc_write_page: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
++ cmd1, cmd3, bus_addr, conf, size);
++
++ status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
++ if (status & NAND_STATUS_FAIL) {
++ printk("%s: fail \n", __func__);
++ return -EIO;
++ }
++
++
++ if (flags & FLAG_VERIFY) { // verify and correct ecc
++ status = nfc_ecc_verify(ra, buf, page, FL_WRITING);
++
++#ifdef RANDOM_GEN_BAD_BLOCK
++ if (((random32() & 0x1ff) == 0x0) && (page >= 0x100)) // randomly create bad block
++ {
++ printk("hmm... create a bad block at page %x\n", (bus_addr >> 16));
++ status = -1;
++ }
++#endif
++
++ if (status != 0) {
++ printk("%s: ecc_verify fail: ret:%x \n", __func__, status);
++ oob[ra->badblockpos] = 0x33;
++ page -= page % (CFG_BLOCKSIZE/CFG_PAGESIZE);
++ printk("create a bad block at page %x\n", page);
++ if (!is_nand_page_2048)
++ status = nfc_write_oob(ra, page, ra->badblockpos, oob+ra->badblockpos, 1, flags);
++ else
++ {
++ status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
++ nfc_write_oob(ra, page, 0, oob, 16, FLAG_NONE);
++ }
++ return -EBADMSG;
++ }
++ }
++
++
++ ra->buffers_page = page; //cached
++ return 0;
++}
++
++
++
++/*************************************************************
++ * nand internal process
++ *************************************************************/
++
++/**
++ * nand_release_device - [GENERIC] release chip
++ * @mtd: MTD device structure
++ *
++ * Deselect, release chip lock and wake up anyone waiting on the device
++ */
++static void nand_release_device(struct ra_nand_chip *ra)
++{
++ /* De-select the NAND device */
++ nfc_select_chip(ra, -1);
++
++ /* Release the controller and the chip */
++ ra->state = FL_READY;
++
++ mutex_unlock(ra->controller);
++}
++
++/**
++ * nand_get_device - [GENERIC] Get chip for selected access
++ * @chip: the nand chip descriptor
++ * @mtd: MTD device structure
++ * @new_state: the state which is requested
++ *
++ * Get the device and lock it for exclusive access
++ */
++static int
++nand_get_device(struct ra_nand_chip *ra, int new_state)
++{
++ int ret = 0;
++
++ ret = mutex_lock_interruptible(ra->controller);
++ if (!ret)
++ ra->state = new_state;
++
++ return ret;
++
++}
++
++
++
++/*************************************************************
++ * nand internal process
++ *************************************************************/
++
++int nand_bbt_get(struct ra_nand_chip *ra, int block)
++{
++ int byte, bits;
++ bits = block * BBTTAG_BITS;
++
++ byte = bits / 8;
++ bits = bits % 8;
++
++ return (ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK;
++}
++
++int nand_bbt_set(struct ra_nand_chip *ra, int block, int tag)
++{
++ int byte, bits;
++ bits = block * BBTTAG_BITS;
++
++ byte = bits / 8;
++ bits = bits % 8;
++
++ // If previous tag is bad, dont overwrite it
++ if (((ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK) == BBT_TAG_BAD)
++ {
++ return BBT_TAG_BAD;
++ }
++
++ ra->bbt[byte] = (ra->bbt[byte] & ~(BBTTAG_BITS_MASK << bits)) | ((tag & BBTTAG_BITS_MASK) << bits);
++
++ return tag;
++}
++
++/**
++ * nand_block_checkbad - [GENERIC] Check if a block is marked bad
++ * @mtd: MTD device structure
++ * @ofs: offset from device start
++ *
++ * Check, if the block is bad. Either by reading the bad block table or
++ * calling of the scan function.
++ */
++int nand_block_checkbad(struct ra_nand_chip *ra, loff_t offs)
++{
++ int page, block;
++ int ret = 4;
++ unsigned int tag;
++ char *str[]= {"UNK", "RES", "BAD", "GOOD"};
++
++ if (ranfc_bbt == 0)
++ return 0;
++
++ {
++ // align with chip
++
++ offs = offs & ((1<<ra->chip_shift) -1);
++
++ page = offs >> ra->page_shift;
++ block = offs >> ra->erase_shift;
++ }
++
++ tag = nand_bbt_get(ra, block);
++
++ if (tag == BBT_TAG_UNKNOWN) {
++ ret = nfc_read_oob(ra, page, ra->badblockpos, (char*)&tag, 1, FLAG_NONE);
++ if (ret == 0)
++ tag = ((le32_to_cpu(tag) & 0x0ff) == 0x0ff) ? BBT_TAG_GOOD : BBT_TAG_BAD;
++ else
++ tag = BBT_TAG_BAD;
++
++ nand_bbt_set(ra, block, tag);
++ }
++
++ if (tag != BBT_TAG_GOOD) {
++ printk("%s: offs:%x tag: %s \n", __func__, (unsigned int)offs, str[tag]);
++ return 1;
++ }
++ else
++ return 0;
++
++}
++
++
++
++/**
++ * nand_block_markbad -
++ */
++int nand_block_markbad(struct ra_nand_chip *ra, loff_t offs)
++{
++ int page, block;
++ int ret = 4;
++ unsigned int tag;
++ char *ecc;
++
++ // align with chip
++ ra_dbg("%s offs: %x \n", __func__, (int)offs);
++
++ offs = offs & ((1<<ra->chip_shift) -1);
++
++ page = offs >> ra->page_shift;
++ block = offs >> ra->erase_shift;
++
++ tag = nand_bbt_get(ra, block);
++
++ if (tag == BBT_TAG_BAD) {
++ printk("%s: mark repeatedly \n", __func__);
++ return 0;
++ }
++
++ // new tag as bad
++ tag =BBT_TAG_BAD;
++ ret = nfc_read_page(ra, ra->buffers, page, FLAG_NONE);
++ if (ret != 0) {
++ printk("%s: fail to read bad block tag \n", __func__);
++ goto tag_bbt;
++ }
++
++ ecc = &ra->buffers[(1<<ra->page_shift)+ra->badblockpos];
++ if (*ecc == (char)0x0ff) {
++ //tag into flash
++ *ecc = (char)tag;
++ ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA);
++ if (ret)
++ printk("%s: fail to write bad block tag \n", __func__);
++
++ }
++
++tag_bbt:
++ //update bbt
++ nand_bbt_set(ra, block, tag);
++
++ return 0;
++}
++
++
++#if defined (WORKAROUND_RX_BUF_OV)
++/**
++ * to find a bad block for ecc verify of read_page
++ */
++unsigned int nand_bbt_find_sandbox(struct ra_nand_chip *ra)
++{
++ loff_t offs = 0;
++ int chipsize = 1 << ra->chip_shift;
++ int blocksize = 1 << ra->erase_shift;
++
++
++ while (offs < chipsize) {
++ if (nand_block_checkbad(ra, offs)) //scan and verify the unknown tag
++ break;
++ offs += blocksize;
++ }
++
++ if (offs >= chipsize) {
++ offs = chipsize - blocksize;
++ }
++
++ nand_bbt_set(ra, (unsigned int)offs>>ra->erase_shift, BBT_TAG_RES); // tag bbt only, instead of update badblockpos of flash.
++ return (offs >> ra->page_shift);
++}
++#endif
++
++
++
++/**
++ * nand_erase_nand - [Internal] erase block(s)
++ * @mtd: MTD device structure
++ * @instr: erase instruction
++ * @allowbbt: allow erasing the bbt area
++ *
++ * Erase one ore more blocks
++ */
++int _nand_erase_nand(struct ra_nand_chip *ra, struct erase_info *instr)
++{
++ int page, len, status, ret;
++ unsigned int addr, blocksize = 1<<ra->erase_shift;
++
++ ra_dbg("%s: start:%x, len:%x \n", __func__,
++ (unsigned int)instr->addr, (unsigned int)instr->len);
++
++//#define BLOCK_ALIGNED(a) ((a) & (blocksize - 1)) // already defined
++
++ if (BLOCK_ALIGNED(instr->addr) || BLOCK_ALIGNED(instr->len)) {
++ ra_dbg("%s: erase block not aligned, addr:%x len:%x\n", __func__, instr->addr, instr->len);
++ return -EINVAL;
++ }
++
++ instr->fail_addr = 0xffffffff;
++
++ len = instr->len;
++ addr = instr->addr;
++ instr->state = MTD_ERASING;
++
++ while (len) {
++
++ page = (int)(addr >> ra->page_shift);
++
++ /* select device and check wp */
++ if (nfc_enable_chip(ra, addr, 0)) {
++ printk("%s: nand is write protected \n", __func__);
++ instr->state = MTD_ERASE_FAILED;
++ goto erase_exit;
++ }
++
++ /* if we have a bad block, we do not erase bad blocks */
++ if (nand_block_checkbad(ra, addr)) {
++ printk(KERN_WARNING "nand_erase: attempt to erase a "
++ "bad block at 0x%08x\n", addr);
++ instr->state = MTD_ERASE_FAILED;
++ goto erase_exit;
++ }
++
++ /*
++ * Invalidate the page cache, if we erase the block which
++ * contains the current cached page
++ */
++ if (BLOCK_ALIGNED(addr) == BLOCK_ALIGNED(ra->buffers_page << ra->page_shift))
++ ra->buffers_page = -1;
++
++ status = nfc_erase_block(ra, page);
++ /* See if block erase succeeded */
++ if (status) {
++ printk("%s: failed erase, page 0x%08x\n", __func__, page);
++ instr->state = MTD_ERASE_FAILED;
++ instr->fail_addr = (page << ra->page_shift);
++ goto erase_exit;
++ }
++
++
++ /* Increment page address and decrement length */
++ len -= blocksize;
++ addr += blocksize;
++
++ }
++ instr->state = MTD_ERASE_DONE;
++
++erase_exit:
++
++ ret = ((instr->state == MTD_ERASE_DONE) ? 0 : -EIO);
++ /* Do call back function */
++ if (!ret)
++ mtd_erase_callback(instr);
++
++ if (ret) {
++ nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
++ }
++
++ /* Return more or less happy */
++ return ret;
++}
++
++static int
++nand_write_oob_buf(struct ra_nand_chip *ra, uint8_t *buf, uint8_t *oob, size_t size,
++ int mode, int ooboffs)
++{
++ size_t oobsize = 1<<ra->oob_shift;
++ struct nand_oobfree *free;
++ uint32_t woffs = ooboffs;
++ int retsize = 0;
++
++ ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
++
++ switch(mode) {
++ case MTD_OPS_PLACE_OOB:
++ case MTD_OPS_RAW:
++ if (ooboffs > oobsize)
++ return -1;
++
++ size = min(size, oobsize - ooboffs);
++ memcpy(buf + ooboffs, oob, size);
++ retsize = size;
++ break;
++
++ case MTD_OPS_AUTO_OOB:
++ if (ooboffs > ra->oob->oobavail)
++ return -1;
++
++ while (size) {
++ for(free = ra->oob->oobfree; free->length && size; free++) {
++ int wlen = free->length - woffs;
++ int bytes = 0;
++
++ /* Write request not from offset 0 ? */
++ if (wlen <= 0) {
++ woffs = -wlen;
++ continue;
++ }
++
++ bytes = min_t(size_t, size, wlen);
++ memcpy (buf + free->offset + woffs, oob, bytes);
++ woffs = 0;
++ oob += bytes;
++ size -= bytes;
++ retsize += bytes;
++ }
++ buf += oobsize;
++ }
++ break;
++
++ default:
++ BUG();
++ }
++
++ return retsize;
++}
++
++static int nand_read_oob_buf(struct ra_nand_chip *ra, uint8_t *oob, size_t size,
++ int mode, int ooboffs)
++{
++ size_t oobsize = 1<<ra->oob_shift;
++ uint8_t *buf = ra->buffers + (1<<ra->page_shift);
++ int retsize=0;
++
++ ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
++
++ switch(mode) {
++ case MTD_OPS_PLACE_OOB:
++ case MTD_OPS_RAW:
++ if (ooboffs > oobsize)
++ return -1;
++
++ size = min(size, oobsize - ooboffs);
++ memcpy(oob, buf + ooboffs, size);
++ return size;
++
++ case MTD_OPS_AUTO_OOB: {
++ struct nand_oobfree *free;
++ uint32_t woffs = ooboffs;
++
++ if (ooboffs > ra->oob->oobavail)
++ return -1;
++
++ size = min(size, ra->oob->oobavail - ooboffs);
++ for(free = ra->oob->oobfree; free->length && size; free++) {
++ int wlen = free->length - woffs;
++ int bytes = 0;
++
++ /* Write request not from offset 0 ? */
++ if (wlen <= 0) {
++ woffs = -wlen;
++ continue;
++ }
++
++ bytes = min_t(size_t, size, wlen);
++ memcpy (oob, buf + free->offset + woffs, bytes);
++ woffs = 0;
++ oob += bytes;
++ size -= bytes;
++ retsize += bytes;
++ }
++ return retsize;
++ }
++ default:
++ BUG();
++ }
++
++ return -1;
++}
++
++/**
++ * nand_do_write_ops - [Internal] NAND write with ECC
++ * @mtd: MTD device structure
++ * @to: offset to write to
++ * @ops: oob operations description structure
++ *
++ * NAND write with ECC
++ */
++static int nand_do_write_ops(struct ra_nand_chip *ra, loff_t to,
++ struct mtd_oob_ops *ops)
++{
++ int page;
++ uint32_t datalen = ops->len;
++ uint32_t ooblen = ops->ooblen;
++ uint8_t *oob = ops->oobbuf;
++ uint8_t *data = ops->datbuf;
++ int pagesize = (1<<ra->page_shift);
++ int pagemask = (pagesize -1);
++ int oobsize = 1<<ra->oob_shift;
++ loff_t addr = to;
++ //int i = 0; //for ra_dbg only
++
++ ra_dbg("%s: to:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x oobmode:%x \n",
++ __func__, (unsigned int)to, data, oob, datalen, ooblen, ops->ooboffs, ops->mode);
++
++ ops->retlen = 0;
++ ops->oobretlen = 0;
++
++
++ /* Invalidate the page cache, when we write to the cached page */
++ ra->buffers_page = -1;
++
++
++ if (data ==0)
++ datalen = 0;
++
++ // oob sequential (burst) write
++ if (datalen == 0 && ooblen) {
++ int len = ((ooblen + ops->ooboffs) + (ra->oob->oobavail - 1)) / ra->oob->oobavail * oobsize;
++
++ /* select chip, and check if it is write protected */
++ if (nfc_enable_chip(ra, addr, 0))
++ return -EIO;
++
++ //FIXME, need sanity check of block boundary
++ page = (int)((to & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
++ memset(ra->buffers, 0x0ff, pagesize);
++ //fixme, should we reserve the original content?
++ if (ops->mode == MTD_OPS_AUTO_OOB) {
++ nfc_read_oob(ra, page, 0, ra->buffers, len, FLAG_NONE);
++ }
++ //prepare buffers
++ if (ooblen != 8)
++ {
++ nand_write_oob_buf(ra, ra->buffers, oob, ooblen, ops->mode, ops->ooboffs);
++ // write out buffer to chip
++ nfc_write_oob(ra, page, 0, ra->buffers, len, FLAG_USE_GDMA);
++ }
++
++ ops->oobretlen = ooblen;
++ ooblen = 0;
++ }
++
++ // data sequential (burst) write
++ if (datalen && ooblen == 0) {
++ // ranfc can not support write_data_burst, since hw-ecc and fifo constraints..
++ }
++
++ // page write
++ while(datalen || ooblen) {
++ int len;
++ int ret;
++ int offs;
++ int ecc_en = 0;
++
++ ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
++ __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
++
++ page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
++
++ /* select chip, and check if it is write protected */
++ if (nfc_enable_chip(ra, addr, 0))
++ return -EIO;
++
++ // oob write
++ if (ops->mode == MTD_OPS_AUTO_OOB) {
++ //fixme, this path is not yet varified
++ nfc_read_oob(ra, page, 0, ra->buffers + pagesize, oobsize, FLAG_NONE);
++ }
++ if (oob && ooblen > 0) {
++ len = nand_write_oob_buf(ra, ra->buffers + pagesize, oob, ooblen, ops->mode, ops->ooboffs);
++ if (len < 0)
++ return -EINVAL;
++
++ oob += len;
++ ops->oobretlen += len;
++ ooblen -= len;
++ }
++
++ // data write
++ offs = addr & pagemask;
++ len = min_t(size_t, datalen, pagesize - offs);
++ if (data && len > 0) {
++ memcpy(ra->buffers + offs, data, len); // we can not sure ops->buf wether is DMA-able.
++
++ data += len;
++ datalen -= len;
++ ops->retlen += len;
++
++ ecc_en = FLAG_ECC_EN;
++ }
++ ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA | FLAG_VERIFY |
++ ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0 : ecc_en ));
++ if (ret) {
++ nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
++ return ret;
++ }
++
++ nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
++
++ addr = (page+1) << ra->page_shift;
++
++ }
++ return 0;
++}
++
++/**
++ * nand_do_read_ops - [Internal] Read data with ECC
++ *
++ * @mtd: MTD device structure
++ * @from: offset to read from
++ * @ops: oob ops structure
++ *
++ * Internal function. Called with chip held.
++ */
++static int nand_do_read_ops(struct ra_nand_chip *ra, loff_t from,
++ struct mtd_oob_ops *ops)
++{
++ int page;
++ uint32_t datalen = ops->len;
++ uint32_t ooblen = ops->ooblen;
++ uint8_t *oob = ops->oobbuf;
++ uint8_t *data = ops->datbuf;
++ int pagesize = (1<<ra->page_shift);
++ int pagemask = (pagesize -1);
++ loff_t addr = from;
++ //int i = 0; //for ra_dbg only
++
++ ra_dbg("%s: addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
++ __func__, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
++
++ ops->retlen = 0;
++ ops->oobretlen = 0;
++ if (data == 0)
++ datalen = 0;
++
++
++ while(datalen || ooblen) {
++ int len;
++ int ret;
++ int offs;
++
++ ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
++ __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
++ /* select chip */
++ if (nfc_enable_chip(ra, addr, 1) < 0)
++ return -EIO;
++
++ page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift);
++
++ ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
++ ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
++ //FIXME, something strange here, some page needs 2 more tries to guarantee read success.
++ if (ret) {
++ printk("read again:\n");
++ ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
++ ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
++
++ if (ret) {
++ printk("read again fail \n");
++ nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
++ if ((ret != -EUCLEAN) && (ret != -EBADMSG)) {
++ return ret;
++ }
++ else {
++ /* ecc verification fail, but data need to be returned. */
++ }
++ }
++ else {
++ printk(" read agian susccess \n");
++ }
++ }
++
++ // oob read
++ if (oob && ooblen > 0) {
++ len = nand_read_oob_buf(ra, oob, ooblen, ops->mode, ops->ooboffs);
++ if (len < 0) {
++ printk("nand_read_oob_buf: fail return %x \n", len);
++ return -EINVAL;
++ }
++
++ oob += len;
++ ops->oobretlen += len;
++ ooblen -= len;
++ }
++
++ // data read
++ offs = addr & pagemask;
++ len = min_t(size_t, datalen, pagesize - offs);
++ if (data && len > 0) {
++ memcpy(data, ra->buffers + offs, len); // we can not sure ops->buf wether is DMA-able.
++
++ data += len;
++ datalen -= len;
++ ops->retlen += len;
++ if (ret)
++ return ret;
++ }
++
++
++ nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
++ // address go further to next page, instead of increasing of length of write. This avoids some special cases wrong.
++ addr = (page+1) << ra->page_shift;
++ }
++ return 0;
++}
++
++static int
++ramtd_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++ struct ra_nand_chip *ra = (struct ra_nand_chip *)mtd->priv;
++ int ret;
++
++ ra_dbg("%s: start:%x, len:%x \n", __func__,
++ (unsigned int)instr->addr, (unsigned int)instr->len);
++
++ nand_get_device(ra, FL_ERASING);
++ ret = _nand_erase_nand((struct ra_nand_chip *)mtd->priv, instr);
++ nand_release_device(ra);
++
++ return ret;
++}
++
++static int
++ramtd_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
++ size_t *retlen, const uint8_t *buf)
++{
++ struct ra_nand_chip *ra = mtd->priv;
++ struct mtd_oob_ops ops;
++ int ret;
++
++ ra_dbg("%s: to 0x%x len=0x%x\n", __func__, to, len);
++
++ if ((to + len) > mtd->size)
++ return -EINVAL;
++
++ if (!len)
++ return 0;
++
++ nand_get_device(ra, FL_WRITING);
++
++ memset(&ops, 0, sizeof(ops));
++ ops.len = len;
++ ops.datbuf = (uint8_t *)buf;
++ ops.oobbuf = NULL;
++ ops.mode = MTD_OPS_AUTO_OOB;
++
++ ret = nand_do_write_ops(ra, to, &ops);
++
++ *retlen = ops.retlen;
++
++ nand_release_device(ra);
++
++ return ret;
++}
++
++static int
++ramtd_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
++ size_t *retlen, uint8_t *buf)
++{
++
++ struct ra_nand_chip *ra = mtd->priv;
++ int ret;
++ struct mtd_oob_ops ops;
++
++ ra_dbg("%s: mtd:%p from:%x, len:%x, buf:%p \n", __func__, mtd, (unsigned int)from, len, buf);
++
++ /* Do not allow reads past end of device */
++ if ((from + len) > mtd->size)
++ return -EINVAL;
++ if (!len)
++ return 0;
++
++ nand_get_device(ra, FL_READING);
++
++ memset(&ops, 0, sizeof(ops));
++ ops.len = len;
++ ops.datbuf = buf;
++ ops.oobbuf = NULL;
++ ops.mode = MTD_OPS_AUTO_OOB;
++
++ ret = nand_do_read_ops(ra, from, &ops);
++
++ *retlen = ops.retlen;
++
++ nand_release_device(ra);
++
++ return ret;
++
++}
++
++static int
++ramtd_nand_readoob(struct mtd_info *mtd, loff_t from,
++ struct mtd_oob_ops *ops)
++{
++ struct ra_nand_chip *ra = mtd->priv;
++ int ret;
++
++ ra_dbg("%s: \n", __func__);
++
++ nand_get_device(ra, FL_READING);
++
++ ret = nand_do_read_ops(ra, from, ops);
++
++ nand_release_device(ra);
++
++ return ret;
++}
++
++static int
++ramtd_nand_writeoob(struct mtd_info *mtd, loff_t to,
++ struct mtd_oob_ops *ops)
++{
++ struct ra_nand_chip *ra = mtd->priv;
++ int ret;
++
++ nand_get_device(ra, FL_READING);
++ ret = nand_do_write_ops(ra, to, ops);
++ nand_release_device(ra);
++
++ return ret;
++}
++
++static int
++ramtd_nand_block_isbad(struct mtd_info *mtd, loff_t offs)
++{
++ if (offs > mtd->size)
++ return -EINVAL;
++
++ return nand_block_checkbad((struct ra_nand_chip *)mtd->priv, offs);
++}
++
++static int
++ramtd_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct ra_nand_chip *ra = mtd->priv;
++ int ret;
++
++ ra_dbg("%s: \n", __func__);
++ nand_get_device(ra, FL_WRITING);
++ ret = nand_block_markbad(ra, ofs);
++ nand_release_device(ra);
++
++ return ret;
++}
++
++// 1-bit error detection
++static int one_bit_correction(char *ecc1, char *ecc2, int *bytes, int *bits)
++{
++ // check if ecc and expected are all valid
++ char *p, nibble, crumb;
++ int i, xor, iecc1 = 0, iecc2 = 0;
++
++ printk("correction : %x %x %x\n", ecc1[0], ecc1[1], ecc1[2]);
++ printk("correction : %x %x %x\n", ecc2[0], ecc2[1], ecc2[2]);
++
++ p = (char *)ecc1;
++ for (i = 0; i < CONFIG_ECC_BYTES; i++)
++ {
++ nibble = *(p+i) & 0xf;
++ if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
++ (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
++ return -1;
++ nibble = ((*(p+i)) >> 4) & 0xf;
++ if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
++ (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
++ return -1;
++ }
++
++ p = (char *)ecc2;
++ for (i = 0; i < CONFIG_ECC_BYTES; i++)
++ {
++ nibble = *(p+i) & 0xf;
++ if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
++ (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
++ return -1;
++ nibble = ((*(p+i)) >> 4) & 0xf;
++ if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
++ (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
++ return -1;
++ }
++
++ memcpy(&iecc1, ecc1, 3);
++ memcpy(&iecc2, ecc2, 3);
++
++ xor = iecc1 ^ iecc2;
++ printk("xor = %x (%x %x)\n", xor, iecc1, iecc2);
++
++ *bytes = 0;
++ for (i = 0; i < 9; i++)
++ {
++ crumb = (xor >> (2*i)) & 0x3;
++ if ((crumb == 0x0) || (crumb == 0x3))
++ return -1;
++ if (crumb == 0x2)
++ *bytes += (1 << i);
++ }
++
++ *bits = 0;
++ for (i = 0; i < 3; i++)
++ {
++ crumb = (xor >> (18 + 2*i)) & 0x3;
++ if ((crumb == 0x0) || (crumb == 0x3))
++ return -1;
++ if (crumb == 0x2)
++ *bits += (1 << i);
++ }
++
++ return 0;
++}
++
++
++
++/************************************************************
++ * the init/exit section.
++ */
++
++static struct nand_ecclayout ra_oob_layout = {
++ .eccbytes = CONFIG_ECC_BYTES,
++ .eccpos = {5, 6, 7},
++ .oobfree = {
++ {.offset = 0, .length = 4},
++ {.offset = 8, .length = 8},
++ {.offset = 0, .length = 0}
++ },
++#define RA_CHIP_OOB_AVAIL (4+8)
++ .oobavail = RA_CHIP_OOB_AVAIL,
++ // 5th byte is bad-block flag.
++};
++
++static int
++mtk_nand_probe(struct platform_device *pdev)
++{
++ struct mtd_part_parser_data ppdata;
++ struct ra_nand_chip *ra;
++ int alloc_size, bbt_size, buffers_size, reg, err;
++ unsigned char chip_mode = 12;
++
++/* if(ra_check_flash_type()!=BOOT_FROM_NAND) {
++ return 0;
++ }*/
++
++ //FIXME: config 512 or 2048-byte page according to HWCONF
++#if defined (CONFIG_RALINK_RT6855A)
++ reg = ra_inl(RALINK_SYSCTL_BASE+0x8c);
++ chip_mode = ((reg>>28) & 0x3)|(((reg>>22) & 0x3)<<2);
++ if (chip_mode == 1) {
++ printk("! nand 2048\n");
++ ra_or(NFC_CONF1, 1);
++ is_nand_page_2048 = 1;
++ nand_addrlen = 5;
++ }
++ else {
++ printk("! nand 512\n");
++ ra_and(NFC_CONF1, ~1);
++ is_nand_page_2048 = 0;
++ nand_addrlen = 4;
++ }
++#elif (defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855))
++ ra_outl(RALINK_SYSCTL_BASE+0x60, ra_inl(RALINK_SYSCTL_BASE+0x60) & ~(0x3<<18));
++ reg = ra_inl(RALINK_SYSCTL_BASE+0x10);
++ chip_mode = (reg & 0x0F);
++ if((chip_mode==1)||(chip_mode==11)) {
++ ra_or(NFC_CONF1, 1);
++ is_nand_page_2048 = 1;
++ nand_addrlen = ((chip_mode!=11) ? 4 : 5);
++ printk("!!! nand page size = 2048, addr len=%d\n", nand_addrlen);
++ }
++ else {
++ ra_and(NFC_CONF1, ~1);
++ is_nand_page_2048 = 0;
++ nand_addrlen = ((chip_mode!=10) ? 3 : 4);
++ printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
++ }
++#else
++ is_nand_page_2048 = 0;
++ nand_addrlen = 3;
++ printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
++#endif
++
++#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855)
++ //config ECC location
++ ra_and(NFC_CONF1, 0xfff000ff);
++ ra_or(NFC_CONF1, ((CONFIG_ECC_OFFSET + 2) << 16) +
++ ((CONFIG_ECC_OFFSET + 1) << 12) +
++ (CONFIG_ECC_OFFSET << 8));
++#endif
++
++#define ALIGNE_16(a) (((unsigned long)(a)+15) & ~15)
++ buffers_size = ALIGNE_16((1<<CONFIG_PAGE_SIZE_BIT) + (1<<CONFIG_OOBSIZE_PER_PAGE_BIT)); //ra->buffers
++ bbt_size = BBTTAG_BITS * (1<<(CONFIG_CHIP_SIZE_BIT - (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))) / 8; //ra->bbt
++ bbt_size = ALIGNE_16(bbt_size);
++
++ alloc_size = buffers_size + bbt_size;
++ alloc_size += buffers_size; //for ra->readback_buffers
++ alloc_size += sizeof(*ra);
++ alloc_size += sizeof(*ranfc_mtd);
++
++ //make sure gpio-0 is input
++ ra_outl(RALINK_PIO_BASE+0x24, ra_inl(RALINK_PIO_BASE+0x24) & ~0x01);
++
++ ra = (struct ra_nand_chip *)kzalloc(alloc_size, GFP_KERNEL | GFP_DMA);
++ if (!ra) {
++ printk("%s: mem alloc fail \n", __func__);
++ return -ENOMEM;
++ }
++ memset(ra, 0, alloc_size);
++
++ //dynamic
++ ra->buffers = (char *)((char *)ra + sizeof(*ra));
++ ra->readback_buffers = ra->buffers + buffers_size;
++ ra->bbt = ra->readback_buffers + buffers_size;
++ ranfc_mtd = (struct mtd_info *)(ra->bbt + bbt_size);
++
++ //static
++ ra->numchips = CONFIG_NUMCHIPS;
++ ra->chip_shift = CONFIG_CHIP_SIZE_BIT;
++ ra->page_shift = CONFIG_PAGE_SIZE_BIT;
++ ra->oob_shift = CONFIG_OOBSIZE_PER_PAGE_BIT;
++ ra->erase_shift = (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT);
++ ra->badblockpos = CONFIG_BAD_BLOCK_POS;
++ ra_oob_layout.eccpos[0] = CONFIG_ECC_OFFSET;
++ ra_oob_layout.eccpos[1] = CONFIG_ECC_OFFSET + 1;
++ ra_oob_layout.eccpos[2] = CONFIG_ECC_OFFSET + 2;
++ ra->oob = &ra_oob_layout;
++ ra->buffers_page = -1;
++
++#if defined (WORKAROUND_RX_BUF_OV)
++ if (ranfc_verify) {
++ ra->sandbox_page = nand_bbt_find_sandbox(ra);
++ }
++#endif
++ ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x01); //set wp to high
++ nfc_all_reset();
++
++ ranfc_mtd->type = MTD_NANDFLASH;
++ ranfc_mtd->flags = MTD_CAP_NANDFLASH;
++ ranfc_mtd->size = CONFIG_NUMCHIPS * CFG_CHIPSIZE;
++ ranfc_mtd->erasesize = CFG_BLOCKSIZE;
++ ranfc_mtd->writesize = CFG_PAGESIZE;
++ ranfc_mtd->oobsize = CFG_PAGE_OOBSIZE;
++ ranfc_mtd->oobavail = RA_CHIP_OOB_AVAIL;
++ ranfc_mtd->name = "ra_nfc";
++ //ranfc_mtd->index
++ ranfc_mtd->ecclayout = &ra_oob_layout;
++ //ranfc_mtd->numberaseregions
++ //ranfc_mtd->eraseregions
++ //ranfc_mtd->bansize
++ ranfc_mtd->_erase = ramtd_nand_erase;
++ //ranfc_mtd->point
++ //ranfc_mtd->unpoint
++ ranfc_mtd->_read = ramtd_nand_read;
++ ranfc_mtd->_write = ramtd_nand_write;
++ ranfc_mtd->_read_oob = ramtd_nand_readoob;
++ ranfc_mtd->_write_oob = ramtd_nand_writeoob;
++ //ranfc_mtd->get_fact_prot_info; ranfc_mtd->read_fact_prot_reg;
++ //ranfc_mtd->get_user_prot_info; ranfc_mtd->read_user_prot_reg;
++ //ranfc_mtd->write_user_prot_reg; ranfc_mtd->lock_user_prot_reg;
++ //ranfc_mtd->writev; ranfc_mtd->sync; ranfc_mtd->lock; ranfc_mtd->unlock; ranfc_mtd->suspend; ranfc_mtd->resume;
++ ranfc_mtd->_block_isbad = ramtd_nand_block_isbad;
++ ranfc_mtd->_block_markbad = ramtd_nand_block_markbad;
++ //ranfc_mtd->reboot_notifier
++ //ranfc_mtd->ecc_stats;
++ // subpage_sht;
++
++ //ranfc_mtd->get_device; ranfc_mtd->put_device
++ ranfc_mtd->priv = ra;
++
++ ranfc_mtd->owner = THIS_MODULE;
++ ra->controller = &ra->hwcontrol;
++ mutex_init(ra->controller);
++
++ printk("%s: alloc %x, at %p , btt(%p, %x), ranfc_mtd:%p\n",
++ __func__ , alloc_size, ra, ra->bbt, bbt_size, ranfc_mtd);
++
++ ppdata.of_node = pdev->dev.of_node;
++ err = mtd_device_parse_register(ranfc_mtd, mtk_probe_types,
++ &ppdata, NULL, 0);
++
++ return err;
++}
++
++static int
++mtk_nand_remove(struct platform_device *pdev)
++{
++ struct ra_nand_chip *ra;
++
++ if (ranfc_mtd) {
++ ra = (struct ra_nand_chip *)ranfc_mtd->priv;
++
++ /* Deregister partitions */
++ //del_mtd_partitions(ranfc_mtd);
++ kfree(ra);
++ }
++ return 0;
++}
++
++static const struct of_device_id mtk_nand_match[] = {
++ { .compatible = "mtk,mt7620-nand" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mtk_nand_match);
++
++static struct platform_driver mtk_nand_driver = {
++ .probe = mtk_nand_probe,
++ .remove = mtk_nand_remove,
++ .driver = {
++ .name = "mt7620_nand",
++ .owner = THIS_MODULE,
++ .of_match_table = mtk_nand_match,
++ },
++};
++
++module_platform_driver(mtk_nand_driver);
++
++
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/mtd/maps/ralink_nand.h
+@@ -0,0 +1,232 @@
++#ifndef RT2880_NAND_H
++#define RT2880_NAND_H
++
++#include <linux/mtd/mtd.h>
++
++//#include "gdma.h"
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_NAND_CTRL_BASE 0xB0000810
++#define CONFIG_RALINK_MT7620
++
++#define SKIP_BAD_BLOCK
++//#define RANDOM_GEN_BAD_BLOCK
++
++#define ra_inl(addr) (*(volatile unsigned int *)(addr))
++#define ra_outl(addr, value) (*(volatile unsigned int *)(addr) = (value))
++#define ra_aor(addr, a_mask, o_value) ra_outl(addr, (ra_inl(addr) & (a_mask)) | (o_value))
++#define ra_and(addr, a_mask) ra_aor(addr, a_mask, 0)
++#define ra_or(addr, o_value) ra_aor(addr, -1, o_value)
++
++
++#define CONFIG_NUMCHIPS 1
++#define CONFIG_NOT_SUPPORT_WP //rt3052 has no WP signal for chip.
++//#define CONFIG_NOT_SUPPORT_RB
++
++extern int is_nand_page_2048;
++extern const unsigned int nand_size_map[2][3];
++
++//chip
++// chip geometry: SAMSUNG small size 32MB.
++#define CONFIG_CHIP_SIZE_BIT (nand_size_map[is_nand_page_2048][nand_addrlen-3]) //! (1<<NAND_SIZE_BYTE) MB
++//#define CONFIG_CHIP_SIZE_BIT (is_nand_page_2048? 29 : 25) //! (1<<NAND_SIZE_BYTE) MB
++#define CONFIG_PAGE_SIZE_BIT (is_nand_page_2048? 11 : 9) //! (1<<PAGE_SIZE) MB
++//#define CONFIG_SUBPAGE_BIT 1 //! these bits will be compensate by command cycle
++#define CONFIG_NUMPAGE_PER_BLOCK_BIT (is_nand_page_2048? 6 : 5) //! order of number of pages a block.
++#define CONFIG_OOBSIZE_PER_PAGE_BIT (is_nand_page_2048? 6 : 4) //! byte number of oob a page.
++#define CONFIG_BAD_BLOCK_POS (is_nand_page_2048? 0 : 4) //! offset of byte to denote bad block.
++#define CONFIG_ECC_BYTES 3 //! ecc has 3 bytes
++#define CONFIG_ECC_OFFSET (is_nand_page_2048? 6 : 5) //! ecc starts from offset 5.
++
++//this section should not be modified.
++//#define CFG_COLUMN_ADDR_MASK ((1 << (CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT)) - 1)
++//#define CFG_COLUMN_ADDR_CYCLE (((CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT) + 7)/8)
++//#define CFG_ROW_ADDR_CYCLE ((CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT + 7)/8)
++//#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
++
++#define CFG_COLUMN_ADDR_CYCLE (is_nand_page_2048? 2 : 1)
++#define CFG_ROW_ADDR_CYCLE (nand_addrlen - CFG_COLUMN_ADDR_CYCLE)
++#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
++
++#define CFG_CHIPSIZE (1 << ((CONFIG_CHIP_SIZE_BIT>=32)? 31 : CONFIG_CHIP_SIZE_BIT))
++//#define CFG_CHIPSIZE (1 << CONFIG_CHIP_SIZE_BIT)
++#define CFG_PAGESIZE (1 << CONFIG_PAGE_SIZE_BIT)
++#define CFG_BLOCKSIZE (CFG_PAGESIZE << CONFIG_NUMPAGE_PER_BLOCK_BIT)
++#define CFG_NUMPAGE (1 << (CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT))
++#define CFG_NUMBLOCK (CFG_NUMPAGE >> CONFIG_NUMPAGE_PER_BLOCK_BIT)
++#define CFG_BLOCK_OOBSIZE (1 << (CONFIG_OOBSIZE_PER_PAGE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))
++#define CFG_PAGE_OOBSIZE (1 << CONFIG_OOBSIZE_PER_PAGE_BIT)
++
++#define NAND_BLOCK_ALIGN(addr) ((addr) & (CFG_BLOCKSIZE-1))
++#define NAND_PAGE_ALIGN(addr) ((addr) & (CFG_PAGESIZE-1))
++
++
++#define NFC_BASE RALINK_NAND_CTRL_BASE
++#define NFC_CTRL (NFC_BASE + 0x0)
++#define NFC_CONF (NFC_BASE + 0x4)
++#define NFC_CMD1 (NFC_BASE + 0x8)
++#define NFC_CMD2 (NFC_BASE + 0xc)
++#define NFC_CMD3 (NFC_BASE + 0x10)
++#define NFC_ADDR (NFC_BASE + 0x14)
++#define NFC_DATA (NFC_BASE + 0x18)
++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++#define NFC_ECC (NFC_BASE + 0x30)
++#else
++#define NFC_ECC (NFC_BASE + 0x1c)
++#endif
++#define NFC_STATUS (NFC_BASE + 0x20)
++#define NFC_INT_EN (NFC_BASE + 0x24)
++#define NFC_INT_ST (NFC_BASE + 0x28)
++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++#define NFC_CONF1 (NFC_BASE + 0x2c)
++#define NFC_ECC_P1 (NFC_BASE + 0x30)
++#define NFC_ECC_P2 (NFC_BASE + 0x34)
++#define NFC_ECC_P3 (NFC_BASE + 0x38)
++#define NFC_ECC_P4 (NFC_BASE + 0x3c)
++#define NFC_ECC_ERR1 (NFC_BASE + 0x40)
++#define NFC_ECC_ERR2 (NFC_BASE + 0x44)
++#define NFC_ECC_ERR3 (NFC_BASE + 0x48)
++#define NFC_ECC_ERR4 (NFC_BASE + 0x4c)
++#define NFC_ADDR2 (NFC_BASE + 0x50)
++#endif
++
++enum _int_stat {
++ INT_ST_ND_DONE = 1<<0,
++ INT_ST_TX_BUF_RDY = 1<<1,
++ INT_ST_RX_BUF_RDY = 1<<2,
++ INT_ST_ECC_ERR = 1<<3,
++ INT_ST_TX_TRAS_ERR = 1<<4,
++ INT_ST_RX_TRAS_ERR = 1<<5,
++ INT_ST_TX_KICK_ERR = 1<<6,
++ INT_ST_RX_KICK_ERR = 1<<7
++};
++
++
++//#define WORKAROUND_RX_BUF_OV 1
++
++
++/*************************************************************
++ * stolen from nand.h
++ *************************************************************/
++
++/*
++ * Standard NAND flash commands
++ */
++#define NAND_CMD_READ0 0
++#define NAND_CMD_READ1 1
++#define NAND_CMD_RNDOUT 5
++#define NAND_CMD_PAGEPROG 0x10
++#define NAND_CMD_READOOB 0x50
++#define NAND_CMD_ERASE1 0x60
++#define NAND_CMD_STATUS 0x70
++#define NAND_CMD_STATUS_MULTI 0x71
++#define NAND_CMD_SEQIN 0x80
++#define NAND_CMD_RNDIN 0x85
++#define NAND_CMD_READID 0x90
++#define NAND_CMD_ERASE2 0xd0
++#define NAND_CMD_RESET 0xff
++
++/* Extended commands for large page devices */
++#define NAND_CMD_READSTART 0x30
++#define NAND_CMD_RNDOUTSTART 0xE0
++#define NAND_CMD_CACHEDPROG 0x15
++
++/* Extended commands for AG-AND device */
++/*
++ * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
++ * there is no way to distinguish that from NAND_CMD_READ0
++ * until the remaining sequence of commands has been completed
++ * so add a high order bit and mask it off in the command.
++ */
++#define NAND_CMD_DEPLETE1 0x100
++#define NAND_CMD_DEPLETE2 0x38
++#define NAND_CMD_STATUS_MULTI 0x71
++#define NAND_CMD_STATUS_ERROR 0x72
++/* multi-bank error status (banks 0-3) */
++#define NAND_CMD_STATUS_ERROR0 0x73
++#define NAND_CMD_STATUS_ERROR1 0x74
++#define NAND_CMD_STATUS_ERROR2 0x75
++#define NAND_CMD_STATUS_ERROR3 0x76
++#define NAND_CMD_STATUS_RESET 0x7f
++#define NAND_CMD_STATUS_CLEAR 0xff
++
++#define NAND_CMD_NONE -1
++
++/* Status bits */
++#define NAND_STATUS_FAIL 0x01
++#define NAND_STATUS_FAIL_N1 0x02
++#define NAND_STATUS_TRUE_READY 0x20
++#define NAND_STATUS_READY 0x40
++#define NAND_STATUS_WP 0x80
++
++typedef enum {
++ FL_READY,
++ FL_READING,
++ FL_WRITING,
++ FL_ERASING,
++ FL_SYNCING,
++ FL_CACHEDPRG,
++ FL_PM_SUSPENDED,
++} nand_state_t;
++
++/*************************************************************/
++
++
++
++typedef enum _ra_flags {
++ FLAG_NONE = 0,
++ FLAG_ECC_EN = (1<<0),
++ FLAG_USE_GDMA = (1<<1),
++ FLAG_VERIFY = (1<<2),
++} RA_FLAGS;
++
++
++#define BBTTAG_BITS 2
++#define BBTTAG_BITS_MASK ((1<<BBTTAG_BITS) -1)
++enum BBT_TAG {
++ BBT_TAG_UNKNOWN = 0, //2'b01
++ BBT_TAG_GOOD = 3, //2'b11
++ BBT_TAG_BAD = 2, //2'b10
++ BBT_TAG_RES = 1, //2'b01
++};
++
++struct ra_nand_chip {
++ int numchips;
++ int chip_shift;
++ int page_shift;
++ int erase_shift;
++ int oob_shift;
++ int badblockpos;
++#if !defined (__UBOOT__)
++ struct mutex hwcontrol;
++ struct mutex *controller;
++#endif
++ struct nand_ecclayout *oob;
++ int state;
++ unsigned int buffers_page;
++ char *buffers; //[CFG_PAGESIZE + CFG_PAGE_OOBSIZE];
++ char *readback_buffers;
++ unsigned char *bbt;
++#if defined (WORKAROUND_RX_BUF_OV)
++ unsigned int sandbox_page; // steal a page (block) for read ECC verification
++#endif
++
++};
++
++
++
++//fixme, gdma api
++int nand_dma_sync(void);
++void release_dma_buf(void);
++int set_gdma_ch(unsigned long dst,
++ unsigned long src, unsigned int len, int burst_size,
++ int soft_mode, int src_req_type, int dst_req_type,
++ int src_burst_mode, int dst_burst_mode);
++
++
++
++
++#endif
--- /dev/null
+From 5db075c5dd038fbf4b5a0196e10f4f9658236372 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 11:05:17 +0100
+Subject: [PATCH 45/57] mtd: add mt7621 nand support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/Kconfig | 6 +
+ drivers/mtd/nand/Makefile | 1 +
+ drivers/mtd/nand/bmt.c | 750 ++++++++++++
+ drivers/mtd/nand/bmt.h | 80 ++
+ drivers/mtd/nand/dev-nand.c | 63 +
+ drivers/mtd/nand/mt6575_typedefs.h | 340 ++++++
+ drivers/mtd/nand/mtk_nand.c | 2304 +++++++++++++++++++++++++++++++++++
+ drivers/mtd/nand/mtk_nand.h | 452 +++++++
+ drivers/mtd/nand/nand_base.c | 6 +-
+ drivers/mtd/nand/nand_bbt.c | 19 +
+ drivers/mtd/nand/nand_def.h | 123 ++
+ drivers/mtd/nand/nand_device_list.h | 55 +
+ drivers/mtd/nand/partition.h | 115 ++
+ 13 files changed, 4311 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/mtd/nand/bmt.c
+ create mode 100644 drivers/mtd/nand/bmt.h
+ create mode 100644 drivers/mtd/nand/dev-nand.c
+ create mode 100644 drivers/mtd/nand/mt6575_typedefs.h
+ create mode 100644 drivers/mtd/nand/mtk_nand.c
+ create mode 100644 drivers/mtd/nand/mtk_nand.h
+ create mode 100644 drivers/mtd/nand/nand_def.h
+ create mode 100644 drivers/mtd/nand/nand_device_list.h
+ create mode 100644 drivers/mtd/nand/partition.h
+
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -516,4 +516,10 @@ config MTD_NAND_XWAY
+ Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ to the External Bus Unit (EBU).
+
++config MTK_MTD_NAND
++ tristate "Support for MTK SoC NAND controller"
++ depends on SOC_MT7621
++ select MTD_NAND_IDS
++ select MTD_NAND_ECC
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -50,5 +50,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740
+ obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
+ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
+ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
++obj-$(CONFIG_MTK_MTD_NAND) += mtk_nand.o bmt.o
+
+ nand-objs := nand_base.o nand_bbt.o nand_timings.o
+--- /dev/null
++++ b/drivers/mtd/nand/bmt.c
+@@ -0,0 +1,750 @@
++#include "bmt.h"
++
++typedef struct
++{
++ char signature[3];
++ u8 version;
++ u8 bad_count; // bad block count in pool
++ u8 mapped_count; // mapped block count in pool
++ u8 checksum;
++ u8 reseverd[13];
++} phys_bmt_header;
++
++typedef struct
++{
++ phys_bmt_header header;
++ bmt_entry table[MAX_BMT_SIZE];
++} phys_bmt_struct;
++
++typedef struct
++{
++ char signature[3];
++} bmt_oob_data;
++
++static char MAIN_SIGNATURE[] = "BMT";
++static char OOB_SIGNATURE[] = "bmt";
++#define SIGNATURE_SIZE (3)
++
++#define MAX_DAT_SIZE 0x1000
++#define MAX_OOB_SIZE 0x80
++
++static struct mtd_info *mtd_bmt;
++static struct nand_chip *nand_chip_bmt;
++#define BLOCK_SIZE_BMT (1 << nand_chip_bmt->phys_erase_shift)
++#define PAGE_SIZE_BMT (1 << nand_chip_bmt->page_shift)
++
++#define OFFSET(block) ((block) * BLOCK_SIZE_BMT)
++#define PAGE_ADDR(block) ((block) * BLOCK_SIZE_BMT / PAGE_SIZE_BMT)
++
++/*********************************************************************
++* Flash is splited into 2 parts, system part is for normal system *
++* system usage, size is system_block_count, another is replace pool *
++* +-------------------------------------------------+ *
++* | system_block_count | bmt_block_count | *
++* +-------------------------------------------------+ *
++*********************************************************************/
++static u32 total_block_count; // block number in flash
++static u32 system_block_count;
++static int bmt_block_count; // bmt table size
++// static int bmt_count; // block used in bmt
++static int page_per_block; // page per count
++
++static u32 bmt_block_index; // bmt block index
++static bmt_struct bmt; // dynamic created global bmt table
++
++static u8 dat_buf[MAX_DAT_SIZE];
++static u8 oob_buf[MAX_OOB_SIZE];
++static bool pool_erased;
++
++/***************************************************************
++*
++* Interface adaptor for preloader/uboot/kernel
++* These interfaces operate on physical address, read/write
++* physical data.
++*
++***************************************************************/
++int nand_read_page_bmt(u32 page, u8 * dat, u8 * oob)
++{
++ return mtk_nand_exec_read_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob);
++}
++
++bool nand_block_bad_bmt(u32 offset)
++{
++ return mtk_nand_block_bad_hw(mtd_bmt, offset);
++}
++
++bool nand_erase_bmt(u32 offset)
++{
++ int status;
++ if (offset < 0x20000)
++ {
++ MSG(INIT, "erase offset: 0x%x\n", offset);
++ }
++
++ status = mtk_nand_erase_hw(mtd_bmt, offset / PAGE_SIZE_BMT); // as nand_chip structure doesn't have a erase function defined
++ if (status & NAND_STATUS_FAIL)
++ return false;
++ else
++ return true;
++}
++
++int mark_block_bad_bmt(u32 offset)
++{
++ return mtk_nand_block_markbad_hw(mtd_bmt, offset); //mark_block_bad_hw(offset);
++}
++
++bool nand_write_page_bmt(u32 page, u8 * dat, u8 * oob)
++{
++ if (mtk_nand_exec_write_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob))
++ return false;
++ else
++ return true;
++}
++
++/***************************************************************
++* *
++* static internal function *
++* *
++***************************************************************/
++static void dump_bmt_info(bmt_struct * bmt)
++{
++ int i;
++
++ MSG(INIT, "BMT v%d. total %d mapping:\n", bmt->version, bmt->mapped_count);
++ for (i = 0; i < bmt->mapped_count; i++)
++ {
++ MSG(INIT, "\t0x%x -> 0x%x\n", bmt->table[i].bad_index, bmt->table[i].mapped_index);
++ }
++}
++
++static bool match_bmt_signature(u8 * dat, u8 * oob)
++{
++
++ if (memcmp(dat + MAIN_SIGNATURE_OFFSET, MAIN_SIGNATURE, SIGNATURE_SIZE))
++ {
++ return false;
++ }
++
++ if (memcmp(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE))
++ {
++ MSG(INIT, "main signature match, oob signature doesn't match, but ignore\n");
++ }
++ return true;
++}
++
++static u8 cal_bmt_checksum(phys_bmt_struct * phys_table, int bmt_size)
++{
++ int i;
++ u8 checksum = 0;
++ u8 *dat = (u8 *) phys_table;
++
++ checksum += phys_table->header.version;
++ checksum += phys_table->header.mapped_count;
++
++ dat += sizeof(phys_bmt_header);
++ for (i = 0; i < bmt_size * sizeof(bmt_entry); i++)
++ {
++ checksum += dat[i];
++ }
++
++ return checksum;
++}
++
++
++static int is_block_mapped(int index)
++{
++ int i;
++ for (i = 0; i < bmt.mapped_count; i++)
++ {
++ if (index == bmt.table[i].mapped_index)
++ return i;
++ }
++ return -1;
++}
++
++static bool is_page_used(u8 * dat, u8 * oob)
++{
++ return ((oob[OOB_INDEX_OFFSET] != 0xFF) || (oob[OOB_INDEX_OFFSET + 1] != 0xFF));
++}
++
++static bool valid_bmt_data(phys_bmt_struct * phys_table)
++{
++ int i;
++ u8 checksum = cal_bmt_checksum(phys_table, bmt_block_count);
++
++ // checksum correct?
++ if (phys_table->header.checksum != checksum)
++ {
++ MSG(INIT, "BMT Data checksum error: %x %x\n", phys_table->header.checksum, checksum);
++ return false;
++ }
++
++ MSG(INIT, "BMT Checksum is: 0x%x\n", phys_table->header.checksum);
++
++ // block index correct?
++ for (i = 0; i < phys_table->header.mapped_count; i++)
++ {
++ if (phys_table->table[i].bad_index >= total_block_count || phys_table->table[i].mapped_index >= total_block_count || phys_table->table[i].mapped_index < system_block_count)
++ {
++ MSG(INIT, "index error: bad_index: %d, mapped_index: %d\n", phys_table->table[i].bad_index, phys_table->table[i].mapped_index);
++ return false;
++ }
++ }
++
++ // pass check, valid bmt.
++ MSG(INIT, "Valid BMT, version v%d\n", phys_table->header.version);
++ return true;
++}
++
++static void fill_nand_bmt_buffer(bmt_struct * bmt, u8 * dat, u8 * oob)
++{
++ phys_bmt_struct phys_bmt;
++
++ dump_bmt_info(bmt);
++
++ // fill phys_bmt_struct structure with bmt_struct
++ memset(&phys_bmt, 0xFF, sizeof(phys_bmt));
++
++ memcpy(phys_bmt.header.signature, MAIN_SIGNATURE, SIGNATURE_SIZE);
++ phys_bmt.header.version = BMT_VERSION;
++ // phys_bmt.header.bad_count = bmt->bad_count;
++ phys_bmt.header.mapped_count = bmt->mapped_count;
++ memcpy(phys_bmt.table, bmt->table, sizeof(bmt_entry) * bmt_block_count);
++
++ phys_bmt.header.checksum = cal_bmt_checksum(&phys_bmt, bmt_block_count);
++
++ memcpy(dat + MAIN_SIGNATURE_OFFSET, &phys_bmt, sizeof(phys_bmt));
++ memcpy(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE);
++}
++
++// return valid index if found BMT, else return 0
++static int load_bmt_data(int start, int pool_size)
++{
++ int bmt_index = start + pool_size - 1; // find from the end
++ phys_bmt_struct phys_table;
++ int i;
++
++ MSG(INIT, "[%s]: begin to search BMT from block 0x%x\n", __FUNCTION__, bmt_index);
++
++ for (bmt_index = start + pool_size - 1; bmt_index >= start; bmt_index--)
++ {
++ if (nand_block_bad_bmt(OFFSET(bmt_index)))
++ {
++ MSG(INIT, "Skip bad block: %d\n", bmt_index);
++ continue;
++ }
++
++ if (!nand_read_page_bmt(PAGE_ADDR(bmt_index), dat_buf, oob_buf))
++ {
++ MSG(INIT, "Error found when read block %d\n", bmt_index);
++ continue;
++ }
++
++ if (!match_bmt_signature(dat_buf, oob_buf))
++ {
++ continue;
++ }
++
++ MSG(INIT, "Match bmt signature @ block: 0x%x\n", bmt_index);
++
++ memcpy(&phys_table, dat_buf + MAIN_SIGNATURE_OFFSET, sizeof(phys_table));
++
++ if (!valid_bmt_data(&phys_table))
++ {
++ MSG(INIT, "BMT data is not correct %d\n", bmt_index);
++ continue;
++ } else
++ {
++ bmt.mapped_count = phys_table.header.mapped_count;
++ bmt.version = phys_table.header.version;
++ // bmt.bad_count = phys_table.header.bad_count;
++ memcpy(bmt.table, phys_table.table, bmt.mapped_count * sizeof(bmt_entry));
++
++ MSG(INIT, "bmt found at block: %d, mapped block: %d\n", bmt_index, bmt.mapped_count);
++
++ for (i = 0; i < bmt.mapped_count; i++)
++ {
++ if (!nand_block_bad_bmt(OFFSET(bmt.table[i].bad_index)))
++ {
++ MSG(INIT, "block 0x%x is not mark bad, should be power lost last time\n", bmt.table[i].bad_index);
++ mark_block_bad_bmt(OFFSET(bmt.table[i].bad_index));
++ }
++ }
++
++ return bmt_index;
++ }
++ }
++
++ MSG(INIT, "bmt block not found!\n");
++ return 0;
++}
++
++/*************************************************************************
++* Find an available block and erase. *
++* start_from_end: if true, find available block from end of flash. *
++* else, find from the beginning of the pool *
++* need_erase: if true, all unmapped blocks in the pool will be erased *
++*************************************************************************/
++static int find_available_block(bool start_from_end)
++{
++ int i; // , j;
++ int block = system_block_count;
++ int direction;
++ // int avail_index = 0;
++ MSG(INIT, "Try to find_available_block, pool_erase: %d\n", pool_erased);
++
++ // erase all un-mapped blocks in pool when finding avaliable block
++ if (!pool_erased)
++ {
++ MSG(INIT, "Erase all un-mapped blocks in pool\n");
++ for (i = 0; i < bmt_block_count; i++)
++ {
++ if (block == bmt_block_index)
++ {
++ MSG(INIT, "Skip bmt block 0x%x\n", block);
++ continue;
++ }
++
++ if (nand_block_bad_bmt(OFFSET(block + i)))
++ {
++ MSG(INIT, "Skip bad block 0x%x\n", block + i);
++ continue;
++ }
++//if(block==4095)
++//{
++// continue;
++//}
++
++ if (is_block_mapped(block + i) >= 0)
++ {
++ MSG(INIT, "Skip mapped block 0x%x\n", block + i);
++ continue;
++ }
++
++ if (!nand_erase_bmt(OFFSET(block + i)))
++ {
++ MSG(INIT, "Erase block 0x%x failed\n", block + i);
++ mark_block_bad_bmt(OFFSET(block + i));
++ }
++ }
++
++ pool_erased = 1;
++ }
++
++ if (start_from_end)
++ {
++ block = total_block_count - 1;
++ direction = -1;
++ } else
++ {
++ block = system_block_count;
++ direction = 1;
++ }
++
++ for (i = 0; i < bmt_block_count; i++, block += direction)
++ {
++ if (block == bmt_block_index)
++ {
++ MSG(INIT, "Skip bmt block 0x%x\n", block);
++ continue;
++ }
++
++ if (nand_block_bad_bmt(OFFSET(block)))
++ {
++ MSG(INIT, "Skip bad block 0x%x\n", block);
++ continue;
++ }
++
++ if (is_block_mapped(block) >= 0)
++ {
++ MSG(INIT, "Skip mapped block 0x%x\n", block);
++ continue;
++ }
++
++ MSG(INIT, "Find block 0x%x available\n", block);
++ return block;
++ }
++
++ return 0;
++}
++
++static unsigned short get_bad_index_from_oob(u8 * oob_buf)
++{
++ unsigned short index;
++ memcpy(&index, oob_buf + OOB_INDEX_OFFSET, OOB_INDEX_SIZE);
++
++ return index;
++}
++
++void set_bad_index_to_oob(u8 * oob, u16 index)
++{
++ memcpy(oob + OOB_INDEX_OFFSET, &index, sizeof(index));
++}
++
++static int migrate_from_bad(int offset, u8 * write_dat, u8 * write_oob)
++{
++ int page;
++ int error_block = offset / BLOCK_SIZE_BMT;
++ int error_page = (offset / PAGE_SIZE_BMT) % page_per_block;
++ int to_index;
++
++ memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
++
++ to_index = find_available_block(false);
++
++ if (!to_index)
++ {
++ MSG(INIT, "Cannot find an available block for BMT\n");
++ return 0;
++ }
++
++ { // migrate error page first
++ MSG(INIT, "Write error page: 0x%x\n", error_page);
++ if (!write_dat)
++ {
++ nand_read_page_bmt(PAGE_ADDR(error_block) + error_page, dat_buf, NULL);
++ write_dat = dat_buf;
++ }
++ // memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
++
++ if (error_block < system_block_count)
++ set_bad_index_to_oob(oob_buf, error_block); // if error_block is already a mapped block, original mapping index is in OOB.
++
++ if (!nand_write_page_bmt(PAGE_ADDR(to_index) + error_page, write_dat, oob_buf))
++ {
++ MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + error_page);
++ mark_block_bad_bmt(to_index);
++ return migrate_from_bad(offset, write_dat, write_oob);
++ }
++ }
++
++ for (page = 0; page < page_per_block; page++)
++ {
++ if (page != error_page)
++ {
++ nand_read_page_bmt(PAGE_ADDR(error_block) + page, dat_buf, oob_buf);
++ if (is_page_used(dat_buf, oob_buf))
++ {
++ if (error_block < system_block_count)
++ {
++ set_bad_index_to_oob(oob_buf, error_block);
++ }
++ MSG(INIT, "\tmigrate page 0x%x to page 0x%x\n", PAGE_ADDR(error_block) + page, PAGE_ADDR(to_index) + page);
++ if (!nand_write_page_bmt(PAGE_ADDR(to_index) + page, dat_buf, oob_buf))
++ {
++ MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + page);
++ mark_block_bad_bmt(to_index);
++ return migrate_from_bad(offset, write_dat, write_oob);
++ }
++ }
++ }
++ }
++
++ MSG(INIT, "Migrate from 0x%x to 0x%x done!\n", error_block, to_index);
++
++ return to_index;
++}
++
++static bool write_bmt_to_flash(u8 * dat, u8 * oob)
++{
++ bool need_erase = true;
++ MSG(INIT, "Try to write BMT\n");
++
++ if (bmt_block_index == 0)
++ {
++ // if we don't have index, we don't need to erase found block as it has been erased in find_available_block()
++ need_erase = false;
++ if (!(bmt_block_index = find_available_block(true)))
++ {
++ MSG(INIT, "Cannot find an available block for BMT\n");
++ return false;
++ }
++ }
++
++ MSG(INIT, "Find BMT block: 0x%x\n", bmt_block_index);
++
++ // write bmt to flash
++ if (need_erase)
++ {
++ if (!nand_erase_bmt(OFFSET(bmt_block_index)))
++ {
++ MSG(INIT, "BMT block erase fail, mark bad: 0x%x\n", bmt_block_index);
++ mark_block_bad_bmt(OFFSET(bmt_block_index));
++ // bmt.bad_count++;
++
++ bmt_block_index = 0;
++ return write_bmt_to_flash(dat, oob); // recursive call
++ }
++ }
++
++ if (!nand_write_page_bmt(PAGE_ADDR(bmt_block_index), dat, oob))
++ {
++ MSG(INIT, "Write BMT data fail, need to write again\n");
++ mark_block_bad_bmt(OFFSET(bmt_block_index));
++ // bmt.bad_count++;
++
++ bmt_block_index = 0;
++ return write_bmt_to_flash(dat, oob); // recursive call
++ }
++
++ MSG(INIT, "Write BMT data to block 0x%x success\n", bmt_block_index);
++ return true;
++}
++
++/*******************************************************************
++* Reconstruct bmt, called when found bmt info doesn't match bad
++* block info in flash.
++*
++* Return NULL for failure
++*******************************************************************/
++bmt_struct *reconstruct_bmt(bmt_struct * bmt)
++{
++ int i;
++ int index = system_block_count;
++ unsigned short bad_index;
++ int mapped;
++
++ // init everything in BMT struct
++ bmt->version = BMT_VERSION;
++ bmt->bad_count = 0;
++ bmt->mapped_count = 0;
++
++ memset(bmt->table, 0, bmt_block_count * sizeof(bmt_entry));
++
++ for (i = 0; i < bmt_block_count; i++, index++)
++ {
++ if (nand_block_bad_bmt(OFFSET(index)))
++ {
++ MSG(INIT, "Skip bad block: 0x%x\n", index);
++ // bmt->bad_count++;
++ continue;
++ }
++
++ MSG(INIT, "read page: 0x%x\n", PAGE_ADDR(index));
++ nand_read_page_bmt(PAGE_ADDR(index), dat_buf, oob_buf);
++ /* if (mtk_nand_read_page_hw(PAGE_ADDR(index), dat_buf))
++ {
++ MSG(INIT, "Error when read block %d\n", bmt_block_index);
++ continue;
++ } */
++
++ if ((bad_index = get_bad_index_from_oob(oob_buf)) >= system_block_count)
++ {
++ MSG(INIT, "get bad index: 0x%x\n", bad_index);
++ if (bad_index != 0xFFFF)
++ MSG(INIT, "Invalid bad index found in block 0x%x, bad index 0x%x\n", index, bad_index);
++ continue;
++ }
++
++ MSG(INIT, "Block 0x%x is mapped to bad block: 0x%x\n", index, bad_index);
++
++ if (!nand_block_bad_bmt(OFFSET(bad_index)))
++ {
++ MSG(INIT, "\tbut block 0x%x is not marked as bad, invalid mapping\n", bad_index);
++ continue; // no need to erase here, it will be erased later when trying to write BMT
++ }
++
++ if ((mapped = is_block_mapped(bad_index)) >= 0)
++ {
++ MSG(INIT, "bad block 0x%x is mapped to 0x%x, should be caused by power lost, replace with one\n", bmt->table[mapped].bad_index, bmt->table[mapped].mapped_index);
++ bmt->table[mapped].mapped_index = index; // use new one instead.
++ } else
++ {
++ // add mapping to BMT
++ bmt->table[bmt->mapped_count].bad_index = bad_index;
++ bmt->table[bmt->mapped_count].mapped_index = index;
++ bmt->mapped_count++;
++ }
++
++ MSG(INIT, "Add mapping: 0x%x -> 0x%x to BMT\n", bad_index, index);
++
++ }
++
++ MSG(INIT, "Scan replace pool done, mapped block: %d\n", bmt->mapped_count);
++ // dump_bmt_info(bmt);
++
++ // fill NAND BMT buffer
++ memset(oob_buf, 0xFF, sizeof(oob_buf));
++ fill_nand_bmt_buffer(bmt, dat_buf, oob_buf);
++
++ // write BMT back
++ if (!write_bmt_to_flash(dat_buf, oob_buf))
++ {
++ MSG(INIT, "TRAGEDY: cannot find a place to write BMT!!!!\n");
++ }
++
++ return bmt;
++}
++
++/*******************************************************************
++* [BMT Interface]
++*
++* Description:
++* Init bmt from nand. Reconstruct if not found or data error
++*
++* Parameter:
++* size: size of bmt and replace pool
++*
++* Return:
++* NULL for failure, and a bmt struct for success
++*******************************************************************/
++bmt_struct *init_bmt(struct nand_chip * chip, int size)
++{
++ struct mtk_nand_host *host;
++
++ if (size > 0 && size < MAX_BMT_SIZE)
++ {
++ MSG(INIT, "Init bmt table, size: %d\n", size);
++ bmt_block_count = size;
++ } else
++ {
++ MSG(INIT, "Invalid bmt table size: %d\n", size);
++ return NULL;
++ }
++ nand_chip_bmt = chip;
++ system_block_count = chip->chipsize >> chip->phys_erase_shift;
++ total_block_count = bmt_block_count + system_block_count;
++ page_per_block = BLOCK_SIZE_BMT / PAGE_SIZE_BMT;
++ host = (struct mtk_nand_host *)chip->priv;
++ mtd_bmt = &host->mtd;
++
++ MSG(INIT, "mtd_bmt: %p, nand_chip_bmt: %p\n", mtd_bmt, nand_chip_bmt);
++ MSG(INIT, "bmt count: %d, system count: %d\n", bmt_block_count, system_block_count);
++
++ // set this flag, and unmapped block in pool will be erased.
++ pool_erased = 0;
++ memset(bmt.table, 0, size * sizeof(bmt_entry));
++ if ((bmt_block_index = load_bmt_data(system_block_count, size)))
++ {
++ MSG(INIT, "Load bmt data success @ block 0x%x\n", bmt_block_index);
++ dump_bmt_info(&bmt);
++ return &bmt;
++ } else
++ {
++ MSG(INIT, "Load bmt data fail, need re-construct!\n");
++#ifndef __UBOOT_NAND__ // BMT is not re-constructed in UBOOT.
++ if (reconstruct_bmt(&bmt))
++ return &bmt;
++ else
++#endif
++ return NULL;
++ }
++}
++
++/*******************************************************************
++* [BMT Interface]
++*
++* Description:
++* Update BMT.
++*
++* Parameter:
++* offset: update block/page offset.
++* reason: update reason, see update_reason_t for reason.
++* dat/oob: data and oob buffer for write fail.
++*
++* Return:
++* Return true for success, and false for failure.
++*******************************************************************/
++bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob)
++{
++ int map_index;
++ int orig_bad_block = -1;
++ // int bmt_update_index;
++ int i;
++ int bad_index = offset / BLOCK_SIZE_BMT;
++
++#ifndef MTK_NAND_BMT
++ return false;
++#endif
++ if (reason == UPDATE_WRITE_FAIL)
++ {
++ MSG(INIT, "Write fail, need to migrate\n");
++ if (!(map_index = migrate_from_bad(offset, dat, oob)))
++ {
++ MSG(INIT, "migrate fail\n");
++ return false;
++ }
++ } else
++ {
++ if (!(map_index = find_available_block(false)))
++ {
++ MSG(INIT, "Cannot find block in pool\n");
++ return false;
++ }
++ }
++
++ // now let's update BMT
++ if (bad_index >= system_block_count) // mapped block become bad, find original bad block
++ {
++ for (i = 0; i < bmt_block_count; i++)
++ {
++ if (bmt.table[i].mapped_index == bad_index)
++ {
++ orig_bad_block = bmt.table[i].bad_index;
++ break;
++ }
++ }
++ // bmt.bad_count++;
++ MSG(INIT, "Mapped block becomes bad, orig bad block is 0x%x\n", orig_bad_block);
++
++ bmt.table[i].mapped_index = map_index;
++ } else
++ {
++ bmt.table[bmt.mapped_count].mapped_index = map_index;
++ bmt.table[bmt.mapped_count].bad_index = bad_index;
++ bmt.mapped_count++;
++ }
++
++ memset(oob_buf, 0xFF, sizeof(oob_buf));
++ fill_nand_bmt_buffer(&bmt, dat_buf, oob_buf);
++ if (!write_bmt_to_flash(dat_buf, oob_buf))
++ return false;
++
++ mark_block_bad_bmt(offset);
++
++ return true;
++}
++
++/*******************************************************************
++* [BMT Interface]
++*
++* Description:
++* Given an block index, return mapped index if it's mapped, else
++* return given index.
++*
++* Parameter:
++* index: given an block index. This value cannot exceed
++* system_block_count.
++*
++* Return NULL for failure
++*******************************************************************/
++u16 get_mapping_block_index(int index)
++{
++ int i;
++#ifndef MTK_NAND_BMT
++ return index;
++#endif
++ if (index > system_block_count)
++ {
++ return index;
++ }
++
++ for (i = 0; i < bmt.mapped_count; i++)
++ {
++ if (bmt.table[i].bad_index == index)
++ {
++ return bmt.table[i].mapped_index;
++ }
++ }
++
++ return index;
++}
++#ifdef __KERNEL_NAND__
++EXPORT_SYMBOL_GPL(init_bmt);
++EXPORT_SYMBOL_GPL(update_bmt);
++EXPORT_SYMBOL_GPL(get_mapping_block_index);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("MediaTek");
++MODULE_DESCRIPTION("Bad Block mapping management for MediaTek NAND Flash Driver");
++#endif
+--- /dev/null
++++ b/drivers/mtd/nand/bmt.h
+@@ -0,0 +1,80 @@
++#ifndef __BMT_H__
++#define __BMT_H__
++
++#include "nand_def.h"
++
++#if defined(__PRELOADER_NAND__)
++
++#include "nand.h"
++
++#elif defined(__UBOOT_NAND__)
++
++#include <linux/mtd/nand.h>
++#include "mtk_nand.h"
++
++#elif defined(__KERNEL_NAND__)
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/module.h>
++#include "mtk_nand.h"
++
++#endif
++
++
++#define MAX_BMT_SIZE (0x80)
++#define BMT_VERSION (1) // initial version
++
++#define MAIN_SIGNATURE_OFFSET (0)
++#define OOB_SIGNATURE_OFFSET (1)
++#define OOB_INDEX_OFFSET (29)
++#define OOB_INDEX_SIZE (2)
++#define FAKE_INDEX (0xAAAA)
++
++typedef struct _bmt_entry_
++{
++ u16 bad_index; // bad block index
++ u16 mapped_index; // mapping block index in the replace pool
++} bmt_entry;
++
++typedef enum
++{
++ UPDATE_ERASE_FAIL,
++ UPDATE_WRITE_FAIL,
++ UPDATE_UNMAPPED_BLOCK,
++ UPDATE_REASON_COUNT,
++} update_reason_t;
++
++typedef struct
++{
++ bmt_entry table[MAX_BMT_SIZE];
++ u8 version;
++ u8 mapped_count; // mapped block count in pool
++ u8 bad_count; // bad block count in pool. Not used in V1
++} bmt_struct;
++
++/***************************************************************
++* *
++* Interface BMT need to use *
++* *
++***************************************************************/
++extern bool mtk_nand_exec_read_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
++extern int mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs);
++extern int mtk_nand_erase_hw(struct mtd_info *mtd, int page);
++extern int mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t ofs);
++extern int mtk_nand_exec_write_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
++
++
++/***************************************************************
++* *
++* Different function interface for preloader/uboot/kernel *
++* *
++***************************************************************/
++void set_bad_index_to_oob(u8 * oob, u16 index);
++
++
++bmt_struct *init_bmt(struct nand_chip *nand, int size);
++bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob);
++unsigned short get_mapping_block_index(int index);
++
++#endif // #ifndef __BMT_H__
+--- /dev/null
++++ b/drivers/mtd/nand/dev-nand.c
+@@ -0,0 +1,63 @@
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++
++#include "mt6575_typedefs.h"
++
++#define RALINK_NAND_CTRL_BASE 0xBE003000
++#define NFI_base RALINK_NAND_CTRL_BASE
++#define RALINK_NANDECC_CTRL_BASE 0xBE003800
++#define NFIECC_base RALINK_NANDECC_CTRL_BASE
++#define MT7621_NFI_IRQ_ID SURFBOARDINT_NAND
++#define MT7621_NFIECC_IRQ_ID SURFBOARDINT_NAND_ECC
++
++#define SURFBOARDINT_NAND 22
++#define SURFBOARDINT_NAND_ECC 23
++
++static struct resource MT7621_resource_nand[] = {
++ {
++ .start = NFI_base,
++ .end = NFI_base + 0x1A0,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = NFIECC_base,
++ .end = NFIECC_base + 0x150,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = MT7621_NFI_IRQ_ID,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .start = MT7621_NFIECC_IRQ_ID,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device MT7621_nand_dev = {
++ .name = "MT7621-NAND",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(MT7621_resource_nand),
++ .resource = MT7621_resource_nand,
++ .dev = {
++ .platform_data = &mt7621_nand_hw,
++ },
++};
++
++
++int __init mtk_nand_register(void)
++{
++
++ int retval = 0;
++
++ retval = platform_device_register(&MT7621_nand_dev);
++ if (retval != 0) {
++ printk(KERN_ERR "register nand device fail\n");
++ return retval;
++ }
++
++
++ return retval;
++}
++arch_initcall(mtk_nand_register);
+--- /dev/null
++++ b/drivers/mtd/nand/mt6575_typedefs.h
+@@ -0,0 +1,340 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++/*****************************************************************************
++* Copyright Statement:
++* --------------------
++* This software is protected by Copyright and the information contained
++* herein is confidential. The software may not be copied and the information
++* contained herein may not be used or disclosed except with the written
++* permission of MediaTek Inc. (C) 2008
++*
++* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
++* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
++* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
++* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
++* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
++*
++* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
++* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
++* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++*
++* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
++* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
++* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
++* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
++* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
++*
++*****************************************************************************/
++
++#ifndef _MT6575_TYPEDEFS_H
++#define _MT6575_TYPEDEFS_H
++
++#if defined (__KERNEL_NAND__)
++#include <linux/bug.h>
++#else
++#define true 1
++#define false 0
++#define bool u8
++#endif
++
++// ---------------------------------------------------------------------------
++// Basic Type Definitions
++// ---------------------------------------------------------------------------
++
++typedef volatile unsigned char *P_kal_uint8;
++typedef volatile unsigned short *P_kal_uint16;
++typedef volatile unsigned int *P_kal_uint32;
++
++typedef long LONG;
++typedef unsigned char UBYTE;
++typedef short SHORT;
++
++typedef signed char kal_int8;
++typedef signed short kal_int16;
++typedef signed int kal_int32;
++typedef long long kal_int64;
++typedef unsigned char kal_uint8;
++typedef unsigned short kal_uint16;
++typedef unsigned int kal_uint32;
++typedef unsigned long long kal_uint64;
++typedef char kal_char;
++
++typedef unsigned int *UINT32P;
++typedef volatile unsigned short *UINT16P;
++typedef volatile unsigned char *UINT8P;
++typedef unsigned char *U8P;
++
++typedef volatile unsigned char *P_U8;
++typedef volatile signed char *P_S8;
++typedef volatile unsigned short *P_U16;
++typedef volatile signed short *P_S16;
++typedef volatile unsigned int *P_U32;
++typedef volatile signed int *P_S32;
++typedef unsigned long long *P_U64;
++typedef signed long long *P_S64;
++
++typedef unsigned char U8;
++typedef signed char S8;
++typedef unsigned short U16;
++typedef signed short S16;
++typedef unsigned int U32;
++typedef signed int S32;
++typedef unsigned long long U64;
++typedef signed long long S64;
++//typedef unsigned char bool;
++
++typedef unsigned char UINT8;
++typedef unsigned short UINT16;
++typedef unsigned int UINT32;
++typedef unsigned short USHORT;
++typedef signed char INT8;
++typedef signed short INT16;
++typedef signed int INT32;
++typedef unsigned int DWORD;
++typedef void VOID;
++typedef unsigned char BYTE;
++typedef float FLOAT;
++
++typedef char *LPCSTR;
++typedef short *LPWSTR;
++
++
++// ---------------------------------------------------------------------------
++// Constants
++// ---------------------------------------------------------------------------
++
++#define IMPORT EXTERN
++#ifndef __cplusplus
++ #define EXTERN extern
++#else
++ #define EXTERN extern "C"
++#endif
++#define LOCAL static
++#define GLOBAL
++#define EXPORT GLOBAL
++
++#define EQ ==
++#define NEQ !=
++#define AND &&
++#define OR ||
++#define XOR(A,B) ((!(A) AND (B)) OR ((A) AND !(B)))
++
++#ifndef FALSE
++ #define FALSE (0)
++#endif
++
++#ifndef TRUE
++ #define TRUE (1)
++#endif
++
++#ifndef NULL
++ #define NULL (0)
++#endif
++
++//enum boolean {false, true};
++enum {RX, TX, NONE};
++
++#ifndef BOOL
++typedef unsigned char BOOL;
++#endif
++
++typedef enum {
++ KAL_FALSE = 0,
++ KAL_TRUE = 1,
++} kal_bool;
++
++
++// ---------------------------------------------------------------------------
++// Type Casting
++// ---------------------------------------------------------------------------
++
++#define AS_INT32(x) (*(INT32 *)((void*)x))
++#define AS_INT16(x) (*(INT16 *)((void*)x))
++#define AS_INT8(x) (*(INT8 *)((void*)x))
++
++#define AS_UINT32(x) (*(UINT32 *)((void*)x))
++#define AS_UINT16(x) (*(UINT16 *)((void*)x))
++#define AS_UINT8(x) (*(UINT8 *)((void*)x))
++
++
++// ---------------------------------------------------------------------------
++// Register Manipulations
++// ---------------------------------------------------------------------------
++
++#define READ_REGISTER_UINT32(reg) \
++ (*(volatile UINT32 * const)(reg))
++
++#define WRITE_REGISTER_UINT32(reg, val) \
++ (*(volatile UINT32 * const)(reg)) = (val)
++
++#define READ_REGISTER_UINT16(reg) \
++ (*(volatile UINT16 * const)(reg))
++
++#define WRITE_REGISTER_UINT16(reg, val) \
++ (*(volatile UINT16 * const)(reg)) = (val)
++
++#define READ_REGISTER_UINT8(reg) \
++ (*(volatile UINT8 * const)(reg))
++
++#define WRITE_REGISTER_UINT8(reg, val) \
++ (*(volatile UINT8 * const)(reg)) = (val)
++
++#define INREG8(x) READ_REGISTER_UINT8((UINT8*)((void*)(x)))
++#define OUTREG8(x, y) WRITE_REGISTER_UINT8((UINT8*)((void*)(x)), (UINT8)(y))
++#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
++#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
++#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
++
++#define INREG16(x) READ_REGISTER_UINT16((UINT16*)((void*)(x)))
++#define OUTREG16(x, y) WRITE_REGISTER_UINT16((UINT16*)((void*)(x)),(UINT16)(y))
++#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
++#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
++#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
++
++#define INREG32(x) READ_REGISTER_UINT32((UINT32*)((void*)(x)))
++#define OUTREG32(x, y) WRITE_REGISTER_UINT32((UINT32*)((void*)(x)), (UINT32)(y))
++#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
++#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
++#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
++
++
++#define DRV_Reg8(addr) INREG8(addr)
++#define DRV_WriteReg8(addr, data) OUTREG8(addr, data)
++#define DRV_SetReg8(addr, data) SETREG8(addr, data)
++#define DRV_ClrReg8(addr, data) CLRREG8(addr, data)
++
++#define DRV_Reg16(addr) INREG16(addr)
++#define DRV_WriteReg16(addr, data) OUTREG16(addr, data)
++#define DRV_SetReg16(addr, data) SETREG16(addr, data)
++#define DRV_ClrReg16(addr, data) CLRREG16(addr, data)
++
++#define DRV_Reg32(addr) INREG32(addr)
++#define DRV_WriteReg32(addr, data) OUTREG32(addr, data)
++#define DRV_SetReg32(addr, data) SETREG32(addr, data)
++#define DRV_ClrReg32(addr, data) CLRREG32(addr, data)
++
++// !!! DEPRECATED, WILL BE REMOVED LATER !!!
++#define DRV_Reg(addr) DRV_Reg16(addr)
++#define DRV_WriteReg(addr, data) DRV_WriteReg16(addr, data)
++#define DRV_SetReg(addr, data) DRV_SetReg16(addr, data)
++#define DRV_ClrReg(addr, data) DRV_ClrReg16(addr, data)
++
++
++// ---------------------------------------------------------------------------
++// Compiler Time Deduction Macros
++// ---------------------------------------------------------------------------
++
++#define _MASK_OFFSET_1(x, n) ((x) & 0x1) ? (n) :
++#define _MASK_OFFSET_2(x, n) _MASK_OFFSET_1((x), (n)) _MASK_OFFSET_1((x) >> 1, (n) + 1)
++#define _MASK_OFFSET_4(x, n) _MASK_OFFSET_2((x), (n)) _MASK_OFFSET_2((x) >> 2, (n) + 2)
++#define _MASK_OFFSET_8(x, n) _MASK_OFFSET_4((x), (n)) _MASK_OFFSET_4((x) >> 4, (n) + 4)
++#define _MASK_OFFSET_16(x, n) _MASK_OFFSET_8((x), (n)) _MASK_OFFSET_8((x) >> 8, (n) + 8)
++#define _MASK_OFFSET_32(x, n) _MASK_OFFSET_16((x), (n)) _MASK_OFFSET_16((x) >> 16, (n) + 16)
++
++#define MASK_OFFSET_ERROR (0xFFFFFFFF)
++
++#define MASK_OFFSET(x) (_MASK_OFFSET_32(x, 0) MASK_OFFSET_ERROR)
++
++
++// ---------------------------------------------------------------------------
++// Assertions
++// ---------------------------------------------------------------------------
++
++#ifndef ASSERT
++ #define ASSERT(expr) BUG_ON(!(expr))
++#endif
++
++#ifndef NOT_IMPLEMENTED
++ #define NOT_IMPLEMENTED() BUG_ON(1)
++#endif
++
++#define STATIC_ASSERT(pred) STATIC_ASSERT_X(pred, __LINE__)
++#define STATIC_ASSERT_X(pred, line) STATIC_ASSERT_XX(pred, line)
++#define STATIC_ASSERT_XX(pred, line) \
++ extern char assertion_failed_at_##line[(pred) ? 1 : -1]
++
++// ---------------------------------------------------------------------------
++// Resolve Compiler Warnings
++// ---------------------------------------------------------------------------
++
++#define NOT_REFERENCED(x) { (x) = (x); }
++
++
++// ---------------------------------------------------------------------------
++// Utilities
++// ---------------------------------------------------------------------------
++
++#define MAXIMUM(A,B) (((A)>(B))?(A):(B))
++#define MINIMUM(A,B) (((A)<(B))?(A):(B))
++
++#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
++#define DVT_DELAYMACRO(u4Num) \
++{ \
++ UINT32 u4Count = 0 ; \
++ for (u4Count = 0; u4Count < u4Num; u4Count++ ); \
++} \
++
++#define A68351B 0
++#define B68351B 1
++#define B68351D 2
++#define B68351E 3
++#define UNKNOWN_IC_VERSION 0xFF
++
++/* NAND driver */
++struct mtk_nand_host_hw {
++ unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
++ unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
++ unsigned int nfi_cs_num; /* NFI_CS_NUM */
++ unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
++ unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
++ unsigned int nand_ecc_size;
++ unsigned int nand_ecc_bytes;
++ unsigned int nand_ecc_mode;
++};
++extern struct mtk_nand_host_hw mt7621_nand_hw;
++extern unsigned int CFG_BLOCKSIZE;
++
++#endif // _MT6575_TYPEDEFS_H
++
+--- /dev/null
++++ b/drivers/mtd/nand/mtk_nand.c
+@@ -0,0 +1,2304 @@
++/******************************************************************************
++* mtk_nand.c - MTK NAND Flash Device Driver
++ *
++* Copyright 2009-2012 MediaTek Co.,Ltd.
++ *
++* DESCRIPTION:
++* This file provid the other drivers nand relative functions
++ *
++* modification history
++* ----------------------------------------
++* v3.0, 11 Feb 2010, mtk
++* ----------------------------------------
++******************************************************************************/
++#include "nand_def.h"
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/wait.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/nand_ecc.h>
++#include <linux/dma-mapping.h>
++#include <linux/jiffies.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/time.h>
++#include <linux/mm.h>
++#include <asm/io.h>
++#include <asm/cacheflush.h>
++#include <asm/uaccess.h>
++#include <linux/miscdevice.h>
++#include "mtk_nand.h"
++#include "nand_device_list.h"
++
++#include "bmt.h"
++#include "partition.h"
++
++unsigned int CFG_BLOCKSIZE;
++
++static int shift_on_bbt = 0;
++extern void nand_bbt_set(struct mtd_info *mtd, int page, int flag);
++extern int nand_bbt_get(struct mtd_info *mtd, int page);
++int mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page);
++
++static const char * const probe_types[] = { "cmdlinepart", "ofpart", NULL };
++
++#define NAND_CMD_STATUS_MULTI 0x71
++
++void show_stack(struct task_struct *tsk, unsigned long *sp);
++extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
++extern void mt_irq_set_polarity(unsigned int irq,unsigned int polarity);
++
++struct mtk_nand_host mtk_nand_host; /* include mtd_info and nand_chip structs */
++struct mtk_nand_host_hw mt7621_nand_hw = {
++ .nfi_bus_width = 8,
++ .nfi_access_timing = NFI_DEFAULT_ACCESS_TIMING,
++ .nfi_cs_num = NFI_CS_NUM,
++ .nand_sec_size = 512,
++ .nand_sec_shift = 9,
++ .nand_ecc_size = 2048,
++ .nand_ecc_bytes = 32,
++ .nand_ecc_mode = NAND_ECC_HW,
++};
++
++
++/*******************************************************************************
++ * Gloable Varible Definition
++ *******************************************************************************/
++
++#define NFI_ISSUE_COMMAND(cmd, col_addr, row_addr, col_num, row_num) \
++ do { \
++ DRV_WriteReg(NFI_CMD_REG16,cmd);\
++ while (DRV_Reg32(NFI_STA_REG32) & STA_CMD_STATE);\
++ DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);\
++ DRV_WriteReg32(NFI_ROWADDR_REG32, row_addr);\
++ DRV_WriteReg(NFI_ADDRNOB_REG16, col_num | (row_num<<ADDR_ROW_NOB_SHIFT));\
++ while (DRV_Reg32(NFI_STA_REG32) & STA_ADDR_STATE);\
++ }while(0);
++
++//-------------------------------------------------------------------------------
++static struct NAND_CMD g_kCMD;
++static u32 g_u4ChipVer;
++bool g_bInitDone;
++static bool g_bcmdstatus;
++static u32 g_value = 0;
++static int g_page_size;
++
++BOOL g_bHwEcc = true;
++
++
++static u8 *local_buffer_16_align; // 16 byte aligned buffer, for HW issue
++static u8 local_buffer[4096 + 512];
++
++extern void nand_release_device(struct mtd_info *mtd);
++extern int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state);
++
++#if defined(MTK_NAND_BMT)
++static bmt_struct *g_bmt;
++#endif
++struct mtk_nand_host *host;
++extern struct mtd_partition g_pasStatic_Partition[];
++int part_num = NUM_PARTITIONS;
++int manu_id;
++int dev_id;
++
++static u8 local_oob_buf[NAND_MAX_OOBSIZE];
++
++static u8 nand_badblock_offset = 0;
++
++void nand_enable_clock(void)
++{
++ //enable_clock(MT65XX_PDN_PERI_NFI, "NAND");
++}
++
++void nand_disable_clock(void)
++{
++ //disable_clock(MT65XX_PDN_PERI_NFI, "NAND");
++}
++
++static struct nand_ecclayout nand_oob_16 = {
++ .eccbytes = 8,
++ .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
++ .oobfree = {{1, 6}, {0, 0}}
++};
++
++struct nand_ecclayout nand_oob_64 = {
++ .eccbytes = 32,
++ .eccpos = {32, 33, 34, 35, 36, 37, 38, 39,
++ 40, 41, 42, 43, 44, 45, 46, 47,
++ 48, 49, 50, 51, 52, 53, 54, 55,
++ 56, 57, 58, 59, 60, 61, 62, 63},
++ .oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 6}, {0, 0}}
++};
++
++struct nand_ecclayout nand_oob_128 = {
++ .eccbytes = 64,
++ .eccpos = {
++ 64, 65, 66, 67, 68, 69, 70, 71,
++ 72, 73, 74, 75, 76, 77, 78, 79,
++ 80, 81, 82, 83, 84, 85, 86, 86,
++ 88, 89, 90, 91, 92, 93, 94, 95,
++ 96, 97, 98, 99, 100, 101, 102, 103,
++ 104, 105, 106, 107, 108, 109, 110, 111,
++ 112, 113, 114, 115, 116, 117, 118, 119,
++ 120, 121, 122, 123, 124, 125, 126, 127},
++ .oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 7}, {33, 7}, {41, 7}, {49, 7}, {57, 6}}
++};
++
++flashdev_info devinfo;
++
++void dump_nfi(void)
++{
++}
++
++void dump_ecc(void)
++{
++}
++
++u32
++nand_virt_to_phys_add(u32 va)
++{
++ u32 pageOffset = (va & (PAGE_SIZE - 1));
++ pgd_t *pgd;
++ pmd_t *pmd;
++ pte_t *pte;
++ u32 pa;
++
++ if (virt_addr_valid(va))
++ return __virt_to_phys(va);
++
++ if (NULL == current) {
++ printk(KERN_ERR "[nand_virt_to_phys_add] ERROR ,current is NULL! \n");
++ return 0;
++ }
++
++ if (NULL == current->mm) {
++ printk(KERN_ERR "[nand_virt_to_phys_add] ERROR current->mm is NULL! tgid=0x%x, name=%s \n", current->tgid, current->comm);
++ return 0;
++ }
++
++ pgd = pgd_offset(current->mm, va); /* what is tsk->mm */
++ if (pgd_none(*pgd) || pgd_bad(*pgd)) {
++ printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pgd invalid! \n", va);
++ return 0;
++ }
++
++ pmd = pmd_offset((pud_t *)pgd, va);
++ if (pmd_none(*pmd) || pmd_bad(*pmd)) {
++ printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pmd invalid! \n", va);
++ return 0;
++ }
++
++ pte = pte_offset_map(pmd, va);
++ if (pte_present(*pte)) {
++ pa = (pte_val(*pte) & (PAGE_MASK)) | pageOffset;
++ return pa;
++ }
++
++ printk(KERN_ERR "[nand_virt_to_phys_add] ERROR va=0x%x, pte invalid! \n", va);
++ return 0;
++}
++EXPORT_SYMBOL(nand_virt_to_phys_add);
++
++bool
++get_device_info(u16 id, u32 ext_id, flashdev_info * pdevinfo)
++{
++ u32 index;
++ for (index = 0; gen_FlashTable[index].id != 0; index++) {
++ if (id == gen_FlashTable[index].id && ext_id == gen_FlashTable[index].ext_id) {
++ pdevinfo->id = gen_FlashTable[index].id;
++ pdevinfo->ext_id = gen_FlashTable[index].ext_id;
++ pdevinfo->blocksize = gen_FlashTable[index].blocksize;
++ pdevinfo->addr_cycle = gen_FlashTable[index].addr_cycle;
++ pdevinfo->iowidth = gen_FlashTable[index].iowidth;
++ pdevinfo->timmingsetting = gen_FlashTable[index].timmingsetting;
++ pdevinfo->advancedmode = gen_FlashTable[index].advancedmode;
++ pdevinfo->pagesize = gen_FlashTable[index].pagesize;
++ pdevinfo->sparesize = gen_FlashTable[index].sparesize;
++ pdevinfo->totalsize = gen_FlashTable[index].totalsize;
++ memcpy(pdevinfo->devciename, gen_FlashTable[index].devciename, sizeof(pdevinfo->devciename));
++ printk(KERN_INFO "Device found in MTK table, ID: %x, EXT_ID: %x\n", id, ext_id);
++
++ goto find;
++ }
++ }
++
++find:
++ if (0 == pdevinfo->id) {
++ printk(KERN_INFO "Device not found, ID: %x\n", id);
++ return false;
++ } else {
++ return true;
++ }
++}
++
++static void
++ECC_Config(struct mtk_nand_host_hw *hw,u32 ecc_bit)
++{
++ u32 u4ENCODESize;
++ u32 u4DECODESize;
++ u32 ecc_bit_cfg = ECC_CNFG_ECC4;
++
++ switch(ecc_bit){
++ case 4:
++ ecc_bit_cfg = ECC_CNFG_ECC4;
++ break;
++ case 8:
++ ecc_bit_cfg = ECC_CNFG_ECC8;
++ break;
++ case 10:
++ ecc_bit_cfg = ECC_CNFG_ECC10;
++ break;
++ case 12:
++ ecc_bit_cfg = ECC_CNFG_ECC12;
++ break;
++ default:
++ break;
++ }
++ DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
++ do {
++ } while (!DRV_Reg16(ECC_DECIDLE_REG16));
++
++ DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
++ do {
++ } while (!DRV_Reg32(ECC_ENCIDLE_REG32));
++
++ /* setup FDM register base */
++ DRV_WriteReg32(ECC_FDMADDR_REG32, NFI_FDM0L_REG32);
++
++ /* Sector + FDM */
++ u4ENCODESize = (hw->nand_sec_size + 8) << 3;
++ /* Sector + FDM + YAFFS2 meta data bits */
++ u4DECODESize = ((hw->nand_sec_size + 8) << 3) + ecc_bit * 13;
++
++ /* configure ECC decoder && encoder */
++ DRV_WriteReg32(ECC_DECCNFG_REG32, ecc_bit_cfg | DEC_CNFG_NFI | DEC_CNFG_EMPTY_EN | (u4DECODESize << DEC_CNFG_CODE_SHIFT));
++
++ DRV_WriteReg32(ECC_ENCCNFG_REG32, ecc_bit_cfg | ENC_CNFG_NFI | (u4ENCODESize << ENC_CNFG_MSG_SHIFT));
++ NFI_SET_REG32(ECC_DECCNFG_REG32, DEC_CNFG_EL);
++}
++
++static void
++ECC_Decode_Start(void)
++{
++ while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
++ ;
++ DRV_WriteReg16(ECC_DECCON_REG16, DEC_EN);
++}
++
++static void
++ECC_Decode_End(void)
++{
++ while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
++ ;
++ DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
++}
++
++static void
++ECC_Encode_Start(void)
++{
++ while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE))
++ ;
++ mb();
++ DRV_WriteReg16(ECC_ENCCON_REG16, ENC_EN);
++}
++
++static void
++ECC_Encode_End(void)
++{
++ /* wait for device returning idle */
++ while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE)) ;
++ mb();
++ DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
++}
++
++static bool
++mtk_nand_check_bch_error(struct mtd_info *mtd, u8 * pDataBuf, u32 u4SecIndex, u32 u4PageAddr)
++{
++ bool bRet = true;
++ u16 u2SectorDoneMask = 1 << u4SecIndex;
++ u32 u4ErrorNumDebug, i, u4ErrNum;
++ u32 timeout = 0xFFFF;
++ // int el;
++ u32 au4ErrBitLoc[6];
++ u32 u4ErrByteLoc, u4BitOffset;
++ u32 u4ErrBitLoc1th, u4ErrBitLoc2nd;
++
++ //4 // Wait for Decode Done
++ while (0 == (u2SectorDoneMask & DRV_Reg16(ECC_DECDONE_REG16))) {
++ timeout--;
++ if (0 == timeout)
++ return false;
++ }
++ /* We will manually correct the error bits in the last sector, not all the sectors of the page! */
++ memset(au4ErrBitLoc, 0x0, sizeof(au4ErrBitLoc));
++ u4ErrorNumDebug = DRV_Reg32(ECC_DECENUM_REG32);
++ u4ErrNum = DRV_Reg32(ECC_DECENUM_REG32) >> (u4SecIndex << 2);
++ u4ErrNum &= 0xF;
++
++ if (u4ErrNum) {
++ if (0xF == u4ErrNum) {
++ mtd->ecc_stats.failed++;
++ bRet = false;
++ //printk(KERN_ERR"UnCorrectable at PageAddr=%d\n", u4PageAddr);
++ } else {
++ for (i = 0; i < ((u4ErrNum + 1) >> 1); ++i) {
++ au4ErrBitLoc[i] = DRV_Reg32(ECC_DECEL0_REG32 + i);
++ u4ErrBitLoc1th = au4ErrBitLoc[i] & 0x1FFF;
++ if (u4ErrBitLoc1th < 0x1000) {
++ u4ErrByteLoc = u4ErrBitLoc1th / 8;
++ u4BitOffset = u4ErrBitLoc1th % 8;
++ pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
++ mtd->ecc_stats.corrected++;
++ } else {
++ mtd->ecc_stats.failed++;
++ }
++ u4ErrBitLoc2nd = (au4ErrBitLoc[i] >> 16) & 0x1FFF;
++ if (0 != u4ErrBitLoc2nd) {
++ if (u4ErrBitLoc2nd < 0x1000) {
++ u4ErrByteLoc = u4ErrBitLoc2nd / 8;
++ u4BitOffset = u4ErrBitLoc2nd % 8;
++ pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
++ mtd->ecc_stats.corrected++;
++ } else {
++ mtd->ecc_stats.failed++;
++ //printk(KERN_ERR"UnCorrectable High ErrLoc=%d\n", au4ErrBitLoc[i]);
++ }
++ }
++ }
++ }
++ if (0 == (DRV_Reg16(ECC_DECFER_REG16) & (1 << u4SecIndex)))
++ bRet = false;
++ }
++ return bRet;
++}
++
++static bool
++mtk_nand_RFIFOValidSize(u16 u2Size)
++{
++ u32 timeout = 0xFFFF;
++ while (FIFO_RD_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) < u2Size) {
++ timeout--;
++ if (0 == timeout)
++ return false;
++ }
++ return true;
++}
++
++static bool
++mtk_nand_WFIFOValidSize(u16 u2Size)
++{
++ u32 timeout = 0xFFFF;
++
++ while (FIFO_WR_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) > u2Size) {
++ timeout--;
++ if (0 == timeout)
++ return false;
++ }
++ return true;
++}
++
++static bool
++mtk_nand_status_ready(u32 u4Status)
++{
++ u32 timeout = 0xFFFF;
++
++ while ((DRV_Reg32(NFI_STA_REG32) & u4Status) != 0) {
++ timeout--;
++ if (0 == timeout)
++ return false;
++ }
++ return true;
++}
++
++static bool
++mtk_nand_reset(void)
++{
++ int timeout = 0xFFFF;
++ if (DRV_Reg16(NFI_MASTERSTA_REG16)) {
++ mb();
++ DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
++ while (DRV_Reg16(NFI_MASTERSTA_REG16)) {
++ timeout--;
++ if (!timeout)
++ MSG(INIT, "Wait for NFI_MASTERSTA timeout\n");
++ }
++ }
++ /* issue reset operation */
++ mb();
++ DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
++
++ return mtk_nand_status_ready(STA_NFI_FSM_MASK | STA_NAND_BUSY) && mtk_nand_RFIFOValidSize(0) && mtk_nand_WFIFOValidSize(0);
++}
++
++static void
++mtk_nand_set_mode(u16 u2OpMode)
++{
++ u16 u2Mode = DRV_Reg16(NFI_CNFG_REG16);
++ u2Mode &= ~CNFG_OP_MODE_MASK;
++ u2Mode |= u2OpMode;
++ DRV_WriteReg16(NFI_CNFG_REG16, u2Mode);
++}
++
++static void
++mtk_nand_set_autoformat(bool bEnable)
++{
++ if (bEnable)
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
++ else
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
++}
++
++static void
++mtk_nand_configure_fdm(u16 u2FDMSize)
++{
++ NFI_CLN_REG16(NFI_PAGEFMT_REG16, PAGEFMT_FDM_MASK | PAGEFMT_FDM_ECC_MASK);
++ NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_SHIFT);
++ NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_ECC_SHIFT);
++}
++
++static void
++mtk_nand_configure_lock(void)
++{
++ u32 u4WriteColNOB = 2;
++ u32 u4WriteRowNOB = 3;
++ u32 u4EraseColNOB = 0;
++ u32 u4EraseRowNOB = 3;
++ DRV_WriteReg16(NFI_LOCKANOB_REG16,
++ (u4WriteColNOB << PROG_CADD_NOB_SHIFT) | (u4WriteRowNOB << PROG_RADD_NOB_SHIFT) | (u4EraseColNOB << ERASE_CADD_NOB_SHIFT) | (u4EraseRowNOB << ERASE_RADD_NOB_SHIFT));
++
++ if (CHIPVER_ECO_1 == g_u4ChipVer) {
++ int i;
++ for (i = 0; i < 16; ++i) {
++ DRV_WriteReg32(NFI_LOCK00ADD_REG32 + (i << 1), 0xFFFFFFFF);
++ DRV_WriteReg32(NFI_LOCK00FMT_REG32 + (i << 1), 0xFFFFFFFF);
++ }
++ //DRV_WriteReg16(NFI_LOCKANOB_REG16, 0x0);
++ DRV_WriteReg32(NFI_LOCKCON_REG32, 0xFFFFFFFF);
++ DRV_WriteReg16(NFI_LOCK_REG16, NFI_LOCK_ON);
++ }
++}
++
++static bool
++mtk_nand_pio_ready(void)
++{
++ int count = 0;
++ while (!(DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1)) {
++ count++;
++ if (count > 0xffff) {
++ printk("PIO_DIRDY timeout\n");
++ return false;
++ }
++ }
++
++ return true;
++}
++
++static bool
++mtk_nand_set_command(u16 command)
++{
++ mb();
++ DRV_WriteReg16(NFI_CMD_REG16, command);
++ return mtk_nand_status_ready(STA_CMD_STATE);
++}
++
++static bool
++mtk_nand_set_address(u32 u4ColAddr, u32 u4RowAddr, u16 u2ColNOB, u16 u2RowNOB)
++{
++ mb();
++ DRV_WriteReg32(NFI_COLADDR_REG32, u4ColAddr);
++ DRV_WriteReg32(NFI_ROWADDR_REG32, u4RowAddr);
++ DRV_WriteReg16(NFI_ADDRNOB_REG16, u2ColNOB | (u2RowNOB << ADDR_ROW_NOB_SHIFT));
++ return mtk_nand_status_ready(STA_ADDR_STATE);
++}
++
++static bool
++mtk_nand_check_RW_count(u16 u2WriteSize)
++{
++ u32 timeout = 0xFFFF;
++ u16 u2SecNum = u2WriteSize >> 9;
++
++ while (ADDRCNTR_CNTR(DRV_Reg16(NFI_ADDRCNTR_REG16)) < u2SecNum) {
++ timeout--;
++ if (0 == timeout) {
++ printk(KERN_INFO "[%s] timeout\n", __FUNCTION__);
++ return false;
++ }
++ }
++ return true;
++}
++
++static bool
++mtk_nand_ready_for_read(struct nand_chip *nand, u32 u4RowAddr, u32 u4ColAddr, bool full, u8 * buf)
++{
++ /* Reset NFI HW internal state machine and flush NFI in/out FIFO */
++ bool bRet = false;
++ u16 sec_num = 1 << (nand->page_shift - 9);
++ u32 col_addr = u4ColAddr;
++ u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
++ if (nand->options & NAND_BUSWIDTH_16)
++ col_addr /= 2;
++
++ if (!mtk_nand_reset())
++ goto cleanup;
++ if (g_bHwEcc) {
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ } else {
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ }
++
++ mtk_nand_set_mode(CNFG_OP_READ);
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
++ DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
++
++ if (full) {
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++
++ if (g_bHwEcc)
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ else
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ } else {
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++ }
++
++ mtk_nand_set_autoformat(full);
++ if (full)
++ if (g_bHwEcc)
++ ECC_Decode_Start();
++ if (!mtk_nand_set_command(NAND_CMD_READ0))
++ goto cleanup;
++ if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
++ goto cleanup;
++ if (!mtk_nand_set_command(NAND_CMD_READSTART))
++ goto cleanup;
++ if (!mtk_nand_status_ready(STA_NAND_BUSY))
++ goto cleanup;
++
++ bRet = true;
++
++cleanup:
++ return bRet;
++}
++
++static bool
++mtk_nand_ready_for_write(struct nand_chip *nand, u32 u4RowAddr, u32 col_addr, bool full, u8 * buf)
++{
++ bool bRet = false;
++ u32 sec_num = 1 << (nand->page_shift - 9);
++ u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
++ if (nand->options & NAND_BUSWIDTH_16)
++ col_addr /= 2;
++
++ /* Reset NFI HW internal state machine and flush NFI in/out FIFO */
++ if (!mtk_nand_reset())
++ return false;
++
++ mtk_nand_set_mode(CNFG_OP_PRGM);
++
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
++
++ DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
++
++ if (full) {
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++ if (g_bHwEcc)
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ else
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ } else {
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++ }
++
++ mtk_nand_set_autoformat(full);
++
++ if (full)
++ if (g_bHwEcc)
++ ECC_Encode_Start();
++
++ if (!mtk_nand_set_command(NAND_CMD_SEQIN))
++ goto cleanup;
++ //1 FIXED ME: For Any Kind of AddrCycle
++ if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
++ goto cleanup;
++
++ if (!mtk_nand_status_ready(STA_NAND_BUSY))
++ goto cleanup;
++
++ bRet = true;
++
++cleanup:
++ return bRet;
++}
++
++static bool
++mtk_nand_check_dececc_done(u32 u4SecNum)
++{
++ u32 timeout, dec_mask;
++
++ timeout = 0xffff;
++ dec_mask = (1 << u4SecNum) - 1;
++ while ((dec_mask != DRV_Reg(ECC_DECDONE_REG16)) && timeout > 0)
++ timeout--;
++ if (timeout == 0) {
++ MSG(VERIFY, "ECC_DECDONE: timeout\n");
++ return false;
++ }
++ return true;
++}
++
++static bool
++mtk_nand_mcu_read_data(u8 * buf, u32 length)
++{
++ int timeout = 0xffff;
++ u32 i;
++ u32 *buf32 = (u32 *) buf;
++ if ((u32) buf % 4 || length % 4)
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++ else
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++
++ //DRV_WriteReg32(NFI_STRADDR_REG32, 0);
++ mb();
++ NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BRD);
++
++ if ((u32) buf % 4 || length % 4) {
++ for (i = 0; (i < (length)) && (timeout > 0);) {
++ if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++ *buf++ = (u8) DRV_Reg32(NFI_DATAR_REG32);
++ i++;
++ } else {
++ timeout--;
++ }
++ if (0 == timeout) {
++ printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++ dump_nfi();
++ return false;
++ }
++ }
++ } else {
++ for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
++ if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++ *buf32++ = DRV_Reg32(NFI_DATAR_REG32);
++ i++;
++ } else {
++ timeout--;
++ }
++ if (0 == timeout) {
++ printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++ dump_nfi();
++ return false;
++ }
++ }
++ }
++ return true;
++}
++
++static bool
++mtk_nand_read_page_data(struct mtd_info *mtd, u8 * pDataBuf, u32 u4Size)
++{
++ return mtk_nand_mcu_read_data(pDataBuf, u4Size);
++}
++
++static bool
++mtk_nand_mcu_write_data(struct mtd_info *mtd, const u8 * buf, u32 length)
++{
++ u32 timeout = 0xFFFF;
++ u32 i;
++ u32 *pBuf32;
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++ mb();
++ NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BWR);
++ pBuf32 = (u32 *) buf;
++
++ if ((u32) buf % 4 || length % 4)
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++ else
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++
++ if ((u32) buf % 4 || length % 4) {
++ for (i = 0; (i < (length)) && (timeout > 0);) {
++ if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++ DRV_WriteReg32(NFI_DATAW_REG32, *buf++);
++ i++;
++ } else {
++ timeout--;
++ }
++ if (0 == timeout) {
++ printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++ dump_nfi();
++ return false;
++ }
++ }
++ } else {
++ for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
++ if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++ DRV_WriteReg32(NFI_DATAW_REG32, *pBuf32++);
++ i++;
++ } else {
++ timeout--;
++ }
++ if (0 == timeout) {
++ printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++ dump_nfi();
++ return false;
++ }
++ }
++ }
++
++ return true;
++}
++
++static bool
++mtk_nand_write_page_data(struct mtd_info *mtd, u8 * buf, u32 size)
++{
++ return mtk_nand_mcu_write_data(mtd, buf, size);
++}
++
++static void
++mtk_nand_read_fdm_data(u8 * pDataBuf, u32 u4SecNum)
++{
++ u32 i;
++ u32 *pBuf32 = (u32 *) pDataBuf;
++
++ if (pBuf32) {
++ for (i = 0; i < u4SecNum; ++i) {
++ *pBuf32++ = DRV_Reg32(NFI_FDM0L_REG32 + (i << 1));
++ *pBuf32++ = DRV_Reg32(NFI_FDM0M_REG32 + (i << 1));
++ }
++ }
++}
++
++static u8 fdm_buf[64];
++static void
++mtk_nand_write_fdm_data(struct nand_chip *chip, u8 * pDataBuf, u32 u4SecNum)
++{
++ u32 i, j;
++ u8 checksum = 0;
++ bool empty = true;
++ struct nand_oobfree *free_entry;
++ u32 *pBuf32;
++
++ memcpy(fdm_buf, pDataBuf, u4SecNum * 8);
++
++ free_entry = chip->ecc.layout->oobfree;
++ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free_entry[i].length; i++) {
++ for (j = 0; j < free_entry[i].length; j++) {
++ if (pDataBuf[free_entry[i].offset + j] != 0xFF)
++ empty = false;
++ checksum ^= pDataBuf[free_entry[i].offset + j];
++ }
++ }
++
++ if (!empty) {
++ fdm_buf[free_entry[i - 1].offset + free_entry[i - 1].length] = checksum;
++ }
++
++ pBuf32 = (u32 *) fdm_buf;
++ for (i = 0; i < u4SecNum; ++i) {
++ DRV_WriteReg32(NFI_FDM0L_REG32 + (i << 1), *pBuf32++);
++ DRV_WriteReg32(NFI_FDM0M_REG32 + (i << 1), *pBuf32++);
++ }
++}
++
++static void
++mtk_nand_stop_read(void)
++{
++ NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
++ mtk_nand_reset();
++ if (g_bHwEcc)
++ ECC_Decode_End();
++ DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
++}
++
++static void
++mtk_nand_stop_write(void)
++{
++ NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
++ if (g_bHwEcc)
++ ECC_Encode_End();
++ DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
++}
++
++bool
++mtk_nand_exec_read_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
++{
++ u8 *buf;
++ bool bRet = true;
++ struct nand_chip *nand = mtd->priv;
++ u32 u4SecNum = u4PageSize >> 9;
++
++ if (((u32) pPageBuf % 16) && local_buffer_16_align)
++ buf = local_buffer_16_align;
++ else
++ buf = pPageBuf;
++ if (mtk_nand_ready_for_read(nand, u4RowAddr, 0, true, buf)) {
++ int j;
++ for (j = 0 ; j < u4SecNum; j++) {
++ if (!mtk_nand_read_page_data(mtd, buf+j*512, 512))
++ bRet = false;
++ if(g_bHwEcc && !mtk_nand_check_dececc_done(j+1))
++ bRet = false;
++ if(g_bHwEcc && !mtk_nand_check_bch_error(mtd, buf+j*512, j, u4RowAddr))
++ bRet = false;
++ }
++ if (!mtk_nand_status_ready(STA_NAND_BUSY))
++ bRet = false;
++
++ mtk_nand_read_fdm_data(pFDMBuf, u4SecNum);
++ mtk_nand_stop_read();
++ }
++
++ if (buf == local_buffer_16_align)
++ memcpy(pPageBuf, buf, u4PageSize);
++
++ return bRet;
++}
++
++int
++mtk_nand_exec_write_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
++{
++ struct nand_chip *chip = mtd->priv;
++ u32 u4SecNum = u4PageSize >> 9;
++ u8 *buf;
++ u8 status;
++
++ MSG(WRITE, "mtk_nand_exec_write_page, page: 0x%x\n", u4RowAddr);
++
++ if (((u32) pPageBuf % 16) && local_buffer_16_align) {
++ printk(KERN_INFO "Data buffer not 16 bytes aligned: %p\n", pPageBuf);
++ memcpy(local_buffer_16_align, pPageBuf, mtd->writesize);
++ buf = local_buffer_16_align;
++ } else
++ buf = pPageBuf;
++
++ if (mtk_nand_ready_for_write(chip, u4RowAddr, 0, true, buf)) {
++ mtk_nand_write_fdm_data(chip, pFDMBuf, u4SecNum);
++ (void)mtk_nand_write_page_data(mtd, buf, u4PageSize);
++ (void)mtk_nand_check_RW_count(u4PageSize);
++ mtk_nand_stop_write();
++ (void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
++ while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY) ;
++ }
++
++ status = chip->waitfunc(mtd, chip);
++ if (status & NAND_STATUS_FAIL)
++ return -EIO;
++ return 0;
++}
++
++static int
++get_start_end_block(struct mtd_info *mtd, int block, int *start_blk, int *end_blk)
++{
++ struct nand_chip *chip = mtd->priv;
++ int i;
++
++ *start_blk = 0;
++ for (i = 0; i <= part_num; i++)
++ {
++ if (i == part_num)
++ {
++ // try the last reset partition
++ *end_blk = (chip->chipsize >> chip->phys_erase_shift) - 1;
++ if (*start_blk <= *end_blk)
++ {
++ if ((block >= *start_blk) && (block <= *end_blk))
++ break;
++ }
++ }
++ // skip All partition entry
++ else if (g_pasStatic_Partition[i].size == MTDPART_SIZ_FULL)
++ {
++ continue;
++ }
++ *end_blk = *start_blk + (g_pasStatic_Partition[i].size >> chip->phys_erase_shift) - 1;
++ if ((block >= *start_blk) && (block <= *end_blk))
++ break;
++ *start_blk = *end_blk + 1;
++ }
++ if (*start_blk > *end_blk)
++ {
++ return -1;
++ }
++ return 0;
++}
++
++static int
++block_remap(struct mtd_info *mtd, int block)
++{
++ struct nand_chip *chip = mtd->priv;
++ int start_blk, end_blk;
++ int j, block_offset;
++ int bad_block = 0;
++
++ if (chip->bbt == NULL) {
++ printk("ERROR!! no bbt table for block_remap\n");
++ return -1;
++ }
++
++ if (get_start_end_block(mtd, block, &start_blk, &end_blk) < 0) {
++ printk("ERROR!! can not find start_blk and end_blk\n");
++ return -1;
++ }
++
++ block_offset = block - start_blk;
++ for (j = start_blk; j <= end_blk;j++) {
++ if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) == 0x0) {
++ if (!block_offset)
++ break;
++ block_offset--;
++ } else {
++ bad_block++;
++ }
++ }
++ if (j <= end_blk) {
++ return j;
++ } else {
++ // remap to the bad block
++ for (j = end_blk; bad_block > 0; j--)
++ {
++ if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) != 0x0)
++ {
++ bad_block--;
++ if (bad_block <= block_offset)
++ return j;
++ }
++ }
++ }
++
++ printk("Error!! block_remap error\n");
++ return -1;
++}
++
++int
++check_block_remap(struct mtd_info *mtd, int block)
++{
++ if (shift_on_bbt)
++ return block_remap(mtd, block);
++ else
++ return block;
++}
++EXPORT_SYMBOL(check_block_remap);
++
++
++static int
++write_next_on_fail(struct mtd_info *mtd, char *write_buf, int page, int * to_blk)
++{
++ struct nand_chip *chip = mtd->priv;
++ int i, j, to_page = 0, first_page;
++ char *buf, *oob;
++ int start_blk = 0, end_blk;
++ int mapped_block;
++ int page_per_block_bit = chip->phys_erase_shift - chip->page_shift;
++ int block = page >> page_per_block_bit;
++
++ // find next available block in the same MTD partition
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++
++ get_start_end_block(mtd, block, &start_blk, &end_blk);
++
++ buf = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL | GFP_DMA);
++ if (buf == NULL)
++ return -1;
++
++ oob = buf + mtd->writesize;
++ for ((*to_blk) = block + 1; (*to_blk) <= end_blk ; (*to_blk)++) {
++ if (nand_bbt_get(mtd, (*to_blk) << page_per_block_bit) == 0) {
++ int status;
++ status = mtk_nand_erase_hw(mtd, (*to_blk) << page_per_block_bit);
++ if (status & NAND_STATUS_FAIL) {
++ mtk_nand_block_markbad_hw(mtd, (*to_blk) << chip->phys_erase_shift);
++ nand_bbt_set(mtd, (*to_blk) << page_per_block_bit, 0x3);
++ } else {
++ /* good block */
++ to_page = (*to_blk) << page_per_block_bit;
++ break;
++ }
++ }
++ }
++
++ if (!to_page) {
++ kfree(buf);
++ return -1;
++ }
++
++ first_page = (page >> page_per_block_bit) << page_per_block_bit;
++ for (i = 0; i < (1 << page_per_block_bit); i++) {
++ if ((first_page + i) != page) {
++ mtk_nand_read_oob_hw(mtd, chip, (first_page+i));
++ for (j = 0; j < mtd->oobsize; j++)
++ if (chip->oob_poi[j] != (unsigned char)0xff)
++ break;
++ if (j < mtd->oobsize) {
++ mtk_nand_exec_read_page(mtd, (first_page+i), mtd->writesize, buf, oob);
++ memset(oob, 0xff, mtd->oobsize);
++ if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)buf, oob) != 0) {
++ int ret, new_blk = 0;
++ nand_bbt_set(mtd, to_page, 0x3);
++ ret = write_next_on_fail(mtd, buf, to_page + i, &new_blk);
++ if (ret) {
++ kfree(buf);
++ mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++ return ret;
++ }
++ mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++ *to_blk = new_blk;
++ to_page = ((*to_blk) << page_per_block_bit);
++ }
++ }
++ } else {
++ memset(chip->oob_poi, 0xff, mtd->oobsize);
++ if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)write_buf, chip->oob_poi) != 0) {
++ int ret, new_blk = 0;
++ nand_bbt_set(mtd, to_page, 0x3);
++ ret = write_next_on_fail(mtd, write_buf, to_page + i, &new_blk);
++ if (ret) {
++ kfree(buf);
++ mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++ return ret;
++ }
++ mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++ *to_blk = new_blk;
++ to_page = ((*to_blk) << page_per_block_bit);
++ }
++ }
++ }
++
++ kfree(buf);
++
++ return 0;
++}
++
++static int
++mtk_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset,
++ int data_len, const u8 * buf, int oob_required, int page, int cached, int raw)
++{
++ int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++ int block = page / page_per_block;
++ u16 page_in_block = page % page_per_block;
++ int mapped_block = block;
++
++#if defined(MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++ // write bad index into oob
++ if (mapped_block != block)
++ set_bad_index_to_oob(chip->oob_poi, block);
++ else
++ set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
++#else
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++ return NAND_STATUS_FAIL;
++ }
++#endif
++ do {
++ if (mtk_nand_exec_write_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, (u8 *)buf, chip->oob_poi)) {
++ MSG(INIT, "write fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
++#if defined(MTK_NAND_BMT)
++ if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift, UPDATE_WRITE_FAIL, (u8 *) buf, chip->oob_poi)) {
++ MSG(INIT, "Update BMT success\n");
++ return 0;
++ } else {
++ MSG(INIT, "Update BMT fail\n");
++ return -EIO;
++ }
++#else
++ {
++ int new_blk;
++ nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
++ if (write_next_on_fail(mtd, (char *)buf, page_in_block + mapped_block * page_per_block, &new_blk) != 0)
++ {
++ mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++ return NAND_STATUS_FAIL;
++ }
++ mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++ break;
++ }
++#endif
++ } else
++ break;
++ } while(1);
++
++ return 0;
++}
++
++static void
++mtk_nand_command_bp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
++{
++ struct nand_chip *nand = mtd->priv;
++
++ switch (command) {
++ case NAND_CMD_SEQIN:
++ memset(g_kCMD.au1OOB, 0xFF, sizeof(g_kCMD.au1OOB));
++ g_kCMD.pDataBuf = NULL;
++ g_kCMD.u4RowAddr = page_addr;
++ g_kCMD.u4ColAddr = column;
++ break;
++
++ case NAND_CMD_PAGEPROG:
++ if (g_kCMD.pDataBuf || (0xFF != g_kCMD.au1OOB[nand_badblock_offset])) {
++ u8 *pDataBuf = g_kCMD.pDataBuf ? g_kCMD.pDataBuf : nand->buffers->databuf;
++ mtk_nand_exec_write_page(mtd, g_kCMD.u4RowAddr, mtd->writesize, pDataBuf, g_kCMD.au1OOB);
++ g_kCMD.u4RowAddr = (u32) - 1;
++ g_kCMD.u4OOBRowAddr = (u32) - 1;
++ }
++ break;
++
++ case NAND_CMD_READOOB:
++ g_kCMD.u4RowAddr = page_addr;
++ g_kCMD.u4ColAddr = column + mtd->writesize;
++ break;
++
++ case NAND_CMD_READ0:
++ g_kCMD.u4RowAddr = page_addr;
++ g_kCMD.u4ColAddr = column;
++ break;
++
++ case NAND_CMD_ERASE1:
++ nand->state=FL_ERASING;
++ (void)mtk_nand_reset();
++ mtk_nand_set_mode(CNFG_OP_ERASE);
++ (void)mtk_nand_set_command(NAND_CMD_ERASE1);
++ (void)mtk_nand_set_address(0, page_addr, 0, devinfo.addr_cycle - 2);
++ break;
++
++ case NAND_CMD_ERASE2:
++ (void)mtk_nand_set_command(NAND_CMD_ERASE2);
++ while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
++ ;
++ break;
++
++ case NAND_CMD_STATUS:
++ (void)mtk_nand_reset();
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++ mtk_nand_set_mode(CNFG_OP_SRD);
++ mtk_nand_set_mode(CNFG_READ_EN);
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ (void)mtk_nand_set_command(NAND_CMD_STATUS);
++ NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
++ mb();
++ DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD | (1 << CON_NFI_NOB_SHIFT));
++ g_bcmdstatus = true;
++ break;
++
++ case NAND_CMD_RESET:
++ (void)mtk_nand_reset();
++ DRV_WriteReg16(NFI_INTR_EN_REG16, INTR_RST_DONE_EN);
++ (void)mtk_nand_set_command(NAND_CMD_RESET);
++ DRV_WriteReg16(NFI_BASE+0x44, 0xF1);
++ while(!(DRV_Reg16(NFI_INTR_REG16)&INTR_RST_DONE_EN))
++ ;
++ break;
++
++ case NAND_CMD_READID:
++ mtk_nand_reset();
++ /* Disable HW ECC */
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN | CNFG_BYTE_RW);
++ (void)mtk_nand_reset();
++ mb();
++ mtk_nand_set_mode(CNFG_OP_SRD);
++ (void)mtk_nand_set_command(NAND_CMD_READID);
++ (void)mtk_nand_set_address(0, 0, 1, 0);
++ DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD);
++ while (DRV_Reg32(NFI_STA_REG32) & STA_DATAR_STATE)
++ ;
++ break;
++
++ default:
++ BUG();
++ break;
++ }
++}
++
++static void
++mtk_nand_select_chip(struct mtd_info *mtd, int chip)
++{
++ if ((chip == -1) && (false == g_bInitDone)) {
++ struct nand_chip *nand = mtd->priv;
++ struct mtk_nand_host *host = nand->priv;
++ struct mtk_nand_host_hw *hw = host->hw;
++ u32 spare_per_sector = mtd->oobsize / (mtd->writesize / 512);
++ u32 ecc_bit = 4;
++ u32 spare_bit = PAGEFMT_SPARE_16;
++
++ if (spare_per_sector >= 28) {
++ spare_bit = PAGEFMT_SPARE_28;
++ ecc_bit = 12;
++ spare_per_sector = 28;
++ } else if (spare_per_sector >= 27) {
++ spare_bit = PAGEFMT_SPARE_27;
++ ecc_bit = 8;
++ spare_per_sector = 27;
++ } else if (spare_per_sector >= 26) {
++ spare_bit = PAGEFMT_SPARE_26;
++ ecc_bit = 8;
++ spare_per_sector = 26;
++ } else if (spare_per_sector >= 16) {
++ spare_bit = PAGEFMT_SPARE_16;
++ ecc_bit = 4;
++ spare_per_sector = 16;
++ } else {
++ MSG(INIT, "[NAND]: NFI not support oobsize: %x\n", spare_per_sector);
++ ASSERT(0);
++ }
++ mtd->oobsize = spare_per_sector*(mtd->writesize/512);
++ MSG(INIT, "[NAND]select ecc bit:%d, sparesize :%d spare_per_sector=%d\n",ecc_bit,mtd->oobsize,spare_per_sector);
++ /* Setup PageFormat */
++ if (4096 == mtd->writesize) {
++ NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_4K);
++ nand->cmdfunc = mtk_nand_command_bp;
++ } else if (2048 == mtd->writesize) {
++ NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_2K);
++ nand->cmdfunc = mtk_nand_command_bp;
++ }
++ ECC_Config(hw,ecc_bit);
++ g_bInitDone = true;
++ }
++ switch (chip) {
++ case -1:
++ break;
++ case 0:
++ case 1:
++ /* Jun Shen, 2011.04.13 */
++ /* Note: MT6577 EVB NAND is mounted on CS0, but FPGA is CS1 */
++ DRV_WriteReg16(NFI_CSEL_REG16, chip);
++ /* Jun Shen, 2011.04.13 */
++ break;
++ }
++}
++
++static uint8_t
++mtk_nand_read_byte(struct mtd_info *mtd)
++{
++ uint8_t retval = 0;
++
++ if (!mtk_nand_pio_ready()) {
++ printk("pio ready timeout\n");
++ retval = false;
++ }
++
++ if (g_bcmdstatus) {
++ retval = DRV_Reg8(NFI_DATAR_REG32);
++ NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
++ mtk_nand_reset();
++ if (g_bHwEcc) {
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ } else {
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ }
++ g_bcmdstatus = false;
++ } else
++ retval = DRV_Reg8(NFI_DATAR_REG32);
++
++ return retval;
++}
++
++static void
++mtk_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
++{
++ struct nand_chip *nand = (struct nand_chip *)mtd->priv;
++ struct NAND_CMD *pkCMD = &g_kCMD;
++ u32 u4ColAddr = pkCMD->u4ColAddr;
++ u32 u4PageSize = mtd->writesize;
++
++ if (u4ColAddr < u4PageSize) {
++ if ((u4ColAddr == 0) && (len >= u4PageSize)) {
++ mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, pkCMD->au1OOB);
++ if (len > u4PageSize) {
++ u32 u4Size = min(len - u4PageSize, sizeof(pkCMD->au1OOB));
++ memcpy(buf + u4PageSize, pkCMD->au1OOB, u4Size);
++ }
++ } else {
++ mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
++ memcpy(buf, nand->buffers->databuf + u4ColAddr, len);
++ }
++ pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
++ } else {
++ u32 u4Offset = u4ColAddr - u4PageSize;
++ u32 u4Size = min(len - u4Offset, sizeof(pkCMD->au1OOB));
++ if (pkCMD->u4OOBRowAddr != pkCMD->u4RowAddr) {
++ mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
++ pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
++ }
++ memcpy(buf, pkCMD->au1OOB + u4Offset, u4Size);
++ }
++ pkCMD->u4ColAddr += len;
++}
++
++static void
++mtk_nand_write_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
++{
++ struct NAND_CMD *pkCMD = &g_kCMD;
++ u32 u4ColAddr = pkCMD->u4ColAddr;
++ u32 u4PageSize = mtd->writesize;
++ int i4Size, i;
++
++ if (u4ColAddr >= u4PageSize) {
++ u32 u4Offset = u4ColAddr - u4PageSize;
++ u8 *pOOB = pkCMD->au1OOB + u4Offset;
++ i4Size = min(len, (int)(sizeof(pkCMD->au1OOB) - u4Offset));
++ for (i = 0; i < i4Size; i++) {
++ pOOB[i] &= buf[i];
++ }
++ } else {
++ pkCMD->pDataBuf = (u8 *) buf;
++ }
++
++ pkCMD->u4ColAddr += len;
++}
++
++static int
++mtk_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, int oob_required)
++{
++ mtk_nand_write_buf(mtd, buf, mtd->writesize);
++ mtk_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
++ return 0;
++}
++
++static int
++mtk_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, int oob_required, int page)
++{
++ struct NAND_CMD *pkCMD = &g_kCMD;
++ u32 u4ColAddr = pkCMD->u4ColAddr;
++ u32 u4PageSize = mtd->writesize;
++
++ if (u4ColAddr == 0) {
++ mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, chip->oob_poi);
++ pkCMD->u4ColAddr += u4PageSize + mtd->oobsize;
++ }
++
++ return 0;
++}
++
++static int
++mtk_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, u8 * buf, int page)
++{
++ int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++ int block = page / page_per_block;
++ u16 page_in_block = page % page_per_block;
++ int mapped_block = block;
++
++#if defined (MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++ if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block,
++ mtd->writesize, buf, chip->oob_poi))
++ return 0;
++#else
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++ return NAND_STATUS_FAIL;
++ }
++
++ if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, buf, chip->oob_poi))
++ return 0;
++ else
++ return -EIO;
++#endif
++}
++
++int
++mtk_nand_erase_hw(struct mtd_info *mtd, int page)
++{
++ struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++
++ chip->erase_cmd(mtd, page);
++
++ return chip->waitfunc(mtd, chip);
++}
++
++static int
++mtk_nand_erase(struct mtd_info *mtd, int page)
++{
++ // get mapping
++ struct nand_chip *chip = mtd->priv;
++ int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++ int page_in_block = page % page_per_block;
++ int block = page / page_per_block;
++ int mapped_block = block;
++
++#if defined(MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++#else
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++ return NAND_STATUS_FAIL;
++ }
++#endif
++
++ do {
++ int status = mtk_nand_erase_hw(mtd, page_in_block + page_per_block * mapped_block);
++
++ if (status & NAND_STATUS_FAIL) {
++#if defined (MTK_NAND_BMT)
++ if (update_bmt( (page_in_block + mapped_block * page_per_block) << chip->page_shift,
++ UPDATE_ERASE_FAIL, NULL, NULL))
++ {
++ MSG(INIT, "Erase fail at block: 0x%x, update BMT success\n", mapped_block);
++ return 0;
++ } else {
++ MSG(INIT, "Erase fail at block: 0x%x, update BMT fail\n", mapped_block);
++ return NAND_STATUS_FAIL;
++ }
++#else
++ mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++ nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++ return NAND_STATUS_FAIL;
++ } else
++ return NAND_STATUS_FAIL;
++#endif
++ } else
++ break;
++ } while(1);
++
++ return 0;
++}
++
++static int
++mtk_nand_read_oob_raw(struct mtd_info *mtd, uint8_t * buf, int page_addr, int len)
++{
++ struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++ u32 col_addr = 0;
++ u32 sector = 0;
++ int res = 0;
++ u32 colnob = 2, rawnob = devinfo.addr_cycle - 2;
++ int randomread = 0;
++ int read_len = 0;
++ int sec_num = 1<<(chip->page_shift-9);
++ int spare_per_sector = mtd->oobsize/sec_num;
++
++ if (len > NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
++ printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
++ return -EINVAL;
++ }
++ if (len > spare_per_sector)
++ randomread = 1;
++ if (!randomread || !(devinfo.advancedmode & RAMDOM_READ)) {
++ while (len > 0) {
++ read_len = min(len, spare_per_sector);
++ col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector); // TODO: Fix this hard-code 16
++ if (!mtk_nand_ready_for_read(chip, page_addr, col_addr, false, NULL)) {
++ printk(KERN_WARNING "mtk_nand_ready_for_read return failed\n");
++ res = -EIO;
++ goto error;
++ }
++ if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
++ printk(KERN_WARNING "mtk_nand_mcu_read_data return failed\n");
++ res = -EIO;
++ goto error;
++ }
++ mtk_nand_check_RW_count(read_len);
++ mtk_nand_stop_read();
++ sector++;
++ len -= read_len;
++ }
++ } else {
++ col_addr = NAND_SECTOR_SIZE;
++ if (chip->options & NAND_BUSWIDTH_16)
++ col_addr /= 2;
++ if (!mtk_nand_reset())
++ goto error;
++ mtk_nand_set_mode(0x6000);
++ NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
++ DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
++
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++ NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++
++ mtk_nand_set_autoformat(false);
++
++ if (!mtk_nand_set_command(NAND_CMD_READ0))
++ goto error;
++ //1 FIXED ME: For Any Kind of AddrCycle
++ if (!mtk_nand_set_address(col_addr, page_addr, colnob, rawnob))
++ goto error;
++ if (!mtk_nand_set_command(NAND_CMD_READSTART))
++ goto error;
++ if (!mtk_nand_status_ready(STA_NAND_BUSY))
++ goto error;
++ read_len = min(len, spare_per_sector);
++ if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
++ printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
++ res = -EIO;
++ goto error;
++ }
++ sector++;
++ len -= read_len;
++ mtk_nand_stop_read();
++ while (len > 0) {
++ read_len = min(len, spare_per_sector);
++ if (!mtk_nand_set_command(0x05))
++ goto error;
++ col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector);
++ if (chip->options & NAND_BUSWIDTH_16)
++ col_addr /= 2;
++ DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);
++ DRV_WriteReg16(NFI_ADDRNOB_REG16, 2);
++ DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
++ if (!mtk_nand_status_ready(STA_ADDR_STATE))
++ goto error;
++ if (!mtk_nand_set_command(0xE0))
++ goto error;
++ if (!mtk_nand_status_ready(STA_NAND_BUSY))
++ goto error;
++ if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
++ printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
++ res = -EIO;
++ goto error;
++ }
++ mtk_nand_stop_read();
++ sector++;
++ len -= read_len;
++ }
++ }
++error:
++ NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
++ return res;
++}
++
++static int
++mtk_nand_write_oob_raw(struct mtd_info *mtd, const uint8_t * buf, int page_addr, int len)
++{
++ struct nand_chip *chip = mtd->priv;
++ u32 col_addr = 0;
++ u32 sector = 0;
++ int write_len = 0;
++ int status;
++ int sec_num = 1<<(chip->page_shift-9);
++ int spare_per_sector = mtd->oobsize/sec_num;
++
++ if (len > NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
++ printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
++ return -EINVAL;
++ }
++
++ while (len > 0) {
++ write_len = min(len, spare_per_sector);
++ col_addr = sector * (NAND_SECTOR_SIZE + spare_per_sector) + NAND_SECTOR_SIZE;
++ if (!mtk_nand_ready_for_write(chip, page_addr, col_addr, false, NULL))
++ return -EIO;
++ if (!mtk_nand_mcu_write_data(mtd, buf + sector * spare_per_sector, write_len))
++ return -EIO;
++ (void)mtk_nand_check_RW_count(write_len);
++ NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
++ (void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
++ while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
++ ;
++ status = chip->waitfunc(mtd, chip);
++ if (status & NAND_STATUS_FAIL) {
++ printk(KERN_INFO "status: %d\n", status);
++ return -EIO;
++ }
++ len -= write_len;
++ sector++;
++ }
++
++ return 0;
++}
++
++static int
++mtk_nand_write_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++ int i, iter;
++ int sec_num = 1<<(chip->page_shift-9);
++ int spare_per_sector = mtd->oobsize/sec_num;
++
++ memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
++
++ // copy ecc data
++ for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
++ iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) * spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
++ local_oob_buf[iter] = chip->oob_poi[chip->ecc.layout->eccpos[i]];
++ }
++
++ // copy FDM data
++ for (i = 0; i < sec_num; i++)
++ memcpy(&local_oob_buf[i * spare_per_sector], &chip->oob_poi[i * OOB_AVAI_PER_SECTOR], OOB_AVAI_PER_SECTOR);
++
++ return mtk_nand_write_oob_raw(mtd, local_oob_buf, page, mtd->oobsize);
++}
++
++static int mtk_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++ int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++ int block = page / page_per_block;
++ u16 page_in_block = page % page_per_block;
++ int mapped_block = block;
++
++#if defined(MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++ // write bad index into oob
++ if (mapped_block != block)
++ set_bad_index_to_oob(chip->oob_poi, block);
++ else
++ set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
++#else
++ if (shift_on_bbt)
++ {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++ return NAND_STATUS_FAIL;
++ }
++#endif
++ do {
++ if (mtk_nand_write_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block /* page */)) {
++ MSG(INIT, "write oob fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
++#if defined(MTK_NAND_BMT)
++ if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift,
++ UPDATE_WRITE_FAIL, NULL, chip->oob_poi))
++ {
++ MSG(INIT, "Update BMT success\n");
++ return 0;
++ } else {
++ MSG(INIT, "Update BMT fail\n");
++ return -EIO;
++ }
++#else
++ mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++ nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, mapped_block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++ return NAND_STATUS_FAIL;
++ } else {
++ return NAND_STATUS_FAIL;
++ }
++#endif
++ } else
++ break;
++ } while (1);
++
++ return 0;
++}
++
++int
++mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t offset)
++{
++ struct nand_chip *chip = mtd->priv;
++ int block = (int)offset >> chip->phys_erase_shift;
++ int page = block * (1 << (chip->phys_erase_shift - chip->page_shift));
++ u8 buf[8];
++
++ memset(buf, 0xFF, 8);
++ buf[0] = 0;
++ return mtk_nand_write_oob_raw(mtd, buf, page, 8);
++}
++
++static int
++mtk_nand_block_markbad(struct mtd_info *mtd, loff_t offset)
++{
++ struct nand_chip *chip = mtd->priv;
++ int block = (int)offset >> chip->phys_erase_shift;
++ int ret;
++ int mapped_block = block;
++
++ nand_get_device(chip, mtd, FL_WRITING);
++
++#if defined(MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++ ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
++#else
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1) {
++ printk("NAND mark bad failed\n");
++ nand_release_device(mtd);
++ return NAND_STATUS_FAIL;
++ }
++ }
++ ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
++#endif
++ nand_release_device(mtd);
++
++ return ret;
++}
++
++int
++mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++ int i;
++ u8 iter = 0;
++
++ int sec_num = 1<<(chip->page_shift-9);
++ int spare_per_sector = mtd->oobsize/sec_num;
++
++ if (mtk_nand_read_oob_raw(mtd, chip->oob_poi, page, mtd->oobsize)) {
++ printk(KERN_ERR "[%s]mtk_nand_read_oob_raw return failed\n", __FUNCTION__);
++ return -EIO;
++ }
++
++ // adjust to ecc physical layout to memory layout
++ /*********************************************************/
++ /* FDM0 | ECC0 | FDM1 | ECC1 | FDM2 | ECC2 | FDM3 | ECC3 */
++ /* 8B | 8B | 8B | 8B | 8B | 8B | 8B | 8B */
++ /*********************************************************/
++
++ memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
++ // copy ecc data
++ for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
++ iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) * spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
++ chip->oob_poi[chip->ecc.layout->eccpos[i]] = local_oob_buf[iter];
++ }
++
++ // copy FDM data
++ for (i = 0; i < sec_num; i++) {
++ memcpy(&chip->oob_poi[i * OOB_AVAI_PER_SECTOR], &local_oob_buf[i * spare_per_sector], OOB_AVAI_PER_SECTOR);
++ }
++
++ return 0;
++}
++
++static int
++mtk_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++ int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++ int block = page / page_per_block;
++ u16 page_in_block = page % page_per_block;
++ int mapped_block = block;
++
++#if defined (MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++ mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block);
++#else
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1)
++ return NAND_STATUS_FAIL;
++ // allow to read oob even if the block is bad
++ }
++ if (mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block)!=0)
++ return -1;
++#endif
++ return 0;
++}
++
++int
++mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs)
++{
++ struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++ int page_addr = (int)(ofs >> chip->page_shift);
++ unsigned int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++ unsigned char oob_buf[8];
++
++ page_addr &= ~(page_per_block - 1);
++ if (mtk_nand_read_oob_raw(mtd, oob_buf, page_addr, sizeof(oob_buf))) {
++ printk(KERN_WARNING "mtk_nand_read_oob_raw return error\n");
++ return 1;
++ }
++
++ if (oob_buf[0] != 0xff) {
++ printk(KERN_WARNING "Bad block detected at 0x%x, oob_buf[0] is 0x%x\n", page_addr, oob_buf[0]);
++ // dump_nfi();
++ return 1;
++ }
++
++ return 0;
++}
++
++static int
++mtk_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
++{
++ int chipnr = 0;
++ struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++ int block = (int)ofs >> chip->phys_erase_shift;
++ int mapped_block = block;
++ int ret;
++
++ if (getchip) {
++ chipnr = (int)(ofs >> chip->chip_shift);
++ nand_get_device(chip, mtd, FL_READING);
++ /* Select the NAND device */
++ chip->select_chip(mtd, chipnr);
++ }
++
++#if defined(MTK_NAND_BMT)
++ mapped_block = get_mapping_block_index(block);
++#else
++ if (shift_on_bbt) {
++ mapped_block = block_remap(mtd, block);
++ if (mapped_block == -1) {
++ if (getchip)
++ nand_release_device(mtd);
++ return NAND_STATUS_FAIL;
++ }
++ }
++#endif
++
++ ret = mtk_nand_block_bad_hw(mtd, mapped_block << chip->phys_erase_shift);
++#if defined (MTK_NAND_BMT)
++ if (ret) {
++ MSG(INIT, "Unmapped bad block: 0x%x\n", mapped_block);
++ if (update_bmt(mapped_block << chip->phys_erase_shift, UPDATE_UNMAPPED_BLOCK, NULL, NULL)) {
++ MSG(INIT, "Update BMT success\n");
++ ret = 0;
++ } else {
++ MSG(INIT, "Update BMT fail\n");
++ ret = 1;
++ }
++ }
++#endif
++
++ if (getchip)
++ nand_release_device(mtd);
++
++ return ret;
++}
++
++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
++char gacBuf[4096 + 288];
++
++static int
++mtk_nand_verify_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
++{
++ struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++ struct NAND_CMD *pkCMD = &g_kCMD;
++ u32 u4PageSize = mtd->writesize;
++ u32 *pSrc, *pDst;
++ int i;
++
++ mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, gacBuf, gacBuf + u4PageSize);
++
++ pSrc = (u32 *) buf;
++ pDst = (u32 *) gacBuf;
++ len = len / sizeof(u32);
++ for (i = 0; i < len; ++i) {
++ if (*pSrc != *pDst) {
++ MSG(VERIFY, "mtk_nand_verify_buf page fail at page %d\n", pkCMD->u4RowAddr);
++ return -1;
++ }
++ pSrc++;
++ pDst++;
++ }
++
++ pSrc = (u32 *) chip->oob_poi;
++ pDst = (u32 *) (gacBuf + u4PageSize);
++
++ if ((pSrc[0] != pDst[0]) || (pSrc[1] != pDst[1]) || (pSrc[2] != pDst[2]) || (pSrc[3] != pDst[3]) || (pSrc[4] != pDst[4]) || (pSrc[5] != pDst[5])) {
++ // TODO: Ask Designer Why?
++ //(pSrc[6] != pDst[6]) || (pSrc[7] != pDst[7]))
++ MSG(VERIFY, "mtk_nand_verify_buf oob fail at page %d\n", pkCMD->u4RowAddr);
++ MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pSrc[0], pSrc[1], pSrc[2], pSrc[3], pSrc[4], pSrc[5], pSrc[6], pSrc[7]);
++ MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pDst[0], pDst[1], pDst[2], pDst[3], pDst[4], pDst[5], pDst[6], pDst[7]);
++ return -1;
++ }
++ return 0;
++}
++#endif
++
++static void
++mtk_nand_init_hw(struct mtk_nand_host *host) {
++ struct mtk_nand_host_hw *hw = host->hw;
++ u32 data;
++
++ data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
++ data &= ~((0x3<<18)|(0x3<<16));
++ data |= ((0x2<<18) |(0x2<<16));
++ DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
++
++ MSG(INIT, "Enable NFI Clock\n");
++ nand_enable_clock();
++
++ g_bInitDone = false;
++ g_kCMD.u4OOBRowAddr = (u32) - 1;
++
++ /* Set default NFI access timing control */
++ DRV_WriteReg32(NFI_ACCCON_REG32, hw->nfi_access_timing);
++ DRV_WriteReg16(NFI_CNFG_REG16, 0);
++ DRV_WriteReg16(NFI_PAGEFMT_REG16, 0);
++
++ /* Reset the state machine and data FIFO, because flushing FIFO */
++ (void)mtk_nand_reset();
++
++ /* Set the ECC engine */
++ if (hw->nand_ecc_mode == NAND_ECC_HW) {
++ MSG(INIT, "%s : Use HW ECC\n", MODULE_NAME);
++ if (g_bHwEcc)
++ NFI_SET_REG32(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++ ECC_Config(host->hw,4);
++ mtk_nand_configure_fdm(8);
++ mtk_nand_configure_lock();
++ }
++
++ NFI_SET_REG16(NFI_IOCON_REG16, 0x47);
++}
++
++static int mtk_nand_dev_ready(struct mtd_info *mtd)
++{
++ return !(DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY);
++}
++
++#define FACT_BBT_BLOCK_NUM 32 // use the latest 32 BLOCK for factory bbt table
++#define FACT_BBT_OOB_SIGNATURE 1
++#define FACT_BBT_SIGNATURE_LEN 7
++const u8 oob_signature[] = "mtknand";
++static u8 *fact_bbt = 0;
++static u32 bbt_size = 0;
++
++static int
++read_fact_bbt(struct mtd_info *mtd, unsigned int page)
++{
++ struct nand_chip *chip = mtd->priv;
++
++ // read oob
++ if (mtk_nand_read_oob_hw(mtd, chip, page)==0)
++ {
++ if (chip->oob_poi[nand_badblock_offset] != 0xFF)
++ {
++ printk("Bad Block on Page %x\n", page);
++ return -1;
++ }
++ if (memcmp(&chip->oob_poi[FACT_BBT_OOB_SIGNATURE], oob_signature, FACT_BBT_SIGNATURE_LEN) != 0)
++ {
++ printk("compare signature failed %x\n", page);
++ return -1;
++ }
++ if (mtk_nand_exec_read_page(mtd, page, mtd->writesize, chip->buffers->databuf, chip->oob_poi))
++ {
++ printk("Signature matched and data read!\n");
++ memcpy(fact_bbt, chip->buffers->databuf, (bbt_size <= mtd->writesize)? bbt_size:mtd->writesize);
++ return 0;
++ }
++
++ }
++ printk("failed at page %x\n", page);
++ return -1;
++}
++
++static int
++load_fact_bbt(struct mtd_info *mtd)
++{
++ struct nand_chip *chip = mtd->priv;
++ int i;
++ u32 total_block;
++
++ total_block = 1 << (chip->chip_shift - chip->phys_erase_shift);
++ bbt_size = total_block >> 2;
++
++ if ((!fact_bbt) && (bbt_size))
++ fact_bbt = (u8 *)kmalloc(bbt_size, GFP_KERNEL);
++ if (!fact_bbt)
++ return -1;
++
++ for (i = total_block - 1; i >= (total_block - FACT_BBT_BLOCK_NUM); i--)
++ {
++ if (read_fact_bbt(mtd, i << (chip->phys_erase_shift - chip->page_shift)) == 0)
++ {
++ printk("load_fact_bbt success %d\n", i);
++ return 0;
++ }
++
++ }
++ printk("load_fact_bbt failed\n");
++ return -1;
++}
++
++static int
++mtk_nand_probe(struct platform_device *pdev)
++{
++ struct mtd_part_parser_data ppdata;
++ struct mtk_nand_host_hw *hw;
++ struct mtd_info *mtd;
++ struct nand_chip *nand_chip;
++ u8 ext_id1, ext_id2, ext_id3;
++ int err = 0;
++ int id;
++ u32 ext_id;
++ int i;
++ u32 data;
++
++ data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
++ data &= ~((0x3<<18)|(0x3<<16));
++ data |= ((0x2<<18) |(0x2<<16));
++ DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
++
++ hw = &mt7621_nand_hw,
++ BUG_ON(!hw);
++ /* Allocate memory for the device structure (and zero it) */
++ host = kzalloc(sizeof(struct mtk_nand_host), GFP_KERNEL);
++ if (!host) {
++ MSG(INIT, "mtk_nand: failed to allocate device structure.\n");
++ return -ENOMEM;
++ }
++
++ /* Allocate memory for 16 byte aligned buffer */
++ local_buffer_16_align = local_buffer + 16 - ((u32) local_buffer % 16);
++ printk(KERN_INFO "Allocate 16 byte aligned buffer: %p\n", local_buffer_16_align);
++ host->hw = hw;
++
++ /* init mtd data structure */
++ nand_chip = &host->nand_chip;
++ nand_chip->priv = host; /* link the private data structures */
++
++ mtd = &host->mtd;
++ mtd->priv = nand_chip;
++ mtd->owner = THIS_MODULE;
++ mtd->name = "MT7621-NAND";
++
++ hw->nand_ecc_mode = NAND_ECC_HW;
++
++ /* Set address of NAND IO lines */
++ nand_chip->IO_ADDR_R = (void __iomem *)NFI_DATAR_REG32;
++ nand_chip->IO_ADDR_W = (void __iomem *)NFI_DATAW_REG32;
++ nand_chip->chip_delay = 20; /* 20us command delay time */
++ nand_chip->ecc.mode = hw->nand_ecc_mode; /* enable ECC */
++ nand_chip->ecc.strength = 1;
++ nand_chip->read_byte = mtk_nand_read_byte;
++ nand_chip->read_buf = mtk_nand_read_buf;
++ nand_chip->write_buf = mtk_nand_write_buf;
++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
++ nand_chip->verify_buf = mtk_nand_verify_buf;
++#endif
++ nand_chip->select_chip = mtk_nand_select_chip;
++ nand_chip->dev_ready = mtk_nand_dev_ready;
++ nand_chip->cmdfunc = mtk_nand_command_bp;
++ nand_chip->ecc.read_page = mtk_nand_read_page_hwecc;
++ nand_chip->ecc.write_page = mtk_nand_write_page_hwecc;
++
++ nand_chip->ecc.layout = &nand_oob_64;
++ nand_chip->ecc.size = hw->nand_ecc_size; //2048
++ nand_chip->ecc.bytes = hw->nand_ecc_bytes; //32
++
++ // For BMT, we need to revise driver architecture
++ nand_chip->write_page = mtk_nand_write_page;
++ nand_chip->ecc.write_oob = mtk_nand_write_oob;
++ nand_chip->block_markbad = mtk_nand_block_markbad; // need to add nand_get_device()/nand_release_device().
++ // nand_chip->erase = mtk_nand_erase;
++ // nand_chip->read_page = mtk_nand_read_page;
++ nand_chip->ecc.read_oob = mtk_nand_read_oob;
++ nand_chip->block_bad = mtk_nand_block_bad;
++
++ //Qwert:Add for Uboot
++ mtk_nand_init_hw(host);
++ /* Select the device */
++ nand_chip->select_chip(mtd, NFI_DEFAULT_CS);
++
++ /*
++ * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
++ * after power-up
++ */
++ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
++
++ memset(&devinfo, 0 , sizeof(flashdev_info));
++
++ /* Send the command for reading device ID */
++
++ nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
++
++ /* Read manufacturer and device IDs */
++ manu_id = nand_chip->read_byte(mtd);
++ dev_id = nand_chip->read_byte(mtd);
++ id = dev_id | (manu_id << 8);
++ ext_id1 = nand_chip->read_byte(mtd);
++ ext_id2 = nand_chip->read_byte(mtd);
++ ext_id3 = nand_chip->read_byte(mtd);
++ ext_id = ext_id1 << 16 | ext_id2 << 8 | ext_id3;
++ if (!get_device_info(id, ext_id, &devinfo)) {
++ u32 chip_mode = RALINK_REG(RALINK_SYSCTL_BASE+0x010)&0x0F;
++ MSG(INIT, "Not Support this Device! \r\n");
++ memset(&devinfo, 0 , sizeof(flashdev_info));
++ MSG(INIT, "chip_mode=%08X\n",chip_mode);
++
++ /* apply bootstrap first */
++ devinfo.addr_cycle = 5;
++ devinfo.iowidth = 8;
++
++ switch (chip_mode) {
++ case 10:
++ devinfo.pagesize = 2048;
++ devinfo.sparesize = 128;
++ devinfo.totalsize = 128;
++ devinfo.blocksize = 128;
++ break;
++ case 11:
++ devinfo.pagesize = 4096;
++ devinfo.sparesize = 128;
++ devinfo.totalsize = 1024;
++ devinfo.blocksize = 256;
++ break;
++ case 12:
++ devinfo.pagesize = 4096;
++ devinfo.sparesize = 224;
++ devinfo.totalsize = 2048;
++ devinfo.blocksize = 512;
++ break;
++ default:
++ case 1:
++ devinfo.pagesize = 2048;
++ devinfo.sparesize = 64;
++ devinfo.totalsize = 128;
++ devinfo.blocksize = 128;
++ break;
++ }
++
++ devinfo.timmingsetting = NFI_DEFAULT_ACCESS_TIMING;
++ devinfo.devciename[0] = 'U';
++ devinfo.advancedmode = 0;
++ }
++ mtd->writesize = devinfo.pagesize;
++ mtd->erasesize = (devinfo.blocksize<<10);
++ mtd->oobsize = devinfo.sparesize;
++
++ nand_chip->chipsize = (devinfo.totalsize<<20);
++ nand_chip->page_shift = ffs(mtd->writesize) - 1;
++ nand_chip->pagemask = (nand_chip->chipsize >> nand_chip->page_shift) - 1;
++ nand_chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
++ nand_chip->chip_shift = ffs(nand_chip->chipsize) - 1;//0x1C;//ffs(nand_chip->chipsize) - 1;
++ nand_chip->oob_poi = nand_chip->buffers->databuf + mtd->writesize;
++ nand_chip->badblockpos = 0;
++
++ if (devinfo.pagesize == 4096)
++ nand_chip->ecc.layout = &nand_oob_128;
++ else if (devinfo.pagesize == 2048)
++ nand_chip->ecc.layout = &nand_oob_64;
++ else if (devinfo.pagesize == 512)
++ nand_chip->ecc.layout = &nand_oob_16;
++
++ nand_chip->ecc.layout->eccbytes = devinfo.sparesize-OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE);
++ for (i = 0; i < nand_chip->ecc.layout->eccbytes; i++)
++ nand_chip->ecc.layout->eccpos[i]=OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE)+i;
++
++ MSG(INIT, "Support this Device in MTK table! %x \r\n", id);
++ hw->nfi_bus_width = devinfo.iowidth;
++ DRV_WriteReg32(NFI_ACCCON_REG32, devinfo.timmingsetting);
++
++ /* 16-bit bus width */
++ if (hw->nfi_bus_width == 16) {
++ MSG(INIT, "%s : Set the 16-bit I/O settings!\n", MODULE_NAME);
++ nand_chip->options |= NAND_BUSWIDTH_16;
++ }
++ mtd->oobsize = devinfo.sparesize;
++ hw->nfi_cs_num = 1;
++
++ /* Scan to find existance of the device */
++ if (nand_scan(mtd, hw->nfi_cs_num)) {
++ MSG(INIT, "%s : nand_scan fail.\n", MODULE_NAME);
++ err = -ENXIO;
++ goto out;
++ }
++
++ g_page_size = mtd->writesize;
++ platform_set_drvdata(pdev, host);
++ if (hw->nfi_bus_width == 16) {
++ NFI_SET_REG16(NFI_PAGEFMT_REG16, PAGEFMT_DBYTE_EN);
++ }
++
++ nand_chip->select_chip(mtd, 0);
++#if defined(MTK_NAND_BMT)
++ nand_chip->chipsize -= (BMT_POOL_SIZE) << nand_chip->phys_erase_shift;
++#endif
++ mtd->size = nand_chip->chipsize;
++
++ CFG_BLOCKSIZE = mtd->erasesize;
++
++#if defined(MTK_NAND_BMT)
++ if (!g_bmt) {
++ if (!(g_bmt = init_bmt(nand_chip, BMT_POOL_SIZE))) {
++ MSG(INIT, "Error: init bmt failed\n");
++ return 0;
++ }
++ }
++#endif
++
++ ppdata.of_node = pdev->dev.of_node;
++ err = mtd_device_parse_register(mtd, probe_types, &ppdata,
++ NULL, 0);
++ if (!err) {
++ MSG(INIT, "[mtk_nand] probe successfully!\n");
++ nand_disable_clock();
++ shift_on_bbt = 1;
++ if (load_fact_bbt(mtd) == 0) {
++ int i;
++ for (i = 0; i < 0x100; i++)
++ nand_chip->bbt[i] |= fact_bbt[i];
++ }
++
++ return err;
++ }
++
++out:
++ MSG(INIT, "[NFI] mtk_nand_probe fail, err = %d!\n", err);
++ nand_release(mtd);
++ platform_set_drvdata(pdev, NULL);
++ kfree(host);
++ nand_disable_clock();
++ return err;
++}
++
++static int
++mtk_nand_remove(struct platform_device *pdev)
++{
++ struct mtk_nand_host *host = platform_get_drvdata(pdev);
++ struct mtd_info *mtd = &host->mtd;
++
++ nand_release(mtd);
++ kfree(host);
++ nand_disable_clock();
++
++ return 0;
++}
++
++static const struct of_device_id mt7621_nand_match[] = {
++ { .compatible = "mtk,mt7621-nand" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mt7621_nand_match);
++
++static struct platform_driver mtk_nand_driver = {
++ .probe = mtk_nand_probe,
++ .remove = mtk_nand_remove,
++ .driver = {
++ .name = "MT7621-NAND",
++ .owner = THIS_MODULE,
++ .of_match_table = mt7621_nand_match,
++ },
++};
++
++static int __init
++mtk_nand_init(void)
++{
++ printk("MediaTek Nand driver init, version %s\n", VERSION);
++
++ return platform_driver_register(&mtk_nand_driver);
++}
++
++static void __exit
++mtk_nand_exit(void)
++{
++ platform_driver_unregister(&mtk_nand_driver);
++}
++
++module_init(mtk_nand_init);
++module_exit(mtk_nand_exit);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/mtd/nand/mtk_nand.h
+@@ -0,0 +1,452 @@
++#ifndef __MTK_NAND_H
++#define __MTK_NAND_H
++
++#define RALINK_NAND_CTRL_BASE 0xBE003000
++#define RALINK_SYSCTL_BASE 0xBE000000
++#define RALINK_NANDECC_CTRL_BASE 0xBE003800
++/*******************************************************************************
++ * NFI Register Definition
++ *******************************************************************************/
++
++#define NFI_CNFG_REG16 ((volatile P_U16)(NFI_BASE+0x0000))
++#define NFI_PAGEFMT_REG16 ((volatile P_U16)(NFI_BASE+0x0004))
++#define NFI_CON_REG16 ((volatile P_U16)(NFI_BASE+0x0008))
++#define NFI_ACCCON_REG32 ((volatile P_U32)(NFI_BASE+0x000C))
++#define NFI_INTR_EN_REG16 ((volatile P_U16)(NFI_BASE+0x0010))
++#define NFI_INTR_REG16 ((volatile P_U16)(NFI_BASE+0x0014))
++
++#define NFI_CMD_REG16 ((volatile P_U16)(NFI_BASE+0x0020))
++
++#define NFI_ADDRNOB_REG16 ((volatile P_U16)(NFI_BASE+0x0030))
++#define NFI_COLADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0034))
++#define NFI_ROWADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0038))
++
++#define NFI_STRDATA_REG16 ((volatile P_U16)(NFI_BASE+0x0040))
++
++#define NFI_DATAW_REG32 ((volatile P_U32)(NFI_BASE+0x0050))
++#define NFI_DATAR_REG32 ((volatile P_U32)(NFI_BASE+0x0054))
++#define NFI_PIO_DIRDY_REG16 ((volatile P_U16)(NFI_BASE+0x0058))
++
++#define NFI_STA_REG32 ((volatile P_U32)(NFI_BASE+0x0060))
++#define NFI_FIFOSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0064))
++#define NFI_LOCKSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0068))
++
++#define NFI_ADDRCNTR_REG16 ((volatile P_U16)(NFI_BASE+0x0070))
++
++#define NFI_STRADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0080))
++#define NFI_BYTELEN_REG16 ((volatile P_U16)(NFI_BASE+0x0084))
++
++#define NFI_CSEL_REG16 ((volatile P_U16)(NFI_BASE+0x0090))
++#define NFI_IOCON_REG16 ((volatile P_U16)(NFI_BASE+0x0094))
++
++#define NFI_FDM0L_REG32 ((volatile P_U32)(NFI_BASE+0x00A0))
++#define NFI_FDM0M_REG32 ((volatile P_U32)(NFI_BASE+0x00A4))
++
++#define NFI_LOCK_REG16 ((volatile P_U16)(NFI_BASE+0x0100))
++#define NFI_LOCKCON_REG32 ((volatile P_U32)(NFI_BASE+0x0104))
++#define NFI_LOCKANOB_REG16 ((volatile P_U16)(NFI_BASE+0x0108))
++#define NFI_LOCK00ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0110))
++#define NFI_LOCK00FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0114))
++#define NFI_LOCK01ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0118))
++#define NFI_LOCK01FMT_REG32 ((volatile P_U32)(NFI_BASE+0x011C))
++#define NFI_LOCK02ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0120))
++#define NFI_LOCK02FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0124))
++#define NFI_LOCK03ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0128))
++#define NFI_LOCK03FMT_REG32 ((volatile P_U32)(NFI_BASE+0x012C))
++#define NFI_LOCK04ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0130))
++#define NFI_LOCK04FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0134))
++#define NFI_LOCK05ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0138))
++#define NFI_LOCK05FMT_REG32 ((volatile P_U32)(NFI_BASE+0x013C))
++#define NFI_LOCK06ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0140))
++#define NFI_LOCK06FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0144))
++#define NFI_LOCK07ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0148))
++#define NFI_LOCK07FMT_REG32 ((volatile P_U32)(NFI_BASE+0x014C))
++#define NFI_LOCK08ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0150))
++#define NFI_LOCK08FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0154))
++#define NFI_LOCK09ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0158))
++#define NFI_LOCK09FMT_REG32 ((volatile P_U32)(NFI_BASE+0x015C))
++#define NFI_LOCK10ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0160))
++#define NFI_LOCK10FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0164))
++#define NFI_LOCK11ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0168))
++#define NFI_LOCK11FMT_REG32 ((volatile P_U32)(NFI_BASE+0x016C))
++#define NFI_LOCK12ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0170))
++#define NFI_LOCK12FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0174))
++#define NFI_LOCK13ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0178))
++#define NFI_LOCK13FMT_REG32 ((volatile P_U32)(NFI_BASE+0x017C))
++#define NFI_LOCK14ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0180))
++#define NFI_LOCK14FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0184))
++#define NFI_LOCK15ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0188))
++#define NFI_LOCK15FMT_REG32 ((volatile P_U32)(NFI_BASE+0x018C))
++
++#define NFI_FIFODATA0_REG32 ((volatile P_U32)(NFI_BASE+0x0190))
++#define NFI_FIFODATA1_REG32 ((volatile P_U32)(NFI_BASE+0x0194))
++#define NFI_FIFODATA2_REG32 ((volatile P_U32)(NFI_BASE+0x0198))
++#define NFI_FIFODATA3_REG32 ((volatile P_U32)(NFI_BASE+0x019C))
++#define NFI_MASTERSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0210))
++
++
++/*******************************************************************************
++ * NFI Register Field Definition
++ *******************************************************************************/
++
++/* NFI_CNFG */
++#define CNFG_AHB (0x0001)
++#define CNFG_READ_EN (0x0002)
++#define CNFG_DMA_BURST_EN (0x0004)
++#define CNFG_BYTE_RW (0x0040)
++#define CNFG_HW_ECC_EN (0x0100)
++#define CNFG_AUTO_FMT_EN (0x0200)
++#define CNFG_OP_IDLE (0x0000)
++#define CNFG_OP_READ (0x1000)
++#define CNFG_OP_SRD (0x2000)
++#define CNFG_OP_PRGM (0x3000)
++#define CNFG_OP_ERASE (0x4000)
++#define CNFG_OP_RESET (0x5000)
++#define CNFG_OP_CUST (0x6000)
++#define CNFG_OP_MODE_MASK (0x7000)
++#define CNFG_OP_MODE_SHIFT (12)
++
++/* NFI_PAGEFMT */
++#define PAGEFMT_512 (0x0000)
++#define PAGEFMT_2K (0x0001)
++#define PAGEFMT_4K (0x0002)
++
++#define PAGEFMT_PAGE_MASK (0x0003)
++
++#define PAGEFMT_DBYTE_EN (0x0008)
++
++#define PAGEFMT_SPARE_16 (0x0000)
++#define PAGEFMT_SPARE_26 (0x0001)
++#define PAGEFMT_SPARE_27 (0x0002)
++#define PAGEFMT_SPARE_28 (0x0003)
++#define PAGEFMT_SPARE_MASK (0x0030)
++#define PAGEFMT_SPARE_SHIFT (4)
++
++#define PAGEFMT_FDM_MASK (0x0F00)
++#define PAGEFMT_FDM_SHIFT (8)
++
++#define PAGEFMT_FDM_ECC_MASK (0xF000)
++#define PAGEFMT_FDM_ECC_SHIFT (12)
++
++/* NFI_CON */
++#define CON_FIFO_FLUSH (0x0001)
++#define CON_NFI_RST (0x0002)
++#define CON_NFI_SRD (0x0010)
++
++#define CON_NFI_NOB_MASK (0x0060)
++#define CON_NFI_NOB_SHIFT (5)
++
++#define CON_NFI_BRD (0x0100)
++#define CON_NFI_BWR (0x0200)
++
++#define CON_NFI_SEC_MASK (0xF000)
++#define CON_NFI_SEC_SHIFT (12)
++
++/* NFI_ACCCON */
++#define ACCCON_SETTING ()
++
++/* NFI_INTR_EN */
++#define INTR_RD_DONE_EN (0x0001)
++#define INTR_WR_DONE_EN (0x0002)
++#define INTR_RST_DONE_EN (0x0004)
++#define INTR_ERASE_DONE_EN (0x0008)
++#define INTR_BSY_RTN_EN (0x0010)
++#define INTR_ACC_LOCK_EN (0x0020)
++#define INTR_AHB_DONE_EN (0x0040)
++#define INTR_ALL_INTR_DE (0x0000)
++#define INTR_ALL_INTR_EN (0x007F)
++
++/* NFI_INTR */
++#define INTR_RD_DONE (0x0001)
++#define INTR_WR_DONE (0x0002)
++#define INTR_RST_DONE (0x0004)
++#define INTR_ERASE_DONE (0x0008)
++#define INTR_BSY_RTN (0x0010)
++#define INTR_ACC_LOCK (0x0020)
++#define INTR_AHB_DONE (0x0040)
++
++/* NFI_ADDRNOB */
++#define ADDR_COL_NOB_MASK (0x0003)
++#define ADDR_COL_NOB_SHIFT (0)
++#define ADDR_ROW_NOB_MASK (0x0030)
++#define ADDR_ROW_NOB_SHIFT (4)
++
++/* NFI_STA */
++#define STA_READ_EMPTY (0x00001000)
++#define STA_ACC_LOCK (0x00000010)
++#define STA_CMD_STATE (0x00000001)
++#define STA_ADDR_STATE (0x00000002)
++#define STA_DATAR_STATE (0x00000004)
++#define STA_DATAW_STATE (0x00000008)
++
++#define STA_NAND_FSM_MASK (0x1F000000)
++#define STA_NAND_BUSY (0x00000100)
++#define STA_NAND_BUSY_RETURN (0x00000200)
++#define STA_NFI_FSM_MASK (0x000F0000)
++#define STA_NFI_OP_MASK (0x0000000F)
++
++/* NFI_FIFOSTA */
++#define FIFO_RD_EMPTY (0x0040)
++#define FIFO_RD_FULL (0x0080)
++#define FIFO_WR_FULL (0x8000)
++#define FIFO_WR_EMPTY (0x4000)
++#define FIFO_RD_REMAIN(x) (0x1F&(x))
++#define FIFO_WR_REMAIN(x) ((0x1F00&(x))>>8)
++
++/* NFI_ADDRCNTR */
++#define ADDRCNTR_CNTR(x) ((0xF000&(x))>>12)
++#define ADDRCNTR_OFFSET(x) (0x03FF&(x))
++
++/* NFI_LOCK */
++#define NFI_LOCK_ON (0x0001)
++
++/* NFI_LOCKANOB */
++#define PROG_RADD_NOB_MASK (0x7000)
++#define PROG_RADD_NOB_SHIFT (12)
++#define PROG_CADD_NOB_MASK (0x0300)
++#define PROG_CADD_NOB_SHIFT (8)
++#define ERASE_RADD_NOB_MASK (0x0070)
++#define ERASE_RADD_NOB_SHIFT (4)
++#define ERASE_CADD_NOB_MASK (0x0007)
++#define ERASE_CADD_NOB_SHIFT (0)
++
++/*******************************************************************************
++ * ECC Register Definition
++ *******************************************************************************/
++
++#define ECC_ENCCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0000))
++#define ECC_ENCCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0004))
++#define ECC_ENCDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0008))
++#define ECC_ENCIDLE_REG32 ((volatile P_U32)(NFIECC_BASE+0x000C))
++#define ECC_ENCPAR0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0010))
++#define ECC_ENCPAR1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0014))
++#define ECC_ENCPAR2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0018))
++#define ECC_ENCPAR3_REG32 ((volatile P_U32)(NFIECC_BASE+0x001C))
++#define ECC_ENCPAR4_REG32 ((volatile P_U32)(NFIECC_BASE+0x0020))
++#define ECC_ENCSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0024))
++#define ECC_ENCIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0028))
++#define ECC_ENCIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x002C))
++
++#define ECC_DECCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0100))
++#define ECC_DECCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0104))
++#define ECC_DECDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0108))
++#define ECC_DECIDLE_REG16 ((volatile P_U16)(NFIECC_BASE+0x010C))
++#define ECC_DECFER_REG16 ((volatile P_U16)(NFIECC_BASE+0x0110))
++#define ECC_DECENUM_REG32 ((volatile P_U32)(NFIECC_BASE+0x0114))
++#define ECC_DECDONE_REG16 ((volatile P_U16)(NFIECC_BASE+0x0118))
++#define ECC_DECEL0_REG32 ((volatile P_U32)(NFIECC_BASE+0x011C))
++#define ECC_DECEL1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0120))
++#define ECC_DECEL2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0124))
++#define ECC_DECEL3_REG32 ((volatile P_U32)(NFIECC_BASE+0x0128))
++#define ECC_DECEL4_REG32 ((volatile P_U32)(NFIECC_BASE+0x012C))
++#define ECC_DECEL5_REG32 ((volatile P_U32)(NFIECC_BASE+0x0130))
++#define ECC_DECIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0134))
++#define ECC_DECIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0138))
++#define ECC_FDMADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x013C))
++#define ECC_DECFSM_REG32 ((volatile P_U32)(NFIECC_BASE+0x0140))
++#define ECC_SYNSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0144))
++#define ECC_DECNFIDI_REG32 ((volatile P_U32)(NFIECC_BASE+0x0148))
++#define ECC_SYN0_REG32 ((volatile P_U32)(NFIECC_BASE+0x014C))
++
++/*******************************************************************************
++ * ECC register definition
++ *******************************************************************************/
++/* ECC_ENCON */
++#define ENC_EN (0x0001)
++#define ENC_DE (0x0000)
++
++/* ECC_ENCCNFG */
++#define ECC_CNFG_ECC4 (0x0000)
++#define ECC_CNFG_ECC6 (0x0001)
++#define ECC_CNFG_ECC8 (0x0002)
++#define ECC_CNFG_ECC10 (0x0003)
++#define ECC_CNFG_ECC12 (0x0004)
++#define ECC_CNFG_ECC_MASK (0x00000007)
++
++#define ENC_CNFG_NFI (0x0010)
++#define ENC_CNFG_MODE_MASK (0x0010)
++
++#define ENC_CNFG_META6 (0x10300000)
++#define ENC_CNFG_META8 (0x10400000)
++
++#define ENC_CNFG_MSG_MASK (0x1FFF0000)
++#define ENC_CNFG_MSG_SHIFT (0x10)
++
++/* ECC_ENCIDLE */
++#define ENC_IDLE (0x0001)
++
++/* ECC_ENCSTA */
++#define STA_FSM (0x001F)
++#define STA_COUNT_PS (0xFF10)
++#define STA_COUNT_MS (0x3FFF0000)
++
++/* ECC_ENCIRQEN */
++#define ENC_IRQEN (0x0001)
++
++/* ECC_ENCIRQSTA */
++#define ENC_IRQSTA (0x0001)
++
++/* ECC_DECCON */
++#define DEC_EN (0x0001)
++#define DEC_DE (0x0000)
++
++/* ECC_ENCCNFG */
++#define DEC_CNFG_ECC4 (0x0000)
++//#define DEC_CNFG_ECC6 (0x0001)
++//#define DEC_CNFG_ECC12 (0x0002)
++#define DEC_CNFG_NFI (0x0010)
++//#define DEC_CNFG_META6 (0x10300000)
++//#define DEC_CNFG_META8 (0x10400000)
++
++#define DEC_CNFG_FER (0x01000)
++#define DEC_CNFG_EL (0x02000)
++#define DEC_CNFG_CORRECT (0x03000)
++#define DEC_CNFG_TYPE_MASK (0x03000)
++
++#define DEC_CNFG_EMPTY_EN (0x80000000)
++
++#define DEC_CNFG_CODE_MASK (0x1FFF0000)
++#define DEC_CNFG_CODE_SHIFT (0x10)
++
++/* ECC_DECIDLE */
++#define DEC_IDLE (0x0001)
++
++/* ECC_DECFER */
++#define DEC_FER0 (0x0001)
++#define DEC_FER1 (0x0002)
++#define DEC_FER2 (0x0004)
++#define DEC_FER3 (0x0008)
++#define DEC_FER4 (0x0010)
++#define DEC_FER5 (0x0020)
++#define DEC_FER6 (0x0040)
++#define DEC_FER7 (0x0080)
++
++/* ECC_DECENUM */
++#define ERR_NUM0 (0x0000000F)
++#define ERR_NUM1 (0x000000F0)
++#define ERR_NUM2 (0x00000F00)
++#define ERR_NUM3 (0x0000F000)
++#define ERR_NUM4 (0x000F0000)
++#define ERR_NUM5 (0x00F00000)
++#define ERR_NUM6 (0x0F000000)
++#define ERR_NUM7 (0xF0000000)
++
++/* ECC_DECDONE */
++#define DEC_DONE0 (0x0001)
++#define DEC_DONE1 (0x0002)
++#define DEC_DONE2 (0x0004)
++#define DEC_DONE3 (0x0008)
++#define DEC_DONE4 (0x0010)
++#define DEC_DONE5 (0x0020)
++#define DEC_DONE6 (0x0040)
++#define DEC_DONE7 (0x0080)
++
++/* ECC_DECIRQEN */
++#define DEC_IRQEN (0x0001)
++
++/* ECC_DECIRQSTA */
++#define DEC_IRQSTA (0x0001)
++
++#define CHIPVER_ECO_1 (0x8a00)
++#define CHIPVER_ECO_2 (0x8a01)
++
++//#define NAND_PFM
++
++/*******************************************************************************
++ * Data Structure Definition
++ *******************************************************************************/
++struct mtk_nand_host
++{
++ struct nand_chip nand_chip;
++ struct mtd_info mtd;
++ struct mtk_nand_host_hw *hw;
++};
++
++struct NAND_CMD
++{
++ u32 u4ColAddr;
++ u32 u4RowAddr;
++ u32 u4OOBRowAddr;
++ u8 au1OOB[288];
++ u8* pDataBuf;
++#ifdef NAND_PFM
++ u32 pureReadOOB;
++ u32 pureReadOOBNum;
++#endif
++};
++
++/*
++ * ECC layout control structure. Exported to userspace for
++ * diagnosis and to allow creation of raw images
++struct nand_ecclayout {
++ uint32_t eccbytes;
++ uint32_t eccpos[64];
++ uint32_t oobavail;
++ struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
++};
++*/
++#define __DEBUG_NAND 1 /* Debug information on/off */
++
++/* Debug message event */
++#define DBG_EVT_NONE 0x00000000 /* No event */
++#define DBG_EVT_INIT 0x00000001 /* Initial related event */
++#define DBG_EVT_VERIFY 0x00000002 /* Verify buffer related event */
++#define DBG_EVT_PERFORMANCE 0x00000004 /* Performance related event */
++#define DBG_EVT_READ 0x00000008 /* Read related event */
++#define DBG_EVT_WRITE 0x00000010 /* Write related event */
++#define DBG_EVT_ERASE 0x00000020 /* Erase related event */
++#define DBG_EVT_BADBLOCK 0x00000040 /* Badblock related event */
++#define DBG_EVT_POWERCTL 0x00000080 /* Suspend/Resume related event */
++
++#define DBG_EVT_ALL 0xffffffff
++
++#define DBG_EVT_MASK (DBG_EVT_INIT)
++
++#if __DEBUG_NAND
++#define MSG(evt, fmt, args...) \
++do { \
++ if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
++ printk(fmt, ##args); \
++ } \
++} while(0)
++
++#define MSG_FUNC_ENTRY(f) MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
++#else
++#define MSG(evt, fmt, args...) do{}while(0)
++#define MSG_FUNC_ENTRY(f) do{}while(0)
++#endif
++
++#define RAMDOM_READ 1<<0
++#define CACHE_READ 1<<1
++
++typedef struct
++{
++ u16 id; //deviceid+menuid
++ u32 ext_id;
++ u8 addr_cycle;
++ u8 iowidth;
++ u16 totalsize;
++ u16 blocksize;
++ u16 pagesize;
++ u16 sparesize;
++ u32 timmingsetting;
++ char devciename[14];
++ u32 advancedmode; //
++}flashdev_info,*pflashdev_info;
++
++/* NAND driver */
++#if 0
++struct mtk_nand_host_hw {
++ unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
++ unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
++ unsigned int nfi_cs_num; /* NFI_CS_NUM */
++ unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
++ unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
++ unsigned int nand_ecc_size;
++ unsigned int nand_ecc_bytes;
++ unsigned int nand_ecc_mode;
++};
++extern struct mtk_nand_host_hw mt7621_nand_hw;
++extern u32 CFG_BLOCKSIZE;
++#endif
++#endif
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -93,7 +93,7 @@ static struct nand_ecclayout nand_oob_12
+ .length = 78} }
+ };
+
+-static int nand_get_device(struct mtd_info *mtd, int new_state);
++int nand_get_device(struct mtd_info *mtd, int new_state);
+
+ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops);
+@@ -131,7 +131,7 @@ static int check_offs_len(struct mtd_inf
+ *
+ * Release chip lock and wake up anyone waiting on the device.
+ */
+-static void nand_release_device(struct mtd_info *mtd)
++void nand_release_device(struct mtd_info *mtd)
+ {
+ struct nand_chip *chip = mtd->priv;
+
+@@ -803,7 +803,7 @@ static void panic_nand_get_device(struct
+ *
+ * Get the device and lock it for exclusive access
+ */
+-static int
++int
+ nand_get_device(struct mtd_info *mtd, int new_state)
+ {
+ struct nand_chip *chip = mtd->priv;
+--- a/drivers/mtd/nand/nand_bbt.c
++++ b/drivers/mtd/nand/nand_bbt.c
+@@ -1372,4 +1372,23 @@ int nand_markbad_bbt(struct mtd_info *mt
+ return ret;
+ }
+
++void nand_bbt_set(struct mtd_info *mtd, int page, int flag)
++{
++ struct nand_chip *this = mtd->priv;
++ int block;
++
++ block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
++ this->bbt[block >> 3] &= ~(0x03 << (block & 0x6));
++ this->bbt[block >> 3] |= (flag & 0x3) << (block & 0x6);
++}
++
++int nand_bbt_get(struct mtd_info *mtd, int page)
++{
++ struct nand_chip *this = mtd->priv;
++ int block;
++
++ block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
++ return (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
++}
++
+ EXPORT_SYMBOL(nand_scan_bbt);
+--- /dev/null
++++ b/drivers/mtd/nand/nand_def.h
+@@ -0,0 +1,123 @@
++#ifndef __NAND_DEF_H__
++#define __NAND_DEF_H__
++
++#define VERSION "v2.1 Fix AHB virt2phys error"
++#define MODULE_NAME "# MTK NAND #"
++#define PROCNAME "driver/nand"
++
++#undef TESTTIME
++//#define __UBOOT_NAND__ 1
++#define __KERNEL_NAND__ 1
++//#define __PRELOADER_NAND__ 1
++//#define PMT 1
++//#define _MTK_NAND_DUMMY_DRIVER
++//#define CONFIG_BADBLOCK_CHECK 1
++//#ifdef CONFIG_BADBLOCK_CHECK
++//#define MTK_NAND_BMT 1
++//#endif
++#define ECC_ENABLE 1
++#define MANUAL_CORRECT 1
++//#define __INTERNAL_USE_AHB_MODE__ (0)
++#define SKIP_BAD_BLOCK
++#define FACT_BBT
++
++#ifndef NAND_OTP_SUPPORT
++#define NAND_OTP_SUPPORT 0
++#endif
++
++/*******************************************************************************
++ * Macro definition
++ *******************************************************************************/
++//#define NFI_SET_REG32(reg, value) (DRV_WriteReg32(reg, DRV_Reg32(reg) | (value)))
++//#define NFI_SET_REG16(reg, value) (DRV_WriteReg16(reg, DRV_Reg16(reg) | (value)))
++//#define NFI_CLN_REG32(reg, value) (DRV_WriteReg32(reg, DRV_Reg32(reg) & (~(value))))
++//#define NFI_CLN_REG16(reg, value) (DRV_WriteReg16(reg, DRV_Reg16(reg) & (~(value))))
++
++#if defined (__KERNEL_NAND__)
++#define NFI_SET_REG32(reg, value) \
++do { \
++ g_value = (DRV_Reg32(reg) | (value));\
++ DRV_WriteReg32(reg, g_value); \
++} while(0)
++
++#define NFI_SET_REG16(reg, value) \
++do { \
++ g_value = (DRV_Reg16(reg) | (value));\
++ DRV_WriteReg16(reg, g_value); \
++} while(0)
++
++#define NFI_CLN_REG32(reg, value) \
++do { \
++ g_value = (DRV_Reg32(reg) & (~(value)));\
++ DRV_WriteReg32(reg, g_value); \
++} while(0)
++
++#define NFI_CLN_REG16(reg, value) \
++do { \
++ g_value = (DRV_Reg16(reg) & (~(value)));\
++ DRV_WriteReg16(reg, g_value); \
++} while(0)
++#endif
++
++#define NFI_WAIT_STATE_DONE(state) do{;}while (__raw_readl(NFI_STA_REG32) & state)
++#define NFI_WAIT_TO_READY() do{;}while (!(__raw_readl(NFI_STA_REG32) & STA_BUSY2READY))
++
++
++#define NAND_SECTOR_SIZE (512)
++#define OOB_PER_SECTOR (16)
++#define OOB_AVAI_PER_SECTOR (8)
++
++#ifndef PART_SIZE_BMTPOOL
++#define BMT_POOL_SIZE (80)
++#else
++#define BMT_POOL_SIZE (PART_SIZE_BMTPOOL)
++#endif
++
++#define PMT_POOL_SIZE (2)
++
++#define TIMEOUT_1 0x1fff
++#define TIMEOUT_2 0x8ff
++#define TIMEOUT_3 0xffff
++#define TIMEOUT_4 0xffff//5000 //PIO
++
++
++/* temporarity definiation */
++#if !defined (__KERNEL_NAND__)
++#define KERN_INFO
++#define KERN_WARNING
++#define KERN_ERR
++#define PAGE_SIZE (4096)
++#endif
++#define AddStorageTrace //AddStorageTrace
++#define STORAGE_LOGGER_MSG_NAND 0
++#define NFI_BASE RALINK_NAND_CTRL_BASE
++#define NFIECC_BASE RALINK_NANDECC_CTRL_BASE
++
++#ifdef __INTERNAL_USE_AHB_MODE__
++#define MT65xx_POLARITY_LOW 0
++#define MT65XX_PDN_PERI_NFI 0
++#define MT65xx_EDGE_SENSITIVE 0
++#define MT6575_NFI_IRQ_ID (58)
++#endif
++
++#if defined (__KERNEL_NAND__)
++#define RALINK_REG(x) (*((volatile u32 *)(x)))
++#define __virt_to_phys(x) virt_to_phys((volatile void*)x)
++#else
++#define CONFIG_MTD_NAND_VERIFY_WRITE (1)
++#define printk printf
++#define ra_dbg printf
++#define BUG() //BUG()
++#define BUG_ON(x) //BUG_ON()
++#define NUM_PARTITIONS 1
++#endif
++
++#define NFI_DEFAULT_ACCESS_TIMING (0x30C77fff) //(0x44333)
++
++//uboot only support 1 cs
++#define NFI_CS_NUM (1)
++#define NFI_DEFAULT_CS (0)
++
++#include "mt6575_typedefs.h"
++
++#endif /* __NAND_DEF_H__ */
+--- /dev/null
++++ b/drivers/mtd/nand/nand_device_list.h
+@@ -0,0 +1,55 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#ifndef __NAND_DEVICE_LIST_H__
++#define __NAND_DEVICE_LIST_H__
++
++static const flashdev_info gen_FlashTable[]={
++ {0x20BC, 0x105554, 5, 16, 512, 128, 2048, 64, 0x1123, "EHD013151MA_5", 0},
++ {0xECBC, 0x005554, 5, 16, 512, 128, 2048, 64, 0x1123, "K524G2GACB_A0", 0},
++ {0x2CBC, 0x905556, 5, 16, 512, 128, 2048, 64, 0x21044333, "MT29C4G96MAZA", 0},
++ {0xADBC, 0x905554, 5, 16, 512, 128, 2048, 64, 0x10801011, "H9DA4GH4JJAMC", 0},
++ {0x01F1, 0x801D01, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "S34ML01G100TF", 0},
++ {0x92F1, 0x8095FF, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "F59L1G81A", 0},
++ {0xECD3, 0x519558, 5, 8, 1024, 128, 2048, 64, 0x44333, "K9K8G8000", 0},
++ {0xC2F1, 0x801DC2, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "MX30LF1G08AA", 0},
++ {0x98D3, 0x902676, 5, 8, 1024, 256, 4096, 224, 0x00C25332, "TC58NVG3S0F", 0},
++ {0x01DA, 0x909546, 5, 8, 256, 128, 2048, 128, 0x30C77fff, "S34ML02G200TF", 0},
++ {0x01DC, 0x909556, 5, 8, 512, 128, 2048, 128, 0x30C77fff, "S34ML04G200TF", 0},
++ {0x0000, 0x000000, 0, 0, 0, 0, 0, 0, 0, "xxxxxxxxxx", 0},
++};
++
++
++#endif
+--- /dev/null
++++ b/drivers/mtd/nand/partition.h
+@@ -0,0 +1,115 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++
++#define RECONFIG_PARTITION_SIZE 1
++
++#define MTD_BOOT_PART_SIZE 0x80000
++#define MTD_CONFIG_PART_SIZE 0x20000
++#define MTD_FACTORY_PART_SIZE 0x20000
++
++extern unsigned int CFG_BLOCKSIZE;
++#define LARGE_MTD_BOOT_PART_SIZE (CFG_BLOCKSIZE<<2)
++#define LARGE_MTD_CONFIG_PART_SIZE (CFG_BLOCKSIZE<<2)
++#define LARGE_MTD_FACTORY_PART_SIZE (CFG_BLOCKSIZE<<1)
++
++/*=======================================================================*/
++/* NAND PARTITION Mapping */
++/*=======================================================================*/
++//#ifdef CONFIG_MTD_PARTITIONS
++static struct mtd_partition g_pasStatic_Partition[] = {
++ {
++ name: "ALL",
++ size: MTDPART_SIZ_FULL,
++ offset: 0,
++ },
++ /* Put your own partition definitions here */
++ {
++ name: "Bootloader",
++ size: MTD_BOOT_PART_SIZE,
++ offset: 0,
++ }, {
++ name: "Config",
++ size: MTD_CONFIG_PART_SIZE,
++ offset: MTDPART_OFS_APPEND
++ }, {
++ name: "Factory",
++ size: MTD_FACTORY_PART_SIZE,
++ offset: MTDPART_OFS_APPEND
++#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
++ }, {
++ name: "Kernel",
++ size: MTD_KERN_PART_SIZE,
++ offset: MTDPART_OFS_APPEND,
++ }, {
++ name: "RootFS",
++ size: MTD_ROOTFS_PART_SIZE,
++ offset: MTDPART_OFS_APPEND,
++#ifdef CONFIG_ROOTFS_IN_FLASH_NO_PADDING
++ }, {
++ name: "Kernel_RootFS",
++ size: MTD_KERN_PART_SIZE + MTD_ROOTFS_PART_SIZE,
++ offset: MTD_BOOT_PART_SIZE + MTD_CONFIG_PART_SIZE + MTD_FACTORY_PART_SIZE,
++#endif
++#else //CONFIG_RT2880_ROOTFS_IN_RAM
++ }, {
++ name: "Kernel",
++ size: 0x10000,
++ offset: MTDPART_OFS_APPEND,
++#endif
++#ifdef CONFIG_DUAL_IMAGE
++ }, {
++ name: "Kernel2",
++ size: MTD_KERN2_PART_SIZE,
++ offset: MTD_KERN2_PART_OFFSET,
++#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
++ }, {
++ name: "RootFS2",
++ size: MTD_ROOTFS2_PART_SIZE,
++ offset: MTD_ROOTFS2_PART_OFFSET,
++#endif
++#endif
++ }
++
++};
++
++#define NUM_PARTITIONS ARRAY_SIZE(g_pasStatic_Partition)
++extern int part_num; // = NUM_PARTITIONS;
++//#endif
++#undef RECONFIG_PARTITION_SIZE
++
--- /dev/null
+From 6827bd971fc4f323fc91e4506771a13b827c49a3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 19:45:30 +0200
+Subject: [PATCH 46/57] DT: Add documentation for gpio-ralink
+
+Describe gpio-ralink binding.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: devicetree@vger.kernel.org
+Cc: linux-gpio@vger.kernel.org
+---
+ .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+@@ -0,0 +1,40 @@
++Ralink SoC GPIO controller bindings
++
++Required properties:
++- compatible:
++ - "ralink,rt2880-gpio" for Ralink controllers
++- #gpio-cells : Should be two.
++ - first cell is the pin number
++ - second cell is used to specify optional parameters (unused)
++- gpio-controller : Marks the device node as a GPIO controller
++- reg : Physical base address and length of the controller's registers
++- interrupt-parent: phandle to the INTC device node
++- interrupts : Specify the INTC interrupt number
++- ralink,num-gpios : Specify the number of GPIOs
++- ralink,register-map : The register layout depends on the GPIO bank and actual
++ SoC type. Register offsets need to be in this order.
++ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
++
++Optional properties:
++- ralink,gpio-base : Specify the GPIO chips base number
++
++Example:
++
++ gpio0: gpio@600 {
++ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
++
++ #gpio-cells = <2>;
++ gpio-controller;
++
++ reg = <0x600 0x34>;
++
++ interrupt-parent = <&intc>;
++ interrupts = <6>;
++
++ ralink,gpio-base = <0>;
++ ralink,num-gpios = <24>;
++ ralink,register-map = [ 00 04 08 0c
++ 20 24 28 2c
++ 30 34 ];
++
++ };
--- /dev/null
+From 4b23ed96930650076caa524ffdde898cb937bdaa Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Aug 2014 20:36:29 +0200
+Subject: [PATCH 47/57] GPIO: MIPS: ralink: add gpio driver for ralink SoC
+
+Add gpio driver for Ralink SoC. This driver makes the gpio core on
+RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: linux-gpio@vger.kernel.org
+---
+ arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
+ drivers/gpio/Kconfig | 6 +
+ drivers/gpio/Makefile | 1 +
+ drivers/gpio/gpio-ralink.c | 345 ++++++++++++++++++++++++++++++
+ 4 files changed, 376 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
+ create mode 100644 drivers/gpio/gpio-ralink.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/gpio.h
+@@ -0,0 +1,24 @@
++/*
++ * Ralink SoC GPIO API support
++ *
++ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++
++#ifndef __ASM_MACH_RALINK_GPIO_H
++#define __ASM_MACH_RALINK_GPIO_H
++
++#define ARCH_NR_GPIOS 128
++#include <asm-generic/gpio.h>
++
++#define gpio_get_value __gpio_get_value
++#define gpio_set_value __gpio_set_value
++#define gpio_cansleep __gpio_cansleep
++#define gpio_to_irq __gpio_to_irq
++
++#endif /* __ASM_MACH_RALINK_GPIO_H */
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -288,6 +288,12 @@ config GPIO_SCH311X
+ To compile this driver as a module, choose M here: the module will
+ be called gpio-sch311x.
+
++config GPIO_RALINK
++ bool "Ralink GPIO Support"
++ depends on RALINK
++ help
++ Say yes here to support the Ralink SoC GPIO device
++
+ config GPIO_SPEAR_SPICS
+ bool "ST SPEAr13xx SPI Chip Select as GPIO support"
+ depends on PLAT_SPEAR
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -67,6 +67,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
+ obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
+ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
+ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
++obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
+ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
+ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
+--- /dev/null
++++ b/drivers/gpio/gpio-ralink.c
+@@ -0,0 +1,355 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/spinlock.h>
++#include <linux/platform_device.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++
++enum ralink_gpio_reg {
++ GPIO_REG_INT = 0,
++ GPIO_REG_EDGE,
++ GPIO_REG_RENA,
++ GPIO_REG_FENA,
++ GPIO_REG_DATA,
++ GPIO_REG_DIR,
++ GPIO_REG_POL,
++ GPIO_REG_SET,
++ GPIO_REG_RESET,
++ GPIO_REG_TOGGLE,
++ GPIO_REG_MAX
++};
++
++struct ralink_gpio_chip {
++ struct gpio_chip chip;
++ u8 regs[GPIO_REG_MAX];
++
++ spinlock_t lock;
++ void __iomem *membase;
++ struct irq_domain *domain;
++ int irq;
++
++ u32 rising;
++ u32 falling;
++};
++
++#define MAP_MAX 4
++static struct irq_domain *irq_map[MAP_MAX];
++static int irq_map_count;
++static atomic_t irq_refcount = ATOMIC_INIT(0);
++
++static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
++{
++ struct ralink_gpio_chip *rg;
++
++ rg = container_of(chip, struct ralink_gpio_chip, chip);
++
++ return rg;
++}
++
++static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
++{
++ iowrite32(val, rg->membase + rg->regs[reg]);
++}
++
++static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
++{
++ return ioread32(rg->membase + rg->regs[reg]);
++}
++
++static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
++{
++ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
++}
++
++static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
++{
++ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
++}
++
++static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++ unsigned long flags;
++ u32 t;
++
++ spin_lock_irqsave(&rg->lock, flags);
++ t = rt_gpio_r32(rg, GPIO_REG_DIR);
++ t &= ~BIT(offset);
++ rt_gpio_w32(rg, GPIO_REG_DIR, t);
++ spin_unlock_irqrestore(&rg->lock, flags);
++
++ return 0;
++}
++
++static int ralink_gpio_direction_output(struct gpio_chip *chip,
++ unsigned offset, int value)
++{
++ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++ unsigned long flags;
++ u32 t;
++
++ spin_lock_irqsave(&rg->lock, flags);
++ ralink_gpio_set(chip, offset, value);
++ t = rt_gpio_r32(rg, GPIO_REG_DIR);
++ t |= BIT(offset);
++ rt_gpio_w32(rg, GPIO_REG_DIR, t);
++ spin_unlock_irqrestore(&rg->lock, flags);
++
++ return 0;
++}
++
++static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
++{
++ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++ if (rg->irq < 1)
++ return -1;
++
++ return irq_create_mapping(rg->domain, pin);
++}
++
++static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++ int i;
++
++ for (i = 0; i < irq_map_count; i++) {
++ struct irq_domain *domain = irq_map[i];
++ struct ralink_gpio_chip *rg;
++ unsigned long pending;
++ int bit;
++
++ rg = (struct ralink_gpio_chip *) domain->host_data;
++ pending = rt_gpio_r32(rg, GPIO_REG_INT);
++
++ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
++ u32 map = irq_find_mapping(domain, bit);
++ generic_handle_irq(map);
++ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
++ }
++ }
++}
++
++static void ralink_gpio_irq_unmask(struct irq_data *d)
++{
++ struct ralink_gpio_chip *rg;
++ unsigned long flags;
++ u32 rise, fall;
++
++ rg = (struct ralink_gpio_chip *) d->domain->host_data;
++ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
++
++ spin_lock_irqsave(&rg->lock, flags);
++ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
++ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
++ spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static void ralink_gpio_irq_mask(struct irq_data *d)
++{
++ struct ralink_gpio_chip *rg;
++ unsigned long flags;
++ u32 rise, fall;
++
++ rg = (struct ralink_gpio_chip *) d->domain->host_data;
++ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
++
++ spin_lock_irqsave(&rg->lock, flags);
++ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
++ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
++ spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++ struct ralink_gpio_chip *rg;
++ u32 mask = BIT(d->hwirq);
++
++ rg = (struct ralink_gpio_chip *) d->domain->host_data;
++
++ if (type == IRQ_TYPE_PROBE) {
++ if ((rg->rising | rg->falling) & mask)
++ return 0;
++
++ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
++ }
++
++ if (type & IRQ_TYPE_EDGE_RISING)
++ rg->rising |= mask;
++ else
++ rg->rising &= ~mask;
++
++ if (type & IRQ_TYPE_EDGE_FALLING)
++ rg->falling |= mask;
++ else
++ rg->falling &= ~mask;
++
++ return 0;
++}
++
++static struct irq_chip ralink_gpio_irq_chip = {
++ .name = "GPIO",
++ .irq_unmask = ralink_gpio_irq_unmask,
++ .irq_mask = ralink_gpio_irq_mask,
++ .irq_mask_ack = ralink_gpio_irq_mask,
++ .irq_set_type = ralink_gpio_irq_type,
++};
++
++static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
++ irq_set_handler_data(irq, d);
++
++ return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = gpio_map,
++};
++
++static void ralink_gpio_irq_init(struct device_node *np,
++ struct ralink_gpio_chip *rg)
++{
++ if (irq_map_count >= MAP_MAX)
++ return;
++
++ rg->irq = irq_of_parse_and_map(np, 0);
++ if (!rg->irq)
++ return;
++
++ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
++ &irq_domain_ops, rg);
++ if (!rg->domain) {
++ dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
++ return;
++ }
++
++ irq_map[irq_map_count++] = rg->domain;
++
++ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
++ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
++
++ if (!atomic_read(&irq_refcount))
++ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
++ atomic_inc(&irq_refcount);
++
++ dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
++}
++
++static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
++{
++ int gpio = chip->base + offset;
++
++ return pinctrl_request_gpio(gpio);
++}
++
++static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
++{
++ int gpio = chip->base + offset;
++
++ pinctrl_free_gpio(gpio);
++}
++
++static int ralink_gpio_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ struct ralink_gpio_chip *rg;
++ const __be32 *ngpio, *gpiobase;
++
++ if (!res) {
++ dev_err(&pdev->dev, "failed to find resource\n");
++ return -ENOMEM;
++ }
++
++ rg = devm_kzalloc(&pdev->dev,
++ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
++ if (!rg)
++ return -ENOMEM;
++
++ rg->membase = devm_ioremap_resource(&pdev->dev, res);
++ if (!rg->membase) {
++ dev_err(&pdev->dev, "cannot remap I/O memory region\n");
++ return -ENOMEM;
++ }
++
++ if (of_property_read_u8_array(np, "ralink,register-map",
++ rg->regs, GPIO_REG_MAX)) {
++ dev_err(&pdev->dev, "failed to read register definition\n");
++ return -EINVAL;
++ }
++
++ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
++ if (!ngpio) {
++ dev_err(&pdev->dev, "failed to read number of pins\n");
++ return -EINVAL;
++ }
++
++ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
++ if (gpiobase)
++ rg->chip.base = be32_to_cpu(*gpiobase);
++ else
++ rg->chip.base = -1;
++
++ spin_lock_init(&rg->lock);
++
++ rg->chip.dev = &pdev->dev;
++ rg->chip.label = dev_name(&pdev->dev);
++ rg->chip.of_node = np;
++ rg->chip.ngpio = be32_to_cpu(*ngpio);
++ rg->chip.direction_input = ralink_gpio_direction_input;
++ rg->chip.direction_output = ralink_gpio_direction_output;
++ rg->chip.get = ralink_gpio_get;
++ rg->chip.set = ralink_gpio_set;
++ rg->chip.request = ralink_gpio_request;
++ rg->chip.to_irq = ralink_gpio_to_irq;
++ rg->chip.free = ralink_gpio_free;
++
++ /* set polarity to low for all lines */
++ rt_gpio_w32(rg, GPIO_REG_POL, 0);
++
++ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
++
++ ralink_gpio_irq_init(np, rg);
++
++ return gpiochip_add(&rg->chip);
++}
++
++static const struct of_device_id ralink_gpio_match[] = {
++ { .compatible = "ralink,rt2880-gpio" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ralink_gpio_match);
++
++static struct platform_driver ralink_gpio_driver = {
++ .probe = ralink_gpio_probe,
++ .driver = {
++ .name = "rt2880_gpio",
++ .owner = THIS_MODULE,
++ .of_match_table = ralink_gpio_match,
++ },
++};
++
++static int __init ralink_gpio_init(void)
++{
++ return platform_driver_register(&ralink_gpio_driver);
++}
++
++subsys_initcall(ralink_gpio_init);
--- /dev/null
+From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 11:00:32 +0100
+Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/Kconfig | 3 +
+ drivers/gpio/Kconfig | 6 ++
+ drivers/gpio/Makefile | 1 +
+ drivers/gpio/gpio-mt7621.c | 177 ++++++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 187 insertions(+)
+ create mode 100644 drivers/gpio/gpio-mt7621.c
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -455,6 +455,9 @@ config RALINK
+ select RESET_CONTROLLER
+ select PINCTRL
+ select PINCTRL_RT2880
++ select ARCH_HAS_RESET_CONTROLLER
++ select RESET_CONTROLLER
++ select ARCH_REQUIRE_GPIOLIB
+
+ config SGI_IP22
+ bool "SGI IP22 (Indy/Indigo2)"
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -898,6 +898,12 @@ config GPIO_BCM_KONA
+ help
+ Turn on GPIO support for Broadcom "Kona" chips.
+
++config GPIO_MT7621
++ bool "Mediatek GPIO Support"
++ depends on SOC_MT7620 || SOC_MT7621
++ help
++ Say yes here to support the Mediatek SoC GPIO device
++
+ comment "USB GPIO expanders:"
+
+ config GPIO_VIPERBOARD
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -107,3 +107,5 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx
+ obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
+ obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
+ obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
++obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
++
+--- /dev/null
++++ b/drivers/gpio/gpio-mt7621.c
+@@ -0,0 +1,178 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/gpio.h>
++#include <linux/module.h>
++#include <linux/of_irq.h>
++#include <linux/spinlock.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++
++#define MTK_BANK_WIDTH 32
++
++enum mediatek_gpio_reg {
++ GPIO_REG_CTRL = 0,
++ GPIO_REG_POL,
++ GPIO_REG_DATA,
++ GPIO_REG_DSET,
++ GPIO_REG_DCLR,
++};
++
++static void __iomem *mtk_gc_membase;
++
++struct mtk_gc {
++ struct gpio_chip chip;
++ spinlock_t lock;
++ int bank;
++};
++
++static inline struct mtk_gc
++*to_mediatek_gpio(struct gpio_chip *chip)
++{
++ struct mtk_gc *mgc;
++
++ mgc = container_of(chip, struct mtk_gc, chip);
++
++ return mgc;
++}
++
++static inline void
++mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
++{
++ iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
++}
++
++static inline u32
++mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
++{
++ return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
++}
++
++static void
++mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
++{
++ struct mtk_gc *rg = to_mediatek_gpio(chip);
++
++ mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
++}
++
++static int
++mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
++{
++ struct mtk_gc *rg = to_mediatek_gpio(chip);
++
++ return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
++}
++
++static int
++mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++ struct mtk_gc *rg = to_mediatek_gpio(chip);
++ unsigned long flags;
++ u32 t;
++
++ spin_lock_irqsave(&rg->lock, flags);
++ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
++ t &= ~BIT(offset);
++ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
++ spin_unlock_irqrestore(&rg->lock, flags);
++
++ return 0;
++}
++
++static int
++mediatek_gpio_direction_output(struct gpio_chip *chip,
++ unsigned offset, int value)
++{
++ struct mtk_gc *rg = to_mediatek_gpio(chip);
++ unsigned long flags;
++ u32 t;
++
++ spin_lock_irqsave(&rg->lock, flags);
++ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
++ t |= BIT(offset);
++ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
++ mediatek_gpio_set(chip, offset, value);
++ spin_unlock_irqrestore(&rg->lock, flags);
++
++ return 0;
++}
++
++static int
++mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
++{
++ const __be32 *id = of_get_property(bank, "reg", NULL);
++ struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
++ sizeof(struct mtk_gc), GFP_KERNEL);
++ if (!rg || !id)
++ return -ENOMEM;
++
++ spin_lock_init(&rg->lock);
++
++ rg->chip.dev = &pdev->dev;
++ rg->chip.label = dev_name(&pdev->dev);
++ rg->chip.of_node = bank;
++ rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
++ rg->chip.ngpio = MTK_BANK_WIDTH;
++ rg->chip.direction_input = mediatek_gpio_direction_input;
++ rg->chip.direction_output = mediatek_gpio_direction_output;
++ rg->chip.get = mediatek_gpio_get;
++ rg->chip.set = mediatek_gpio_set;
++ rg->bank = be32_to_cpu(*id);
++
++ /* set polarity to low for all gpios */
++ mtk_gpio_w32(rg, GPIO_REG_POL, 0);
++
++ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
++
++ return gpiochip_add(&rg->chip);
++}
++
++static int
++mediatek_gpio_probe(struct platform_device *pdev)
++{
++ struct device_node *bank, *np = pdev->dev.of_node;
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ mtk_gc_membase = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(mtk_gc_membase))
++ return PTR_ERR(mtk_gc_membase);
++
++ for_each_child_of_node(np, bank)
++ if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
++ mediatek_gpio_bank_probe(pdev, bank);
++
++ return 0;
++}
++
++static const struct of_device_id mediatek_gpio_match[] = {
++ { .compatible = "mtk,mt7621-gpio" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
++
++static struct platform_driver mediatek_gpio_driver = {
++ .probe = mediatek_gpio_probe,
++ .driver = {
++ .name = "mt7621_gpio",
++ .owner = THIS_MODULE,
++ .of_match_table = mediatek_gpio_match,
++ },
++};
++
++static int __init
++mediatek_gpio_init(void)
++{
++ return platform_driver_register(&mediatek_gpio_driver);
++}
++
++subsys_initcall(mediatek_gpio_init);
--- /dev/null
+From 6ed8d03e5f4283b60dffea5c10ff1484141824e7 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 9 Aug 2013 20:12:59 +0200
+Subject: [PATCH 49/57] DT: Add documentation for spi-rt2880
+
+Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
+@@ -0,0 +1,28 @@
++Ralink SoC RT2880 SPI master controller.
++
++This SPI controller is found on most wireless SoCs made by ralink.
++
++Required properties:
++- compatible : "ralink,rt2880-spi"
++- reg : The register base for the controller.
++- #address-cells : <1>, as required by generic SPI binding.
++- #size-cells : <0>, also as required by generic SPI binding.
++
++Child nodes as per the generic SPI binding.
++
++Example:
++
++ spi@b00 {
++ compatible = "ralink,rt2880-spi";
++ reg = <0xb00 0x100>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ m25p80@0 {
++ compatible = "m25p80";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++ };
++ };
++
--- /dev/null
+From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 11:15:12 +0100
+Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
+
+Add the driver needed to make SPI work on Ralink SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/Kconfig | 6 +
+ drivers/spi/Makefile | 1 +
+ drivers/spi/spi-rt2880.c | 432 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 439 insertions(+)
+ create mode 100644 drivers/spi/spi-rt2880.c
+
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -433,6 +433,12 @@ config SPI_QUP
+ This driver can also be built as a module. If so, the module
+ will be called spi_qup.
+
++config SPI_RT2880
++ tristate "Ralink RT288x SPI Controller"
++ depends on RALINK
++ help
++ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
++
+ config SPI_S3C24XX
+ tristate "Samsung S3C24XX series SPI"
+ depends on ARCH_S3C24XX
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -65,6 +65,7 @@ obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa
+ obj-$(CONFIG_SPI_QUP) += spi-qup.o
+ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
+ obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
++obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
+ obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y := spi-s3c24xx.o
+ spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
+--- /dev/null
++++ b/drivers/spi/spi-rt2880.c
+@@ -0,0 +1,432 @@
++/*
++ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
++ *
++ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
++ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Some parts are based on spi-orion.c:
++ * Author: Shadi Ammouri <shadi@marvell.com>
++ * Copyright (C) 2007-2008 Marvell Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/reset.h>
++#include <linux/spi/spi.h>
++#include <linux/platform_device.h>
++
++#define DRIVER_NAME "spi-rt2880"
++/* only one slave is supported*/
++#define RALINK_NUM_CHIPSELECTS 1
++/* in usec */
++#define RALINK_SPI_WAIT_MAX_LOOP 2000
++
++#define RAMIPS_SPI_STAT 0x00
++#define RAMIPS_SPI_CFG 0x10
++#define RAMIPS_SPI_CTL 0x14
++#define RAMIPS_SPI_DATA 0x20
++#define RAMIPS_SPI_FIFO_STAT 0x38
++
++/* SPISTAT register bit field */
++#define SPISTAT_BUSY BIT(0)
++
++/* SPICFG register bit field */
++#define SPICFG_LSBFIRST 0
++#define SPICFG_MSBFIRST BIT(8)
++#define SPICFG_SPICLKPOL BIT(6)
++#define SPICFG_RXCLKEDGE_FALLING BIT(5)
++#define SPICFG_TXCLKEDGE_FALLING BIT(4)
++#define SPICFG_SPICLK_PRESCALE_MASK 0x7
++#define SPICFG_SPICLK_DIV2 0
++#define SPICFG_SPICLK_DIV4 1
++#define SPICFG_SPICLK_DIV8 2
++#define SPICFG_SPICLK_DIV16 3
++#define SPICFG_SPICLK_DIV32 4
++#define SPICFG_SPICLK_DIV64 5
++#define SPICFG_SPICLK_DIV128 6
++#define SPICFG_SPICLK_DISABLE 7
++
++/* SPICTL register bit field */
++#define SPICTL_HIZSDO BIT(3)
++#define SPICTL_STARTWR BIT(2)
++#define SPICTL_STARTRD BIT(1)
++#define SPICTL_SPIENA BIT(0)
++
++/* SPIFIFOSTAT register bit field */
++#define SPIFIFOSTAT_TXFULL BIT(17)
++
++struct rt2880_spi {
++ struct spi_master *master;
++ void __iomem *base;
++ unsigned int sys_freq;
++ unsigned int speed;
++ struct clk *clk;
++ spinlock_t lock;
++};
++
++static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
++{
++ return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
++{
++ return ioread32(rs->base + reg);
++}
++
++static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
++{
++ iowrite32(val, rs->base + reg);
++}
++
++static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
++{
++ void __iomem *addr = rs->base + reg;
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&rs->lock, flags);
++ val = ioread32(addr);
++ val |= mask;
++ iowrite32(val, addr);
++ spin_unlock_irqrestore(&rs->lock, flags);
++}
++
++static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
++{
++ void __iomem *addr = rs->base + reg;
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&rs->lock, flags);
++ val = ioread32(addr);
++ val &= ~mask;
++ iowrite32(val, addr);
++ spin_unlock_irqrestore(&rs->lock, flags);
++}
++
++static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
++{
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ u32 rate;
++ u32 prescale;
++ u32 reg;
++
++ dev_dbg(&spi->dev, "speed:%u\n", speed);
++
++ /*
++ * the supported rates are: 2, 4, 8, ... 128
++ * round up as we look for equal or less speed
++ */
++ rate = DIV_ROUND_UP(rs->sys_freq, speed);
++ dev_dbg(&spi->dev, "rate-1:%u\n", rate);
++ rate = roundup_pow_of_two(rate);
++ dev_dbg(&spi->dev, "rate-2:%u\n", rate);
++
++ /* check if requested speed is too small */
++ if (rate > 128)
++ return -EINVAL;
++
++ if (rate < 2)
++ rate = 2;
++
++ /* Convert the rate to SPI clock divisor value. */
++ prescale = ilog2(rate / 2);
++ dev_dbg(&spi->dev, "prescale:%u\n", prescale);
++
++ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
++ reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
++ rs->speed = speed;
++ return 0;
++}
++
++/*
++ * called only when no transfer is active on the bus
++ */
++static int
++rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
++{
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ unsigned int speed = spi->max_speed_hz;
++ int rc;
++
++ if ((t != NULL) && t->speed_hz)
++ speed = t->speed_hz;
++
++ if (rs->speed != speed) {
++ dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
++ rc = rt2880_spi_baudrate_set(spi, speed);
++ if (rc)
++ return rc;
++ }
++
++ return 0;
++}
++
++static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
++{
++ if (enable)
++ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++ else
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++}
++
++static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
++{
++ int i;
++
++ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
++ u32 status;
++
++ status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
++ if ((status & SPISTAT_BUSY) == 0)
++ return 0;
++
++ cpu_relax();
++ udelay(1);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static unsigned int
++rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
++{
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ unsigned count = 0;
++ u8 *rx = xfer->rx_buf;
++ const u8 *tx = xfer->tx_buf;
++ int err;
++
++ dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
++ (tx != NULL) ? "tx" : " ",
++ (rx != NULL) ? "rx" : " ");
++
++ if (tx) {
++ for (count = 0; count < xfer->len; count++) {
++ rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
++ err = rt2880_spi_wait_till_ready(rs);
++ if (err) {
++ dev_err(&spi->dev, "TX failed, err=%d\n", err);
++ goto out;
++ }
++ }
++ }
++
++ if (rx) {
++ for (count = 0; count < xfer->len; count++) {
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
++ err = rt2880_spi_wait_till_ready(rs);
++ if (err) {
++ dev_err(&spi->dev, "RX failed, err=%d\n", err);
++ goto out;
++ }
++ rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
++ }
++ }
++
++out:
++ return count;
++}
++
++static int rt2880_spi_transfer_one_message(struct spi_master *master,
++ struct spi_message *m)
++{
++ struct rt2880_spi *rs = spi_master_get_devdata(master);
++ struct spi_device *spi = m->spi;
++ struct spi_transfer *t = NULL;
++ int par_override = 0;
++ int status = 0;
++ int cs_active = 0;
++
++ /* Load defaults */
++ status = rt2880_spi_setup_transfer(spi, NULL);
++ if (status < 0)
++ goto msg_done;
++
++ list_for_each_entry(t, &m->transfers, transfer_list) {
++ if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
++ dev_err(&spi->dev,
++ "message rejected: invalid transfer data buffers\n");
++ status = -EIO;
++ goto msg_done;
++ }
++
++ if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
++ dev_err(&spi->dev,
++ "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
++ (rs->sys_freq / 128), t->speed_hz);
++ status = -EIO;
++ goto msg_done;
++ }
++
++ if (par_override || t->speed_hz || t->bits_per_word) {
++ par_override = 1;
++ status = rt2880_spi_setup_transfer(spi, t);
++ if (status < 0)
++ goto msg_done;
++ if (!t->speed_hz && !t->bits_per_word)
++ par_override = 0;
++ }
++
++ if (!cs_active) {
++ rt2880_spi_set_cs(rs, 1);
++ cs_active = 1;
++ }
++
++ if (t->len)
++ m->actual_length += rt2880_spi_write_read(spi, t);
++
++ if (t->delay_usecs)
++ udelay(t->delay_usecs);
++
++ if (t->cs_change) {
++ rt2880_spi_set_cs(rs, 0);
++ cs_active = 0;
++ }
++ }
++
++msg_done:
++ if (cs_active)
++ rt2880_spi_set_cs(rs, 0);
++
++ m->status = status;
++ spi_finalize_current_message(master);
++
++ return 0;
++}
++
++static int rt2880_spi_setup(struct spi_device *spi)
++{
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++
++ if ((spi->max_speed_hz == 0) ||
++ (spi->max_speed_hz > (rs->sys_freq / 2)))
++ spi->max_speed_hz = (rs->sys_freq / 2);
++
++ if (spi->max_speed_hz < (rs->sys_freq / 128)) {
++ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
++ spi->max_speed_hz);
++ return -EINVAL;
++ }
++
++ /*
++ * baudrate & width will be set rt2880_spi_setup_transfer
++ */
++ return 0;
++}
++
++static void rt2880_spi_reset(struct rt2880_spi *rs)
++{
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG,
++ SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
++ SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
++ rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
++}
++
++static int rt2880_spi_probe(struct platform_device *pdev)
++{
++ struct spi_master *master;
++ struct rt2880_spi *rs;
++ unsigned long flags;
++ void __iomem *base;
++ struct resource *r;
++ int status = 0;
++ struct clk *clk;
++
++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ base = devm_ioremap_resource(&pdev->dev, r);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
++ status);
++ return PTR_ERR(clk);
++ }
++
++ status = clk_prepare_enable(clk);
++ if (status)
++ return status;
++
++ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
++ if (master == NULL) {
++ dev_dbg(&pdev->dev, "master allocation failed\n");
++ return -ENOMEM;
++ }
++
++ /* we support only mode 0, and no options */
++ master->mode_bits = 0;
++
++ master->setup = rt2880_spi_setup;
++ master->transfer_one_message = rt2880_spi_transfer_one_message;
++ master->num_chipselect = RALINK_NUM_CHIPSELECTS;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
++ master->dev.of_node = pdev->dev.of_node;
++
++ dev_set_drvdata(&pdev->dev, master);
++
++ rs = spi_master_get_devdata(master);
++ rs->base = base;
++ rs->clk = clk;
++ rs->master = master;
++ rs->sys_freq = clk_get_rate(rs->clk);
++ dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
++ spin_lock_irqsave(&rs->lock, flags);
++
++ device_reset(&pdev->dev);
++
++ rt2880_spi_reset(rs);
++
++ return spi_register_master(master);
++}
++
++static int rt2880_spi_remove(struct platform_device *pdev)
++{
++ struct spi_master *master;
++ struct rt2880_spi *rs;
++
++ master = dev_get_drvdata(&pdev->dev);
++ rs = spi_master_get_devdata(master);
++
++ clk_disable(rs->clk);
++ spi_unregister_master(master);
++
++ return 0;
++}
++
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
++static const struct of_device_id rt2880_spi_match[] = {
++ { .compatible = "ralink,rt2880-spi" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt2880_spi_match);
++
++static struct platform_driver rt2880_spi_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = rt2880_spi_match,
++ },
++ .probe = rt2880_spi_probe,
++ .remove = rt2880_spi_remove,
++};
++
++module_platform_driver(rt2880_spi_driver);
++
++MODULE_DESCRIPTION("Ralink SPI driver");
++MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 6 Aug 2014 10:53:40 +0200
+Subject: [PATCH 51/57] SPI: MIPS: ralink: add rt5350 dual SPI support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 205 insertions(+), 13 deletions(-)
+
+--- a/drivers/spi/spi-rt2880.c
++++ b/drivers/spi/spi-rt2880.c
+@@ -21,19 +21,25 @@
+ #include <linux/io.h>
+ #include <linux/reset.h>
+ #include <linux/spi/spi.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+
++#include <ralink_regs.h>
++
++#define SPI_BPW_MASK(bits) BIT((bits) - 1)
++
+ #define DRIVER_NAME "spi-rt2880"
+-/* only one slave is supported*/
+-#define RALINK_NUM_CHIPSELECTS 1
+ /* in usec */
+ #define RALINK_SPI_WAIT_MAX_LOOP 2000
+
+-#define RAMIPS_SPI_STAT 0x00
+-#define RAMIPS_SPI_CFG 0x10
+-#define RAMIPS_SPI_CTL 0x14
+-#define RAMIPS_SPI_DATA 0x20
+-#define RAMIPS_SPI_FIFO_STAT 0x38
++#define RAMIPS_SPI_DEV_OFFSET 0x40
++
++#define RAMIPS_SPI_STAT(cs) (0x00 + (cs * RAMIPS_SPI_DEV_OFFSET))
++#define RAMIPS_SPI_CFG(cs) (0x10 + (cs * RAMIPS_SPI_DEV_OFFSET))
++#define RAMIPS_SPI_CTL(cs) (0x14 + (cs * RAMIPS_SPI_DEV_OFFSET))
++#define RAMIPS_SPI_DATA(cs) (0x20 + (cs * RAMIPS_SPI_DEV_OFFSET))
++#define RAMIPS_SPI_FIFO_STAT(cs) (0x38 + (cs * RAMIPS_SPI_DEV_OFFSET))
++#define RAMIPS_SPI_ARBITER 0xF0
+
+ /* SPISTAT register bit field */
+ #define SPISTAT_BUSY BIT(0)
+@@ -63,6 +69,19 @@
+ /* SPIFIFOSTAT register bit field */
+ #define SPIFIFOSTAT_TXFULL BIT(17)
+
++#define SPICTL_ARB_EN BIT(31)
++#define SPI1_POR BIT(1)
++#define SPI0_POR BIT(0)
++
++#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
++
++struct rt2880_spi;
++
++struct rt2880_spi_ops {
++ void (*init_hw)(struct rt2880_spi *rs);
++ int num_cs;
++};
++
+ struct rt2880_spi {
+ struct spi_master *master;
+ void __iomem *base;
+@@ -70,6 +89,8 @@ struct rt2880_spi {
+ unsigned int speed;
+ struct clk *clk;
+ spinlock_t lock;
++
++ struct rt2880_spi_ops *ops;
+ };
+
+ static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
+@@ -115,6 +136,7 @@ static inline void rt2880_spi_clrbits(st
+
+ static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
+ {
++ int cs = spi->chip_select;
+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
+ u32 rate;
+ u32 prescale;
+@@ -142,9 +164,9 @@ static int rt2880_spi_baudrate_set(struc
+ prescale = ilog2(rate / 2);
+ dev_dbg(&spi->dev, "prescale:%u\n", prescale);
+
+- reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
++ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
+ reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
+- rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
+ rs->speed = speed;
+ return 0;
+ }
+@@ -157,7 +179,8 @@ rt2880_spi_setup_transfer(struct spi_dev
+ {
+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
+ unsigned int speed = spi->max_speed_hz;
+- int rc;
++ int rc, cs = spi->chip_select;
++ u32 reg;
+
+ if ((t != NULL) && t->speed_hz)
+ speed = t->speed_hz;
+@@ -169,25 +192,68 @@ rt2880_spi_setup_transfer(struct spi_dev
+ return rc;
+ }
+
++ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG(cs));
++
++ reg = (reg & ~SPICFG_MSBFIRST);
++ if (!(spi->mode & SPI_LSB_FIRST))
++ reg |= SPICFG_MSBFIRST;
++
++ reg = (reg & ~(SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING |SPICFG_TXCLKEDGE_FALLING));
++ switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
++ case SPI_MODE_0:
++ reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
++ break;
++ case SPI_MODE_1:
++ reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
++ break;
++ case SPI_MODE_2:
++ reg |= SPICFG_RXCLKEDGE_FALLING;
++ break;
++ case SPI_MODE_3:
++ reg |= SPICFG_TXCLKEDGE_FALLING;
++ break;
++ }
++
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs), reg);
++
++ reg = SPICTL_ARB_EN;
++ if (spi->mode & SPI_CS_HIGH) {
++ switch(cs) {
++ case 0:
++ reg |= SPI0_POR;
++ break;
++ case 1:
++ reg |= SPI1_POR;
++ break;
++ }
++ }
++
++ rt2880_spi_write(rs, RAMIPS_SPI_ARBITER, reg);
++
+ return 0;
+ }
+
+-static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
++static void rt2880_spi_set_cs(struct spi_device *spi, int enable)
+ {
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ int cs = spi->chip_select;
++
+ if (enable)
+- rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
+ else
+- rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
+ }
+
+-static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
++static inline int rt2880_spi_wait_till_ready(struct spi_device *spi)
+ {
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ int cs = spi->chip_select;
+ int i;
+
+ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
+ u32 status;
+
+- status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
++ status = rt2880_spi_read(rs, RAMIPS_SPI_STAT(cs));
+ if ((status & SPISTAT_BUSY) == 0)
+ return 0;
+
+@@ -199,9 +265,10 @@ static inline int rt2880_spi_wait_till_r
+ }
+
+ static unsigned int
+-rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
++rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
+ {
+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ int cs = spi->chip_select;
+ unsigned count = 0;
+ u8 *rx = xfer->rx_buf;
+ const u8 *tx = xfer->tx_buf;
+@@ -213,9 +280,9 @@ rt2880_spi_write_read(struct spi_device
+
+ if (tx) {
+ for (count = 0; count < xfer->len; count++) {
+- rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
+- rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
+- err = rt2880_spi_wait_till_ready(rs);
++ rt2880_spi_write(rs, RAMIPS_SPI_DATA(cs), tx[count]);
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTWR);
++ err = rt2880_spi_wait_till_ready(spi);
+ if (err) {
+ dev_err(&spi->dev, "TX failed, err=%d\n", err);
+ goto out;
+@@ -225,13 +292,13 @@ rt2880_spi_write_read(struct spi_device
+
+ if (rx) {
+ for (count = 0; count < xfer->len; count++) {
+- rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
+- err = rt2880_spi_wait_till_ready(rs);
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_STARTRD);
++ err = rt2880_spi_wait_till_ready(spi);
+ if (err) {
+ dev_err(&spi->dev, "RX failed, err=%d\n", err);
+ goto out;
+ }
+- rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
++ rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA(cs));
+ }
+ }
+
+@@ -280,25 +347,25 @@ static int rt2880_spi_transfer_one_messa
+ }
+
+ if (!cs_active) {
+- rt2880_spi_set_cs(rs, 1);
++ rt2880_spi_set_cs(spi, 1);
+ cs_active = 1;
+ }
+
+ if (t->len)
+- m->actual_length += rt2880_spi_write_read(spi, t);
++ m->actual_length += rt2880_spi_write_read(spi, &m->transfers, t);
+
+ if (t->delay_usecs)
+ udelay(t->delay_usecs);
+
+ if (t->cs_change) {
+- rt2880_spi_set_cs(rs, 0);
++ rt2880_spi_set_cs(spi, 0);
+ cs_active = 0;
+ }
+ }
+
+ msg_done:
+ if (cs_active)
+- rt2880_spi_set_cs(rs, 0);
++ rt2880_spi_set_cs(spi, 0);
+
+ m->status = status;
+ spi_finalize_current_message(master);
+@@ -311,7 +378,7 @@ static int rt2880_spi_setup(struct spi_d
+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
+
+ if ((spi->max_speed_hz == 0) ||
+- (spi->max_speed_hz > (rs->sys_freq / 2)))
++ (spi->max_speed_hz > (rs->sys_freq / 2)))
+ spi->max_speed_hz = (rs->sys_freq / 2);
+
+ if (spi->max_speed_hz < (rs->sys_freq / 128)) {
+@@ -328,14 +395,47 @@ static int rt2880_spi_setup(struct spi_d
+
+ static void rt2880_spi_reset(struct rt2880_spi *rs)
+ {
+- rt2880_spi_write(rs, RAMIPS_SPI_CFG,
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG(0),
+ SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
+ SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
+- rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
++ rt2880_spi_write(rs, RAMIPS_SPI_CTL(0), SPICTL_HIZSDO | SPICTL_SPIENA);
+ }
+
++static void rt5350_spi_reset(struct rt2880_spi *rs)
++{
++ int cs;
++
++ rt2880_spi_write(rs, RAMIPS_SPI_ARBITER,
++ SPICTL_ARB_EN);
++
++ for (cs = 0; cs < rs->ops->num_cs; cs++) {
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs),
++ SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
++ SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
++ rt2880_spi_write(rs, RAMIPS_SPI_CTL(cs), SPICTL_HIZSDO | SPICTL_SPIENA);
++ }
++}
++
++static struct rt2880_spi_ops spi_ops[] = {
++ {
++ .init_hw = rt2880_spi_reset,
++ .num_cs = 1,
++ }, {
++ .init_hw = rt5350_spi_reset,
++ .num_cs = 2,
++ },
++};
++
++static const struct of_device_id rt2880_spi_match[] = {
++ { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
++ { .compatible = "ralink,rt5350-spi", .data = &spi_ops[1]},
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt2880_spi_match);
++
+ static int rt2880_spi_probe(struct platform_device *pdev)
+ {
++ const struct of_device_id *match;
+ struct spi_master *master;
+ struct rt2880_spi *rs;
+ unsigned long flags;
+@@ -343,6 +443,12 @@ static int rt2880_spi_probe(struct platf
+ struct resource *r;
+ int status = 0;
+ struct clk *clk;
++ struct rt2880_spi_ops *ops;
++
++ match = of_match_device(rt2880_spi_match, &pdev->dev);
++ if (!match)
++ return -EINVAL;
++ ops = (struct rt2880_spi_ops *)match->data;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, r);
+@@ -366,14 +472,13 @@ static int rt2880_spi_probe(struct platf
+ return -ENOMEM;
+ }
+
+- /* we support only mode 0, and no options */
+- master->mode_bits = 0;
++ master->mode_bits = RT2880_SPI_MODE_BITS;
+
+ master->setup = rt2880_spi_setup;
+ master->transfer_one_message = rt2880_spi_transfer_one_message;
+- master->num_chipselect = RALINK_NUM_CHIPSELECTS;
+ master->bits_per_word_mask = SPI_BPW_MASK(8);
+ master->dev.of_node = pdev->dev.of_node;
++ master->num_chipselect = ops->num_cs;
+
+ dev_set_drvdata(&pdev->dev, master);
+
+@@ -382,12 +487,13 @@ static int rt2880_spi_probe(struct platf
+ rs->clk = clk;
+ rs->master = master;
+ rs->sys_freq = clk_get_rate(rs->clk);
++ rs->ops = ops;
+ dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
+ spin_lock_irqsave(&rs->lock, flags);
+
+ device_reset(&pdev->dev);
+
+- rt2880_spi_reset(rs);
++ rs->ops->init_hw(rs);
+
+ return spi_register_master(master);
+ }
+@@ -408,12 +514,6 @@ static int rt2880_spi_remove(struct plat
+
+ MODULE_ALIAS("platform:" DRIVER_NAME);
+
+-static const struct of_device_id rt2880_spi_match[] = {
+- { .compatible = "ralink,rt2880-spi" },
+- {},
+-};
+-MODULE_DEVICE_TABLE(of, rt2880_spi_match);
+-
+ static struct platform_driver rt2880_spi_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
--- /dev/null
+From 225f36695bb07dad9510f9affd79e63f1a44a195 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:52:56 +0100
+Subject: [PATCH 52/57] i2c: MIPS: adds ralink I2C driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
+ drivers/i2c/busses/Kconfig | 4 +
+ drivers/i2c/busses/Makefile | 1 +
+ drivers/i2c/busses/i2c-ralink.c | 274 ++++++++++++++++++++
+ 4 files changed, 306 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+ create mode 100644 drivers/i2c/busses/i2c-ralink.c
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+@@ -0,0 +1,27 @@
++I2C for Ralink platforms
++
++Required properties :
++- compatible : Must be "link,rt3052-i2c"
++- reg: physical base address of the controller and length of memory mapped
++ region.
++- #address-cells = <1>;
++- #size-cells = <0>;
++
++Optional properties:
++- Child nodes conforming to i2c bus binding
++
++Example :
++
++palmbus@10000000 {
++ i2c@900 {
++ compatible = "link,rt3052-i2c";
++ reg = <0x900 0x100>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hwmon@4b {
++ compatible = "national,lm92";
++ reg = <0x4b>;
++ };
++ };
++};
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -710,6 +710,10 @@ config I2C_RK3X
+ This driver can also be built as a module. If so, the module will
+ be called i2c-rk3x.
+
++config I2C_RALINK
++ tristate "Ralink I2C Controller"
++ select OF_I2C
++
+ config HAVE_S3C2410_I2C
+ bool
+ help
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -66,6 +66,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
+ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
+ obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
+ obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
++obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
+ obj-$(CONFIG_I2C_QUP) += i2c-qup.o
+ obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
+ obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-ralink.c
+@@ -0,0 +1,299 @@
++/*
++ * drivers/i2c/busses/i2c-ralink.c
++ *
++ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
++ *
++ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
++ * (C) 2014 Sittisak <sittisaks@hotmail.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <linux/io.h>
++#include <linux/err.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define REG_CONFIG_REG 0x00
++#define REG_CLKDIV_REG 0x04
++#define REG_DEVADDR_REG 0x08
++#define REG_ADDR_REG 0x0C
++#define REG_DATAOUT_REG 0x10
++#define REG_DATAIN_REG 0x14
++#define REG_STATUS_REG 0x18
++#define REG_STARTXFR_REG 0x1C
++#define REG_BYTECNT_REG 0x20
++
++#define I2C_STARTERR BIT(4)
++#define I2C_ACKERR BIT(3)
++#define I2C_DATARDY BIT(2)
++#define I2C_SDOEMPTY BIT(1)
++#define I2C_BUSY BIT(0)
++
++#define I2C_DEVADLEN_7 (6 << 2)
++#define I2C_ADDRDIS BIT(1)
++
++#define I2C_RETRY 0x1000
++
++#define CLKDIV_VALUE 200 // clock rate is 40M, 40M / (200*2) = 100k (standard i2c bus rate).
++//#define CLKDIV_VALUE 50 // clock rate is 40M, 40M / (50*2) = 400k (fast i2c bus rate).
++
++#define READ_CMD 0x01
++#define WRITE_CMD 0x00
++#define READ_BLOCK 64
++
++static void __iomem *membase;
++static struct i2c_adapter *adapter;
++
++static void rt_i2c_w32(u32 val, unsigned reg)
++{
++ iowrite32(val, membase + reg);
++}
++
++static u32 rt_i2c_r32(unsigned reg)
++{
++ return ioread32(membase + reg);
++}
++
++static inline int rt_i2c_get_ack(void)
++{
++ return (rt_i2c_r32(REG_STATUS_REG) & I2C_ACKERR) ? -EIO : 0;
++}
++
++static inline int rt_i2c_wait_rx_done(void)
++{
++ int retries = I2C_RETRY;
++
++ do {
++ if (!retries--)
++ break;
++ } while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
++
++ return (retries < 0) ? -ETIMEDOUT : 0;
++}
++
++static inline int rt_i2c_wait_idle(void)
++{
++ int retries = I2C_RETRY;
++
++ do {
++ if (!retries--)
++ break;
++ } while(rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
++
++ return (retries < 0);
++}
++
++static inline int rt_i2c_wait_tx_done(void)
++{
++ int retries = I2C_RETRY;
++
++ do {
++ if (!retries--)
++ break;
++ } while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
++
++ return (retries < 0) ? -ETIMEDOUT : 0;
++}
++
++static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
++{
++ int i = 0, j = 0, pos = 0;
++ int nblock = msg->len / READ_BLOCK;
++ int rem = msg->len % READ_BLOCK;
++ int ret = 0;
++
++ if (msg->flags & I2C_M_TEN) {
++ printk("10 bits addr not supported\n");
++ return -EINVAL;
++ }
++
++ if (msg->flags & I2C_M_RD) {
++ for (i = 0; i < nblock; i++) {
++ if (rt_i2c_wait_idle()) {
++ printk("i2c-read line busy\n");
++ return -ETIMEDOUT;
++ }
++ rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
++ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
++ for (j = 0; j < READ_BLOCK; j++) {
++ if (rt_i2c_wait_rx_done() < 0)
++ ret = rt_i2c_wait_rx_done();
++ if (rt_i2c_get_ack() < 0)
++ ret = rt_i2c_get_ack();
++ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
++ }
++ }
++
++ if (rt_i2c_wait_idle()) {
++ printk("i2c-read line busy\n");
++ return -ETIMEDOUT;
++ }
++ if (rem) {
++ rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
++ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
++ }
++ for (i = 0; i < rem; i++) {
++ if (rt_i2c_wait_rx_done() < 0)
++ ret = rt_i2c_wait_rx_done();
++ if (rt_i2c_get_ack() < 0)
++ ret = rt_i2c_get_ack();
++
++ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
++ }
++ } else {
++ if (rt_i2c_wait_idle()) {
++ printk("i2c-write line busy\n");
++ return -ETIMEDOUT;
++ }
++ rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
++ for (i = 0; i < msg->len; i++) {
++ rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
++ rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
++
++ if (rt_i2c_wait_tx_done() < 0)
++ ret = rt_i2c_wait_tx_done();
++ if (rt_i2c_get_ack() < 0)
++ ret = rt_i2c_get_ack();
++ }
++ }
++
++ return ret;
++}
++
++static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
++{
++ int i = 0;
++ int ret = 0;
++
++ if (rt_i2c_wait_idle()) {
++ printk("i2c-master_xfer line busy\n");
++ return -ETIMEDOUT;
++ }
++
++ device_reset(a->dev.parent);
++
++ rt_i2c_w32(m->addr, REG_DEVADDR_REG);
++ rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
++ rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
++
++ for (i = 0; i < n && !ret; i++) {
++ ret = rt_i2c_handle_msg(a, &m[i]);
++
++ if (ret < 0) {
++ return ret;
++ }
++ }
++
++ return n;
++}
++
++static u32 rt_i2c_func(struct i2c_adapter *a)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static const struct i2c_algorithm rt_i2c_algo = {
++ .master_xfer = rt_i2c_master_xfer,
++ .functionality = rt_i2c_func,
++};
++
++static int rt_i2c_probe(struct platform_device *pdev)
++{
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ int ret;
++
++ if (!res) {
++ dev_err(&pdev->dev, "no memory resource found\n");
++ return -ENODEV;
++ }
++
++ adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
++ if (!adapter) {
++ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
++ return -ENOMEM;
++ }
++
++ membase = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(membase))
++ return PTR_ERR(membase);
++
++ strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
++ adapter->owner = THIS_MODULE;
++ adapter->nr = pdev->id;
++ adapter->timeout = HZ;
++ adapter->algo = &rt_i2c_algo;
++ adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++ adapter->dev.parent = &pdev->dev;
++ adapter->dev.of_node = pdev->dev.of_node;
++
++ ret = i2c_add_numbered_adapter(adapter);
++ if (ret)
++ return ret;
++
++ platform_set_drvdata(pdev, adapter);
++
++ dev_info(&pdev->dev, "loaded\n");
++
++ return 0;
++}
++
++static int rt_i2c_remove(struct platform_device *pdev)
++{
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++static const struct of_device_id i2c_rt_dt_ids[] = {
++ { .compatible = "ralink,rt2880-i2c", },
++ { /* sentinel */ }
++};
++
++MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
++
++static struct platform_driver rt_i2c_driver = {
++ .probe = rt_i2c_probe,
++ .remove = rt_i2c_remove,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "i2c-ralink",
++ .of_match_table = i2c_rt_dt_ids,
++ },
++};
++
++static int __init i2c_rt_init (void)
++{
++ return platform_driver_register(&rt_i2c_driver);
++}
++subsys_initcall(i2c_rt_init);
++
++static void __exit i2c_rt_exit (void)
++{
++ platform_driver_unregister(&rt_i2c_driver);
++}
++
++module_exit (i2c_rt_exit);
++
++MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
++MODULE_DESCRIPTION("Ralink I2c host driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:Ralink-I2C");
--- /dev/null
+From f954801c6f48fc291c39ca8a888dbdfda1021415 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 13 Nov 2014 19:08:40 +0100
+Subject: [PATCH] mmc: MIPS: ralink: add sdhci for mt7620a SoC
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mmc/host/Kconfig | 2 +
+ drivers/mmc/host/Makefile | 1 +
+ drivers/mmc/host/mtk-mmc/Kconfig | 16 +
+ drivers/mmc/host/mtk-mmc/Makefile | 42 +
+ drivers/mmc/host/mtk-mmc/board.h | 137 ++
+ drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
+ drivers/mmc/host/mtk-mmc/dbg.h | 153 ++
+ drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
+ drivers/mmc/host/mtk-mmc/sd.c | 3041 ++++++++++++++++++++++++++++++++++
+ 9 files changed, 4740 insertions(+)
+ create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
+ create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
+ create mode 100644 drivers/mmc/host/mtk-mmc/board.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
+ create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
+
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -773,3 +773,5 @@ config MMC_SUNXI
+ help
+ This selects support for the SD/MMC Host Controller on
+ Allwinner sunxi SoCs.
++
++source "drivers/mmc/host/mtk-mmc/Kconfig"
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for MMC/SD host controller drivers
+ #
+
++obj-$(CONFIG_MTK_MMC) += mtk-mmc/
+ obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
+ obj-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
+ obj-$(CONFIG_MMC_PXA) += pxamci.o
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/Kconfig
+@@ -0,0 +1,16 @@
++config MTK_MMC
++ tristate "MTK SD/MMC"
++ depends on !MTD_NAND_RALINK
++
++config MTK_AEE_KDUMP
++ bool "MTK AEE KDUMP"
++ depends on MTK_MMC
++
++config MTK_MMC_CD_POLL
++ bool "Card Detect with Polling"
++ depends on MTK_MMC
++
++config MTK_MMC_EMMC_8BIT
++ bool "eMMC 8-bit support"
++ depends on MTK_MMC && RALINK_MT7628
++
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/Makefile
+@@ -0,0 +1,42 @@
++# Copyright Statement:
++#
++# This software/firmware and related documentation ("MediaTek Software") are
++# protected under relevant copyright laws. The information contained herein
++# is confidential and proprietary to MediaTek Inc. and/or its licensors.
++# Without the prior written permission of MediaTek inc. and/or its licensors,
++# any reproduction, modification, use or disclosure of MediaTek Software,
++# and information contained herein, in whole or in part, shall be strictly prohibited.
++#
++# MediaTek Inc. (C) 2010. All rights reserved.
++#
++# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++#
++# The following software/firmware and/or related documentation ("MediaTek Software")
++# have been modified by MediaTek Inc. All revisions are subject to any receiver's
++# applicable license agreements with MediaTek Inc.
++
++obj-$(CONFIG_MTK_MMC) += mtk_sd.o
++mtk_sd-objs := sd.o dbg.o
++ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
++EXTRA_CFLAGS += -DMT6575_SD_DEBUG
++endif
++
++clean:
++ @rm -f *.o modules.order .*.cmd
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/board.h
+@@ -0,0 +1,137 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#ifndef __ARCH_ARM_MACH_BOARD_H
++#define __ARCH_ARM_MACH_BOARD_H
++
++#include <generated/autoconf.h>
++#include <linux/pm.h>
++/* --- chhung */
++// #include <mach/mt6575.h>
++// #include <board-custom.h>
++/* end of chhung */
++
++typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
++typedef void (*pm_callback_t)(pm_message_t state, void *data);
++
++#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
++#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
++#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
++#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
++#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
++#define MSDC_REMOVABLE (1 << 5) /* removable slot */
++#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
++#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
++#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
++#define MSDC_DDR (1 << 9) /* ddr mode support */
++
++
++#define MSDC_SMPL_RISING (0)
++#define MSDC_SMPL_FALLING (1)
++
++#define MSDC_CMD_PIN (0)
++#define MSDC_DAT_PIN (1)
++#define MSDC_CD_PIN (2)
++#define MSDC_WP_PIN (3)
++#define MSDC_RST_PIN (4)
++
++enum {
++ MSDC_CLKSRC_48MHZ = 0,
++// MSDC_CLKSRC_26MHZ = 0,
++// MSDC_CLKSRC_197MHZ = 1,
++// MSDC_CLKSRC_208MHZ = 2
++};
++
++struct msdc_hw {
++ unsigned char clk_src; /* host clock source */
++ unsigned char cmd_edge; /* command latch edge */
++ unsigned char data_edge; /* data latch edge */
++ unsigned char clk_drv; /* clock pad driving */
++ unsigned char cmd_drv; /* command pad driving */
++ unsigned char dat_drv; /* data pad driving */
++ unsigned long flags; /* hardware capability flags */
++ unsigned long data_pins; /* data pins */
++ unsigned long data_offset; /* data address offset */
++
++ /* config gpio pull mode */
++ void (*config_gpio_pin)(int type, int pull);
++
++ /* external power control for card */
++ void (*ext_power_on)(void);
++ void (*ext_power_off)(void);
++
++ /* external sdio irq operations */
++ void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
++ void (*enable_sdio_eirq)(void);
++ void (*disable_sdio_eirq)(void);
++
++ /* external cd irq operations */
++ void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
++ void (*enable_cd_eirq)(void);
++ void (*disable_cd_eirq)(void);
++ int (*get_cd_status)(void);
++
++ /* power management callback for external module */
++ void (*register_pm)(pm_callback_t pm_cb, void *data);
++};
++
++extern struct msdc_hw msdc0_hw;
++extern struct msdc_hw msdc1_hw;
++extern struct msdc_hw msdc2_hw;
++extern struct msdc_hw msdc3_hw;
++
++/*GPS driver*/
++#define GPS_FLAG_FORCE_OFF 0x0001
++struct mt3326_gps_hardware {
++ int (*ext_power_on)(int);
++ int (*ext_power_off)(int);
++};
++extern struct mt3326_gps_hardware mt3326_gps_hw;
++
++/* NAND driver */
++struct mt6575_nand_host_hw {
++ unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
++ unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
++ unsigned int nfi_cs_num; /* NFI_CS_NUM */
++ unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
++ unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
++ unsigned int nand_ecc_size;
++ unsigned int nand_ecc_bytes;
++ unsigned int nand_ecc_mode;
++};
++extern struct mt6575_nand_host_hw mt6575_nand_hw;
++
++#endif /* __ARCH_ARM_MACH_BOARD_H */
++
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/dbg.c
+@@ -0,0 +1,347 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ *
++ * MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/proc_fs.h>
++#include <linux/string.h>
++#include <linux/uaccess.h>
++// #include <mach/mt6575_gpt.h> /* --- by chhung */
++#include "dbg.h"
++#include "mt6575_sd.h"
++#include <linux/seq_file.h>
++
++static char cmd_buf[256];
++
++/* for debug zone */
++unsigned int sd_debug_zone[4]={
++ 0,
++ 0,
++ 0,
++ 0
++};
++
++/* mode select */
++u32 dma_size[4]={
++ 512,
++ 512,
++ 512,
++ 512
++};
++msdc_mode drv_mode[4]={
++ MODE_SIZE_DEP, /* using DMA or not depend on the size */
++ MODE_SIZE_DEP,
++ MODE_SIZE_DEP,
++ MODE_SIZE_DEP
++};
++
++#if defined (MT6575_SD_DEBUG)
++/* for driver profile */
++#define TICKS_ONE_MS (13000)
++u32 gpt_enable = 0;
++u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
++u32 sdio_pro_time = 0; /* no more than 30s */
++struct sdio_profile sdio_perfomance = {0};
++
++#if 0 /* --- chhung */
++void msdc_init_gpt(void)
++{
++ GPT_CONFIG config;
++
++ config.num = GPT6;
++ config.mode = GPT_FREE_RUN;
++ config.clkSrc = GPT_CLK_SRC_SYS;
++ config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
++
++ if (GPT_Config(config) == FALSE )
++ return;
++
++ GPT_Start(GPT6);
++}
++#endif /* end of --- */
++
++u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
++{
++ u32 ret = 0;
++
++ if (new_H32 == old_H32) {
++ ret = new_L32 - old_L32;
++ } else if(new_H32 == (old_H32 + 1)) {
++ if (new_L32 > old_L32) {
++ printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
++ }
++ ret = (0xffffffff - old_L32);
++ ret += new_L32;
++ } else {
++ printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
++ }
++
++ return ret;
++}
++
++void msdc_sdio_profile(struct sdio_profile* result)
++{
++ struct cmd_profile* cmd;
++ u32 i;
++
++ printk("sdio === performance dump ===\n");
++ printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
++ result->total_tc, result->total_tc / TICKS_ONE_MS,
++ result->total_tx_bytes, result->total_rx_bytes);
++
++ /* CMD52 Dump */
++ cmd = &result->cmd52_rx;
++ printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
++ cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
++ cmd = &result->cmd52_tx;
++ printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
++ cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
++
++ /* CMD53 Rx bytes + block mode */
++ for (i=0; i<512; i++) {
++ cmd = &result->cmd53_rx_byte[i];
++ if (cmd->count) {
++ printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
++ cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
++ cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
++ }
++ }
++ for (i=0; i<100; i++) {
++ cmd = &result->cmd53_rx_blk[i];
++ if (cmd->count) {
++ printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
++ cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
++ cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
++ }
++ }
++
++ /* CMD53 Tx bytes + block mode */
++ for (i=0; i<512; i++) {
++ cmd = &result->cmd53_tx_byte[i];
++ if (cmd->count) {
++ printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
++ cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
++ cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
++ }
++ }
++ for (i=0; i<100; i++) {
++ cmd = &result->cmd53_tx_blk[i];
++ if (cmd->count) {
++ printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
++ cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
++ cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
++ }
++ }
++
++ printk("sdio === performance dump done ===\n");
++}
++
++//========= sdio command table ===========
++void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
++{
++ struct sdio_profile* result = &sdio_perfomance;
++ struct cmd_profile* cmd;
++ u32 block;
++
++ if (sdio_pro_enable == 0) {
++ return;
++ }
++
++ if (opcode == 52) {
++ cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
++ } else if (opcode == 53) {
++ if (sizes < 512) {
++ cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
++ } else {
++ block = sizes / 512;
++ if (block >= 99) {
++ printk("cmd53 error blocks\n");
++ while(1);
++ }
++ cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
++ }
++ } else {
++ return;
++ }
++
++ /* update the members */
++ if (ticks > cmd->max_tc){
++ cmd->max_tc = ticks;
++ }
++ if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
++ cmd->min_tc = ticks;
++ }
++ cmd->tot_tc += ticks;
++ cmd->tot_bytes += sizes;
++ cmd->count ++;
++
++ if (bRx) {
++ result->total_rx_bytes += sizes;
++ } else {
++ result->total_tx_bytes += sizes;
++ }
++ result->total_tc += ticks;
++
++ /* dump when total_tc > 30s */
++ if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
++ msdc_sdio_profile(result);
++ memset(result, 0 , sizeof(struct sdio_profile));
++ }
++}
++
++//========== driver proc interface ===========
++static int msdc_debug_proc_read(struct seq_file *s, void *p)
++{
++ seq_printf(s, "\n=========================================\n");
++ seq_printf(s, "Index<0> + Id + Zone\n");
++ seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
++ seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
++ seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
++ seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
++ seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
++ seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
++
++ seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
++ seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
++ seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
++ seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
++ seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
++ seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
++ seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
++
++ seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
++ seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
++ seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
++ seq_printf(s, "=========================================\n\n");
++
++ return 0;
++}
++
++static ssize_t msdc_debug_proc_write(struct file *file,
++ const char __user *buf, size_t count, loff_t *data)
++{
++ int ret;
++
++ int cmd, p1, p2;
++ int id, zone;
++ int mode, size;
++
++ if (count == 0)return -1;
++ if(count > 255)count = 255;
++
++ ret = copy_from_user(cmd_buf, buf, count);
++ if (ret < 0)return -1;
++
++ cmd_buf[count] = '\0';
++ printk("msdc Write %s\n", cmd_buf);
++
++ sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
++
++ if(cmd == SD_TOOL_ZONE) {
++ id = p1; zone = p2; zone &= 0x3ff;
++ printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
++ if(id >=0 && id<=3){
++ sd_debug_zone[id] = zone;
++ }
++ else if(id == 4){
++ sd_debug_zone[0] = sd_debug_zone[1] = zone;
++ sd_debug_zone[2] = sd_debug_zone[3] = zone;
++ }
++ else{
++ printk("msdc host_id error when set debug zone\n");
++ }
++ } else if (cmd == SD_TOOL_DMA_SIZE) {
++ id = p1>>4; mode = (p1&0xf); size = p2;
++ if(id >=0 && id<=3){
++ drv_mode[id] = mode;
++ dma_size[id] = p2;
++ }
++ else if(id == 4){
++ drv_mode[0] = drv_mode[1] = mode;
++ drv_mode[2] = drv_mode[3] = mode;
++ dma_size[0] = dma_size[1] = p2;
++ dma_size[2] = dma_size[3] = p2;
++ }
++ else{
++ printk("msdc host_id error when select mode\n");
++ }
++ } else if (cmd == SD_TOOL_SDIO_PROFILE) {
++ if (p1 == 1) { /* enable profile */
++ if (gpt_enable == 0) {
++ // msdc_init_gpt(); /* --- by chhung */
++ gpt_enable = 1;
++ }
++ sdio_pro_enable = 1;
++ if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
++ sdio_pro_time = p2 ;
++ } else if (p1 == 0) {
++ /* todo */
++ sdio_pro_enable = 0;
++ }
++ }
++
++ return count;
++}
++
++static int msdc_debug_show(struct inode *inode, struct file *file)
++{
++ return single_open(file, msdc_debug_proc_read, NULL);
++}
++
++static const struct file_operations msdc_debug_fops = {
++ .owner = THIS_MODULE,
++ .open = msdc_debug_show,
++ .read = seq_read,
++ .write = msdc_debug_proc_write,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++int msdc_debug_proc_init(void)
++{
++ struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
++
++ if (!de || IS_ERR(de))
++ printk("!! Create MSDC debug PROC fail !!\n");
++
++ return 0 ;
++}
++EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
++#endif
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/dbg.h
+@@ -0,0 +1,156 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ *
++ * MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++#ifndef __MT_MSDC_DEUBG__
++#define __MT_MSDC_DEUBG__
++
++//==========================
++extern u32 sdio_pro_enable;
++/* for a type command, e.g. CMD53, 2 blocks */
++struct cmd_profile {
++ u32 max_tc; /* Max tick count */
++ u32 min_tc;
++ u32 tot_tc; /* total tick count */
++ u32 tot_bytes;
++ u32 count; /* the counts of the command */
++};
++
++/* dump when total_tc and total_bytes */
++struct sdio_profile {
++ u32 total_tc; /* total tick count of CMD52 and CMD53 */
++ u32 total_tx_bytes; /* total bytes of CMD53 Tx */
++ u32 total_rx_bytes; /* total bytes of CMD53 Rx */
++
++ /*CMD52*/
++ struct cmd_profile cmd52_tx;
++ struct cmd_profile cmd52_rx;
++
++ /*CMD53 in byte unit */
++ struct cmd_profile cmd53_tx_byte[512];
++ struct cmd_profile cmd53_rx_byte[512];
++
++ /*CMD53 in block unit */
++ struct cmd_profile cmd53_tx_blk[100];
++ struct cmd_profile cmd53_rx_blk[100];
++};
++
++//==========================
++typedef enum {
++ SD_TOOL_ZONE = 0,
++ SD_TOOL_DMA_SIZE = 1,
++ SD_TOOL_PM_ENABLE = 2,
++ SD_TOOL_SDIO_PROFILE = 3,
++} msdc_dbg;
++
++typedef enum {
++ MODE_PIO = 0,
++ MODE_DMA = 1,
++ MODE_SIZE_DEP = 2,
++} msdc_mode;
++extern msdc_mode drv_mode[4];
++extern u32 dma_size[4];
++
++/* Debug message event */
++#define DBG_EVT_NONE (0) /* No event */
++#define DBG_EVT_DMA (1 << 0) /* DMA related event */
++#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
++#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
++#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
++#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
++#define DBG_EVT_FUC (1 << 5) /* Function event */
++#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
++#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
++#define DBG_EVT_WRN (1 << 8) /* Warning event */
++#define DBG_EVT_PWR (1 << 9) /* Power event */
++#define DBG_EVT_ALL (0xffffffff)
++
++#define DBG_EVT_MASK (DBG_EVT_ALL)
++
++extern unsigned int sd_debug_zone[4];
++#define TAG "msdc"
++#if 0 /* +++ chhung */
++#define BUG_ON(x) \
++do { \
++ if (x) { \
++ printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
++ while(1); \
++ } \
++}while(0)
++#endif /* end of +++ */
++
++#define N_MSG(evt, fmt, args...)
++/*
++do { \
++ if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
++ printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
++ host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
++ } \
++} while(0)
++*/
++
++#define ERR_MSG(fmt, args...) \
++do { \
++ printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
++ host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
++} while(0);
++
++#if 1
++//defined CONFIG_MTK_MMC_CD_POLL
++#define INIT_MSG(fmt, args...)
++#define IRQ_MSG(fmt, args...)
++#else
++#define INIT_MSG(fmt, args...) \
++do { \
++ printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
++ host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
++} while(0);
++
++/* PID in ISR in not corrent */
++#define IRQ_MSG(fmt, args...) \
++do { \
++ printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
++ host->id, ##args , __FUNCTION__, __LINE__); \
++} while(0);
++#endif
++
++int msdc_debug_proc_init(void);
++
++#if 0 /* --- chhung */
++void msdc_init_gpt(void);
++extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
++#endif /* end of --- */
++u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
++void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
++
++#endif
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
+@@ -0,0 +1,1001 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#ifndef MT6575_SD_H
++#define MT6575_SD_H
++
++#include <linux/bitops.h>
++#include <linux/mmc/host.h>
++
++// #include <mach/mt6575_reg_base.h> /* --- by chhung */
++
++/*--------------------------------------------------------------------------*/
++/* Common Macro */
++/*--------------------------------------------------------------------------*/
++#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
++
++/*--------------------------------------------------------------------------*/
++/* Common Definition */
++/*--------------------------------------------------------------------------*/
++#define MSDC_FIFO_SZ (128)
++#define MSDC_FIFO_THD (64) // (128)
++#define MSDC_NUM (4)
++
++#define MSDC_MS (0)
++#define MSDC_SDMMC (1)
++
++#define MSDC_MODE_UNKNOWN (0)
++#define MSDC_MODE_PIO (1)
++#define MSDC_MODE_DMA_BASIC (2)
++#define MSDC_MODE_DMA_DESC (3)
++#define MSDC_MODE_DMA_ENHANCED (4)
++#define MSDC_MODE_MMC_STREAM (5)
++
++#define MSDC_BUS_1BITS (0)
++#define MSDC_BUS_4BITS (1)
++#define MSDC_BUS_8BITS (2)
++
++#define MSDC_BRUST_8B (3)
++#define MSDC_BRUST_16B (4)
++#define MSDC_BRUST_32B (5)
++#define MSDC_BRUST_64B (6)
++
++#define MSDC_PIN_PULL_NONE (0)
++#define MSDC_PIN_PULL_DOWN (1)
++#define MSDC_PIN_PULL_UP (2)
++#define MSDC_PIN_KEEP (3)
++
++#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
++#define MSDC_MIN_SCLK (260000)
++
++#define MSDC_AUTOCMD12 (0x0001)
++#define MSDC_AUTOCMD23 (0x0002)
++#define MSDC_AUTOCMD19 (0x0003)
++
++#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
++#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
++
++enum {
++ RESP_NONE = 0,
++ RESP_R1,
++ RESP_R2,
++ RESP_R3,
++ RESP_R4,
++ RESP_R5,
++ RESP_R6,
++ RESP_R7,
++ RESP_R1B
++};
++
++/*--------------------------------------------------------------------------*/
++/* Register Offset */
++/*--------------------------------------------------------------------------*/
++#define OFFSET_MSDC_CFG (0x0)
++#define OFFSET_MSDC_IOCON (0x04)
++#define OFFSET_MSDC_PS (0x08)
++#define OFFSET_MSDC_INT (0x0c)
++#define OFFSET_MSDC_INTEN (0x10)
++#define OFFSET_MSDC_FIFOCS (0x14)
++#define OFFSET_MSDC_TXDATA (0x18)
++#define OFFSET_MSDC_RXDATA (0x1c)
++#define OFFSET_SDC_CFG (0x30)
++#define OFFSET_SDC_CMD (0x34)
++#define OFFSET_SDC_ARG (0x38)
++#define OFFSET_SDC_STS (0x3c)
++#define OFFSET_SDC_RESP0 (0x40)
++#define OFFSET_SDC_RESP1 (0x44)
++#define OFFSET_SDC_RESP2 (0x48)
++#define OFFSET_SDC_RESP3 (0x4c)
++#define OFFSET_SDC_BLK_NUM (0x50)
++#define OFFSET_SDC_CSTS (0x58)
++#define OFFSET_SDC_CSTS_EN (0x5c)
++#define OFFSET_SDC_DCRC_STS (0x60)
++#define OFFSET_EMMC_CFG0 (0x70)
++#define OFFSET_EMMC_CFG1 (0x74)
++#define OFFSET_EMMC_STS (0x78)
++#define OFFSET_EMMC_IOCON (0x7c)
++#define OFFSET_SDC_ACMD_RESP (0x80)
++#define OFFSET_SDC_ACMD19_TRG (0x84)
++#define OFFSET_SDC_ACMD19_STS (0x88)
++#define OFFSET_MSDC_DMA_SA (0x90)
++#define OFFSET_MSDC_DMA_CA (0x94)
++#define OFFSET_MSDC_DMA_CTRL (0x98)
++#define OFFSET_MSDC_DMA_CFG (0x9c)
++#define OFFSET_MSDC_DBG_SEL (0xa0)
++#define OFFSET_MSDC_DBG_OUT (0xa4)
++#define OFFSET_MSDC_PATCH_BIT (0xb0)
++#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
++#define OFFSET_MSDC_PAD_CTL0 (0xe0)
++#define OFFSET_MSDC_PAD_CTL1 (0xe4)
++#define OFFSET_MSDC_PAD_CTL2 (0xe8)
++#define OFFSET_MSDC_PAD_TUNE (0xec)
++#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
++#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
++#define OFFSET_MSDC_HW_DBG (0xf8)
++#define OFFSET_MSDC_VERSION (0x100)
++#define OFFSET_MSDC_ECO_VER (0x104)
++
++/*--------------------------------------------------------------------------*/
++/* Register Address */
++/*--------------------------------------------------------------------------*/
++
++/* common register */
++#define MSDC_CFG REG_ADDR(MSDC_CFG)
++#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
++#define MSDC_PS REG_ADDR(MSDC_PS)
++#define MSDC_INT REG_ADDR(MSDC_INT)
++#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
++#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
++#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
++#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
++#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
++
++/* sdmmc register */
++#define SDC_CFG REG_ADDR(SDC_CFG)
++#define SDC_CMD REG_ADDR(SDC_CMD)
++#define SDC_ARG REG_ADDR(SDC_ARG)
++#define SDC_STS REG_ADDR(SDC_STS)
++#define SDC_RESP0 REG_ADDR(SDC_RESP0)
++#define SDC_RESP1 REG_ADDR(SDC_RESP1)
++#define SDC_RESP2 REG_ADDR(SDC_RESP2)
++#define SDC_RESP3 REG_ADDR(SDC_RESP3)
++#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
++#define SDC_CSTS REG_ADDR(SDC_CSTS)
++#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
++#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
++
++/* emmc register*/
++#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
++#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
++#define EMMC_STS REG_ADDR(EMMC_STS)
++#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
++
++/* auto command register */
++#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
++#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
++#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
++
++/* dma register */
++#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
++#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
++#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
++#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
++
++/* pad ctrl register */
++#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
++#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
++#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
++
++/* data read delay */
++#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
++#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
++
++/* debug register */
++#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
++#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
++
++/* misc register */
++#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
++#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
++#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
++#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
++#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
++#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
++
++/*--------------------------------------------------------------------------*/
++/* Register Mask */
++/*--------------------------------------------------------------------------*/
++
++/* MSDC_CFG mask */
++#define MSDC_CFG_MODE (0x1 << 0) /* RW */
++#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
++#define MSDC_CFG_RST (0x1 << 2) /* RW */
++#define MSDC_CFG_PIO (0x1 << 3) /* RW */
++#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
++#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
++#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
++#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
++#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
++#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
++
++/* MSDC_IOCON mask */
++#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
++#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
++#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
++#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
++#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
++#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
++#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
++#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
++#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
++#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
++#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
++#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
++#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
++#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
++#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
++
++/* MSDC_PS mask */
++#define MSDC_PS_CDEN (0x1 << 0) /* RW */
++#define MSDC_PS_CDSTS (0x1 << 1) /* R */
++#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
++#define MSDC_PS_DAT (0xff << 16) /* R */
++#define MSDC_PS_CMD (0x1 << 24) /* R */
++#define MSDC_PS_WP (0x1UL<< 31) /* R */
++
++/* MSDC_INT mask */
++#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
++#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
++#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
++#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
++#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
++#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
++#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
++#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
++#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
++#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
++#define MSDC_INT_CSTA (0x1 << 11) /* R */
++#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
++#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
++#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
++#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
++#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
++
++/* MSDC_INTEN mask */
++#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
++#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
++#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
++#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
++#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
++#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
++#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
++#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
++#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
++#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
++#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
++#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
++#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
++#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
++#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
++#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
++
++/* MSDC_FIFOCS mask */
++#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
++#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
++#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
++
++/* SDC_CFG mask */
++#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
++#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
++#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
++#define SDC_CFG_SDIO (0x1 << 19) /* RW */
++#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
++#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
++#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
++
++/* SDC_CMD mask */
++#define SDC_CMD_OPC (0x3f << 0) /* RW */
++#define SDC_CMD_BRK (0x1 << 6) /* RW */
++#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
++#define SDC_CMD_DTYP (0x3 << 11) /* RW */
++#define SDC_CMD_DTYP (0x3 << 11) /* RW */
++#define SDC_CMD_RW (0x1 << 13) /* RW */
++#define SDC_CMD_STOP (0x1 << 14) /* RW */
++#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
++#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
++#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
++#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
++
++/* SDC_STS mask */
++#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
++#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
++#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
++
++/* SDC_DCRC_STS mask */
++#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
++#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
++
++/* EMMC_CFG0 mask */
++#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
++#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
++#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
++#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
++#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
++#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
++
++/* EMMC_CFG1 mask */
++#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
++#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
++
++/* EMMC_STS mask */
++#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
++#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
++#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
++#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
++#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
++#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
++#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
++
++/* EMMC_IOCON mask */
++#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
++
++/* SDC_ACMD19_TRG mask */
++#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
++
++/* MSDC_DMA_CTRL mask */
++#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
++#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
++#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
++#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
++#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
++#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
++#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
++
++/* MSDC_DMA_CFG mask */
++#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
++#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
++#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
++#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
++
++/* MSDC_PATCH_BIT mask */
++#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
++#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
++#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
++#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
++#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
++#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
++#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
++#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
++#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
++#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
++#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
++#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
++
++/* MSDC_PATCH_BIT1 mask */
++#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
++#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
++
++/* MSDC_PAD_CTL0 mask */
++#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
++#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
++#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
++#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
++#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
++#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
++#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
++#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
++#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
++
++/* MSDC_PAD_CTL1 mask */
++#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
++#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
++#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
++#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
++#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
++#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
++#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
++#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
++#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
++
++/* MSDC_PAD_CTL2 mask */
++#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
++#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
++#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
++#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
++#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
++#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
++#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
++#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
++#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
++
++/* MSDC_PAD_TUNE mask */
++#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
++#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
++#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
++#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
++#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
++
++/* MSDC_DAT_RDDLY0/1 mask */
++#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
++#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
++#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
++#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
++
++#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
++#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
++#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
++#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
++
++#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
++#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
++#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
++#define CARD_READY_FOR_DATA (1<<8)
++#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
++
++/*--------------------------------------------------------------------------*/
++/* Descriptor Structure */
++/*--------------------------------------------------------------------------*/
++typedef struct {
++ u32 hwo:1; /* could be changed by hw */
++ u32 bdp:1;
++ u32 rsv0:6;
++ u32 chksum:8;
++ u32 intr:1;
++ u32 rsv1:15;
++ void *next;
++ void *ptr;
++ u32 buflen:16;
++ u32 extlen:8;
++ u32 rsv2:8;
++ u32 arg;
++ u32 blknum;
++ u32 cmd;
++} gpd_t;
++
++typedef struct {
++ u32 eol:1;
++ u32 rsv0:7;
++ u32 chksum:8;
++ u32 rsv1:1;
++ u32 blkpad:1;
++ u32 dwpad:1;
++ u32 rsv2:13;
++ void *next;
++ void *ptr;
++ u32 buflen:16;
++ u32 rsv3:16;
++} bd_t;
++
++/*--------------------------------------------------------------------------*/
++/* Register Debugging Structure */
++/*--------------------------------------------------------------------------*/
++
++typedef struct {
++ u32 msdc:1;
++ u32 ckpwn:1;
++ u32 rst:1;
++ u32 pio:1;
++ u32 ckdrven:1;
++ u32 start18v:1;
++ u32 pass18v:1;
++ u32 ckstb:1;
++ u32 ckdiv:8;
++ u32 ckmod:2;
++ u32 pad:14;
++} msdc_cfg_reg;
++typedef struct {
++ u32 sdr104cksel:1;
++ u32 rsmpl:1;
++ u32 dsmpl:1;
++ u32 ddlysel:1;
++ u32 ddr50ckd:1;
++ u32 dsplsel:1;
++ u32 pad1:10;
++ u32 d0spl:1;
++ u32 d1spl:1;
++ u32 d2spl:1;
++ u32 d3spl:1;
++ u32 d4spl:1;
++ u32 d5spl:1;
++ u32 d6spl:1;
++ u32 d7spl:1;
++ u32 riscsz:1;
++ u32 pad2:7;
++} msdc_iocon_reg;
++typedef struct {
++ u32 cden:1;
++ u32 cdsts:1;
++ u32 pad1:10;
++ u32 cddebounce:4;
++ u32 dat:8;
++ u32 cmd:1;
++ u32 pad2:6;
++ u32 wp:1;
++} msdc_ps_reg;
++typedef struct {
++ u32 mmcirq:1;
++ u32 cdsc:1;
++ u32 pad1:1;
++ u32 atocmdrdy:1;
++ u32 atocmdtmo:1;
++ u32 atocmdcrc:1;
++ u32 dmaqempty:1;
++ u32 sdioirq:1;
++ u32 cmdrdy:1;
++ u32 cmdtmo:1;
++ u32 rspcrc:1;
++ u32 csta:1;
++ u32 xfercomp:1;
++ u32 dxferdone:1;
++ u32 dattmo:1;
++ u32 datcrc:1;
++ u32 atocmd19done:1;
++ u32 pad2:15;
++} msdc_int_reg;
++typedef struct {
++ u32 mmcirq:1;
++ u32 cdsc:1;
++ u32 pad1:1;
++ u32 atocmdrdy:1;
++ u32 atocmdtmo:1;
++ u32 atocmdcrc:1;
++ u32 dmaqempty:1;
++ u32 sdioirq:1;
++ u32 cmdrdy:1;
++ u32 cmdtmo:1;
++ u32 rspcrc:1;
++ u32 csta:1;
++ u32 xfercomp:1;
++ u32 dxferdone:1;
++ u32 dattmo:1;
++ u32 datcrc:1;
++ u32 atocmd19done:1;
++ u32 pad2:15;
++} msdc_inten_reg;
++typedef struct {
++ u32 rxcnt:8;
++ u32 pad1:8;
++ u32 txcnt:8;
++ u32 pad2:7;
++ u32 clr:1;
++} msdc_fifocs_reg;
++typedef struct {
++ u32 val;
++} msdc_txdat_reg;
++typedef struct {
++ u32 val;
++} msdc_rxdat_reg;
++typedef struct {
++ u32 sdiowkup:1;
++ u32 inswkup:1;
++ u32 pad1:14;
++ u32 buswidth:2;
++ u32 pad2:1;
++ u32 sdio:1;
++ u32 sdioide:1;
++ u32 intblkgap:1;
++ u32 pad4:2;
++ u32 dtoc:8;
++} sdc_cfg_reg;
++typedef struct {
++ u32 cmd:6;
++ u32 brk:1;
++ u32 rsptyp:3;
++ u32 pad1:1;
++ u32 dtype:2;
++ u32 rw:1;
++ u32 stop:1;
++ u32 goirq:1;
++ u32 blklen:12;
++ u32 atocmd:2;
++ u32 volswth:1;
++ u32 pad2:1;
++} sdc_cmd_reg;
++typedef struct {
++ u32 arg;
++} sdc_arg_reg;
++typedef struct {
++ u32 sdcbusy:1;
++ u32 cmdbusy:1;
++ u32 pad:29;
++ u32 swrcmpl:1;
++} sdc_sts_reg;
++typedef struct {
++ u32 val;
++} sdc_resp0_reg;
++typedef struct {
++ u32 val;
++} sdc_resp1_reg;
++typedef struct {
++ u32 val;
++} sdc_resp2_reg;
++typedef struct {
++ u32 val;
++} sdc_resp3_reg;
++typedef struct {
++ u32 num;
++} sdc_blknum_reg;
++typedef struct {
++ u32 sts;
++} sdc_csts_reg;
++typedef struct {
++ u32 sts;
++} sdc_cstsen_reg;
++typedef struct {
++ u32 datcrcsts:8;
++ u32 ddrcrcsts:4;
++ u32 pad:20;
++} sdc_datcrcsts_reg;
++typedef struct {
++ u32 bootstart:1;
++ u32 bootstop:1;
++ u32 bootmode:1;
++ u32 pad1:9;
++ u32 bootwaidly:3;
++ u32 bootsupp:1;
++ u32 pad2:16;
++} emmc_cfg0_reg;
++typedef struct {
++ u32 bootcrctmc:16;
++ u32 pad:4;
++ u32 bootacktmc:12;
++} emmc_cfg1_reg;
++typedef struct {
++ u32 bootcrcerr:1;
++ u32 bootackerr:1;
++ u32 bootdattmo:1;
++ u32 bootacktmo:1;
++ u32 bootupstate:1;
++ u32 bootackrcv:1;
++ u32 bootdatrcv:1;
++ u32 pad:25;
++} emmc_sts_reg;
++typedef struct {
++ u32 bootrst:1;
++ u32 pad:31;
++} emmc_iocon_reg;
++typedef struct {
++ u32 val;
++} msdc_acmd_resp_reg;
++typedef struct {
++ u32 tunesel:4;
++ u32 pad:28;
++} msdc_acmd19_trg_reg;
++typedef struct {
++ u32 val;
++} msdc_acmd19_sts_reg;
++typedef struct {
++ u32 addr;
++} msdc_dma_sa_reg;
++typedef struct {
++ u32 addr;
++} msdc_dma_ca_reg;
++typedef struct {
++ u32 start:1;
++ u32 stop:1;
++ u32 resume:1;
++ u32 pad1:5;
++ u32 mode:1;
++ u32 pad2:1;
++ u32 lastbuf:1;
++ u32 pad3:1;
++ u32 brustsz:3;
++ u32 pad4:1;
++ u32 xfersz:16;
++} msdc_dma_ctrl_reg;
++typedef struct {
++ u32 status:1;
++ u32 decsen:1;
++ u32 pad1:2;
++ u32 bdcsen:1;
++ u32 gpdcsen:1;
++ u32 pad2:26;
++} msdc_dma_cfg_reg;
++typedef struct {
++ u32 sel:16;
++ u32 pad2:16;
++} msdc_dbg_sel_reg;
++typedef struct {
++ u32 val;
++} msdc_dbg_out_reg;
++typedef struct {
++ u32 clkdrvn:3;
++ u32 rsv0:1;
++ u32 clkdrvp:3;
++ u32 rsv1:1;
++ u32 clksr:1;
++ u32 rsv2:7;
++ u32 clkpd:1;
++ u32 clkpu:1;
++ u32 clksmt:1;
++ u32 clkies:1;
++ u32 clktdsel:4;
++ u32 clkrdsel:8;
++} msdc_pad_ctl0_reg;
++typedef struct {
++ u32 cmddrvn:3;
++ u32 rsv0:1;
++ u32 cmddrvp:3;
++ u32 rsv1:1;
++ u32 cmdsr:1;
++ u32 rsv2:7;
++ u32 cmdpd:1;
++ u32 cmdpu:1;
++ u32 cmdsmt:1;
++ u32 cmdies:1;
++ u32 cmdtdsel:4;
++ u32 cmdrdsel:8;
++} msdc_pad_ctl1_reg;
++typedef struct {
++ u32 datdrvn:3;
++ u32 rsv0:1;
++ u32 datdrvp:3;
++ u32 rsv1:1;
++ u32 datsr:1;
++ u32 rsv2:7;
++ u32 datpd:1;
++ u32 datpu:1;
++ u32 datsmt:1;
++ u32 daties:1;
++ u32 dattdsel:4;
++ u32 datrdsel:8;
++} msdc_pad_ctl2_reg;
++typedef struct {
++ u32 wrrxdly:3;
++ u32 pad1:5;
++ u32 rdrxdly:8;
++ u32 pad2:16;
++} msdc_pad_tune_reg;
++typedef struct {
++ u32 dat0:5;
++ u32 rsv0:3;
++ u32 dat1:5;
++ u32 rsv1:3;
++ u32 dat2:5;
++ u32 rsv2:3;
++ u32 dat3:5;
++ u32 rsv3:3;
++} msdc_dat_rddly0;
++typedef struct {
++ u32 dat4:5;
++ u32 rsv4:3;
++ u32 dat5:5;
++ u32 rsv5:3;
++ u32 dat6:5;
++ u32 rsv6:3;
++ u32 dat7:5;
++ u32 rsv7:3;
++} msdc_dat_rddly1;
++typedef struct {
++ u32 dbg0sel:8;
++ u32 dbg1sel:6;
++ u32 pad1:2;
++ u32 dbg2sel:6;
++ u32 pad2:2;
++ u32 dbg3sel:6;
++ u32 pad3:2;
++} msdc_hw_dbg_reg;
++typedef struct {
++ u32 val;
++} msdc_version_reg;
++typedef struct {
++ u32 val;
++} msdc_eco_ver_reg;
++
++struct msdc_regs {
++ msdc_cfg_reg msdc_cfg; /* base+0x00h */
++ msdc_iocon_reg msdc_iocon; /* base+0x04h */
++ msdc_ps_reg msdc_ps; /* base+0x08h */
++ msdc_int_reg msdc_int; /* base+0x0ch */
++ msdc_inten_reg msdc_inten; /* base+0x10h */
++ msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
++ msdc_txdat_reg msdc_txdat; /* base+0x18h */
++ msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
++ u32 rsv1[4];
++ sdc_cfg_reg sdc_cfg; /* base+0x30h */
++ sdc_cmd_reg sdc_cmd; /* base+0x34h */
++ sdc_arg_reg sdc_arg; /* base+0x38h */
++ sdc_sts_reg sdc_sts; /* base+0x3ch */
++ sdc_resp0_reg sdc_resp0; /* base+0x40h */
++ sdc_resp1_reg sdc_resp1; /* base+0x44h */
++ sdc_resp2_reg sdc_resp2; /* base+0x48h */
++ sdc_resp3_reg sdc_resp3; /* base+0x4ch */
++ sdc_blknum_reg sdc_blknum; /* base+0x50h */
++ u32 rsv2[1];
++ sdc_csts_reg sdc_csts; /* base+0x58h */
++ sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
++ sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
++ u32 rsv3[3];
++ emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
++ emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
++ emmc_sts_reg emmc_sts; /* base+0x78h */
++ emmc_iocon_reg emmc_iocon; /* base+0x7ch */
++ msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
++ msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
++ msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
++ u32 rsv4[1];
++ msdc_dma_sa_reg dma_sa; /* base+0x90h */
++ msdc_dma_ca_reg dma_ca; /* base+0x94h */
++ msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
++ msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
++ msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
++ msdc_dbg_out_reg dbg_out; /* base+0xa4h */
++ u32 rsv5[2];
++ u32 patch0; /* base+0xb0h */
++ u32 patch1; /* base+0xb4h */
++ u32 rsv6[10];
++ msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
++ msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
++ msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
++ msdc_pad_tune_reg pad_tune; /* base+0xech */
++ msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
++ msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
++ msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
++ u32 rsv7[1];
++ msdc_version_reg version; /* base+0x100h */
++ msdc_eco_ver_reg eco_ver; /* base+0x104h */
++};
++
++struct scatterlist_ex {
++ u32 cmd;
++ u32 arg;
++ u32 sglen;
++ struct scatterlist *sg;
++};
++
++#define DMA_FLAG_NONE (0x00000000)
++#define DMA_FLAG_EN_CHKSUM (0x00000001)
++#define DMA_FLAG_PAD_BLOCK (0x00000002)
++#define DMA_FLAG_PAD_DWORD (0x00000004)
++
++struct msdc_dma {
++ u32 flags; /* flags */
++ u32 xfersz; /* xfer size in bytes */
++ u32 sglen; /* size of scatter list */
++ u32 blklen; /* block size */
++ struct scatterlist *sg; /* I/O scatter list */
++ struct scatterlist_ex *esg; /* extended I/O scatter list */
++ u8 mode; /* dma mode */
++ u8 burstsz; /* burst size */
++ u8 intr; /* dma done interrupt */
++ u8 padding; /* padding */
++ u32 cmd; /* enhanced mode command */
++ u32 arg; /* enhanced mode arg */
++ u32 rsp; /* enhanced mode command response */
++ u32 autorsp; /* auto command response */
++
++ gpd_t *gpd; /* pointer to gpd array */
++ bd_t *bd; /* pointer to bd array */
++ dma_addr_t gpd_addr; /* the physical address of gpd array */
++ dma_addr_t bd_addr; /* the physical address of bd array */
++ u32 used_gpd; /* the number of used gpd elements */
++ u32 used_bd; /* the number of used bd elements */
++};
++
++struct msdc_host
++{
++ struct msdc_hw *hw;
++
++ struct mmc_host *mmc; /* mmc structure */
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++ struct mmc_request *mrq;
++ int cmd_rsp;
++ int cmd_rsp_done;
++ int cmd_r1b_done;
++
++ int error;
++ spinlock_t lock; /* mutex */
++ struct semaphore sem;
++
++ u32 blksz; /* host block size */
++ u32 base; /* host base address */
++ int id; /* host id */
++ int pwr_ref; /* core power reference count */
++
++ u32 xfer_size; /* total transferred size */
++
++ struct msdc_dma dma; /* dma channel */
++ u32 dma_addr; /* dma transfer address */
++ u32 dma_left_size; /* dma transfer left size */
++ u32 dma_xfer_size; /* dma transfer size in bytes */
++ int dma_xfer; /* dma transfer mode */
++
++ u32 timeout_ns; /* data timeout ns */
++ u32 timeout_clks; /* data timeout clks */
++
++ atomic_t abort; /* abort transfer */
++
++ int irq; /* host interrupt */
++
++ struct tasklet_struct card_tasklet;
++#if 0
++ struct work_struct card_workqueue;
++#else
++ struct delayed_work card_delaywork;
++#endif
++
++ struct completion cmd_done;
++ struct completion xfer_done;
++ struct pm_message pm_state;
++
++ u32 mclk; /* mmc subsystem clock */
++ u32 hclk; /* host clock speed */
++ u32 sclk; /* SD/MS clock speed */
++ u8 core_clkon; /* Host core clock on ? */
++ u8 card_clkon; /* Card clock on ? */
++ u8 core_power; /* core power */
++ u8 power_mode; /* host power mode */
++ u8 card_inserted; /* card inserted ? */
++ u8 suspend; /* host suspended ? */
++ u8 reserved;
++ u8 app_cmd; /* for app command */
++ u32 app_cmd_arg;
++ u64 starttime;
++};
++
++static inline unsigned int uffs(unsigned int x)
++{
++ unsigned int r = 1;
++
++ if (!x)
++ return 0;
++ if (!(x & 0xffff)) {
++ x >>= 16;
++ r += 16;
++ }
++ if (!(x & 0xff)) {
++ x >>= 8;
++ r += 8;
++ }
++ if (!(x & 0xf)) {
++ x >>= 4;
++ r += 4;
++ }
++ if (!(x & 3)) {
++ x >>= 2;
++ r += 2;
++ }
++ if (!(x & 1)) {
++ x >>= 1;
++ r += 1;
++ }
++ return r;
++}
++#define sdr_read8(reg) __raw_readb(reg)
++#define sdr_read16(reg) __raw_readw(reg)
++#define sdr_read32(reg) __raw_readl(reg)
++#define sdr_write8(reg,val) __raw_writeb(val,reg)
++#define sdr_write16(reg,val) __raw_writew(val,reg)
++#define sdr_write32(reg,val) __raw_writel(val,reg)
++
++#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
++#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
++
++#define sdr_set_field(reg,field,val) \
++ do { \
++ volatile unsigned int tv = sdr_read32(reg); \
++ tv &= ~(field); \
++ tv |= ((val) << (uffs((unsigned int)field) - 1)); \
++ sdr_write32(reg,tv); \
++ } while(0)
++#define sdr_get_field(reg,field,val) \
++ do { \
++ volatile unsigned int tv = sdr_read32(reg); \
++ val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
++ } while(0)
++
++#endif
++
+--- /dev/null
++++ b/drivers/mmc/host/mtk-mmc/sd.c
+@@ -0,0 +1,3047 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ *
++ * MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/timer.h>
++#include <linux/ioport.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/blkdev.h>
++#include <linux/slab.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/core.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/sd.h>
++#include <linux/mmc/sdio.h>
++#include <linux/dma-mapping.h>
++
++/* +++ by chhung */
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/pm.h>
++
++#define MSDC_SMPL_FALLING (1)
++#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
++#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
++#define MSDC_REMOVABLE (1 << 5) /* removable slot */
++#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
++#define MSDC_HIGHSPEED (1 << 7)
++
++//#define IRQ_SDC 14 //MT7620 /*FIXME*/
++#ifdef CONFIG_SOC_MT7621
++#define RALINK_SYSCTL_BASE 0xbe000000
++#define RALINK_MSDC_BASE 0xbe130000
++#else
++#define RALINK_SYSCTL_BASE 0xb0000000
++#define RALINK_MSDC_BASE 0xb0130000
++#endif
++#define IRQ_SDC 22 /*FIXME*/
++
++#include <asm/dma.h>
++/* end of +++ */
++
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#if 0 /* --- by chhung */
++#include <mach/board.h>
++#include <mach/mt6575_devs.h>
++#include <mach/mt6575_typedefs.h>
++#include <mach/mt6575_clock_manager.h>
++#include <mach/mt6575_pm_ldo.h>
++//#include <mach/mt6575_pll.h>
++//#include <mach/mt6575_gpio.h>
++//#include <mach/mt6575_gpt_sw.h>
++#include <asm/tcm.h>
++// #include <mach/mt6575_gpt.h>
++#endif /* end of --- */
++
++#include "mt6575_sd.h"
++#include "dbg.h"
++
++/* +++ by chhung */
++#include "board.h"
++/* end of +++ */
++
++#if 0 /* --- by chhung */
++#define isb() __asm__ __volatile__ ("" : : : "memory")
++#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
++ : : "r" (0) : "memory")
++#define dmb() __asm__ __volatile__ ("" : : : "memory")
++#endif /* end of --- */
++
++#define DRV_NAME "mtk-sd"
++
++#define HOST_MAX_NUM (1) /* +/- by chhung */
++
++#if defined (CONFIG_SOC_MT7620)
++#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
++#elif defined (CONFIG_SOC_MT7621)
++#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
++#endif
++#define HOST_MIN_MCLK (260000)
++
++#define HOST_MAX_BLKSZ (2048)
++
++#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
++
++#define GPIO_PULL_DOWN (0)
++#define GPIO_PULL_UP (1)
++
++#if 0 /* --- by chhung */
++#define MSDC_CLKSRC_REG (0xf100000C)
++#define PDN_REG (0xF1000010)
++#endif /* end of --- */
++
++#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
++#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
++
++#define CMD_TIMEOUT (HZ/10) /* 100ms */
++#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
++
++#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
++
++#define MAX_GPD_NUM (1 + 1) /* one null gpd */
++#define MAX_BD_NUM (1024)
++#define MAX_BD_PER_GPD (MAX_BD_NUM)
++
++#define MAX_HW_SGMTS (MAX_BD_NUM)
++#define MAX_PHY_SGMTS (MAX_BD_NUM)
++#define MAX_SGMT_SZ (MAX_DMA_CNT)
++#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
++
++#ifdef MT6575_SD_DEBUG
++static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
++#endif
++
++//=================================
++#define PERI_MSDC0_PDN (15)
++//#define PERI_MSDC1_PDN (16)
++//#define PERI_MSDC2_PDN (17)
++//#define PERI_MSDC3_PDN (18)
++
++struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
++#if 0 /* --- by chhung */
++/* gate means clock power down */
++static int g_clk_gate = 0;
++#define msdc_gate_clock(id) \
++ do { \
++ g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
++ } while(0)
++/* not like power down register. 1 means clock on. */
++#define msdc_ungate_clock(id) \
++ do { \
++ g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
++ } while(0)
++
++// do we need sync object or not
++void msdc_clk_status(int * status)
++{
++ *status = g_clk_gate;
++}
++#endif /* end of --- */
++
++/* +++ by chhung */
++struct msdc_hw msdc0_hw = {
++ .clk_src = 0,
++ .cmd_edge = MSDC_SMPL_FALLING,
++ .data_edge = MSDC_SMPL_FALLING,
++ .clk_drv = 4,
++ .cmd_drv = 4,
++ .dat_drv = 4,
++ .data_pins = 4,
++ .data_offset = 0,
++ .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
++// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
++};
++
++static struct resource mtk_sd_resources[] = {
++ [0] = {
++ .start = RALINK_MSDC_BASE,
++ .end = RALINK_MSDC_BASE+0x3fff,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = IRQ_SDC, /*FIXME*/
++ .end = IRQ_SDC, /*FIXME*/
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device mtk_sd_device = {
++ .name = "mtk-sd",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(mtk_sd_resources),
++ .resource = mtk_sd_resources,
++};
++/* end of +++ */
++
++static int msdc_rsp[] = {
++ 0, /* RESP_NONE */
++ 1, /* RESP_R1 */
++ 2, /* RESP_R2 */
++ 3, /* RESP_R3 */
++ 4, /* RESP_R4 */
++ 1, /* RESP_R5 */
++ 1, /* RESP_R6 */
++ 1, /* RESP_R7 */
++ 7, /* RESP_R1b */
++};
++
++/* For Inhanced DMA */
++#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
++ do { \
++ ((gpd_t*)gpd)->extlen = extlen; \
++ ((gpd_t*)gpd)->cmd = cmd; \
++ ((gpd_t*)gpd)->arg = arg; \
++ ((gpd_t*)gpd)->blknum = blknum; \
++ }while(0)
++
++#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
++ do { \
++ BUG_ON(dlen > 0xFFFFUL); \
++ ((bd_t*)bd)->blkpad = blkpad; \
++ ((bd_t*)bd)->dwpad = dwpad; \
++ ((bd_t*)bd)->ptr = (void*)dptr; \
++ ((bd_t*)bd)->buflen = dlen; \
++ }while(0)
++
++#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
++#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
++#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
++#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
++#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
++#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
++
++
++#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
++#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
++
++#define msdc_retry(expr,retry,cnt) \
++ do { \
++ int backup = cnt; \
++ while (retry) { \
++ if (!(expr)) break; \
++ if (cnt-- == 0) { \
++ retry--; mdelay(1); cnt = backup; \
++ } \
++ } \
++ WARN_ON(retry == 0); \
++ } while(0)
++
++#if 0 /* --- by chhung */
++#define msdc_reset() \
++ do { \
++ int retry = 3, cnt = 1000; \
++ sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
++ dsb(); \
++ msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
++ } while(0)
++#else
++#define msdc_reset() \
++ do { \
++ int retry = 3, cnt = 1000; \
++ sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
++ msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
++ } while(0)
++#endif /* end of +/- */
++
++#define msdc_clr_int() \
++ do { \
++ volatile u32 val = sdr_read32(MSDC_INT); \
++ sdr_write32(MSDC_INT, val); \
++ } while(0)
++
++#define msdc_clr_fifo() \
++ do { \
++ int retry = 3, cnt = 1000; \
++ sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
++ msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
++ } while(0)
++
++#define msdc_irq_save(val) \
++ do { \
++ val = sdr_read32(MSDC_INTEN); \
++ sdr_clr_bits(MSDC_INTEN, val); \
++ } while(0)
++
++#define msdc_irq_restore(val) \
++ do { \
++ sdr_set_bits(MSDC_INTEN, val); \
++ } while(0)
++
++/* clock source for host: global */
++#if defined (CONFIG_SOC_MT7620)
++static u32 hclks[] = {48000000}; /* +/- by chhung */
++#elif defined (CONFIG_SOC_MT7621)
++static u32 hclks[] = {50000000}; /* +/- by chhung */
++#endif
++
++//============================================
++// the power for msdc host controller: global
++// always keep the VMC on.
++//============================================
++#define msdc_vcore_on(host) \
++ do { \
++ INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
++ (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
++ } while (0)
++#define msdc_vcore_off(host) \
++ do { \
++ INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
++ (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
++ } while (0)
++
++//====================================
++// the vdd output for card: global
++// always keep the VMCH on.
++//====================================
++#define msdc_vdd_on(host) \
++ do { \
++ (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
++ } while (0)
++#define msdc_vdd_off(host) \
++ do { \
++ (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
++ } while (0)
++
++#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
++#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
++
++#define sdc_send_cmd(cmd,arg) \
++ do { \
++ sdr_write32(SDC_ARG, (arg)); \
++ sdr_write32(SDC_CMD, (cmd)); \
++ } while(0)
++
++// can modify to read h/w register.
++//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
++#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
++
++/* +++ by chhung */
++#ifndef __ASSEMBLY__
++#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
++#else
++#define PHYSADDR(a) ((a) & 0x1fffffff)
++#endif
++/* end of +++ */
++static unsigned int msdc_do_command(struct msdc_host *host,
++ struct mmc_command *cmd,
++ int tune,
++ unsigned long timeout);
++
++static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
++
++#ifdef MT6575_SD_DEBUG
++static void msdc_dump_card_status(struct msdc_host *host, u32 status)
++{
++ static char *state[] = {
++ "Idle", /* 0 */
++ "Ready", /* 1 */
++ "Ident", /* 2 */
++ "Stby", /* 3 */
++ "Tran", /* 4 */
++ "Data", /* 5 */
++ "Rcv", /* 6 */
++ "Prg", /* 7 */
++ "Dis", /* 8 */
++ "Reserved", /* 9 */
++ "Reserved", /* 10 */
++ "Reserved", /* 11 */
++ "Reserved", /* 12 */
++ "Reserved", /* 13 */
++ "Reserved", /* 14 */
++ "I/O mode", /* 15 */
++ };
++ if (status & R1_OUT_OF_RANGE)
++ N_MSG(RSP, "[CARD_STATUS] Out of Range");
++ if (status & R1_ADDRESS_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] Address Error");
++ if (status & R1_BLOCK_LEN_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] Block Len Error");
++ if (status & R1_ERASE_SEQ_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
++ if (status & R1_ERASE_PARAM)
++ N_MSG(RSP, "[CARD_STATUS] Erase Param");
++ if (status & R1_WP_VIOLATION)
++ N_MSG(RSP, "[CARD_STATUS] WP Violation");
++ if (status & R1_CARD_IS_LOCKED)
++ N_MSG(RSP, "[CARD_STATUS] Card is Locked");
++ if (status & R1_LOCK_UNLOCK_FAILED)
++ N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
++ if (status & R1_COM_CRC_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
++ if (status & R1_ILLEGAL_COMMAND)
++ N_MSG(RSP, "[CARD_STATUS] Illegal Command");
++ if (status & R1_CARD_ECC_FAILED)
++ N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
++ if (status & R1_CC_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] CC Error");
++ if (status & R1_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] Error");
++ if (status & R1_UNDERRUN)
++ N_MSG(RSP, "[CARD_STATUS] Underrun");
++ if (status & R1_OVERRUN)
++ N_MSG(RSP, "[CARD_STATUS] Overrun");
++ if (status & R1_CID_CSD_OVERWRITE)
++ N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
++ if (status & R1_WP_ERASE_SKIP)
++ N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
++ if (status & R1_CARD_ECC_DISABLED)
++ N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
++ if (status & R1_ERASE_RESET)
++ N_MSG(RSP, "[CARD_STATUS] Erase Reset");
++ if (status & R1_READY_FOR_DATA)
++ N_MSG(RSP, "[CARD_STATUS] Ready for Data");
++ if (status & R1_SWITCH_ERROR)
++ N_MSG(RSP, "[CARD_STATUS] Switch error");
++ if (status & R1_APP_CMD)
++ N_MSG(RSP, "[CARD_STATUS] App Command");
++
++ N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
++}
++
++static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
++{
++ if (resp & (1 << 7))
++ N_MSG(RSP, "[OCR] Low Voltage Range");
++ if (resp & (1 << 15))
++ N_MSG(RSP, "[OCR] 2.7-2.8 volt");
++ if (resp & (1 << 16))
++ N_MSG(RSP, "[OCR] 2.8-2.9 volt");
++ if (resp & (1 << 17))
++ N_MSG(RSP, "[OCR] 2.9-3.0 volt");
++ if (resp & (1 << 18))
++ N_MSG(RSP, "[OCR] 3.0-3.1 volt");
++ if (resp & (1 << 19))
++ N_MSG(RSP, "[OCR] 3.1-3.2 volt");
++ if (resp & (1 << 20))
++ N_MSG(RSP, "[OCR] 3.2-3.3 volt");
++ if (resp & (1 << 21))
++ N_MSG(RSP, "[OCR] 3.3-3.4 volt");
++ if (resp & (1 << 22))
++ N_MSG(RSP, "[OCR] 3.4-3.5 volt");
++ if (resp & (1 << 23))
++ N_MSG(RSP, "[OCR] 3.5-3.6 volt");
++ if (resp & (1 << 24))
++ N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
++ if (resp & (1 << 30))
++ N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
++ if (resp & (1 << 31))
++ N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
++ else
++ N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
++}
++
++static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
++{
++ u32 status = (((resp >> 15) & 0x1) << 23) |
++ (((resp >> 14) & 0x1) << 22) |
++ (((resp >> 13) & 0x1) << 19) |
++ (resp & 0x1fff);
++
++ N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
++ msdc_dump_card_status(host, status);
++}
++
++static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
++{
++ u32 flags = (resp >> 8) & 0xFF;
++ char *state[] = {"DIS", "CMD", "TRN", "RFU"};
++
++ if (flags & (1 << 7))
++ N_MSG(RSP, "[IO] COM_CRC_ERR");
++ if (flags & (1 << 6))
++ N_MSG(RSP, "[IO] Illgal command");
++ if (flags & (1 << 3))
++ N_MSG(RSP, "[IO] Error");
++ if (flags & (1 << 2))
++ N_MSG(RSP, "[IO] RFU");
++ if (flags & (1 << 1))
++ N_MSG(RSP, "[IO] Function number error");
++ if (flags & (1 << 0))
++ N_MSG(RSP, "[IO] Out of range");
++
++ N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
++}
++#endif
++
++static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
++{
++ u32 base = host->base;
++ u32 timeout, clk_ns;
++
++ host->timeout_ns = ns;
++ host->timeout_clks = clks;
++
++ clk_ns = 1000000000UL / host->sclk;
++ timeout = ns / clk_ns + clks;
++ timeout = timeout >> 16; /* in 65536 sclk cycle unit */
++ timeout = timeout > 1 ? timeout - 1 : 0;
++ timeout = timeout > 255 ? 255 : timeout;
++
++ sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
++
++ N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
++ ns, clks, timeout + 1);
++}
++
++/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
++static void msdc_eirq_sdio(void *data)
++{
++ struct msdc_host *host = (struct msdc_host *)data;
++
++ N_MSG(INT, "SDIO EINT");
++
++ mmc_signal_sdio_irq(host->mmc);
++}
++
++/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
++static void msdc_eirq_cd(void *data)
++{
++ struct msdc_host *host = (struct msdc_host *)data;
++
++ N_MSG(INT, "CD EINT");
++
++#if 0
++ tasklet_hi_schedule(&host->card_tasklet);
++#else
++ schedule_delayed_work(&host->card_delaywork, HZ);
++#endif
++}
++
++#if 0
++static void msdc_tasklet_card(unsigned long arg)
++{
++ struct msdc_host *host = (struct msdc_host *)arg;
++#else
++static void msdc_tasklet_card(struct work_struct *work)
++{
++ struct msdc_host *host = (struct msdc_host *)container_of(work,
++ struct msdc_host, card_delaywork.work);
++#endif
++ struct msdc_hw *hw = host->hw;
++ u32 base = host->base;
++ u32 inserted;
++ u32 status = 0;
++ //u32 change = 0;
++
++ spin_lock(&host->lock);
++
++ if (hw->get_cd_status) { // NULL
++ inserted = hw->get_cd_status();
++ } else {
++ status = sdr_read32(MSDC_PS);
++ inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
++ }
++
++#if 0
++ change = host->card_inserted ^ inserted;
++ host->card_inserted = inserted;
++
++ if (change && !host->suspend) {
++ if (inserted) {
++ host->mmc->f_max = HOST_MAX_MCLK; // work around
++ }
++ mmc_detect_change(host->mmc, msecs_to_jiffies(20));
++ }
++#else /* Make sure: handle the last interrupt */
++ host->card_inserted = inserted;
++
++ if (!host->suspend) {
++ host->mmc->f_max = HOST_MAX_MCLK;
++ mmc_detect_change(host->mmc, msecs_to_jiffies(20));
++ }
++
++ IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
++#endif
++
++ spin_unlock(&host->lock);
++}
++
++#if 0 /* --- by chhung */
++/* For E2 only */
++static u8 clk_src_bit[4] = {
++ 0, 3, 5, 7
++};
++
++static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
++{
++ u32 val;
++ u32 base = host->base;
++
++ BUG_ON(clksrc > 3);
++ INIT_MSG("set clock source to <%d>", clksrc);
++
++ val = sdr_read32(MSDC_CLKSRC_REG);
++ if (sdr_read32(MSDC_ECO_VER) >= 4) {
++ val &= ~(0x3 << clk_src_bit[host->id]);
++ val |= clksrc << clk_src_bit[host->id];
++ } else {
++ val &= ~0x3; val |= clksrc;
++ }
++ sdr_write32(MSDC_CLKSRC_REG, val);
++
++ host->hclk = hclks[clksrc];
++ host->hw->clk_src = clksrc;
++}
++#endif /* end of --- */
++
++static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
++{
++ //struct msdc_hw *hw = host->hw;
++ u32 base = host->base;
++ u32 mode;
++ u32 flags;
++ u32 div;
++ u32 sclk;
++ u32 hclk = host->hclk;
++ //u8 clksrc = hw->clk_src;
++
++ if (!hz) { // set mmc system clock to 0 ?
++ ERR_MSG("set mclk to 0!!!");
++ msdc_reset();
++ return;
++ }
++
++ msdc_irq_save(flags);
++
++#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
++ mode = 0x0; /* use divisor */
++ if (hz >= (hclk >> 1)) {
++ div = 0; /* mean div = 1/2 */
++ sclk = hclk >> 1; /* sclk = clk / 2 */
++ } else {
++ div = (hclk + ((hz << 2) - 1)) / (hz << 2);
++ sclk = (hclk >> 2) / div;
++ }
++#else
++ if (ddr) {
++ mode = 0x2; /* ddr mode and use divisor */
++ if (hz >= (hclk >> 2)) {
++ div = 1; /* mean div = 1/4 */
++ sclk = hclk >> 2; /* sclk = clk / 4 */
++ } else {
++ div = (hclk + ((hz << 2) - 1)) / (hz << 2);
++ sclk = (hclk >> 2) / div;
++ }
++ } else if (hz >= hclk) { /* bug fix */
++ mode = 0x1; /* no divisor and divisor is ignored */
++ div = 0;
++ sclk = hclk;
++ } else {
++ mode = 0x0; /* use divisor */
++ if (hz >= (hclk >> 1)) {
++ div = 0; /* mean div = 1/2 */
++ sclk = hclk >> 1; /* sclk = clk / 2 */
++ } else {
++ div = (hclk + ((hz << 2) - 1)) / (hz << 2);
++ sclk = (hclk >> 2) / div;
++ }
++ }
++#endif
++ /* set clock mode and divisor */
++ sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
++ sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
++
++ /* wait clock stable */
++ while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
++
++ host->sclk = sclk;
++ host->mclk = hz;
++ msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
++
++ INIT_MSG("================");
++ INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
++ INIT_MSG("================");
++
++ msdc_irq_restore(flags);
++}
++
++/* Fix me. when need to abort */
++static void msdc_abort_data(struct msdc_host *host)
++{
++ u32 base = host->base;
++ struct mmc_command *stop = host->mrq->stop;
++
++ ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
++
++ msdc_reset();
++ msdc_clr_fifo();
++ msdc_clr_int();
++
++ // need to check FIFO count 0 ?
++
++ if (stop) { /* try to stop, but may not success */
++ ERR_MSG("stop when abort CMD<%d>", stop->opcode);
++ (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
++ }
++
++ //if (host->mclk >= 25000000) {
++ // msdc_set_mclk(host, 0, host->mclk >> 1);
++ //}
++}
++
++#if 0 /* --- by chhung */
++static void msdc_pin_config(struct msdc_host *host, int mode)
++{
++ struct msdc_hw *hw = host->hw;
++ u32 base = host->base;
++ int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
++
++ /* Config WP pin */
++ if (hw->flags & MSDC_WP_PIN_EN) {
++ if (hw->config_gpio_pin) /* NULL */
++ hw->config_gpio_pin(MSDC_WP_PIN, pull);
++ }
++
++ switch (mode) {
++ case MSDC_PIN_PULL_UP:
++ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
++ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
++ break;
++ case MSDC_PIN_PULL_DOWN:
++ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
++ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
++ break;
++ case MSDC_PIN_PULL_NONE:
++ default:
++ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
++ //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
++ break;
++ }
++
++ N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
++ mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
++}
++
++void msdc_pin_reset(struct msdc_host *host, int mode)
++{
++ struct msdc_hw *hw = (struct msdc_hw *)host->hw;
++ u32 base = host->base;
++ int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
++
++ /* Config reset pin */
++ if (hw->flags & MSDC_RST_PIN_EN) {
++ if (hw->config_gpio_pin) /* NULL */
++ hw->config_gpio_pin(MSDC_RST_PIN, pull);
++
++ if (mode == MSDC_PIN_PULL_UP) {
++ sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
++ } else {
++ sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
++ }
++ }
++}
++
++static void msdc_core_power(struct msdc_host *host, int on)
++{
++ N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
++ on ? "on" : "off", "core", host->core_power, on);
++
++ if (on && host->core_power == 0) {
++ msdc_vcore_on(host);
++ host->core_power = 1;
++ msleep(1);
++ } else if (!on && host->core_power == 1) {
++ msdc_vcore_off(host);
++ host->core_power = 0;
++ msleep(1);
++ }
++}
++
++static void msdc_host_power(struct msdc_host *host, int on)
++{
++ N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
++
++ if (on) {
++ //msdc_core_power(host, 1); // need do card detection.
++ msdc_pin_reset(host, MSDC_PIN_PULL_UP);
++ } else {
++ msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
++ //msdc_core_power(host, 0);
++ }
++}
++
++static void msdc_card_power(struct msdc_host *host, int on)
++{
++ N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
++
++ if (on) {
++ msdc_pin_config(host, MSDC_PIN_PULL_UP);
++ if (host->hw->ext_power_on) {
++ host->hw->ext_power_on();
++ } else {
++ //msdc_vdd_on(host); // need todo card detection.
++ }
++ msleep(1);
++ } else {
++ if (host->hw->ext_power_off) {
++ host->hw->ext_power_off();
++ } else {
++ //msdc_vdd_off(host);
++ }
++ msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
++ msleep(1);
++ }
++}
++
++static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
++{
++ N_MSG(CFG, "Set power mode(%d)", mode);
++
++ if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
++ msdc_host_power(host, 1);
++ msdc_card_power(host, 1);
++ } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
++ msdc_card_power(host, 0);
++ msdc_host_power(host, 0);
++ }
++ host->power_mode = mode;
++}
++#endif /* end of --- */
++
++#ifdef CONFIG_PM
++/*
++ register as callback function of WIFI(combo_sdio_register_pm) .
++ can called by msdc_drv_suspend/resume too.
++*/
++static void msdc_pm(pm_message_t state, void *data)
++{
++ struct msdc_host *host = (struct msdc_host *)data;
++ int evt = state.event;
++
++ if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
++ INIT_MSG("USR_%s: suspend<%d> power<%d>",
++ evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
++ host->suspend, host->power_mode);
++ }
++
++ if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
++ if (host->suspend) /* already suspend */ /* default 0*/
++ return;
++
++ /* for memory card. already power off by mmc */
++ if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
++ return;
++
++ host->suspend = 1;
++ host->pm_state = state; /* default PMSG_RESUME */
++
++ INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
++ if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
++ (void)mmc_suspend_host(host->mmc);
++ else {
++ // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
++ mmc_remove_host(host->mmc);
++ }
++ } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
++ if (!host->suspend){
++ //ERR_MSG("warning: already resume");
++ return;
++ }
++
++ /* No PM resume when USR suspend */
++ if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
++ ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
++ return;
++ }
++
++ host->suspend = 0;
++ host->pm_state = state;
++
++ INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
++ if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
++ (void)mmc_resume_host(host->mmc);
++ }
++ else {
++ // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
++ mmc_add_host(host->mmc);
++ }
++ }
++}
++#endif
++
++/*--------------------------------------------------------------------------*/
++/* mmc_host_ops members */
++/*--------------------------------------------------------------------------*/
++static unsigned int msdc_command_start(struct msdc_host *host,
++ struct mmc_command *cmd,
++ int tune, /* not used */
++ unsigned long timeout)
++{
++ u32 base = host->base;
++ u32 opcode = cmd->opcode;
++ u32 rawcmd;
++ u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
++ MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
++ MSDC_INT_ACMD19_DONE;
++
++ u32 resp;
++ unsigned long tmo;
++
++ /* Protocol layer does not provide response type, but our hardware needs
++ * to know exact type, not just size!
++ */
++ if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
++ resp = RESP_R3;
++ else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
++ resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
++ else if (opcode == MMC_FAST_IO)
++ resp = RESP_R4;
++ else if (opcode == MMC_GO_IRQ_STATE)
++ resp = RESP_R5;
++ else if (opcode == MMC_SELECT_CARD)
++ resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
++ else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
++ resp = RESP_R1; /* SDIO workaround. */
++ else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
++ resp = RESP_R1;
++ else {
++ switch (mmc_resp_type(cmd)) {
++ case MMC_RSP_R1:
++ resp = RESP_R1;
++ break;
++ case MMC_RSP_R1B:
++ resp = RESP_R1B;
++ break;
++ case MMC_RSP_R2:
++ resp = RESP_R2;
++ break;
++ case MMC_RSP_R3:
++ resp = RESP_R3;
++ break;
++ case MMC_RSP_NONE:
++ default:
++ resp = RESP_NONE;
++ break;
++ }
++ }
++
++ cmd->error = 0;
++ /* rawcmd :
++ * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
++ * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
++ */
++ rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
++
++ if (opcode == MMC_READ_MULTIPLE_BLOCK) {
++ rawcmd |= (2 << 11);
++ } else if (opcode == MMC_READ_SINGLE_BLOCK) {
++ rawcmd |= (1 << 11);
++ } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
++ rawcmd |= ((2 << 11) | (1 << 13));
++ } else if (opcode == MMC_WRITE_BLOCK) {
++ rawcmd |= ((1 << 11) | (1 << 13));
++ } else if (opcode == SD_IO_RW_EXTENDED) {
++ if (cmd->data->flags & MMC_DATA_WRITE)
++ rawcmd |= (1 << 13);
++ if (cmd->data->blocks > 1)
++ rawcmd |= (2 << 11);
++ else
++ rawcmd |= (1 << 11);
++ } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
++ rawcmd |= (1 << 14);
++ } else if ((opcode == SD_APP_SEND_SCR) ||
++ (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
++ (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
++ (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
++ (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
++ rawcmd |= (1 << 11);
++ } else if (opcode == MMC_STOP_TRANSMISSION) {
++ rawcmd |= (1 << 14);
++ rawcmd &= ~(0x0FFF << 16);
++ }
++
++ N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
++
++ tmo = jiffies + timeout;
++
++ if (opcode == MMC_SEND_STATUS) {
++ for (;;) {
++ if (!sdc_is_cmd_busy())
++ break;
++
++ if (time_after(jiffies, tmo)) {
++ ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
++ cmd->error = (unsigned int)-ETIMEDOUT;
++ msdc_reset();
++ goto end;
++ }
++ }
++ }else {
++ for (;;) {
++ if (!sdc_is_busy())
++ break;
++ if (time_after(jiffies, tmo)) {
++ ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
++ cmd->error = (unsigned int)-ETIMEDOUT;
++ msdc_reset();
++ goto end;
++ }
++ }
++ }
++
++ //BUG_ON(in_interrupt());
++ host->cmd = cmd;
++ host->cmd_rsp = resp;
++
++ init_completion(&host->cmd_done);
++
++ sdr_set_bits(MSDC_INTEN, wints);
++ sdc_send_cmd(rawcmd, cmd->arg);
++
++end:
++ return cmd->error;
++}
++
++static unsigned int msdc_command_resp(struct msdc_host *host,
++ struct mmc_command *cmd,
++ int tune,
++ unsigned long timeout)
++{
++ u32 base = host->base;
++ u32 opcode = cmd->opcode;
++ //u32 rawcmd;
++ u32 resp;
++ u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
++ MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
++ MSDC_INT_ACMD19_DONE;
++
++ resp = host->cmd_rsp;
++
++ BUG_ON(in_interrupt());
++ //init_completion(&host->cmd_done);
++ //sdr_set_bits(MSDC_INTEN, wints);
++
++ spin_unlock(&host->lock);
++ if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
++ ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
++ cmd->error = (unsigned int)-ETIMEDOUT;
++ msdc_reset();
++ }
++ spin_lock(&host->lock);
++
++ sdr_clr_bits(MSDC_INTEN, wints);
++ host->cmd = NULL;
++
++//end:
++#ifdef MT6575_SD_DEBUG
++ switch (resp) {
++ case RESP_NONE:
++ N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
++ break;
++ case RESP_R2:
++ N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
++ opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
++ cmd->resp[2], cmd->resp[3]);
++ break;
++ default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
++ N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
++ opcode, cmd->error, resp, cmd->resp[0]);
++ if (cmd->error == 0) {
++ switch (resp) {
++ case RESP_R1:
++ case RESP_R1B:
++ msdc_dump_card_status(host, cmd->resp[0]);
++ break;
++ case RESP_R3:
++ msdc_dump_ocr_reg(host, cmd->resp[0]);
++ break;
++ case RESP_R5:
++ msdc_dump_io_resp(host, cmd->resp[0]);
++ break;
++ case RESP_R6:
++ msdc_dump_rca_resp(host, cmd->resp[0]);
++ break;
++ }
++ }
++ break;
++ }
++#endif
++
++ /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
++
++ if (!tune) {
++ return cmd->error;
++ }
++
++ /* memory card CRC */
++ if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
++ if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
++ msdc_abort_data(host);
++ } else {
++ /* do basic: reset*/
++ msdc_reset();
++ msdc_clr_fifo();
++ msdc_clr_int();
++ }
++ cmd->error = msdc_tune_cmdrsp(host,cmd);
++ }
++
++ // check DAT0
++ /* if (resp == RESP_R1B) {
++ while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
++ } */
++ /* CMD12 Error Handle */
++
++ return cmd->error;
++}
++
++static unsigned int msdc_do_command(struct msdc_host *host,
++ struct mmc_command *cmd,
++ int tune,
++ unsigned long timeout)
++{
++ if (msdc_command_start(host, cmd, tune, timeout))
++ goto end;
++
++ if (msdc_command_resp(host, cmd, tune, timeout))
++ goto end;
++
++end:
++
++ N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
++ return cmd->error;
++}
++
++/* The abort condition when PIO read/write
++ tmo:
++*/
++static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
++{
++ int ret = 0;
++ u32 base = host->base;
++
++ if (atomic_read(&host->abort)) {
++ ret = 1;
++ }
++
++ if (time_after(jiffies, tmo)) {
++ data->error = (unsigned int)-ETIMEDOUT;
++ ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
++ ret = 1;
++ }
++
++ if(ret) {
++ msdc_reset();
++ msdc_clr_fifo();
++ msdc_clr_int();
++ ERR_MSG("msdc pio find abort");
++ }
++ return ret;
++}
++
++/*
++ Need to add a timeout, or WDT timeout, system reboot.
++*/
++// pio mode data read/write
++static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
++{
++ struct scatterlist *sg = data->sg;
++ u32 base = host->base;
++ u32 num = data->sg_len;
++ u32 *ptr;
++ u8 *u8ptr;
++ u32 left = 0;
++ u32 count, size = 0;
++ u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
++ unsigned long tmo = jiffies + DAT_TIMEOUT;
++
++ sdr_set_bits(MSDC_INTEN, wints);
++ while (num) {
++ left = sg_dma_len(sg);
++ ptr = sg_virt(sg);
++ while (left) {
++ if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
++ count = MSDC_FIFO_THD >> 2;
++ do {
++ *ptr++ = msdc_fifo_read32();
++ } while (--count);
++ left -= MSDC_FIFO_THD;
++ } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
++ while (left > 3) {
++ *ptr++ = msdc_fifo_read32();
++ left -= 4;
++ }
++
++ u8ptr = (u8 *)ptr;
++ while(left) {
++ * u8ptr++ = msdc_fifo_read8();
++ left--;
++ }
++ }
++
++ if (msdc_pio_abort(host, data, tmo)) {
++ goto end;
++ }
++ }
++ size += sg_dma_len(sg);
++ sg = sg_next(sg); num--;
++ }
++end:
++ data->bytes_xfered += size;
++ N_MSG(FIO, " PIO Read<%d>bytes", size);
++
++ sdr_clr_bits(MSDC_INTEN, wints);
++ if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
++ return data->error;
++}
++
++/* please make sure won't using PIO when size >= 512
++ which means, memory card block read/write won't using pio
++ then don't need to handle the CMD12 when data error.
++*/
++static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
++{
++ u32 base = host->base;
++ struct scatterlist *sg = data->sg;
++ u32 num = data->sg_len;
++ u32 *ptr;
++ u8 *u8ptr;
++ u32 left;
++ u32 count, size = 0;
++ u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
++ unsigned long tmo = jiffies + DAT_TIMEOUT;
++
++ sdr_set_bits(MSDC_INTEN, wints);
++ while (num) {
++ left = sg_dma_len(sg);
++ ptr = sg_virt(sg);
++
++ while (left) {
++ if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
++ count = MSDC_FIFO_SZ >> 2;
++ do {
++ msdc_fifo_write32(*ptr); ptr++;
++ } while (--count);
++ left -= MSDC_FIFO_SZ;
++ } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
++ while (left > 3) {
++ msdc_fifo_write32(*ptr); ptr++;
++ left -= 4;
++ }
++
++ u8ptr = (u8*)ptr;
++ while(left){
++ msdc_fifo_write8(*u8ptr); u8ptr++;
++ left--;
++ }
++ }
++
++ if (msdc_pio_abort(host, data, tmo)) {
++ goto end;
++ }
++ }
++ size += sg_dma_len(sg);
++ sg = sg_next(sg); num--;
++ }
++end:
++ data->bytes_xfered += size;
++ N_MSG(FIO, " PIO Write<%d>bytes", size);
++ if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
++
++ sdr_clr_bits(MSDC_INTEN, wints);
++ return data->error;
++}
++
++#if 0 /* --- by chhung */
++// DMA resume / start / stop
++static void msdc_dma_resume(struct msdc_host *host)
++{
++ u32 base = host->base;
++
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
++
++ N_MSG(DMA, "DMA resume");
++}
++#endif /* end of --- */
++
++static void msdc_dma_start(struct msdc_host *host)
++{
++ u32 base = host->base;
++ u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
++
++ sdr_set_bits(MSDC_INTEN, wints);
++ //dsb(); /* --- by chhung */
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
++
++ N_MSG(DMA, "DMA start");
++}
++
++static void msdc_dma_stop(struct msdc_host *host)
++{
++ u32 base = host->base;
++ //u32 retries=500;
++ u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
++
++ N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
++ //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
++
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
++ while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
++
++ //dsb(); /* --- by chhung */
++ sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
++
++ N_MSG(DMA, "DMA stop");
++}
++
++#if 0 /* --- by chhung */
++/* dump a gpd list */
++static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
++{
++ gpd_t *gpd = dma->gpd;
++ bd_t *bd = dma->bd;
++ bd_t *ptr;
++ int i = 0;
++ int p_to_v;
++
++ if (dma->mode != MSDC_MODE_DMA_DESC) {
++ return;
++ }
++
++ ERR_MSG("try to dump gpd and bd");
++
++ /* dump gpd */
++ ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
++ ERR_MSG("...hwo <%d>", gpd->hwo );
++ ERR_MSG("...bdp <%d>", gpd->bdp );
++ ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
++ //ERR_MSG("...intr <0x%.8x>", gpd->intr );
++ ERR_MSG("...next <0x%.8x>", (int)gpd->next );
++ ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
++ ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
++ //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
++ //ERR_MSG("...arg <0x%.8x>", gpd->arg );
++ //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
++ //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
++
++ /* dump bd */
++ ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
++ ptr = bd;
++ p_to_v = ((u32)bd - (u32)dma->bd_addr);
++ while (1) {
++ ERR_MSG(".bd[%d]", i); i++;
++ ERR_MSG("...eol <%d>", ptr->eol );
++ ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
++ //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
++ //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
++ ERR_MSG("...next <0x%.8x>", (int)ptr->next );
++ ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
++ ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
++
++ if (ptr->eol == 1) {
++ break;
++ }
++
++ /* find the next bd, virtual address of ptr->next */
++ /* don't need to enable when use malloc */
++ //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
++ //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
++ ptr++;
++ }
++
++ ERR_MSG("dump gpd and bd finished");
++}
++#endif /* end of --- */
++
++/* calc checksum */
++static u8 msdc_dma_calcs(u8 *buf, u32 len)
++{
++ u32 i, sum = 0;
++ for (i = 0; i < len; i++) {
++ sum += buf[i];
++ }
++ return 0xFF - (u8)sum;
++}
++
++/* gpd bd setup + dma registers */
++static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
++{
++ u32 base = host->base;
++ u32 sglen = dma->sglen;
++ //u32 i, j, num, bdlen, arg, xfersz;
++ u32 j, num, bdlen;
++ u8 blkpad, dwpad, chksum;
++ struct scatterlist *sg = dma->sg;
++ gpd_t *gpd;
++ bd_t *bd;
++
++ switch (dma->mode) {
++ case MSDC_MODE_DMA_BASIC:
++ BUG_ON(dma->xfersz > 65535);
++ BUG_ON(dma->sglen != 1);
++ sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
++//#if defined (CONFIG_RALINK_MT7620)
++ if (ralink_soc == MT762X_SOC_MT7620A)
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
++//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
++ else
++ sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
++//#endif
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
++ break;
++ case MSDC_MODE_DMA_DESC:
++ blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
++ dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
++ chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
++
++ /* calculate the required number of gpd */
++ num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
++ BUG_ON(num !=1 );
++
++ gpd = dma->gpd;
++ bd = dma->bd;
++ bdlen = sglen;
++
++ /* modify gpd*/
++ //gpd->intr = 0;
++ gpd->hwo = 1; /* hw will clear it */
++ gpd->bdp = 1;
++ gpd->chksum = 0; /* need to clear first. */
++ gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
++
++ /* modify bd*/
++ for (j = 0; j < bdlen; j++) {
++ msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
++ if(j == bdlen - 1) {
++ bd[j].eol = 1; /* the last bd */
++ } else {
++ bd[j].eol = 0;
++ }
++ bd[j].chksum = 0; /* checksume need to clear first */
++ bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
++ sg++;
++ }
++
++ dma->used_gpd += 2;
++ dma->used_bd += bdlen;
++
++ sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
++ sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
++
++ sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
++ break;
++
++ default:
++ break;
++ }
++
++ N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
++ N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
++ N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
++
++ return 0;
++}
++
++static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
++ struct scatterlist *sg, unsigned int sglen)
++{
++ BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
++
++ dma->sg = sg;
++ dma->flags = DMA_FLAG_EN_CHKSUM;
++ //dma->flags = DMA_FLAG_NONE; /* CHECKME */
++ dma->sglen = sglen;
++ dma->xfersz = host->xfer_size;
++ dma->burstsz = MSDC_BRUST_64B;
++
++ if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
++ dma->mode = MSDC_MODE_DMA_BASIC;
++ else
++ dma->mode = MSDC_MODE_DMA_DESC;
++
++ N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
++
++ msdc_dma_config(host, dma);
++
++ /*if (dma->mode == MSDC_MODE_DMA_DESC) {
++ //msdc_dma_dump(host, dma);
++ } */
++}
++
++/* set block number before send command */
++static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
++{
++ u32 base = host->base;
++
++ sdr_write32(SDC_BLK_NUM, blknum);
++}
++
++static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++ u32 base = host->base;
++ //u32 intsts = 0;
++ unsigned int left=0;
++ int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
++
++ #define SND_DAT 0
++ #define SND_CMD 1
++
++ BUG_ON(mmc == NULL);
++ BUG_ON(mrq == NULL);
++
++ host->error = 0;
++ atomic_set(&host->abort, 0);
++
++ cmd = mrq->cmd;
++ data = mrq->cmd->data;
++
++#if 0 /* --- by chhung */
++ //if(host->id ==1){
++ N_MSG(OPS, "enable clock!");
++ msdc_ungate_clock(host->id);
++ //}
++#endif /* end of --- */
++
++ if (!data) {
++ send_type=SND_CMD;
++ if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
++ goto done;
++ }
++ } else {
++ BUG_ON(data->blksz > HOST_MAX_BLKSZ);
++ send_type=SND_DAT;
++
++ data->error = 0;
++ read = data->flags & MMC_DATA_READ ? 1 : 0;
++ host->data = data;
++ host->xfer_size = data->blocks * data->blksz;
++ host->blksz = data->blksz;
++
++ /* deside the transfer mode */
++ if (drv_mode[host->id] == MODE_PIO) {
++ host->dma_xfer = dma = 0;
++ } else if (drv_mode[host->id] == MODE_DMA) {
++ host->dma_xfer = dma = 1;
++ } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
++ host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
++ }
++
++ if (read) {
++ if ((host->timeout_ns != data->timeout_ns) ||
++ (host->timeout_clks != data->timeout_clks)) {
++ msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
++ }
++ }
++
++ msdc_set_blknum(host, data->blocks);
++ //msdc_clr_fifo(); /* no need */
++
++ if (dma) {
++ msdc_dma_on(); /* enable DMA mode first!! */
++ init_completion(&host->xfer_done);
++
++ /* start the command first*/
++ if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
++ goto done;
++
++ dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
++ (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
++ msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
++
++ /* then wait command done */
++ if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
++ goto done;
++
++ /* for read, the data coming too fast, then CRC error
++ start DMA no business with CRC. */
++ //init_completion(&host->xfer_done);
++ msdc_dma_start(host);
++
++ spin_unlock(&host->lock);
++ if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
++ ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
++ ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
++ ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
++ ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
++ ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
++ data->error = (unsigned int)-ETIMEDOUT;
++
++ msdc_reset();
++ msdc_clr_fifo();
++ msdc_clr_int();
++ }
++ spin_lock(&host->lock);
++ msdc_dma_stop(host);
++ } else {
++ /* Firstly: send command */
++ if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
++ goto done;
++ }
++
++ /* Secondly: pio data phase */
++ if (read) {
++ if (msdc_pio_read(host, data)){
++ goto done;
++ }
++ } else {
++ if (msdc_pio_write(host, data)) {
++ goto done;
++ }
++ }
++
++ /* For write case: make sure contents in fifo flushed to device */
++ if (!read) {
++ while (1) {
++ left=msdc_txfifocnt();
++ if (left == 0) {
++ break;
++ }
++ if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
++ break;
++ /* Fix me: what about if data error, when stop ? how to? */
++ }
++ }
++ } else {
++ /* Fix me: read case: need to check CRC error */
++ }
++
++ /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
++ For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
++ */
++
++ /* try not to wait xfer_comp interrupt.
++ the next command will check SDC_BUSY.
++ SDC_BUSY means xfer_comp assert
++ */
++
++ } // PIO mode
++
++ /* Last: stop transfer */
++ if (data->stop){
++ if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
++ goto done;
++ }
++ }
++ }
++
++done:
++ if (data != NULL) {
++ host->data = NULL;
++ host->dma_xfer = 0;
++ if (dma != 0) {
++ msdc_dma_off();
++ host->dma.used_bd = 0;
++ host->dma.used_gpd = 0;
++ dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
++ }
++ host->blksz = 0;
++
++#if 0 // don't stop twice!
++ if(host->hw->flags & MSDC_REMOVABLE && data->error) {
++ msdc_abort_data(host);
++ /* reset in IRQ, stop command has issued. -> No need */
++ }
++#endif
++
++ N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
++ (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
++ }
++
++#if 0 /* --- by chhung */
++#if 1
++ //if(host->id==1) {
++ if(send_type==SND_CMD) {
++ if(cmd->opcode == MMC_SEND_STATUS) {
++ if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
++ N_MSG(OPS,"disable clock, CMD13 IDLE");
++ msdc_gate_clock(host->id);
++ }
++ } else {
++ N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
++ msdc_gate_clock(host->id);
++ }
++ } else {
++ if(read) {
++ N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
++ msdc_gate_clock(host->id);
++ }
++ }
++ //}
++#else
++ msdc_gate_clock(host->id);
++#endif
++#endif /* end of --- */
++
++ if (mrq->cmd->error) host->error = 0x001;
++ if (mrq->data && mrq->data->error) host->error |= 0x010;
++ if (mrq->stop && mrq->stop->error) host->error |= 0x100;
++
++ //if (host->error) ERR_MSG("host->error<%d>", host->error);
++
++ return host->error;
++}
++
++static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
++{
++ struct mmc_command cmd;
++ struct mmc_request mrq;
++ u32 err;
++
++ memset(&cmd, 0, sizeof(struct mmc_command));
++ cmd.opcode = MMC_APP_CMD;
++#if 0 /* bug: we meet mmc->card is null when ACMD6 */
++ cmd.arg = mmc->card->rca << 16;
++#else
++ cmd.arg = host->app_cmd_arg;
++#endif
++ cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
++
++ memset(&mrq, 0, sizeof(struct mmc_request));
++ mrq.cmd = &cmd; cmd.mrq = &mrq;
++ cmd.data = NULL;
++
++ err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
++ return err;
++}
++
++static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
++{
++ int result = -1;
++ u32 base = host->base;
++ u32 rsmpl, cur_rsmpl, orig_rsmpl;
++ u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
++ u32 skip = 1;
++
++ /* ==== don't support 3.0 now ====
++ 1: R_SMPL[1]
++ 2: PAD_CMD_RESP_RXDLY[26:22]
++ ==========================*/
++
++ // save the previous tune result
++ sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
++ sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
++
++ rrdly = 0;
++ do {
++ for (rsmpl = 0; rsmpl < 2; rsmpl++) {
++ /* Lv1: R_SMPL[1] */
++ cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
++ if (skip == 1) {
++ skip = 0;
++ continue;
++ }
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
++
++ if (host->app_cmd) {
++ result = msdc_app_cmd(host->mmc, host);
++ if (result) {
++ ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
++ host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
++ continue;
++ }
++ }
++ result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
++ ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
++ (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
++
++ if (result == 0) {
++ return 0;
++ }
++ if (result != (unsigned int)(-EIO)) {
++ ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
++ return result;
++ }
++
++ /* should be EIO */
++ if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
++ msdc_abort_data(host);
++ }
++ }
++
++ /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
++ cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
++ sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
++ }while (++rrdly < 32);
++
++ return result;
++}
++
++/* Support SD2.0 Only */
++static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ u32 base = host->base;
++ u32 ddr=0;
++ u32 dcrc=0;
++ u32 rxdly, cur_rxdly0, cur_rxdly1;
++ u32 dsmpl, cur_dsmpl, orig_dsmpl;
++ u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
++ u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
++ u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
++ u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
++ int result = -1;
++ u32 skip = 1;
++
++ sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
++
++ /* Tune Method 2. */
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
++
++ rxdly = 0;
++ do {
++ for (dsmpl = 0; dsmpl < 2; dsmpl++) {
++ cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
++ if (skip == 1) {
++ skip = 0;
++ continue;
++ }
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
++
++ if (host->app_cmd) {
++ result = msdc_app_cmd(host->mmc, host);
++ if (result) {
++ ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
++ continue;
++ }
++ }
++ result = msdc_do_request(mmc,mrq);
++
++ sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
++ if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
++ ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
++ (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
++ sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
++
++ /* Fix me: result is 0, but dcrc is still exist */
++ if (result == 0 && dcrc == 0) {
++ goto done;
++ } else {
++ /* there is a case: command timeout, and data phase not processed */
++ if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
++ ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
++ result, mrq->cmd->error, mrq->data->error);
++ goto done;
++ }
++ }
++ }
++
++ cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
++ cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
++
++ /* E1 ECO. YD: Reverse */
++ if (sdr_read32(MSDC_ECO_VER) >= 4) {
++ orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
++ orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
++ orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
++ orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
++ orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
++ orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
++ orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
++ orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
++ } else {
++ orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
++ orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
++ orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
++ orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
++ orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
++ orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
++ orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
++ orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
++ }
++
++ if (ddr) {
++ cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
++ cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
++ cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
++ cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
++ } else {
++ cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
++ cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
++ cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
++ cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
++ }
++ cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
++ cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
++ cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
++ cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
++
++ cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
++ cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
++
++ sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
++ sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
++
++ } while (++rxdly < 32);
++
++done:
++ return result;
++}
++
++static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ u32 base = host->base;
++
++ u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
++ u32 dsmpl, cur_dsmpl, orig_dsmpl;
++ u32 rxdly, cur_rxdly0;
++ u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
++ u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
++ int result = -1;
++ u32 skip = 1;
++
++ // MSDC_IOCON_DDR50CKD need to check. [Fix me]
++
++ sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
++ sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
++
++ /* Tune Method 2. just DAT0 */
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
++ cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
++
++ /* E1 ECO. YD: Reverse */
++ if (sdr_read32(MSDC_ECO_VER) >= 4) {
++ orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
++ orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
++ orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
++ orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
++ } else {
++ orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
++ orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
++ orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
++ orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
++ }
++
++ rxdly = 0;
++ do {
++ wrrdly = 0;
++ do {
++ for (dsmpl = 0; dsmpl < 2; dsmpl++) {
++ cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
++ if (skip == 1) {
++ skip = 0;
++ continue;
++ }
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
++
++ if (host->app_cmd) {
++ result = msdc_app_cmd(host->mmc, host);
++ if (result) {
++ ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
++ continue;
++ }
++ }
++ result = msdc_do_request(mmc,mrq);
++
++ ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
++ result == 0 ? "PASS" : "FAIL",
++ cur_dsmpl, cur_wrrdly, cur_rxdly0);
++
++ if (result == 0) {
++ goto done;
++ }
++ else {
++ /* there is a case: command timeout, and data phase not processed */
++ if (mrq->data->error != (unsigned int)(-EIO)) {
++ ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
++ result, mrq->cmd->error, mrq->data->error);
++ goto done;
++ }
++ }
++ }
++ cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
++ sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
++ } while (++wrrdly < 32);
++
++ cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
++ cur_dat1 = orig_dat1;
++ cur_dat2 = orig_dat2;
++ cur_dat3 = orig_dat3;
++
++ cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
++ sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
++ } while (++rxdly < 32);
++
++done:
++ return result;
++}
++
++static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
++{
++ struct mmc_command cmd;
++ struct mmc_request mrq;
++ u32 err;
++
++ memset(&cmd, 0, sizeof(struct mmc_command));
++ cmd.opcode = MMC_SEND_STATUS;
++ if (mmc->card) {
++ cmd.arg = mmc->card->rca << 16;
++ } else {
++ ERR_MSG("cmd13 mmc card is null");
++ cmd.arg = host->app_cmd_arg;
++ }
++ cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
++
++ memset(&mrq, 0, sizeof(struct mmc_request));
++ mrq.cmd = &cmd; cmd.mrq = &mrq;
++ cmd.data = NULL;
++
++ err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
++
++ if (status) {
++ *status = cmd.resp[0];
++ }
++
++ return err;
++}
++
++static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
++{
++ u32 err = 0;
++ u32 status = 0;
++
++ do {
++ err = msdc_get_card_status(mmc, host, &status);
++ if (err) return err;
++ /* need cmd12? */
++ ERR_MSG("cmd<13> resp<0x%x>", status);
++ } while (R1_CURRENT_STATE(status) == 7);
++
++ return err;
++}
++
++/* failed when msdc_do_request */
++static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ struct mmc_command *cmd;
++ struct mmc_data *data;
++ //u32 base = host->base;
++ int ret=0, read;
++
++ cmd = mrq->cmd;
++ data = mrq->cmd->data;
++
++ read = data->flags & MMC_DATA_READ ? 1 : 0;
++
++ if (read) {
++ if (data->error == (unsigned int)(-EIO)) {
++ ret = msdc_tune_bread(mmc,mrq);
++ }
++ } else {
++ ret = msdc_check_busy(mmc, host);
++ if (ret){
++ ERR_MSG("XXX cmd13 wait program done failed");
++ return ret;
++ }
++ /* CRC and TO */
++ /* Fix me: don't care card status? */
++ ret = msdc_tune_bwrite(mmc,mrq);
++ }
++
++ return ret;
++}
++
++/* ops.request */
++static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++
++ //=== for sdio profile ===
++#if 0 /* --- by chhung */
++ u32 old_H32, old_L32, new_H32, new_L32;
++ u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
++#endif /* end of --- */
++
++ if(host->mrq){
++ ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
++ BUG();
++ }
++
++ if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
++ ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
++ mrq->cmd->error = (unsigned int)-ENOMEDIUM;
++
++#if 1
++ mrq->done(mrq); // call done directly.
++#else
++ mrq->cmd->retries = 0; // please don't retry.
++ mmc_request_done(mmc, mrq);
++#endif
++
++ return;
++ }
++
++ /* start to process */
++ spin_lock(&host->lock);
++#if 0 /* --- by chhung */
++ if (sdio_pro_enable) { //=== for sdio profile ===
++ if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
++ GPT_GetCounter64(&old_L32, &old_H32);
++ }
++ }
++#endif /* end of --- */
++
++ host->mrq = mrq;
++
++ if (msdc_do_request(mmc,mrq)) {
++ if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error) {
++ msdc_tune_request(mmc,mrq);
++ }
++ }
++
++ /* ==== when request done, check if app_cmd ==== */
++ if (mrq->cmd->opcode == MMC_APP_CMD) {
++ host->app_cmd = 1;
++ host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
++ } else {
++ host->app_cmd = 0;
++ //host->app_cmd_arg = 0;
++ }
++
++ host->mrq = NULL;
++
++#if 0 /* --- by chhung */
++ //=== for sdio profile ===
++ if (sdio_pro_enable) {
++ if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
++ GPT_GetCounter64(&new_L32, &new_H32);
++ ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
++
++ opcode = mrq->cmd->opcode;
++ if (mrq->cmd->data) {
++ sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
++ bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
++ } else {
++ bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
++ }
++
++ if (!mrq->cmd->error) {
++ msdc_performance(opcode, sizes, bRx, ticks);
++ }
++ }
++ }
++#endif /* end of --- */
++ spin_unlock(&host->lock);
++
++ mmc_request_done(mmc, mrq);
++
++ return;
++}
++
++/* called by ops.set_ios */
++static void msdc_set_buswidth(struct msdc_host *host, u32 width)
++{
++ u32 base = host->base;
++ u32 val = sdr_read32(SDC_CFG);
++
++ val &= ~SDC_CFG_BUSWIDTH;
++
++ switch (width) {
++ default:
++ case MMC_BUS_WIDTH_1:
++ width = 1;
++ val |= (MSDC_BUS_1BITS << 16);
++ break;
++ case MMC_BUS_WIDTH_4:
++ val |= (MSDC_BUS_4BITS << 16);
++ break;
++ case MMC_BUS_WIDTH_8:
++ val |= (MSDC_BUS_8BITS << 16);
++ break;
++ }
++
++ sdr_write32(SDC_CFG, val);
++
++ N_MSG(CFG, "Bus Width = %d", width);
++}
++
++/* ops.set_ios */
++static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ struct msdc_hw *hw=host->hw;
++ u32 base = host->base;
++ u32 ddr = 0;
++
++#ifdef MT6575_SD_DEBUG
++ static char *vdd[] = {
++ "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
++ "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
++ "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
++ "3.40v", "3.50v", "3.60v"
++ };
++ static char *power_mode[] = {
++ "OFF", "UP", "ON"
++ };
++ static char *bus_mode[] = {
++ "UNKNOWN", "OPENDRAIN", "PUSHPULL"
++ };
++ static char *timing[] = {
++ "LEGACY", "MMC_HS", "SD_HS"
++ };
++
++ printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
++ ios->clock / 1000, bus_mode[ios->bus_mode],
++ (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
++ power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
++#endif
++
++ msdc_set_buswidth(host, ios->bus_width);
++
++ /* Power control ??? */
++ switch (ios->power_mode) {
++ case MMC_POWER_OFF:
++ case MMC_POWER_UP:
++ // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
++ break;
++ case MMC_POWER_ON:
++ host->power_mode = MMC_POWER_ON;
++ break;
++ default:
++ break;
++ }
++
++ /* Clock control */
++ if (host->mclk != ios->clock) {
++ if(ios->clock > 25000000) {
++ //if (!(host->hw->flags & MSDC_REMOVABLE)) {
++ INIT_MSG("SD data latch edge<%d>", hw->data_edge);
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
++ sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
++ //} /* for tuning debug */
++ } else { /* default value */
++ sdr_write32(MSDC_IOCON, 0x00000000);
++ // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
++ sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
++ sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
++ // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
++ sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
++ }
++ msdc_set_mclk(host, ddr, ios->clock);
++ }
++}
++
++/* ops.get_ro */
++static int msdc_ops_get_ro(struct mmc_host *mmc)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ u32 base = host->base;
++ unsigned long flags;
++ int ro = 0;
++
++ if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
++ spin_lock_irqsave(&host->lock, flags);
++ ro = (sdr_read32(MSDC_PS) >> 31);
++ spin_unlock_irqrestore(&host->lock, flags);
++ }
++ return ro;
++}
++
++/* ops.get_cd */
++static int msdc_ops_get_cd(struct mmc_host *mmc)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ u32 base = host->base;
++ unsigned long flags;
++ int present = 1;
++
++ /* for sdio, MSDC_REMOVABLE not set, always return 1 */
++ if (!(host->hw->flags & MSDC_REMOVABLE)) {
++ /* For sdio, read H/W always get<1>, but may timeout some times */
++#if 1
++ host->card_inserted = 1;
++ return 1;
++#else
++ host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
++ INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
++ return host->card_inserted;
++#endif
++ }
++
++ /* MSDC_CD_PIN_EN set for card */
++ if (host->hw->flags & MSDC_CD_PIN_EN) {
++ spin_lock_irqsave(&host->lock, flags);
++#if 0
++ present = host->card_inserted; /* why not read from H/W: Fix me*/
++#else
++ present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
++ host->card_inserted = present;
++#endif
++ spin_unlock_irqrestore(&host->lock, flags);
++ } else {
++ present = 0; /* TODO? Check DAT3 pins for card detection */
++ }
++
++ INIT_MSG("ops_get_cd return<%d>", present);
++ return present;
++}
++
++/* ops.enable_sdio_irq */
++static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++ struct msdc_host *host = mmc_priv(mmc);
++ struct msdc_hw *hw = host->hw;
++ u32 base = host->base;
++ u32 tmp;
++
++ if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
++ if (enable) {
++ hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
++ } else {
++ hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
++ }
++ } else {
++ ERR_MSG("XXX "); /* so never enter here */
++ tmp = sdr_read32(SDC_CFG);
++ /* FIXME. Need to interrupt gap detection */
++ if (enable) {
++ tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
++ } else {
++ tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
++ }
++ sdr_write32(SDC_CFG, tmp);
++ }
++}
++
++static struct mmc_host_ops mt_msdc_ops = {
++ .request = msdc_ops_request,
++ .set_ios = msdc_ops_set_ios,
++ .get_ro = msdc_ops_get_ro,
++ .get_cd = msdc_ops_get_cd,
++ .enable_sdio_irq = msdc_ops_enable_sdio_irq,
++};
++
++/*--------------------------------------------------------------------------*/
++/* interrupt handler */
++/*--------------------------------------------------------------------------*/
++static irqreturn_t msdc_irq(int irq, void *dev_id)
++{
++ struct msdc_host *host = (struct msdc_host *)dev_id;
++ struct mmc_data *data = host->data;
++ struct mmc_command *cmd = host->cmd;
++ u32 base = host->base;
++
++ u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
++ MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
++ MSDC_INT_ACMD19_DONE;
++ u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
++
++ u32 intsts = sdr_read32(MSDC_INT);
++ u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
++
++ sdr_write32(MSDC_INT, intsts); /* clear interrupts */
++ /* MSG will cause fatal error */
++
++ /* card change interrupt */
++ if (intsts & MSDC_INT_CDSC){
++#if defined CONFIG_MTK_MMC_CD_POLL
++ return IRQ_HANDLED;
++#endif
++ IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
++#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
++ tasklet_hi_schedule(&host->card_tasklet);
++#else
++ schedule_delayed_work(&host->card_delaywork, HZ);
++#endif
++ /* tuning when plug card ? */
++ }
++
++ /* sdio interrupt */
++ if (intsts & MSDC_INT_SDIOIRQ){
++ IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
++ //mmc_signal_sdio_irq(host->mmc);
++ }
++
++ /* transfer complete interrupt */
++ if (data != NULL) {
++ if (inten & MSDC_INT_XFER_COMPL) {
++ data->bytes_xfered = host->dma.xfersz;
++ complete(&host->xfer_done);
++ }
++
++ if (intsts & datsts) {
++ /* do basic reset, or stop command will sdc_busy */
++ msdc_reset();
++ msdc_clr_fifo();
++ msdc_clr_int();
++ atomic_set(&host->abort, 1); /* For PIO mode exit */
++
++ if (intsts & MSDC_INT_DATTMO){
++ IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
++ data->error = (unsigned int)-ETIMEDOUT;
++ }
++ else if (intsts & MSDC_INT_DATCRCERR){
++ IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
++ data->error = (unsigned int)-EIO;
++ }
++
++ //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
++ if (host->dma_xfer) {
++ complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
++ } /* PIO mode can't do complete, because not init */
++ }
++ }
++
++ /* command interrupts */
++ if ((cmd != NULL) && (intsts & cmdsts)) {
++ if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
++ (intsts & MSDC_INT_ACMD19_DONE)) {
++ u32 *rsp = &cmd->resp[0];
++
++ switch (host->cmd_rsp) {
++ case RESP_NONE:
++ break;
++ case RESP_R2:
++ *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
++ *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
++ break;
++ default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
++ if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
++ *rsp = sdr_read32(SDC_ACMD_RESP);
++ } else {
++ *rsp = sdr_read32(SDC_RESP0);
++ }
++ break;
++ }
++ } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
++ if(intsts & MSDC_INT_ACMDCRCERR){
++ IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
++ }
++ else {
++ IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
++ }
++ cmd->error = (unsigned int)-EIO;
++ } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
++ if(intsts & MSDC_INT_ACMDTMO){
++ IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
++ }
++ else {
++ IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
++ }
++ cmd->error = (unsigned int)-ETIMEDOUT;
++ msdc_reset();
++ msdc_clr_fifo();
++ msdc_clr_int();
++ }
++ complete(&host->cmd_done);
++ }
++
++ /* mmc irq interrupts */
++ if (intsts & MSDC_INT_MMCIRQ) {
++ printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
++ }
++
++#ifdef MT6575_SD_DEBUG
++ {
++ msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
++ N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
++ intsts,
++ int_reg->mmcirq,
++ int_reg->cdsc,
++ int_reg->atocmdrdy,
++ int_reg->atocmdtmo,
++ int_reg->atocmdcrc,
++ int_reg->atocmd19done);
++ N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
++ intsts,
++ int_reg->sdioirq,
++ int_reg->cmdrdy,
++ int_reg->cmdtmo,
++ int_reg->rspcrc,
++ int_reg->csta);
++ N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
++ intsts,
++ int_reg->xfercomp,
++ int_reg->dxferdone,
++ int_reg->dattmo,
++ int_reg->datcrc,
++ int_reg->dmaqempty);
++
++ }
++#endif
++
++ return IRQ_HANDLED;
++}
++
++/*--------------------------------------------------------------------------*/
++/* platform_driver members */
++/*--------------------------------------------------------------------------*/
++/* called by msdc_drv_probe/remove */
++static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
++{
++ struct msdc_hw *hw = host->hw;
++ u32 base = host->base;
++
++ /* for sdio, not set */
++ if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
++ /* Pull down card detection pin since it is not avaiable */
++ /*
++ if (hw->config_gpio_pin)
++ hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
++ */
++ sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
++ sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
++ sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
++ return;
++ }
++
++ N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
++
++ if (enable) {
++ if (hw->enable_cd_eirq) { /* not set, never enter */
++ hw->enable_cd_eirq();
++ } else {
++ /* card detection circuit relies on the core power so that the core power
++ * shouldn't be turned off. Here adds a reference count to keep
++ * the core power alive.
++ */
++ //msdc_vcore_on(host); //did in msdc_init_hw()
++
++ if (hw->config_gpio_pin) /* NULL */
++ hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
++
++ sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
++ sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
++ sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
++ sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
++ }
++ } else {
++ if (hw->disable_cd_eirq) {
++ hw->disable_cd_eirq();
++ } else {
++ if (hw->config_gpio_pin) /* NULL */
++ hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
++
++ sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
++ sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
++ sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
++
++ /* Here decreases a reference count to core power since card
++ * detection circuit is shutdown.
++ */
++ //msdc_vcore_off(host);
++ }
++ }
++}
++
++/* called by msdc_drv_probe */
++static void msdc_init_hw(struct msdc_host *host)
++{
++ u32 base = host->base;
++ struct msdc_hw *hw = host->hw;
++
++#ifdef MT6575_SD_DEBUG
++ msdc_reg[host->id] = (struct msdc_regs *)host->base;
++#endif
++
++ /* Power on */
++#if 0 /* --- by chhung */
++ msdc_vcore_on(host);
++ msdc_pin_reset(host, MSDC_PIN_PULL_UP);
++ msdc_select_clksrc(host, hw->clk_src);
++ enable_clock(PERI_MSDC0_PDN + host->id, "SD");
++ msdc_vdd_on(host);
++#endif /* end of --- */
++ /* Configure to MMC/SD mode */
++ sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
++
++ /* Reset */
++ msdc_reset();
++ msdc_clr_fifo();
++
++ /* Disable card detection */
++ sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
++
++ /* Disable and clear all interrupts */
++ sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
++ sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
++
++#if 1
++ /* reset tuning parameter */
++ sdr_write32(MSDC_PAD_CTL0, 0x00090000);
++ sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
++ sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
++ // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
++ sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
++ // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
++ sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
++ sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
++ sdr_write32(MSDC_IOCON, 0x00000000);
++#if 0 // use MT7620 default value: 0x403c004f
++ sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
++#endif
++
++ if (sdr_read32(MSDC_ECO_VER) >= 4) {
++ if (host->id == 1) {
++ sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
++ sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
++
++ /* internal clock: latch read data */
++ sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
++ }
++ }
++#endif
++
++ /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
++ pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
++ set when kernel driver wants to use SDIO bus interrupt */
++ /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
++ sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
++
++ /* disable detect SDIO device interupt function */
++ sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
++
++ /* eneable SMT for glitch filter */
++ sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
++ sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
++ sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
++
++#if 1
++ /* set clk, cmd, dat pad driving */
++ sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
++ sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
++#else
++ sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
++ sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
++ sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
++ sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
++#endif
++
++ /* set sampling edge */
++
++ /* write crc timeout detection */
++ sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
++
++ /* Configure to default data timeout */
++ sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
++
++ msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
++
++ N_MSG(FUC, "init hardware done!");
++}
++
++/* called by msdc_drv_remove */
++static void msdc_deinit_hw(struct msdc_host *host)
++{
++ u32 base = host->base;
++
++ /* Disable and clear all interrupts */
++ sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
++ sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
++
++ /* Disable card detection */
++ msdc_enable_cd_irq(host, 0);
++ // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
++}
++
++/* init gpd and bd list in msdc_drv_probe */
++static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
++{
++ gpd_t *gpd = dma->gpd;
++ bd_t *bd = dma->bd;
++ bd_t *ptr, *prev;
++
++ /* we just support one gpd */
++ int bdlen = MAX_BD_PER_GPD;
++
++ /* init the 2 gpd */
++ memset(gpd, 0, sizeof(gpd_t) * 2);
++ //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
++ //gpd->next = (dma->gpd_addr + 1); /* bug */
++ gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
++
++ //gpd->intr = 0;
++ gpd->bdp = 1; /* hwo, cs, bd pointer */
++ //gpd->ptr = (void*)virt_to_phys(bd);
++ gpd->ptr = (void *)dma->bd_addr; /* physical address */
++
++ memset(bd, 0, sizeof(bd_t) * bdlen);
++ ptr = bd + bdlen - 1;
++ //ptr->eol = 1; /* 0 or 1 [Fix me]*/
++ //ptr->next = 0;
++
++ while (ptr != bd) {
++ prev = ptr - 1;
++ prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
++ ptr = prev;
++ }
++}
++
++static int msdc_drv_probe(struct platform_device *pdev)
++{
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ __iomem void *base;
++ struct mmc_host *mmc;
++ struct resource *mem;
++ struct msdc_host *host;
++ struct msdc_hw *hw;
++ int ret, irq;
++
++ pdev->dev.platform_data = &msdc0_hw;
++
++ /* Allocate MMC host for this device */
++ mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
++ if (!mmc) return -ENOMEM;
++
++ hw = (struct msdc_hw*)pdev->dev.platform_data;
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ irq = platform_get_irq(pdev, 0);
++
++ //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
++
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ /* Set host parameters to mmc */
++ mmc->ops = &mt_msdc_ops;
++ mmc->f_min = HOST_MIN_MCLK;
++ mmc->f_max = HOST_MAX_MCLK;
++ mmc->ocr_avail = MSDC_OCR_AVAIL;
++
++ /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
++ For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
++ if (hw->flags & MSDC_HIGHSPEED) {
++ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
++ }
++ if (hw->data_pins == 4) { /* current data_pins are all 4*/
++ mmc->caps |= MMC_CAP_4_BIT_DATA;
++ } else if (hw->data_pins == 8) {
++ mmc->caps |= MMC_CAP_8_BIT_DATA;
++ }
++ if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
++ mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
++
++#if defined CONFIG_MTK_MMC_CD_POLL
++ mmc->caps |= MMC_CAP_NEEDS_POLL;
++#endif
++
++ /* MMC core transfer sizes tunable parameters */
++#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
++ mmc->max_segs = MAX_HW_SGMTS;
++#else
++ mmc->max_hw_segs = MAX_HW_SGMTS;
++ mmc->max_phys_segs = MAX_PHY_SGMTS;
++#endif
++ mmc->max_seg_size = MAX_SGMT_SZ;
++ mmc->max_blk_size = HOST_MAX_BLKSZ;
++ mmc->max_req_size = MAX_REQ_SZ;
++ mmc->max_blk_count = mmc->max_req_size;
++
++ host = mmc_priv(mmc);
++ host->hw = hw;
++ host->mmc = mmc;
++ host->id = pdev->id;
++ host->error = 0;
++ host->irq = irq;
++ host->base = (unsigned long) base;
++ host->mclk = 0; /* mclk: the request clock of mmc sub-system */
++ host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
++ host->sclk = 0; /* sclk: the really clock after divition */
++ host->pm_state = PMSG_RESUME;
++ host->suspend = 0;
++ host->core_clkon = 0;
++ host->card_clkon = 0;
++ host->core_power = 0;
++ host->power_mode = MMC_POWER_OFF;
++// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
++ host->timeout_ns = 0;
++ host->timeout_clks = DEFAULT_DTOC * 65536;
++
++ host->mrq = NULL;
++ //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
++
++ host->dma.used_gpd = 0;
++ host->dma.used_bd = 0;
++
++ /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
++ host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
++ host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
++ BUG_ON((!host->dma.gpd) || (!host->dma.bd));
++ msdc_init_gpd_bd(host, &host->dma);
++ /*for emmc*/
++ msdc_6575_host[pdev->id] = host;
++
++#if 0
++ tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
++#else
++ INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
++#endif
++ spin_lock_init(&host->lock);
++ msdc_init_hw(host);
++
++ ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
++ if (ret) goto release;
++ // mt65xx_irq_unmask(irq); /* --- by chhung */
++
++ if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
++ if (hw->request_cd_eirq) { /* not set for MT6575 */
++ hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
++ }
++ }
++
++ if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
++ hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
++
++ if (hw->register_pm) {/* yes for sdio */
++#ifdef CONFIG_PM
++ hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
++#endif
++ if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
++ ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
++ }
++ //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
++ }
++
++ platform_set_drvdata(pdev, mmc);
++
++ ret = mmc_add_host(mmc);
++ if (ret) goto free_irq;
++
++ /* Config card detection pin and enable interrupts */
++ if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
++ msdc_enable_cd_irq(host, 1);
++ } else {
++ msdc_enable_cd_irq(host, 0);
++ }
++
++ return 0;
++
++free_irq:
++ free_irq(irq, host);
++release:
++ platform_set_drvdata(pdev, NULL);
++ msdc_deinit_hw(host);
++
++#if 0
++ tasklet_kill(&host->card_tasklet);
++#else
++ cancel_delayed_work_sync(&host->card_delaywork);
++#endif
++
++ if (mem)
++ release_mem_region(mem->start, mem->end - mem->start + 1);
++
++ mmc_free_host(mmc);
++
++ return ret;
++}
++
++/* 4 device share one driver, using "drvdata" to show difference */
++static int msdc_drv_remove(struct platform_device *pdev)
++{
++ struct mmc_host *mmc;
++ struct msdc_host *host;
++ struct resource *mem;
++
++ mmc = platform_get_drvdata(pdev);
++ BUG_ON(!mmc);
++
++ host = mmc_priv(mmc);
++ BUG_ON(!host);
++
++ ERR_MSG("removed !!!");
++
++ platform_set_drvdata(pdev, NULL);
++ mmc_remove_host(host->mmc);
++ msdc_deinit_hw(host);
++
++#if 0
++ tasklet_kill(&host->card_tasklet);
++#else
++ cancel_delayed_work_sync(&host->card_delaywork);
++#endif
++ free_irq(host->irq, host);
++
++ dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
++ dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
++
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (mem)
++ release_mem_region(mem->start, mem->end - mem->start + 1);
++
++ mmc_free_host(host->mmc);
++
++ return 0;
++}
++
++/* Fix me: Power Flow */
++#ifdef CONFIG_PM
++static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ int ret = 0;
++ struct mmc_host *mmc = platform_get_drvdata(pdev);
++ struct msdc_host *host = mmc_priv(mmc);
++
++ if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
++ msdc_pm(state, (void*)host);
++ }
++
++ return ret;
++}
++
++static int msdc_drv_resume(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct mmc_host *mmc = platform_get_drvdata(pdev);
++ struct msdc_host *host = mmc_priv(mmc);
++ struct pm_message state;
++
++ state.event = PM_EVENT_RESUME;
++ if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
++ msdc_pm(state, (void*)host);
++ }
++
++ /* This mean WIFI not controller by PM */
++
++ return ret;
++}
++#endif
++
++static const struct of_device_id mt7620_sdhci_match[] = {
++ { .compatible = "ralink,mt7620-sdhci" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
++
++static struct platform_driver mt_msdc_driver = {
++ .probe = msdc_drv_probe,
++ .remove = msdc_drv_remove,
++#ifdef CONFIG_PM
++ .suspend = msdc_drv_suspend,
++ .resume = msdc_drv_resume,
++#endif
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = mt7620_sdhci_match,
++ },
++};
++
++/*--------------------------------------------------------------------------*/
++/* module init/exit */
++/*--------------------------------------------------------------------------*/
++static int __init mt_msdc_init(void)
++{
++ int ret;
++/* +++ by chhung */
++ u32 reg;
++
++#if defined (CONFIG_MTD_ANY_RALINK)
++ extern int ra_check_flash_type(void);
++ if(ra_check_flash_type() == 2) { /* NAND */
++ printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
++ return 0;
++ }
++#endif
++ printk("MTK MSDC device init.\n");
++ mtk_sd_device.dev.platform_data = &msdc0_hw;
++if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
++//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++ reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
++//#if defined (CONFIG_RALINK_MT7620)
++ if (ralink_soc == MT762X_SOC_MT7620A)
++ reg |= 0x1<<18;
++//#endif
++} else {
++//#elif defined (CONFIG_RALINK_MT7628)
++ /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
++ reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
++ reg |= 0x1e << 16;
++ sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
++
++ reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
++#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
++ reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
++ msdc0_hw.data_pins = 8,
++#endif
++//#endif
++}
++ sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
++ //platform_device_register(&mtk_sd_device);
++/* end of +++ */
++
++ ret = platform_driver_register(&mt_msdc_driver);
++ if (ret) {
++ printk(KERN_ERR DRV_NAME ": Can't register driver");
++ return ret;
++ }
++ printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
++
++#if defined (MT6575_SD_DEBUG)
++ msdc_debug_proc_init();
++#endif
++ return 0;
++}
++
++static void __exit mt_msdc_exit(void)
++{
++// platform_device_unregister(&mtk_sd_device);
++ platform_driver_unregister(&mt_msdc_driver);
++}
++
++module_init(mt_msdc_init);
++module_exit(mt_msdc_exit);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
++MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
++
++EXPORT_SYMBOL(msdc_6575_host);
--- /dev/null
+From cf93418a4bd5e69f069a65da92537bd4d6191223 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:29:51 +0100
+Subject: [PATCH 54/57] DMA: ralink: add rt2880 dma engine
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/dma/Kconfig | 6 +
+ drivers/dma/Makefile | 1 +
+ drivers/dma/dmaengine.c | 26 ++
+ drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/dmaengine.h | 1 +
+ 5 files changed, 611 insertions(+)
+ create mode 100644 drivers/dma/ralink-gdma.c
+
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -409,6 +409,12 @@ config NBPFAXI_DMA
+ help
+ Support for "Type-AXI" NBPF DMA IPs from Renesas
+
++config DMA_RALINK
++ tristate "RALINK DMA support"
++ depends on RALINK && SOC_MT7620
++ select DMA_ENGINE
++ select DMA_VIRTUAL_CHANNELS
++
+ config DMA_ENGINE
+ bool
+
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -49,3 +49,4 @@ obj-y += xilinx/
+ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o
+ obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o
+ obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
++obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
+--- /dev/null
++++ b/drivers/dma/ralink-gdma.c
+@@ -0,0 +1,577 @@
++/*
++ * Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
++ * GDMA4740 DMAC support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/of_dma.h>
++
++#include "virt-dma.h"
++
++#define GDMA_NR_CHANS 16
++
++#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
++#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
++
++#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
++#define GDMA_REG_CTRL0_TX_MASK 0xffff
++#define GDMA_REG_CTRL0_TX_SHIFT 16
++#define GDMA_REG_CTRL0_CURR_MASK 0xff
++#define GDMA_REG_CTRL0_CURR_SHIFT 8
++#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
++#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
++#define GDMA_REG_CTRL0_BURST_MASK 0x7
++#define GDMA_REG_CTRL0_BURST_SHIFT 3
++#define GDMA_REG_CTRL0_DONE_INT BIT(2)
++#define GDMA_REG_CTRL0_ENABLE BIT(1)
++#define GDMA_REG_CTRL0_HW_MODE 0
++
++#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
++#define GDMA_REG_CTRL1_SEG_MASK 0xf
++#define GDMA_REG_CTRL1_SEG_SHIFT 22
++#define GDMA_REG_CTRL1_REQ_MASK 0x3f
++#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
++#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
++#define GDMA_REG_CTRL1_CONTINOUS BIT(14)
++#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
++#define GDMA_REG_CTRL1_NEXT_SHIFT 3
++#define GDMA_REG_CTRL1_COHERENT BIT(2)
++#define GDMA_REG_CTRL1_FAIL BIT(1)
++#define GDMA_REG_CTRL1_MASK BIT(0)
++
++#define GDMA_REG_UNMASK_INT 0x200
++#define GDMA_REG_DONE_INT 0x204
++
++#define GDMA_REG_GCT 0x220
++#define GDMA_REG_GCT_CHAN_MASK 0x3
++#define GDMA_REG_GCT_CHAN_SHIFT 3
++#define GDMA_REG_GCT_VER_MASK 0x3
++#define GDMA_REG_GCT_VER_SHIFT 1
++#define GDMA_REG_GCT_ARBIT_RR BIT(0)
++
++enum gdma_dma_transfer_size {
++ GDMA_TRANSFER_SIZE_4BYTE = 0,
++ GDMA_TRANSFER_SIZE_8BYTE = 1,
++ GDMA_TRANSFER_SIZE_16BYTE = 2,
++ GDMA_TRANSFER_SIZE_32BYTE = 3,
++};
++
++struct gdma_dma_sg {
++ dma_addr_t addr;
++ unsigned int len;
++};
++
++struct gdma_dma_desc {
++ struct virt_dma_desc vdesc;
++
++ enum dma_transfer_direction direction;
++ bool cyclic;
++
++ unsigned int num_sgs;
++ struct gdma_dma_sg sg[];
++};
++
++struct gdma_dmaengine_chan {
++ struct virt_dma_chan vchan;
++ unsigned int id;
++
++ dma_addr_t fifo_addr;
++ unsigned int transfer_shift;
++
++ struct gdma_dma_desc *desc;
++ unsigned int next_sg;
++};
++
++struct gdma_dma_dev {
++ struct dma_device ddev;
++ void __iomem *base;
++ struct clk *clk;
++
++ struct gdma_dmaengine_chan chan[GDMA_NR_CHANS];
++};
++
++static struct gdma_dma_dev *gdma_dma_chan_get_dev(
++ struct gdma_dmaengine_chan *chan)
++{
++ return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
++ ddev);
++}
++
++static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
++{
++ return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
++}
++
++static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
++{
++ return container_of(vdesc, struct gdma_dma_desc, vdesc);
++}
++
++static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
++ unsigned int reg)
++{
++ return readl(dma_dev->base + reg);
++}
++
++static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
++ unsigned reg, uint32_t val)
++{
++ //printk("gdma --> %p = 0x%08X\n", dma_dev->base + reg, val);
++ writel(val, dma_dev->base + reg);
++}
++
++static inline void gdma_dma_write_mask(struct gdma_dma_dev *dma_dev,
++ unsigned int reg, uint32_t val, uint32_t mask)
++{
++ uint32_t tmp;
++
++ tmp = gdma_dma_read(dma_dev, reg);
++ tmp &= ~mask;
++ tmp |= val;
++ gdma_dma_write(dma_dev, reg, tmp);
++}
++
++static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
++{
++ return kzalloc(sizeof(struct gdma_dma_desc) +
++ sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
++}
++
++static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
++{
++ if (maxburst <= 7)
++ return GDMA_TRANSFER_SIZE_4BYTE;
++ else if (maxburst <= 15)
++ return GDMA_TRANSFER_SIZE_8BYTE;
++ else if (maxburst <= 31)
++ return GDMA_TRANSFER_SIZE_16BYTE;
++
++ return GDMA_TRANSFER_SIZE_32BYTE;
++}
++
++static int gdma_dma_slave_config(struct dma_chan *c,
++ const struct dma_slave_config *config)
++{
++ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
++ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
++ enum gdma_dma_transfer_size transfer_size;
++ uint32_t flags;
++ uint32_t ctrl0, ctrl1;
++
++ switch (config->direction) {
++ case DMA_MEM_TO_DEV:
++ ctrl1 = 32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
++ ctrl1 |= config->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT;
++ flags = GDMA_REG_CTRL0_DST_ADDR_FIXED;
++ transfer_size = gdma_dma_maxburst(config->dst_maxburst);
++ chan->fifo_addr = config->dst_addr;
++ break;
++
++ case DMA_DEV_TO_MEM:
++ ctrl1 = config->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
++ ctrl1 |= 32 << GDMA_REG_CTRL1_DST_REQ_SHIFT;
++ flags = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
++ transfer_size = gdma_dma_maxburst(config->src_maxburst);
++ chan->fifo_addr = config->src_addr;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ chan->transfer_shift = 1 + transfer_size;
++
++ ctrl0 = flags | GDMA_REG_CTRL0_HW_MODE;
++ ctrl0 |= GDMA_REG_CTRL0_DONE_INT;
++
++ ctrl1 &= ~(GDMA_REG_CTRL1_NEXT_MASK << GDMA_REG_CTRL1_NEXT_SHIFT);
++ ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
++ ctrl1 |= GDMA_REG_CTRL1_FAIL;
++ ctrl1 &= ~GDMA_REG_CTRL1_CONTINOUS;
++ gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
++ gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
++
++ return 0;
++}
++
++static int gdma_dma_terminate_all(struct dma_chan *c)
++{
++ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
++ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
++ unsigned long flags;
++ LIST_HEAD(head);
++
++ spin_lock_irqsave(&chan->vchan.lock, flags);
++ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
++ GDMA_REG_CTRL0_ENABLE);
++ chan->desc = NULL;
++ vchan_get_all_descriptors(&chan->vchan, &head);
++ spin_unlock_irqrestore(&chan->vchan.lock, flags);
++
++ vchan_dma_desc_free_list(&chan->vchan, &head);
++
++ return 0;
++}
++
++static int gdma_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
++ unsigned long arg)
++{
++ struct dma_slave_config *config = (struct dma_slave_config *)arg;
++
++ switch (cmd) {
++ case DMA_SLAVE_CONFIG:
++ return gdma_dma_slave_config(chan, config);
++ case DMA_TERMINATE_ALL:
++ return gdma_dma_terminate_all(chan);
++ default:
++ return -ENOSYS;
++ }
++}
++
++static int gdma_dma_start_transfer(struct gdma_dmaengine_chan *chan)
++{
++ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
++ dma_addr_t src_addr, dst_addr;
++ struct virt_dma_desc *vdesc;
++ struct gdma_dma_sg *sg;
++
++ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
++ GDMA_REG_CTRL0_ENABLE);
++
++ if (!chan->desc) {
++ vdesc = vchan_next_desc(&chan->vchan);
++ if (!vdesc)
++ return 0;
++ chan->desc = to_gdma_dma_desc(vdesc);
++ chan->next_sg = 0;
++ }
++
++ if (chan->next_sg == chan->desc->num_sgs)
++ chan->next_sg = 0;
++
++ sg = &chan->desc->sg[chan->next_sg];
++
++ if (chan->desc->direction == DMA_MEM_TO_DEV) {
++ src_addr = sg->addr;
++ dst_addr = chan->fifo_addr;
++ } else {
++ src_addr = chan->fifo_addr;
++ dst_addr = sg->addr;
++ }
++ gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
++ gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
++ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id),
++ (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | GDMA_REG_CTRL0_ENABLE,
++ GDMA_REG_CTRL0_TX_MASK << GDMA_REG_CTRL0_TX_SHIFT);
++ chan->next_sg++;
++ gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL1(chan->id), 0, GDMA_REG_CTRL1_MASK);
++
++ return 0;
++}
++
++static void gdma_dma_chan_irq(struct gdma_dmaengine_chan *chan)
++{
++ spin_lock(&chan->vchan.lock);
++ if (chan->desc) {
++ if (chan->desc && chan->desc->cyclic) {
++ vchan_cyclic_callback(&chan->desc->vdesc);
++ } else {
++ if (chan->next_sg == chan->desc->num_sgs) {
++ chan->desc = NULL;
++ vchan_cookie_complete(&chan->desc->vdesc);
++ }
++ }
++ }
++ gdma_dma_start_transfer(chan);
++ spin_unlock(&chan->vchan.lock);
++}
++
++static irqreturn_t gdma_dma_irq(int irq, void *devid)
++{
++ struct gdma_dma_dev *dma_dev = devid;
++ uint32_t unmask, done;
++ unsigned int i;
++
++ unmask = gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT);
++ gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, unmask);
++ done = gdma_dma_read(dma_dev, GDMA_REG_DONE_INT);
++
++ for (i = 0; i < GDMA_NR_CHANS; ++i)
++ if (done & BIT(i))
++ gdma_dma_chan_irq(&dma_dev->chan[i]);
++ gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, done);
++
++ return IRQ_HANDLED;
++}
++
++static void gdma_dma_issue_pending(struct dma_chan *c)
++{
++ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
++ unsigned long flags;
++
++ spin_lock_irqsave(&chan->vchan.lock, flags);
++ if (vchan_issue_pending(&chan->vchan) && !chan->desc)
++ gdma_dma_start_transfer(chan);
++ spin_unlock_irqrestore(&chan->vchan.lock, flags);
++}
++
++static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
++ struct dma_chan *c, struct scatterlist *sgl,
++ unsigned int sg_len, enum dma_transfer_direction direction,
++ unsigned long flags, void *context)
++{
++ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
++ struct gdma_dma_desc *desc;
++ struct scatterlist *sg;
++ unsigned int i;
++
++ desc = gdma_dma_alloc_desc(sg_len);
++ if (!desc)
++ return NULL;
++
++ for_each_sg(sgl, sg, sg_len, i) {
++ desc->sg[i].addr = sg_dma_address(sg);
++ desc->sg[i].len = sg_dma_len(sg);
++ }
++
++ desc->num_sgs = sg_len;
++ desc->direction = direction;
++ desc->cyclic = false;
++
++ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
++}
++
++static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
++ struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
++ size_t period_len, enum dma_transfer_direction direction,
++ unsigned long flags, void *context)
++{
++ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
++ struct gdma_dma_desc *desc;
++ unsigned int num_periods, i;
++
++ if (buf_len % period_len)
++ return NULL;
++
++ num_periods = buf_len / period_len;
++
++ desc = gdma_dma_alloc_desc(num_periods);
++ if (!desc)
++ return NULL;
++
++ for (i = 0; i < num_periods; i++) {
++ desc->sg[i].addr = buf_addr;
++ desc->sg[i].len = period_len;
++ buf_addr += period_len;
++ }
++
++ desc->num_sgs = num_periods;
++ desc->direction = direction;
++ desc->cyclic = true;
++
++ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
++}
++
++static size_t gdma_dma_desc_residue(struct gdma_dmaengine_chan *chan,
++ struct gdma_dma_desc *desc, unsigned int next_sg)
++{
++ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
++ unsigned int residue, count;
++ unsigned int i;
++
++ residue = 0;
++
++ for (i = next_sg; i < desc->num_sgs; i++)
++ residue += desc->sg[i].len;
++
++ if (next_sg != 0) {
++ count = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
++ count >>= GDMA_REG_CTRL0_CURR_SHIFT;
++ count &= GDMA_REG_CTRL0_CURR_MASK;
++ residue += count << chan->transfer_shift;
++ }
++
++ return residue;
++}
++
++static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
++ dma_cookie_t cookie, struct dma_tx_state *state)
++{
++ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
++ struct virt_dma_desc *vdesc;
++ enum dma_status status;
++ unsigned long flags;
++
++ status = dma_cookie_status(c, cookie, state);
++ if (status == DMA_SUCCESS || !state)
++ return status;
++
++ spin_lock_irqsave(&chan->vchan.lock, flags);
++ vdesc = vchan_find_desc(&chan->vchan, cookie);
++ if (cookie == chan->desc->vdesc.tx.cookie) {
++ state->residue = gdma_dma_desc_residue(chan, chan->desc,
++ chan->next_sg);
++ } else if (vdesc) {
++ state->residue = gdma_dma_desc_residue(chan,
++ to_gdma_dma_desc(vdesc), 0);
++ } else {
++ state->residue = 0;
++ }
++ spin_unlock_irqrestore(&chan->vchan.lock, flags);
++
++ return status;
++}
++
++static int gdma_dma_alloc_chan_resources(struct dma_chan *c)
++{
++ return 0;
++}
++
++static void gdma_dma_free_chan_resources(struct dma_chan *c)
++{
++ vchan_free_chan_resources(to_virt_chan(c));
++}
++
++static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
++{
++ kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
++}
++
++static struct dma_chan *
++of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
++ struct of_dma *ofdma)
++{
++ struct gdma_dma_dev *dma_dev = ofdma->of_dma_data;
++ unsigned int request = dma_spec->args[0];
++
++ if (request >= GDMA_NR_CHANS)
++ return NULL;
++
++ return dma_get_slave_channel(&(dma_dev->chan[request].vchan.chan));
++}
++
++static int gdma_dma_probe(struct platform_device *pdev)
++{
++ struct gdma_dmaengine_chan *chan;
++ struct gdma_dma_dev *dma_dev;
++ struct dma_device *dd;
++ unsigned int i;
++ struct resource *res;
++ uint32_t gct;
++ int ret;
++ int irq;
++
++
++ dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
++ if (!dma_dev)
++ return -EINVAL;
++
++ dd = &dma_dev->ddev;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ dma_dev->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(dma_dev->base))
++ return PTR_ERR(dma_dev->base);
++
++ dma_cap_set(DMA_SLAVE, dd->cap_mask);
++ dma_cap_set(DMA_CYCLIC, dd->cap_mask);
++ dd->device_alloc_chan_resources = gdma_dma_alloc_chan_resources;
++ dd->device_free_chan_resources = gdma_dma_free_chan_resources;
++ dd->device_tx_status = gdma_dma_tx_status;
++ dd->device_issue_pending = gdma_dma_issue_pending;
++ dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
++ dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
++ dd->device_control = gdma_dma_control;
++ dd->dev = &pdev->dev;
++ dd->chancnt = GDMA_NR_CHANS;
++ INIT_LIST_HEAD(&dd->channels);
++
++ for (i = 0; i < dd->chancnt; i++) {
++ chan = &dma_dev->chan[i];
++ chan->id = i;
++ chan->vchan.desc_free = gdma_dma_desc_free;
++ vchan_init(&chan->vchan, dd);
++ }
++
++ ret = dma_async_device_register(dd);
++ if (ret)
++ return ret;
++
++ ret = of_dma_controller_register(pdev->dev.of_node,
++ of_dma_xlate_by_chan_id, dma_dev);
++ if (ret)
++ goto err_unregister;
++
++ irq = platform_get_irq(pdev, 0);
++ ret = request_irq(irq, gdma_dma_irq, 0, dev_name(&pdev->dev), dma_dev);
++ if (ret)
++ goto err_unregister;
++
++ gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, 0);
++ gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, BIT(dd->chancnt) - 1);
++
++ gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
++ dev_info(&pdev->dev, "revision: %d, channels: %d\n",
++ (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
++ 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & GDMA_REG_GCT_CHAN_MASK));
++ platform_set_drvdata(pdev, dma_dev);
++
++ gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
++
++ return 0;
++
++err_unregister:
++ dma_async_device_unregister(dd);
++ return ret;
++}
++
++static int gdma_dma_remove(struct platform_device *pdev)
++{
++ struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
++ int irq = platform_get_irq(pdev, 0);
++
++ free_irq(irq, dma_dev);
++ of_dma_controller_free(pdev->dev.of_node);
++ dma_async_device_unregister(&dma_dev->ddev);
++
++ return 0;
++}
++
++static const struct of_device_id gdma_of_match_table[] = {
++ { .compatible = "ralink,rt2880-gdma" },
++ { },
++};
++
++static struct platform_driver gdma_dma_driver = {
++ .probe = gdma_dma_probe,
++ .remove = gdma_dma_remove,
++ .driver = {
++ .name = "gdma-rt2880",
++ .owner = THIS_MODULE,
++ .of_match_table = gdma_of_match_table,
++ },
++};
++module_platform_driver(gdma_dma_driver);
++
++MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
++MODULE_DESCRIPTION("GDMA4740 DMA driver");
++MODULE_LICENSE("GPLv2");
+--- a/include/linux/dmaengine.h
++++ b/include/linux/dmaengine.h
+@@ -1058,6 +1058,7 @@ struct dma_chan *dma_request_slave_chann
+ const char *name);
+ struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
+ void dma_release_channel(struct dma_chan *chan);
++struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
+ #else
+ static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
+ {
--- /dev/null
+From 241188942603dc73f62cf2553c53cae2235c9957 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:31:47 +0100
+Subject: [PATCH 55/57] asoc: add mt7620 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c | 2 +
+ sound/soc/Kconfig | 1 +
+ sound/soc/Makefile | 1 +
+ sound/soc/ralink/Kconfig | 15 ++
+ sound/soc/ralink/Makefile | 11 +
+ sound/soc/ralink/mt7620-i2s.c | 466 ++++++++++++++++++++++++++++++++++++++
+ sound/soc/ralink/mt7620-wm8960.c | 125 ++++++++++
+ sound/soc/soc-io.c | 10 -
+ 8 files changed, 621 insertions(+), 10 deletions(-)
+ create mode 100644 sound/soc/ralink/Kconfig
+ create mode 100644 sound/soc/ralink/Makefile
+ create mode 100644 sound/soc/ralink/mt7620-i2s.c
+ create mode 100644 sound/soc/ralink/mt7620-wm8960.c
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -15,6 +15,7 @@
+ #include <linux/of_fdt.h>
+ #include <linux/kernel.h>
+ #include <linux/bootmem.h>
++#include <linux/module.h>
+ #include <linux/of_platform.h>
+ #include <linux/of_address.h>
+
+@@ -26,6 +27,7 @@
+ #include "common.h"
+
+ __iomem void *rt_sysc_membase;
++EXPORT_SYMBOL(rt_sysc_membase);
+ __iomem void *rt_memc_membase;
+
+ __iomem void *plat_of_remap_node(const char *node)
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -48,6 +48,7 @@ source "sound/soc/intel/Kconfig"
+ source "sound/soc/mxs/Kconfig"
+ source "sound/soc/pxa/Kconfig"
+ source "sound/soc/rockchip/Kconfig"
++source "sound/soc/ralink/Kconfig"
+ source "sound/soc/samsung/Kconfig"
+ source "sound/soc/sh/Kconfig"
+ source "sound/soc/sirf/Kconfig"
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -25,6 +25,7 @@ obj-$(CONFIG_SND_SOC) += omap/
+ obj-$(CONFIG_SND_SOC) += kirkwood/
+ obj-$(CONFIG_SND_SOC) += pxa/
+ obj-$(CONFIG_SND_SOC) += rockchip/
++obj-$(CONFIG_SND_SOC) += ralink/
+ obj-$(CONFIG_SND_SOC) += samsung/
+ obj-$(CONFIG_SND_SOC) += sh/
+ obj-$(CONFIG_SND_SOC) += sirf/
+--- /dev/null
++++ b/sound/soc/ralink/Kconfig
+@@ -0,0 +1,15 @@
++config SND_MT7620_SOC_I2S
++ depends on SOC_MT7620 && SND_SOC
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++ tristate "SoC Audio (I2S protocol) for Ralink MT7620 SoC"
++ help
++ Say Y if you want to use I2S protocol and I2S codec on Ingenic MT7620
++ based boards.
++
++config SND_MT7620_SOC_WM8960
++ tristate "SoC Audio support for Ralink WM8960"
++ select SND_MT7620_SOC_I2S
++ select SND_SOC_WM8960
++ help
++ Say Y if you want to add support for ASoC audio on the Qi LB60 board
++ a.k.a Qi Ben NanoNote.
+--- /dev/null
++++ b/sound/soc/ralink/Makefile
+@@ -0,0 +1,11 @@
++#
++# Jz4740 Platform Support
++#
++snd-soc-mt7620-i2s-objs := mt7620-i2s.o
++
++obj-$(CONFIG_SND_MT7620_SOC_I2S) += snd-soc-mt7620-i2s.o
++
++# Jz4740 Machine Support
++snd-soc-mt7620-wm8960-objs := mt7620-wm8960.o
++
++obj-$(CONFIG_SND_MT7620_SOC_WM8960) += snd-soc-mt7620-wm8960.o
+--- /dev/null
++++ b/sound/soc/ralink/mt7620-i2s.c
+@@ -0,0 +1,436 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <linux/delay.h>
++
++#include <linux/dma-mapping.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/dmaengine_pcm.h>
++
++#include <ralink_regs.h>
++
++#define I2S_REG_CFG0 0x00
++#define I2S_REG_CFG0_EN BIT(31)
++#define I2S_REG_CFG0_DMA_EN BIT(30)
++#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
++#define I2S_REG_CFG0_TX_EN BIT(24)
++#define I2S_REG_CFG0_RX_EN BIT(20)
++#define I2S_REG_CFG0_SLAVE BIT(16)
++#define I2S_REG_CFG0_RX_THRES 12
++#define I2S_REG_CFG0_TX_THRES 4
++#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
++ (4 << I2S_REG_CFG0_TX_THRES)
++
++#define I2S_REG_INT_STATUS 0x04
++#define I2S_REG_INT_EN 0x08
++#define I2S_REG_FF_STATUS 0x0c
++#define I2S_REG_WREG 0x10
++#define I2S_REG_RREG 0x14
++#define I2S_REG_CFG1 0x18
++
++#define I2S_REG_DIVCMP 0x20
++#define I2S_REG_DIVINT 0x24
++#define I2S_REG_CLK_EN BIT(31)
++
++struct mt7620_i2s {
++ struct resource *mem;
++ void __iomem *base;
++ dma_addr_t phys_base;
++
++ struct snd_dmaengine_dai_dma_data playback_dma_data;
++ struct snd_dmaengine_dai_dma_data capture_dma_data;
++};
++
++static inline uint32_t mt7620_i2s_read(const struct mt7620_i2s *i2s,
++ unsigned int reg)
++{
++ return readl(i2s->base + reg);
++}
++
++static inline void mt7620_i2s_write(const struct mt7620_i2s *i2s,
++ unsigned int reg, uint32_t value)
++{
++ //printk("i2s --> %p = 0x%08X\n", i2s->base + reg, value);
++ writel(value, i2s->base + reg);
++}
++
++static int mt7620_i2s_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ uint32_t cfg;
++
++ if (dai->active)
++ return 0;
++
++ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
++ cfg |= I2S_REG_CFG0_EN;
++ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
++
++ return 0;
++}
++
++static void mt7620_i2s_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ uint32_t cfg;
++
++ if (dai->active)
++ return;
++
++ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
++ cfg &= ~I2S_REG_CFG0_EN;
++ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
++}
++
++static int mt7620_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *dai)
++{
++ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++ uint32_t cfg;
++ uint32_t mask;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ mask = I2S_REG_CFG0_TX_EN;
++ else
++ mask = I2S_REG_CFG0_RX_EN;
++
++ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ cfg |= mask;
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ cfg &= ~mask;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (cfg & (I2S_REG_CFG0_TX_EN | I2S_REG_CFG0_RX_EN))
++ cfg |= I2S_REG_CFG0_DMA_EN;
++ else
++ cfg &= ~I2S_REG_CFG0_DMA_EN;
++
++ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
++
++ return 0;
++}
++
++static int mt7620_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ uint32_t cfg;
++
++ cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ cfg |= I2S_REG_CFG0_SLAVE;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ cfg &= ~I2S_REG_CFG0_SLAVE;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFS:
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ case SND_SOC_DAIFMT_MSB:
++ cfg &= ~I2S_REG_CFG0_BYTE_SWAP;
++ break;
++ case SND_SOC_DAIFMT_LSB:
++ cfg |= I2S_REG_CFG0_BYTE_SWAP;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
++
++ return 0;
++}
++
++static int mt7620_i2s_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++
++ return 0;
++}
++
++unsigned long i2sMaster_inclk_int[11] = {
++ 78, 56, 52, 39, 28, 26, 19, 14, 13, 9, 6};
++unsigned long i2sMaster_inclk_comp[11] = {
++ 64, 352, 42, 32, 176, 21, 272, 88, 10, 455, 261};
++
++
++static int mt7620_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++ unsigned int freq, int dir)
++{
++ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++ printk("Internal REFCLK with fractional division\n");
++
++ mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
++ mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
++ i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
++
++/* struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ struct clk *parent;
++ int ret = 0;
++
++ switch (clk_id) {
++ case JZ4740_I2S_CLKSRC_EXT:
++ parent = clk_get(NULL, "ext");
++ clk_set_parent(i2s->clk_i2s, parent);
++ break;
++ case JZ4740_I2S_CLKSRC_PLL:
++ parent = clk_get(NULL, "pll half");
++ clk_set_parent(i2s->clk_i2s, parent);
++ ret = clk_set_rate(i2s->clk_i2s, freq);
++ break;
++ default:
++ return -EINVAL;
++ }
++ clk_put(parent);
++
++ return ret;*/
++ return 0;
++}
++
++static void mt7620_i2c_init_pcm_config(struct mt7620_i2s *i2s)
++{
++ struct snd_dmaengine_dai_dma_data *dma_data;
++
++ /* Playback */
++ dma_data = &i2s->playback_dma_data;
++ dma_data->maxburst = 16;
++ dma_data->slave_id = 2; //JZ4740_DMA_TYPE_AIC_TRANSMIT;
++ dma_data->addr = i2s->phys_base + I2S_REG_WREG;
++
++ /* Capture */
++ dma_data = &i2s->capture_dma_data;
++ dma_data->maxburst = 16;
++ dma_data->slave_id = 3; //JZ4740_DMA_TYPE_AIC_RECEIVE;
++ dma_data->addr = i2s->phys_base + I2S_REG_RREG;
++}
++
++static int mt7620_i2s_dai_probe(struct snd_soc_dai *dai)
++{
++ struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ uint32_t data;
++
++ mt7620_i2c_init_pcm_config(i2s);
++ dai->playback_dma_data = &i2s->playback_dma_data;
++ dai->capture_dma_data = &i2s->capture_dma_data;
++
++ /* set share pins to i2s/gpio mode and i2c mode */
++ data = rt_sysc_r32(0x60);
++ data &= 0xFFFFFFE2;
++ data |= 0x00000018;
++ rt_sysc_w32(data, 0x60);
++
++ printk("Internal REFCLK with fractional division\n");
++
++ mt7620_i2s_write(i2s, I2S_REG_CFG0, I2S_REG_CFG0_DFT_THRES);
++ mt7620_i2s_write(i2s, I2S_REG_CFG1, 0);
++ mt7620_i2s_write(i2s, I2S_REG_INT_EN, 0);
++
++ mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
++ mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
++ i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
++
++ return 0;
++}
++
++static int mt7620_i2s_dai_remove(struct snd_soc_dai *dai)
++{
++ return 0;
++}
++
++static const struct snd_soc_dai_ops mt7620_i2s_dai_ops = {
++ .startup = mt7620_i2s_startup,
++ .shutdown = mt7620_i2s_shutdown,
++ .trigger = mt7620_i2s_trigger,
++ .hw_params = mt7620_i2s_hw_params,
++ .set_fmt = mt7620_i2s_set_fmt,
++ .set_sysclk = mt7620_i2s_set_sysclk,
++};
++
++#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++static struct snd_soc_dai_driver mt7620_i2s_dai = {
++ .probe = mt7620_i2s_dai_probe,
++ .remove = mt7620_i2s_dai_remove,
++ .playback = {
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_48000,
++ .formats = JZ4740_I2S_FMTS,
++ },
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_8000_48000,
++ .formats = JZ4740_I2S_FMTS,
++ },
++ .symmetric_rates = 1,
++ .ops = &mt7620_i2s_dai_ops,
++};
++
++static const struct snd_pcm_hardware mt7620_pcm_hardware = {
++ .info = SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID |
++ SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
++ .period_bytes_min = PAGE_SIZE,
++ .period_bytes_max = 64 * 1024,
++ .periods_min = 2,
++ .periods_max = 128,
++ .buffer_bytes_max = 128 * 1024,
++ .fifo_size = 32,
++};
++
++static const struct snd_dmaengine_pcm_config mt7620_dmaengine_pcm_config = {
++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++ .pcm_hardware = &mt7620_pcm_hardware,
++ .prealloc_buffer_size = 256 * PAGE_SIZE,
++};
++
++static const struct snd_soc_component_driver mt7620_i2s_component = {
++ .name = "mt7620-i2s",
++};
++
++static int mt7620_i2s_dev_probe(struct platform_device *pdev)
++{
++ struct mt7620_i2s *i2s;
++ int ret;
++
++ snd_dmaengine_pcm_register(&pdev->dev,
++ &mt7620_dmaengine_pcm_config,
++ SND_DMAENGINE_PCM_FLAG_COMPAT);
++
++ i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
++ if (!i2s)
++ return -ENOMEM;
++
++ i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!i2s->mem) {
++ ret = -ENOENT;
++ goto err_free;
++ }
++
++ i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
++ pdev->name);
++ if (!i2s->mem) {
++ ret = -EBUSY;
++ goto err_free;
++ }
++
++ i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
++ if (!i2s->base) {
++ ret = -EBUSY;
++ goto err_release_mem_region;
++ }
++
++ i2s->phys_base = i2s->mem->start;
++
++ platform_set_drvdata(pdev, i2s);
++ ret = snd_soc_register_component(&pdev->dev, &mt7620_i2s_component,
++ &mt7620_i2s_dai, 1);
++
++ if (!ret) {
++ dev_err(&pdev->dev, "loaded\n");
++ return ret;
++ }
++
++ dev_err(&pdev->dev, "Failed to register DAI\n");
++ iounmap(i2s->base);
++
++err_release_mem_region:
++ release_mem_region(i2s->mem->start, resource_size(i2s->mem));
++err_free:
++ kfree(i2s);
++
++ return ret;
++}
++
++static int mt7620_i2s_dev_remove(struct platform_device *pdev)
++{
++ struct mt7620_i2s *i2s = platform_get_drvdata(pdev);
++
++ snd_soc_unregister_component(&pdev->dev);
++
++ iounmap(i2s->base);
++ release_mem_region(i2s->mem->start, resource_size(i2s->mem));
++
++ kfree(i2s);
++
++ snd_dmaengine_pcm_unregister(&pdev->dev);
++
++ return 0;
++}
++
++static const struct of_device_id mt7620_i2s_match[] = {
++ { .compatible = "ralink,mt7620a-i2s" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mt7620_i2s_match);
++
++static struct platform_driver mt7620_i2s_driver = {
++ .probe = mt7620_i2s_dev_probe,
++ .remove = mt7620_i2s_dev_remove,
++ .driver = {
++ .name = "mt7620-i2s",
++ .owner = THIS_MODULE,
++ .of_match_table = mt7620_i2s_match,
++ },
++};
++
++module_platform_driver(mt7620_i2s_driver);
++
++MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
++MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mt7620-i2s");
+--- /dev/null
++++ b/sound/soc/ralink/mt7620-wm8960.c
+@@ -0,0 +1,233 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * Based on mt7620-sgtl5000.c
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <sound/soc-dapm.h>
++#include <linux/pinctrl/consumer.h>
++
++#include "../codecs/wm8960.h"
++
++#define DAI_NAME_SIZE 32
++
++struct mt7620_wm8960_data {
++ struct snd_soc_dai_link dai;
++ struct snd_soc_card card;
++ char codec_dai_name[DAI_NAME_SIZE];
++ char platform_name[DAI_NAME_SIZE];
++ unsigned int clk_frequency;
++};
++
++struct mt7620_priv {
++ struct platform_device *pdev;
++};
++static struct mt7620_priv card_priv;
++
++static const struct snd_soc_dapm_widget mt7620_wm8960_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_SPK("Ext Spk", NULL),
++ SND_SOC_DAPM_MIC("AMIC", NULL),
++ SND_SOC_DAPM_MIC("DMIC", NULL),
++};
++
++static int sample_rate = 44100;
++static snd_pcm_format_t sample_format = SNDRV_PCM_FORMAT_S16_LE;
++
++static int mt7620_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ sample_rate = params_rate(params);
++ sample_format = params_format(params);
++
++ return 0;
++}
++
++static struct snd_soc_ops mt7620_hifi_ops = {
++ .hw_params = mt7620_hifi_hw_params,
++};
++
++static int mt7620_wm8960_set_bias_level(struct snd_soc_card *card,
++ struct snd_soc_dapm_context *dapm,
++ enum snd_soc_bias_level level)
++{
++ struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
++ struct mt7620_priv *priv = &card_priv;
++ struct mt7620_wm8960_data *data = snd_soc_card_get_drvdata(card);
++ struct device *dev = &priv->pdev->dev;
++ int ret;
++
++ if (dapm->dev != codec_dai->dev)
++ return 0;
++
++ switch (level) {
++ case SND_SOC_BIAS_PREPARE:
++ if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
++ }
++ break;
++
++ case SND_SOC_BIAS_STANDBY:
++ if (dapm->bias_level == SND_SOC_BIAS_PREPARE) {
++ ret = snd_soc_dai_set_sysclk(codec_dai,
++ WM8960_SYSCLK_MCLK, data->clk_frequency,
++ SND_SOC_CLOCK_IN);
++ if (ret < 0) {
++ dev_err(dev,
++ "failed to switch away from FLL: %d\n",
++ ret);
++ return ret;
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++static int mt7620_wm8960_late_probe(struct snd_soc_card *card)
++{
++ struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
++ struct mt7620_priv *priv = &card_priv;
++ struct mt7620_wm8960_data *data = snd_soc_card_get_drvdata(card);
++ struct device *dev = &priv->pdev->dev;
++ int ret;
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8960_SYSCLK_MCLK,
++ data->clk_frequency, SND_SOC_CLOCK_IN);
++ if (ret < 0)
++ dev_err(dev, "failed to set sysclk in %s\n", __func__);
++
++ return ret;
++}
++
++static int mt7620_wm8960_probe(struct platform_device *pdev)
++{
++ struct device_node *i2s_np, *codec_np;
++ struct platform_device *i2s_pdev;
++ struct mt7620_priv *priv = &card_priv;
++ struct i2c_client *codec_dev;
++ struct mt7620_wm8960_data *data;
++ int ret;
++
++ priv->pdev = pdev;
++
++ i2s_np = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0);
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!i2s_np || !codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ i2s_pdev = of_find_device_by_node(i2s_np);
++ if (!i2s_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++ codec_dev = of_find_i2c_device_by_node(codec_np);
++ if (!codec_dev || !codec_dev->dev.driver) {
++ dev_err(&pdev->dev, "failed to find codec platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ data->clk_frequency = 12000000;
++ data->dai.name = "HiFi";
++ data->dai.stream_name = "HiFi";
++ data->dai.codec_dai_name = "wm8960-hifi";
++ data->dai.codec_of_node = codec_np;
++ data->dai.cpu_dai_name = dev_name(&i2s_pdev->dev);
++ data->dai.platform_of_node = i2s_np;
++ data->dai.ops = &mt7620_hifi_ops;
++ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ data->card.dev = &pdev->dev;
++ ret = snd_soc_of_parse_card_name(&data->card, "model");
++ if (ret)
++ goto fail;
++ ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
++ if (ret)
++ goto fail;
++ data->card.num_links = 1;
++ data->card.dai_link = &data->dai;
++ data->card.dapm_widgets = mt7620_wm8960_dapm_widgets;
++ data->card.num_dapm_widgets = ARRAY_SIZE(mt7620_wm8960_dapm_widgets);
++
++ data->card.late_probe = mt7620_wm8960_late_probe;
++ data->card.set_bias_level = mt7620_wm8960_set_bias_level;
++
++ platform_set_drvdata(pdev, &data->card);
++ snd_soc_card_set_drvdata(&data->card, data);
++
++ ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
++ if (ret) {
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++ goto fail;
++ }
++
++ of_node_put(i2s_np);
++ of_node_put(codec_np);
++
++ return 0;
++fail:
++ if (i2s_np)
++ of_node_put(i2s_np);
++ if (codec_np)
++ of_node_put(codec_np);
++
++ return ret;
++}
++
++static int mt7620_wm8960_remove(struct platform_device *pdev)
++{
++ return 0;
++}
++
++static const struct of_device_id mt7620_wm8960_dt_ids[] = {
++ { .compatible = "mediatek,mt7620-audio-wm8960", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, mt7620_wm8960_dt_ids);
++
++static struct platform_driver mt7620_wm8960_driver = {
++ .driver = {
++ .name = "mt7620-wm8960",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = mt7620_wm8960_dt_ids,
++ },
++ .probe = mt7620_wm8960_probe,
++ .remove = mt7620_wm8960_remove,
++};
++module_platform_driver(mt7620_wm8960_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale i.MX WM8962 ASoC machine driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:mt7620-wm8962");
--- /dev/null
+From 6a42dd698ddf91b6e9902b17e21dc13c6ae412ff Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 05:24:42 +0000
+Subject: [PATCH 56/57] watchdog: add MT7621 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/watchdog/Kconfig | 7 ++
+ drivers/watchdog/Makefile | 1 +
+ drivers/watchdog/mt7621_wdt.c | 185 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 193 insertions(+)
+ create mode 100644 drivers/watchdog/mt7621_wdt.c
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1257,6 +1257,13 @@ config RALINK_WDT
+ help
+ Hardware driver for the Ralink SoC Watchdog Timer.
+
++config MT7621_WDT
++ tristate "Mediatek SoC watchdog"
++ select WATCHDOG_CORE
++ depends on SOC_MT7620 || SOC_MT7621
++ help
++ Hardware driver for the Ralink SoC Watchdog Timer.
++
+ # PARISC Architecture
+
+ # POWERPC Architecture
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -143,6 +143,7 @@ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
+ octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
+ obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
+ obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
++obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o
+
+ # PARISC Architecture
+
+--- /dev/null
++++ b/drivers/watchdog/mt7621_wdt.c
+@@ -0,0 +1,185 @@
++/*
++ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ *
++ * This driver was based on: drivers/watchdog/softdog.c
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/miscdevice.h>
++#include <linux/moduleparam.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define SYSC_RSTSTAT 0x38
++#define WDT_RST_CAUSE BIT(1)
++
++#define RALINK_WDT_TIMEOUT 30
++
++#define TIMER_REG_TMRSTAT 0x00
++#define TIMER_REG_TMR1LOAD 0x24
++#define TIMER_REG_TMR1CTL 0x20
++
++#define TMR1CTL_ENABLE BIT(7)
++#define TMR1CTL_RESTART BIT(9)
++
++static void __iomem *mt762x_wdt_base;
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, bool, 0);
++MODULE_PARM_DESC(nowayout,
++ "Watchdog cannot be stopped once started (default="
++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static inline void rt_wdt_w32(unsigned reg, u32 val)
++{
++ iowrite32(val, mt762x_wdt_base + reg);
++}
++
++static inline u32 rt_wdt_r32(unsigned reg)
++{
++ return ioread32(mt762x_wdt_base + reg);
++}
++
++static int mt762x_wdt_ping(struct watchdog_device *w)
++{
++ rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
++
++ return 0;
++}
++
++static int mt762x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
++{
++ w->timeout = t;
++ rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
++ mt762x_wdt_ping(w);
++
++ return 0;
++}
++
++static int mt762x_wdt_start(struct watchdog_device *w)
++{
++ u32 t;
++
++ rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << 16);
++ mt762x_wdt_set_timeout(w, w->timeout);
++
++ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++ t |= TMR1CTL_ENABLE;
++ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++ return 0;
++}
++
++static int mt762x_wdt_stop(struct watchdog_device *w)
++{
++ u32 t;
++
++ mt762x_wdt_ping(w);
++
++ t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++ t &= ~TMR1CTL_ENABLE;
++ rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++ return 0;
++}
++
++static int mt762x_wdt_bootcause(void)
++{
++ if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
++ return WDIOF_CARDRESET;
++
++ return 0;
++}
++
++static struct watchdog_info mt762x_wdt_info = {
++ .identity = "Mediatek Watchdog",
++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++};
++
++static struct watchdog_ops mt762x_wdt_ops = {
++ .owner = THIS_MODULE,
++ .start = mt762x_wdt_start,
++ .stop = mt762x_wdt_stop,
++ .ping = mt762x_wdt_ping,
++ .set_timeout = mt762x_wdt_set_timeout,
++};
++
++static struct watchdog_device mt762x_wdt_dev = {
++ .info = &mt762x_wdt_info,
++ .ops = &mt762x_wdt_ops,
++ .min_timeout = 1,
++};
++
++static int mt762x_wdt_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ int ret;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ mt762x_wdt_base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(mt762x_wdt_base))
++ return PTR_ERR(mt762x_wdt_base);
++
++ device_reset(&pdev->dev);
++
++ mt762x_wdt_dev.dev = &pdev->dev;
++ mt762x_wdt_dev.bootstatus = mt762x_wdt_bootcause();
++ mt762x_wdt_dev.max_timeout = (0xfffful / 1000);
++ mt762x_wdt_dev.timeout = mt762x_wdt_dev.max_timeout;
++
++ watchdog_set_nowayout(&mt762x_wdt_dev, nowayout);
++
++ ret = watchdog_register_device(&mt762x_wdt_dev);
++ if (!ret)
++ dev_info(&pdev->dev, "Initialized\n");
++
++ return 0;
++}
++
++static int mt762x_wdt_remove(struct platform_device *pdev)
++{
++ watchdog_unregister_device(&mt762x_wdt_dev);
++
++ return 0;
++}
++
++static void mt762x_wdt_shutdown(struct platform_device *pdev)
++{
++ mt762x_wdt_stop(&mt762x_wdt_dev);
++}
++
++static const struct of_device_id mt762x_wdt_match[] = {
++ { .compatible = "mtk,mt7621-wdt" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mt762x_wdt_match);
++
++static struct platform_driver mt762x_wdt_driver = {
++ .probe = mt762x_wdt_probe,
++ .remove = mt762x_wdt_remove,
++ .shutdown = mt762x_wdt_shutdown,
++ .driver = {
++ .name = KBUILD_MODNAME,
++ .owner = THIS_MODULE,
++ .of_match_table = mt762x_wdt_match,
++ },
++};
++
++module_platform_driver(mt762x_wdt_driver);
++
++MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
--- /dev/null
+From 0d3e92b4d3e2160873b610aabd46bbc4853ff82e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 19 Sep 2013 01:50:59 +0200
+Subject: [PATCH 57/57] uvc: add iPassion iP2970 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/media/usb/uvc/uvc_driver.c | 14 ++++
+ drivers/media/usb/uvc/uvc_status.c | 2 +
+ drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++
+ drivers/media/usb/uvc/uvcvideo.h | 3 +
+ 4 files changed, 166 insertions(+)
+
+--- a/drivers/media/usb/uvc/uvc_driver.c
++++ b/drivers/media/usb/uvc/uvc_driver.c
+@@ -2504,6 +2504,20 @@ static struct usb_device_id uvc_ids[] =
+ .bInterfaceProtocol = 0,
+ .driver_info = UVC_QUIRK_PROBE_MINMAX
+ | UVC_QUIRK_IGNORE_SELECTOR_UNIT },
++
++/* iPassion iP2970 */
++ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
++ | USB_DEVICE_ID_MATCH_INT_INFO,
++ .idVendor = 0x1B3B,
++ .idProduct = 0x2970,
++ .bInterfaceClass = USB_CLASS_VIDEO,
++ .bInterfaceSubClass = 1,
++ .bInterfaceProtocol = 0,
++ .driver_info = UVC_QUIRK_PROBE_MINMAX
++ | UVC_QUIRK_STREAM_NO_FID
++ | UVC_QUIRK_MOTION
++ | UVC_QUIRK_SINGLE_ISO },
++
+ /* Generic USB Video Class */
+ { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) },
+ {}
+--- a/drivers/media/usb/uvc/uvc_status.c
++++ b/drivers/media/usb/uvc/uvc_status.c
+@@ -139,6 +139,7 @@ static void uvc_status_complete(struct u
+ switch (dev->status[0] & 0x0f) {
+ case UVC_STATUS_TYPE_CONTROL:
+ uvc_event_control(dev, dev->status, len);
++ dev->motion = 1;
+ break;
+
+ case UVC_STATUS_TYPE_STREAMING:
+@@ -182,6 +183,7 @@ int uvc_status_init(struct uvc_device *d
+ }
+
+ pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
++ dev->motion = 0;
+
+ /* For high-speed interrupt endpoints, the bInterval value is used as
+ * an exponent of two. Some developers forgot about it.
+--- a/drivers/media/usb/uvc/uvc_video.c
++++ b/drivers/media/usb/uvc/uvc_video.c
+@@ -21,6 +21,11 @@
+ #include <linux/wait.h>
+ #include <linux/atomic.h>
+ #include <asm/unaligned.h>
++#include <linux/skbuff.h>
++#include <linux/kobject.h>
++#include <linux/netlink.h>
++#include <linux/kobject.h>
++#include <linux/workqueue.h>
+
+ #include <media/v4l2-common.h>
+
+@@ -1080,9 +1085,149 @@ static void uvc_video_decode_data(struct
+ }
+ }
+
++struct bh_priv {
++ unsigned long seen;
++};
++
++struct bh_event {
++ const char *name;
++ struct sk_buff *skb;
++ struct work_struct work;
++};
++
++#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args )
++#define BH_DBG(fmt, args...) do {} while (0)
++#define BH_SKB_SIZE 2048
++
++extern u64 uevent_next_seqnum(void);
++static int seen = 0;
++
++static int bh_event_add_var(struct bh_event *event, int argv,
++ const char *format, ...)
++{
++ static char buf[128];
++ char *s;
++ va_list args;
++ int len;
++
++ if (argv)
++ return 0;
++
++ va_start(args, format);
++ len = vsnprintf(buf, sizeof(buf), format, args);
++ va_end(args);
++
++ if (len >= sizeof(buf)) {
++ BH_ERR("buffer size too small\n");
++ WARN_ON(1);
++ return -ENOMEM;
++ }
++
++ s = skb_put(event->skb, len + 1);
++ strcpy(s, buf);
++
++ BH_DBG("added variable '%s'\n", s);
++
++ return 0;
++}
++
++static int motion_hotplug_fill_event(struct bh_event *event)
++{
++ int s = jiffies;
++ int ret;
++
++ if (!seen)
++ seen = jiffies;
++
++ ret = bh_event_add_var(event, 0, "HOME=%s", "/");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "PATH=%s",
++ "/sbin:/bin:/usr/sbin:/usr/bin");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "ACTION=motion");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen);
++ if (ret)
++ return ret;
++ seen = s;
++
++ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());
++
++ return ret;
++}
++
++static void motion_hotplug_work(struct work_struct *work)
++{
++ struct bh_event *event = container_of(work, struct bh_event, work);
++ int ret = 0;
++
++ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
++ if (!event->skb)
++ goto out_free_event;
++
++ ret = bh_event_add_var(event, 0, "%s@", "add");
++ if (ret)
++ goto out_free_skb;
++
++ ret = motion_hotplug_fill_event(event);
++ if (ret)
++ goto out_free_skb;
++
++ NETLINK_CB(event->skb).dst_group = 1;
++ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);
++
++out_free_skb:
++ if (ret) {
++ BH_ERR("work error %d\n", ret);
++ kfree_skb(event->skb);
++ }
++out_free_event:
++ kfree(event);
++}
++
++static int motion_hotplug_create_event(void)
++{
++ struct bh_event *event;
++
++ event = kzalloc(sizeof(*event), GFP_KERNEL);
++ if (!event)
++ return -ENOMEM;
++
++ event->name = "motion";
++
++ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);
++ schedule_work(&event->work);
++
++ return 0;
++}
++
++#define MOTION_FLAG_OFFSET 4
+ static void uvc_video_decode_end(struct uvc_streaming *stream,
+ struct uvc_buffer *buf, const __u8 *data, int len)
+ {
++ if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
++ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
++ u8 *mem;
++ buf->state = UVC_BUF_STATE_READY;
++ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);
++ if ( stream->dev->motion ) {
++ stream->dev->motion = 0;
++ motion_hotplug_create_event();
++ } else {
++ *mem &= 0x7f;
++ }
++ }
++
+ /* Mark the buffer as done if the EOF marker is set. */
+ if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
+ uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n");
+@@ -1495,6 +1640,8 @@ static int uvc_init_video_isoc(struct uv
+ if (npackets == 0)
+ return -ENOMEM;
+
++ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)
++ npackets = 1;
+ size = npackets * psize;
+
+ for (i = 0; i < UVC_URBS; ++i) {
+--- a/drivers/media/usb/uvc/uvcvideo.h
++++ b/drivers/media/usb/uvc/uvcvideo.h
+@@ -148,6 +148,8 @@
+ #define UVC_QUIRK_PROBE_DEF 0x00000100
+ #define UVC_QUIRK_RESTRICT_FRAME_RATE 0x00000200
+ #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400
++#define UVC_QUIRK_MOTION 0x00000800
++#define UVC_QUIRK_SINGLE_ISO 0x00001000
+
+ /* Format flags */
+ #define UVC_FMT_FLAG_COMPRESSED 0x00000001
+@@ -551,6 +553,7 @@ struct uvc_device {
+ __u8 *status;
+ struct input_dev *input;
+ char input_phys[64];
++ int motion;
+ };
+
+ enum uvc_handle_state {
--- /dev/null
+--- a/drivers/usb/dwc2/hcd.c
++++ b/drivers/usb/dwc2/hcd.c
+@@ -47,6 +47,7 @@
+ #include <linux/io.h>
+ #include <linux/slab.h>
+ #include <linux/usb.h>
++#include <linux/reset.h>
+
+ #include <linux/usb/hcd.h>
+ #include <linux/usb/ch11.h>
+@@ -2780,6 +2781,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
+
+ dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
+
++ device_reset(hsotg->dev);
++
+ /* Detect config values from hardware */
+ retval = dwc2_get_hwparams(hsotg);
+
--- /dev/null
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -13,14 +13,6 @@
+ #ifndef _MT7620_REGS_H_
+ #define _MT7620_REGS_H_
+
+-enum mt762x_soc_type {
+- MT762X_SOC_UNKNOWN = 0,
+- MT762X_SOC_MT7620A,
+- MT762X_SOC_MT7620N,
+- MT762X_SOC_MT7628AN,
+-};
+-extern enum mt762x_soc_type mt762x_soc;
+-
+ #define MT7620_SYSC_BASE 0x10000000
+
+ #define SYSC_REG_CHIP_NAME0 0x00
+--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+@@ -13,6 +13,20 @@
+ #ifndef _RALINK_REGS_H_
+ #define _RALINK_REGS_H_
+
++enum ralink_soc_type {
++ RALINK_UNKNOWN = 0,
++ RT305X_SOC_RT3050,
++ RT305X_SOC_RT3052,
++ RT305X_SOC_RT3350,
++ RT305X_SOC_RT3352,
++ RT305X_SOC_RT5350,
++ MT762X_SOC_MT7620A,
++ MT762X_SOC_MT7620N,
++ MT762X_SOC_MT7621AT,
++ MT762X_SOC_MT7628AN,
++};
++extern enum ralink_soc_type ralink_soc;
++
+ extern __iomem void *rt_sysc_membase;
+ extern __iomem void *rt_memc_membase;
+
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -13,25 +13,16 @@
+ #ifndef _RT305X_REGS_H_
+ #define _RT305X_REGS_H_
+
+-enum rt305x_soc_type {
+- RT305X_SOC_UNKNOWN = 0,
+- RT305X_SOC_RT3050,
+- RT305X_SOC_RT3052,
+- RT305X_SOC_RT3350,
+- RT305X_SOC_RT3352,
+- RT305X_SOC_RT5350,
+-};
+-
+-extern enum rt305x_soc_type rt305x_soc;
++extern enum ralink_soc_type ralink_soc;
+
+ static inline int soc_is_rt3050(void)
+ {
+- return rt305x_soc == RT305X_SOC_RT3050;
++ return ralink_soc == RT305X_SOC_RT3050;
+ }
+
+ static inline int soc_is_rt3052(void)
+ {
+- return rt305x_soc == RT305X_SOC_RT3052;
++ return ralink_soc == RT305X_SOC_RT3052;
+ }
+
+ static inline int soc_is_rt305x(void)
+@@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void)
+
+ static inline int soc_is_rt3350(void)
+ {
+- return rt305x_soc == RT305X_SOC_RT3350;
++ return ralink_soc == RT305X_SOC_RT3350;
+ }
+
+ static inline int soc_is_rt3352(void)
+ {
+- return rt305x_soc == RT305X_SOC_RT3352;
++ return ralink_soc == RT305X_SOC_RT3352;
+ }
+
+ static inline int soc_is_rt5350(void)
+ {
+- return rt305x_soc == RT305X_SOC_RT5350;
++ return ralink_soc == RT305X_SOC_RT5350;
+ }
+
+ #define RT305X_SYSC_BASE 0x10000000
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -43,8 +43,6 @@
+ #define CLKCFG_FFRAC_MASK 0x001f
+ #define CLKCFG_FFRAC_USB_VAL 0x0003
+
+-enum mt762x_soc_type mt762x_soc;
+-
+ /* does the board have sdram or ddram */
+ static int dram_type;
+
+@@ -375,7 +373,7 @@ void __init ralink_clk_init(void)
+ #define RINT(x) ((x) / 1000000)
+ #define RFRAC(x) (((x) / 1000) % 1000)
+
+- if (mt762x_soc == MT762X_SOC_MT7628AN) {
++ if (ralink_soc == MT762X_SOC_MT7628AN) {
+ if (xtal_rate == MHZ(40))
+ cpu_rate = MHZ(580);
+ else
+@@ -418,7 +416,7 @@ void __init ralink_clk_init(void)
+ ralink_clk_add("10000c00.uartlite", periph_rate);
+ ralink_clk_add("10180000.wmac", xtal_rate);
+
+- if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
++ if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) {
+ /*
+ * When the CPU goes into sleep mode, the BUS clock will be too low for
+ * USB to function properly
+@@ -506,11 +504,11 @@ void prom_soc_init(struct ralink_soc_inf
+
+ if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
+ if (bga) {
+- mt762x_soc = MT762X_SOC_MT7620A;
++ ralink_soc = MT762X_SOC_MT7620A;
+ name = "MT7620A";
+ soc_info->compatible = "ralink,mt7620a-soc";
+ } else {
+- mt762x_soc = MT762X_SOC_MT7620N;
++ ralink_soc = MT762X_SOC_MT7620N;
+ name = "MT7620N";
+ soc_info->compatible = "ralink,mt7620n-soc";
+ #ifdef CONFIG_PCI
+@@ -518,7 +516,7 @@ void prom_soc_init(struct ralink_soc_inf
+ #endif
+ }
+ } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
+- mt762x_soc = MT762X_SOC_MT7628AN;
++ ralink_soc = MT762X_SOC_MT7628AN;
+ name = "MT7628AN";
+ soc_info->compatible = "ralink,mt7628an-soc";
+ } else {
+@@ -535,7 +533,7 @@ void prom_soc_init(struct ralink_soc_inf
+ dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
+
+ soc_info->mem_base = MT7620_DRAM_BASE;
+- if (mt762x_soc == MT762X_SOC_MT7628AN)
++ if (ralink_soc == MT762X_SOC_MT7628AN)
+ mt7628_dram_init(soc_info);
+ else
+ mt7620_dram_init(soc_info);
+@@ -548,7 +546,7 @@ void prom_soc_init(struct ralink_soc_inf
+ pr_info("Digital PMU set to %s control\n",
+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+
+- if (mt762x_soc == MT762X_SOC_MT7628AN)
++ if (ralink_soc == MT762X_SOC_MT7628AN)
+ rt2880_pinmux_data = mt7628an_pinmux_data;
+ else
+ rt2880_pinmux_data = mt7620a_pinmux_data;
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -21,8 +21,6 @@
+
+ #include "common.h"
+
+-enum rt305x_soc_type rt305x_soc;
+-
+ static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
+ static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
+ static struct rt2880_pmx_func uartf_func[] = {
+@@ -234,24 +232,24 @@ void prom_soc_init(struct ralink_soc_inf
+
+ icache_sets = (read_c0_config1() >> 22) & 7;
+ if (icache_sets == 1) {
+- rt305x_soc = RT305X_SOC_RT3050;
++ ralink_soc = RT305X_SOC_RT3050;
+ name = "RT3050";
+ soc_info->compatible = "ralink,rt3050-soc";
+ } else {
+- rt305x_soc = RT305X_SOC_RT3052;
++ ralink_soc = RT305X_SOC_RT3052;
+ name = "RT3052";
+ soc_info->compatible = "ralink,rt3052-soc";
+ }
+ } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
+- rt305x_soc = RT305X_SOC_RT3350;
++ ralink_soc = RT305X_SOC_RT3350;
+ name = "RT3350";
+ soc_info->compatible = "ralink,rt3350-soc";
+ } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
+- rt305x_soc = RT305X_SOC_RT3352;
++ ralink_soc = RT305X_SOC_RT3352;
+ name = "RT3352";
+ soc_info->compatible = "ralink,rt3352-soc";
+ } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
+- rt305x_soc = RT305X_SOC_RT5350;
++ ralink_soc = RT305X_SOC_RT5350;
+ name = "RT5350";
+ soc_info->compatible = "ralink,rt5350-soc";
+ } else {
+--- a/arch/mips/ralink/prom.c
++++ b/arch/mips/ralink/prom.c
+@@ -15,9 +15,13 @@
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
+
++#include <asm/mach-ralink/ralink_regs.h>
++
+ #include "common.h"
+
+ struct ralink_soc_info soc_info;
++enum ralink_soc_type ralink_soc;
++EXPORT_SYMBOL_GPL(ralink_soc);
+
+ const char *get_system_type(void)
+ {
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -175,6 +175,7 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
+ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
+ soc_info->mem_base = MT7621_DRAM_BASE;
++ ralink_soc = MT762X_SOC_MT7621AT;
+
+ rt2880_pinmux_data = mt7621_pinmux_data;
+
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -439,6 +439,12 @@ config SPI_RT2880
+ help
+ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
+
++config SPI_MT7621
++ tristate "MediaTek MT7621 SPI Controller"
++ depends on RALINK
++ help
++ This selects a driver for the MediaTek MT7621 SPI Controller.
++
+ config SPI_S3C24XX
+ tristate "Samsung S3C24XX series SPI"
+ depends on ARCH_S3C24XX
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70l
+ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
+ obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
+ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
++obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
+ obj-$(CONFIG_SPI_MXS) += spi-mxs.o
+ obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
+ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
+--- /dev/null
++++ b/drivers/spi/spi-mt7621.c
+@@ -0,0 +1,315 @@
++/*
++ * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
++ *
++ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
++ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
++ *
++ * Some parts are based on spi-orion.c:
++ * Author: Shadi Ammouri <shadi@marvell.com>
++ * Copyright (C) 2007-2008 Marvell Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/reset.h>
++#include <linux/spi/spi.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/swab.h>
++
++#include <ralink_regs.h>
++
++#define SPI_BPW_MASK(bits) BIT((bits) - 1)
++
++#define DRIVER_NAME "spi-mt7621"
++/* in usec */
++#define RALINK_SPI_WAIT_MAX_LOOP 2000
++
++/* SPISTAT register bit field */
++#define SPISTAT_BUSY BIT(0)
++
++#define MT7621_SPI_TRANS 0x00
++#define SPITRANS_BUSY BIT(16)
++
++#define MT7621_SPI_OPCODE 0x04
++#define MT7621_SPI_DATA0 0x08
++#define SPI_CTL_TX_RX_CNT_MASK 0xff
++#define SPI_CTL_START BIT(8)
++
++#define MT7621_SPI_POLAR 0x38
++#define MT7621_SPI_MASTER 0x28
++#define MT7621_SPI_MOREBUF 0x2c
++#define MT7621_SPI_SPACE 0x3c
++
++#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
++
++struct mt7621_spi;
++
++struct mt7621_spi {
++ struct spi_master *master;
++ void __iomem *base;
++ unsigned int sys_freq;
++ unsigned int speed;
++ struct clk *clk;
++ spinlock_t lock;
++
++ struct mt7621_spi_ops *ops;
++};
++
++static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
++{
++ return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
++{
++ return ioread32(rs->base + reg);
++}
++
++static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
++{
++ iowrite32(val, rs->base + reg);
++}
++
++static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
++{
++ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
++ u32 polar = mt7621_spi_read(rs, MT7621_SPI_POLAR);
++
++ if (enable)
++ polar |= 1;
++ else
++ polar &= ~1;
++ mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
++}
++
++static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
++{
++ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
++ int i;
++
++ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
++ u32 status;
++
++ status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
++ if ((status & SPITRANS_BUSY) == 0) {
++ return 0;
++ }
++ cpu_relax();
++ udelay(1);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static int mt7621_spi_transfer_one_message(struct spi_master *master,
++ struct spi_message *m)
++{
++ struct mt7621_spi *rs = spi_master_get_devdata(master);
++ struct spi_device *spi = m->spi;
++ struct spi_transfer *t = NULL;
++ int status = 0;
++ int i, len = 0;
++ int rx_len = 0;
++ u32 data[9] = { 0 };
++ u32 val;
++
++ mt7621_spi_wait_till_ready(spi);
++
++ list_for_each_entry(t, &m->transfers, transfer_list) {
++ const u8 *buf = t->tx_buf;
++
++ if (t->rx_buf)
++ rx_len += t->len;
++
++ if (!buf)
++ continue;
++
++ if (WARN_ON(len + t->len > 36)) {
++ status = -EIO;
++ goto msg_done;
++ }
++
++ for (i = 0; i < t->len; i++, len++)
++ data[len / 4] |= buf[i] << (8 * (len & 3));
++ }
++
++ if (WARN_ON(rx_len > 32)) {
++ status = -EIO;
++ goto msg_done;
++ }
++
++ data[0] = swab32(data[0]);
++ if (len < 4)
++ data[0] >>= (4 - len) * 8;
++
++ for (i = 0; i < len; i += 4)
++ mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
++
++ val = (min_t(int, len, 4) * 8) << 24;
++ if (len > 4)
++ val |= (len - 4) * 8;
++ val |= (rx_len * 8) << 12;
++ mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
++
++ mt7621_spi_set_cs(spi, 1);
++
++ val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
++ val |= SPI_CTL_START;
++ mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
++
++ mt7621_spi_wait_till_ready(spi);
++
++ mt7621_spi_set_cs(spi, 0);
++
++ for (i = 0; i < rx_len; i += 4)
++ data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
++
++ m->actual_length = len + rx_len;
++
++ len = 0;
++ list_for_each_entry(t, &m->transfers, transfer_list) {
++ u8 *buf = t->rx_buf;
++
++ if (!buf)
++ continue;
++
++ for (i = 0; i < t->len; i++, len++)
++ buf[i] = data[len / 4] >> (8 * (len & 3));
++ }
++
++msg_done:
++ m->status = status;
++ spi_finalize_current_message(master);
++
++ return 0;
++}
++
++static int mt7621_spi_setup(struct spi_device *spi)
++{
++ return 0;
++}
++
++static void mt7621_spi_reset(struct mt7621_spi *rs)
++{
++ u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
++
++ master &= ~(0xfff << 16);
++ master |= 13 << 16;
++ master |= 7 << 29;
++ master |= 1 << 2;
++
++ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
++}
++
++static const struct of_device_id mt7621_spi_match[] = {
++ { .compatible = "ralink,mt7621-spi" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mt7621_spi_match);
++
++static int mt7621_spi_probe(struct platform_device *pdev)
++{
++ const struct of_device_id *match;
++ struct spi_master *master;
++ struct mt7621_spi *rs;
++ unsigned long flags;
++ void __iomem *base;
++ struct resource *r;
++ int status = 0;
++ struct clk *clk;
++ struct mt7621_spi_ops *ops;
++
++ match = of_match_device(mt7621_spi_match, &pdev->dev);
++ if (!match)
++ return -EINVAL;
++ ops = (struct mt7621_spi_ops *)match->data;
++
++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ base = devm_ioremap_resource(&pdev->dev, r);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
++ status);
++ return PTR_ERR(clk);
++ }
++
++ status = clk_prepare_enable(clk);
++ if (status)
++ return status;
++
++ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
++ if (master == NULL) {
++ dev_dbg(&pdev->dev, "master allocation failed\n");
++ return -ENOMEM;
++ }
++
++ master->mode_bits = RT2880_SPI_MODE_BITS;
++
++ master->setup = mt7621_spi_setup;
++ master->transfer_one_message = mt7621_spi_transfer_one_message;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
++ master->dev.of_node = pdev->dev.of_node;
++ master->num_chipselect = 1;
++
++ dev_set_drvdata(&pdev->dev, master);
++
++ rs = spi_master_get_devdata(master);
++ rs->base = base;
++ rs->clk = clk;
++ rs->master = master;
++ rs->sys_freq = clk_get_rate(rs->clk);
++ rs->ops = ops;
++ dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
++ spin_lock_irqsave(&rs->lock, flags);
++
++ device_reset(&pdev->dev);
++
++ mt7621_spi_reset(rs);
++
++ return spi_register_master(master);
++}
++
++static int mt7621_spi_remove(struct platform_device *pdev)
++{
++ struct spi_master *master;
++ struct mt7621_spi *rs;
++
++ master = dev_get_drvdata(&pdev->dev);
++ rs = spi_master_get_devdata(master);
++
++ clk_disable(rs->clk);
++ spi_unregister_master(master);
++
++ return 0;
++}
++
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
++static struct platform_driver mt7621_spi_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = mt7621_spi_match,
++ },
++ .probe = mt7621_spi_probe,
++ .remove = mt7621_spi_remove,
++};
++
++module_platform_driver(mt7621_spi_driver);
++
++MODULE_DESCRIPTION("MT7621 SPI driver");
++MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
++MODULE_LICENSE("GPL");
--- /dev/null
+--- a/drivers/mtd/mtdpart.c
++++ b/drivers/mtd/mtdpart.c
+@@ -821,9 +821,6 @@ static void split_uimage(struct mtd_info
+ return;
+
+ len = be32_to_cpu(hdr.size) + 0x40;
+- len = mtd_pad_erasesize(master, part->offset, len);
+- if (len + master->erasesize > part->mtd.size)
+- return;
+
+ if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW))
+ pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n");
--- /dev/null
+--- a/drivers/mtd/mtdpart.c
++++ b/drivers/mtd/mtdpart.c
+@@ -809,8 +809,11 @@ static void split_uimage(struct mtd_info
+ {
+ struct {
+ __be32 magic;
+- __be32 pad[2];
++ __be32 pad0[2];
+ __be32 size;
++ __be32 pad1[4];
++ __be32 name[7];
++ __be32 kern_size;
+ } hdr;
+ size_t len;
+
+@@ -820,7 +823,10 @@ static void split_uimage(struct mtd_info
+ if (len != sizeof(hdr) || hdr.magic != cpu_to_be32(UBOOT_MAGIC))
+ return;
+
+- len = be32_to_cpu(hdr.size) + 0x40;
++ if (hdr.kern_size != 0 && hdr.name[0] == 0)
++ len = be32_to_cpu(hdr.kern_size);
++ else
++ len = be32_to_cpu(hdr.size) + 0x40;
+
+ if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW))
+ pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n");
--- /dev/null
+From c174d2250e402399ad7dbdd57d51883d8804bba0 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:40:37 +0200
+Subject: [PATCH 31/33] owrt: MIPS: add OWRTDTB secion
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/head.S | 3 +++
+ arch/mips/ralink/Makefile | 2 +-
+ arch/mips/ralink/of.c | 4 +++-
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/kernel/head.S
++++ b/arch/mips/kernel/head.S
+@@ -86,6 +86,9 @@ EXPORT(__image_cmdline)
+ .fill 0x400
+ #endif /* CONFIG_IMAGE_CMDLINE_HACK */
+
++ .ascii "OWRTDTB:"
++ EXPORT(__image_dtb)
++ .fill 0x4000
+ __REF
+
+ NESTED(kernel_entry, 16, sp) # kernel entry point
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -66,6 +66,8 @@ static int __init early_init_dt_find_mem
+ return 0;
+ }
+
++extern struct boot_param_header __image_dtb;
++
+ void __init plat_mem_setup(void)
+ {
+ set_io_port_base(KSEG1);
+@@ -74,7 +76,7 @@ void __init plat_mem_setup(void)
+ * Load the builtin devicetree. This causes the chosen node to be
+ * parsed resulting in our memory appearing
+ */
+- __dt_setup_arch(__dtb_start);
++ __dt_setup_arch(&__image_dtb);
+
+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+
--- /dev/null
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -3,7 +3,7 @@
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2008-2014 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+@@ -66,6 +66,17 @@ static int __init early_init_dt_find_mem
+ return 0;
+ }
+
++static int chosen_dtb;
++
++static int __init early_init_dt_find_chosen(unsigned long node, const char *uname,
++ int depth, void *data)
++{
++ if (depth == 1 && !strcmp(uname, "chosen"))
++ chosen_dtb = 1;
++
++ return 0;
++}
++
+ extern struct boot_param_header __image_dtb;
+
+ void __init plat_mem_setup(void)
+@@ -78,7 +89,9 @@ void __init plat_mem_setup(void)
+ */
+ __dt_setup_arch(&__image_dtb);
+
+- strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
++ of_scan_flat_dt(early_init_dt_find_chosen, NULL);
++ if (chosen_dtb)
++ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+
+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
+ if (memory_dtb)
--- /dev/null
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
+@@ -0,0 +1,65 @@
++/*
++ * Ralink MT7621 specific CPU feature overrides
++ *
++ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ * Copyright (C) 2003, 2004 Ralf Baechle
++ * Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
++#define _MT7621_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_has_tlb 1
++#define cpu_has_4kex 1
++#define cpu_has_3k_cache 0
++#define cpu_has_4k_cache 1
++#define cpu_has_tx39_cache 0
++#define cpu_has_sb1_cache 0
++#define cpu_has_fpu 0
++#define cpu_has_32fpr 0
++#define cpu_has_counter 1
++#define cpu_has_watch 1
++#define cpu_has_divec 1
++
++#define cpu_has_prefetch 1
++#define cpu_has_ejtag 1
++#define cpu_has_llsc 1
++
++#define cpu_has_mips16 1
++#define cpu_has_mdmx 0
++#define cpu_has_mips3d 0
++#define cpu_has_smartmips 0
++
++#define cpu_has_mips32r1 1
++#define cpu_has_mips32r2 1
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
++#define cpu_has_dsp 1
++#define cpu_has_dsp2 0
++#define cpu_has_mipsmt 1
++
++#define cpu_has_64bits 0
++#define cpu_has_64bit_zero_reg 0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses 0
++
++#define cpu_dcache_line_size() 32
++#define cpu_icache_line_size() 32
++
++#define cpu_has_dc_aliases 0
++#define cpu_has_vtag_icache 0
++
++#define cpu_has_rixi 0
++#define cpu_has_tlbinv 0
++#define cpu_has_userlocal 1
++
++#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void
+ {
+ _machine_restart = ralink_restart;
+ _machine_halt = ralink_halt;
+- pm_power_off = ralink_halt;
+
+ return 0;
+ }
--- /dev/null
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -511,9 +511,6 @@ void prom_soc_init(struct ralink_soc_inf
+ ralink_soc = MT762X_SOC_MT7620N;
+ name = "MT7620N";
+ soc_info->compatible = "ralink,mt7620n-soc";
+-#ifdef CONFIG_PCI
+- panic("mt7620n is only supported for non pci kernels");
+-#endif
+ }
+ } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
+ ralink_soc = MT762X_SOC_MT7628AN;
--- /dev/null
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -11,6 +11,7 @@
+ #include <linux/pm.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
++#include <linux/delay.h>
+ #include <linux/reset-controller.h>
+
+ #include <asm/reboot.h>
+@@ -18,8 +19,10 @@
+ #include <asm/mach-ralink/ralink_regs.h>
+
+ /* Reset Control */
+-#define SYSC_REG_RESET_CTRL 0x034
+-#define RSTCTL_RESET_SYSTEM BIT(0)
++#define SYSC_REG_RESET_CTRL 0x034
++
++#define RSTCTL_RESET_PCI BIT(26)
++#define RSTCTL_RESET_SYSTEM BIT(0)
+
+ static int ralink_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+@@ -83,6 +86,11 @@ void ralink_rst_init(void)
+
+ static void ralink_restart(char *command)
+ {
++ if (IS_ENABLED(CONFIG_PCI)) {
++ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
++ mdelay(50);
++ }
++
+ local_irq_disable();
+ rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
+ unreachable();
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT2880_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EARLY_PRINTK_8250 is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IP17XX_PHY=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=4
-CONFIG_MIPS_L1_CACHE_SHIFT_4=y
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_O32_FP64_SUPPORT is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_LZMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PCI is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-# CONFIG_RALINK_USBPHY is not set
-CONFIG_RALINK_WDT=y
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-CONFIG_SOC_RT288X=y
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT2880_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EARLY_PRINTK_8250 is not set
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_WORK=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=4
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_LZMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_RT2880=y
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PCI is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PINCONF is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+# CONFIG_RALINK_USBPHY is not set
+CONFIG_RALINK_WDT=y
+CONFIG_RA_NAT_NONE=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+CONFIG_SOC_RT288X=y
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_ZBUD is not set
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT305X_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-# CONFIG_DWC_OTG is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EARLY_PRINTK_8250 is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_O32_FP64_SUPPORT is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_ESW_RT3052=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-CONFIG_SOC_RT305X=y
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT305X_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_WORK=y
+CONFIG_KERNFS=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SUPPORT=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_ESW_RT3052=y
+CONFIG_NET_RALINK_RT305X=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+CONFIG_RALINK_WDT=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+CONFIG_SOC_RT305X=y
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
+++ /dev/null
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT3883_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EARLY_PRINTK_8250 is not set
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_WORK=y
-CONFIG_MDIO_BOARDINFO=y
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_O32_FP64_SUPPORT is not set
-# CONFIG_MLX5_CORE is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NET_RX_BUSY_POLL=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-CONFIG_RA_NAT_NONE=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTL8366_SMI=y
-CONFIG_RTL8367B_PHY=y
-CONFIG_RTL8367_PHY=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-CONFIG_SOC_RT3883=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_ZBUD is not set
-CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT3883_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_WORK=y
+CONFIG_KERNFS=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_O32_FP64_SUPPORT is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_SUPPORT=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_RALINK=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_RT2880=y
+CONFIG_NET_RALINK_RT3883=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+CONFIG_RALINK_WDT=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367B_PHY=y
+CONFIG_RTL8367_PHY=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+CONFIG_SOC_RT3883=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZONE_DMA_FLAG=0
projects / openwrt / staging / jow.git / commitdiff