drm/amd/display: align DCLK to voltage level
authorTony Cheng <tony.cheng@amd.com>
Wed, 27 Sep 2017 13:20:51 +0000 (09:20 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 21 Oct 2017 20:44:13 +0000 (16:44 -0400)
in past program SMU will use all voltage headroom.  RV does not

if DAL need higher voltage for DCFCLK or DISPCLK, also increase FCLK
to improve stutter as voltage is already

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

index cf474eb1cde873cad7458cda000326913a1aa3b5..9337ccadc32115ad6312e5ddd8c4100947d5d31f 100644 (file)
@@ -1049,6 +1049,10 @@ bool dcn_validate_bandwidth(
                else
                        bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
 
+               if (bw_consumed < v->fabric_and_dram_bandwidth)
+                       if (dc->debug.voltage_align_fclk)
+                               bw_consumed = v->fabric_and_dram_bandwidth;
+
                display_pipe_configuration(v);
                calc_wm_sets_and_perf_params(context, v);
                context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
index cf9cd108539fc0b3fe3c48e2ddb56a34bcfa9ccd..dbbe1d621bee21b58b5962f70f38c0a5a1b85919 100644 (file)
@@ -188,6 +188,7 @@ struct dc_debug {
        enum dcc_option disable_dcc;
        enum pipe_split_policy pipe_split_policy;
        bool force_single_disp_pipe_split;
+       bool voltage_align_fclk;
 
        bool disable_dfs_bypass;
        bool disable_dpp_power_gate;
index 30c275e05796454f95f3797fc6f44d192d509c90..4018e831eb4baafe13529c0a489f3cd53dd01117 100644 (file)
@@ -428,6 +428,7 @@ static const struct dc_debug debug_defaults_drv = {
 
                .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
                .disable_dcc = DCC_ENABLE,
+               .voltage_align_fclk = true,
 };
 
 static const struct dc_debug debug_defaults_diags = {