ARM: OMAP2: skip unnecessary TLDR write during non-autoreload for gptimer

The GPTIMER TLDR register does not need to be written if the GPTIMER
is not in autoreload mode.  This is the usual case for dynamic tick-enabled
kernels.

Simulation data indicate that skipping the read that occurs as part of
the write should save at least 300-320 ns for each GPTIMER1 timer
reprogram.  (This assumes L4-Wakeup is at 19MHz and GPTIMER write
posting is enabled.)  Skipping the write itself probably won't have
much impact since it should be posted on the OCP interconnect.

Tested on 2430SDP and 3430SDP.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 595e3d5092c9566efdc54fe7438546e1f238c293..e4f0ce04ba928130f8bfd973c9cc04d05b013f19 100644 (file)
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -549,14 +549,15 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
        u32 l;
 
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
-       if (autoreload)
+       if (autoreload) {
                l |= OMAP_TIMER_CTRL_AR;
-       else
+               omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
+       } else {
                l &= ~OMAP_TIMER_CTRL_AR;
+       }
        l |= OMAP_TIMER_CTRL_ST;
 
        omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
-       omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 }