drm/amdgpu: correct ras error count type
authorGuchun Chen <guchun.chen@amd.com>
Fri, 16 Aug 2019 07:06:52 +0000 (15:06 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 23 Aug 2019 16:30:32 +0000 (11:30 -0500)
Use unsigned long type for the same ras count variable.
This will avoid overflow on 64 bit system.

Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

index f1f3a6f12b4d8094a31da57e268eed3b99772ce2..6614d8a6f4c8d367dcb8bb281f70514f6a054f22 100644 (file)
@@ -351,7 +351,7 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
 {
        struct amdgpu_ctx *ctx;
        struct amdgpu_ctx_mgr *mgr;
-       uint32_t ras_counter;
+       unsigned long ras_counter;
 
        if (!fpriv)
                return -EINVAL;
index 5f1b54c9bcdb730ede45d17f9ab644e7c42215fa..da808633732b18a1ff3c9eff4ed8ff4c31bcb8ce 100644 (file)
@@ -49,8 +49,8 @@ struct amdgpu_ctx {
        enum drm_sched_priority         override_priority;
        struct mutex                    lock;
        atomic_t                        guilty;
-       uint32_t                        ras_counter_ce;
-       uint32_t                        ras_counter_ue;
+       unsigned long                   ras_counter_ce;
+       unsigned long                   ras_counter_ue;
 };
 
 struct amdgpu_ctx_mgr {
index 76d0021f5dd178d2ec7909cbb319eb2159f7a2c8..016ea274b955cac5ba37418701084faa0c7e41cd 100644 (file)
@@ -688,7 +688,7 @@ int amdgpu_ras_error_cure(struct amdgpu_device *adev,
 }
 
 /* get the total error counts on all IPs */
-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
                bool is_ce)
 {
        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -696,7 +696,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
        struct ras_err_data data = {0, 0};
 
        if (!con)
-               return -EINVAL;
+               return 0;
 
        list_for_each_entry(obj, &con->head, node) {
                struct ras_query_if info = {
@@ -704,7 +704,7 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
                };
 
                if (amdgpu_ras_error_query(adev, &info))
-                       return -EINVAL;
+                       return 0;
 
                data.ce_count += info.ce_count;
                data.ue_count += info.ue_count;
index 2765f2dbb1e63a5367d93c5363df01655a5174d5..02a51e3dfa14cad95f80e0d62ffcfcc77243a604 100644 (file)
@@ -484,7 +484,7 @@ int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
 void amdgpu_ras_resume(struct amdgpu_device *adev);
 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 
-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
                bool is_ce);
 
 /* error handling functions */