ARM: dts: exynos: Use defines for MCT interrupt GIC SPI/PPI specifier
authorKrzysztof Kozlowski <krzk@kernel.org>
Mon, 23 Sep 2019 16:15:20 +0000 (18:15 +0200)
committerKrzysztof Kozlowski <krzk@kernel.org>
Wed, 2 Oct 2019 15:39:57 +0000 (17:39 +0200)
Replace hard-coded number with appropriate define for GIC SPI or PPI
specifier in interrupt.  This makes code easier to read.  No expected
functionality change.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm/boot/dts/exynos4210.dtsi
arch/arm/boot/dts/exynos4412.dtsi
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/boot/dts/exynos54xx.dtsi

index 5fa33d43821e936814d1bbf87f1483146f47a277..aac3b7a20a37d12f26fef14b16667e8b68835c71 100644 (file)
                        reg = <0x10050000 0x800>;
                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
                        clock-names = "fin_pll", "mct";
-                       interrupts-extended = <&gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                                              <&combiner 12 6>,
                                              <&combiner 12 7>,
-                                             <&gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
+                                             <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                watchdog: watchdog@10060000 {
index 9b5fb4e54d7cf9b95cd5feb13fe69be059fd33f2..96a5ef3a28643c38078c3367ec1e456fd03c6581 100644 (file)
                        reg = <0x10050000 0x800>;
                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
                        clock-names = "fin_pll", "mct";
-                       interrupts-extended = <&gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+                       interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                                              <&combiner 12 5>,
                                              <&combiner 12 6>,
                                              <&combiner 12 7>,
-                                             <&gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
+                                             <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                watchdog: watchdog@10060000 {
index bca133c68cf499b86e6981fdf79e901a865d4c08..9e986a5c5bf90cfda6b96336bd273cf2ff048aa5 100644 (file)
                                              <&combiner 23 4>,
                                              <&combiner 25 2>,
                                              <&combiner 25 3>,
-                                             <&gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
+                                             <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                pinctrl_0: pinctrl@11400000 {
index 8a162b5c5bf425dd82afcaf763176832db74bddf..7bea3d2ade61d99ace69285a4a2ae666a058ccab 100644 (file)
                                              <&combiner 23 4>,
                                              <&combiner 25 2>,
                                              <&combiner 25 3>,
-                                             <&gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
-                                             <&gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
+                                             <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
                };
 
                watchdog: watchdog@101d0000 {