--- /dev/null
+From 42541838d9fdbad8573141d69cf8e38831a6cbb6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:40:42 +0000
+Subject: [PATCH] MIPS: pci-ar724x: convert into a platform driver
+
+commit 58d2e9bcd682d76bcb9575dc56c85f1d82a81bfa upstream.
+
+The patch converts the pci-ar724x driver into a
+platform driver. This makes it possible to register
+the PCI controller as a plain platform device.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4905/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c | 57 ++++++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 55 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,6 +11,8 @@
+
+ #include <linux/irq.h>
+ #include <linux/pci.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+@@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_ch
+ .irq_mask_ack = ar724x_pci_irq_mask,
+ };
+
+-static void __init ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(int irq)
+ {
+ void __iomem *base;
+ int i;
+@@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(i
+ irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+
+-int __init ar724x_pcibios_init(int irq)
++int ar724x_pcibios_init(int irq)
+ {
+ int ret;
+
+@@ -312,3 +314,54 @@ err_unmap_devcfg:
+ err:
+ return ret;
+ }
++
++static int ar724x_pci_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ int irq;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
++ if (!res)
++ return -EINVAL;
++
++ ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (ar724x_pci_ctrl_base == NULL)
++ return -EBUSY;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++ if (!res)
++ return -EINVAL;
++
++ ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!ar724x_pci_devcfg_base)
++ return -EBUSY;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return -EINVAL;
++
++ ar724x_pci_link_up = ar724x_pci_check_link();
++ if (!ar724x_pci_link_up)
++ dev_warn(&pdev->dev, "PCIe link is down\n");
++
++ ar724x_pci_irq_init(irq);
++
++ register_pci_controller(&ar724x_pci_controller);
++
++ return 0;
++}
++
++static struct platform_driver ar724x_pci_driver = {
++ .probe = ar724x_pci_probe,
++ .driver = {
++ .name = "ar724x-pci",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init ar724x_pci_init(void)
++{
++ return platform_driver_register(&ar724x_pci_driver);
++}
++
++postcore_initcall(ar724x_pci_init);
--- /dev/null
+From 060c9a226a25e044167e877d9830ec53f836da9e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:40:43 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: convert into a platform driver
+
+commit fb167e891d5cc6386840dd092af2d461b38eb802 upstream.
+
+The patch converts the pci-ar71xx driver into a
+platform driver. This makes it possible to register
+the PCI controller as a plain platform device.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4906/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 60 +++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 56 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -18,6 +18,8 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+ .irq_mask_ack = ar71xx_pci_irq_mask,
+ };
+
+-static __init void ar71xx_pci_irq_init(void)
++static void ar71xx_pci_irq_init(int irq)
+ {
+ void __iomem *base = ath79_reset_base;
+ int i;
+@@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(v
+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ handle_level_irq);
+
+- irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
++ irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
+ }
+
+-static __init void ar71xx_pci_reset(void)
++static void ar71xx_pci_reset(void)
+ {
+ void __iomem *ddr_base = ath79_ddr_base;
+
+@@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void)
+ /* clear bus errors */
+ ar71xx_pci_check_error(1);
+
+- ar71xx_pci_irq_init();
++ ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+
+ register_pci_controller(&ar71xx_pci_controller);
+
+ return 0;
+ }
++
++static int ar71xx_pci_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ int irq;
++ u32 t;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
++ if (!res)
++ return -EINVAL;
++
++ ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!ar71xx_pcicfg_base)
++ return -ENOMEM;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return -EINVAL;
++
++ ar71xx_pci_reset();
++
++ /* setup COMMAND register */
++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
++ ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++
++ /* clear bus errors */
++ ar71xx_pci_check_error(1);
++
++ ar71xx_pci_irq_init(irq);
++
++ register_pci_controller(&ar71xx_pci_controller);
++
++ return 0;
++}
++
++static struct platform_driver ar71xx_pci_driver = {
++ .probe = ar71xx_pci_probe,
++ .driver = {
++ .name = "ar71xx-pci",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init ar71xx_pci_init(void)
++{
++ return platform_driver_register(&ar71xx_pci_driver);
++}
++
++postcore_initcall(ar71xx_pci_init);
--- /dev/null
+From 1dece618b107f5db28c8f63d4d32424dd18324d1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 4 Feb 2013 11:56:53 +0100
+Subject: [PATCH] MIPS: ath79: move global PCI defines into a common header
+
+commit ad4ce92e919f7ad5561a2060deb58899de58b40c upstream.
+
+The constants will be used by a subsequent patch.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4907/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 24 ++++++++++++++++++++++++
+ arch/mips/pci/pci-ar71xx.c | 16 ----------------
+ arch/mips/pci/pci-ar724x.c | 8 --------
+ 3 files changed, 24 insertions(+), 24 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -41,11 +41,35 @@
+ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE 0x100
+
++#define AR71XX_PCI_MEM_BASE 0x10000000
++#define AR71XX_PCI_MEM_SIZE 0x07000000
++
++#define AR71XX_PCI_WIN0_OFFS 0x10000000
++#define AR71XX_PCI_WIN1_OFFS 0x11000000
++#define AR71XX_PCI_WIN2_OFFS 0x12000000
++#define AR71XX_PCI_WIN3_OFFS 0x13000000
++#define AR71XX_PCI_WIN4_OFFS 0x14000000
++#define AR71XX_PCI_WIN5_OFFS 0x15000000
++#define AR71XX_PCI_WIN6_OFFS 0x16000000
++#define AR71XX_PCI_WIN7_OFFS 0x07000000
++
++#define AR71XX_PCI_CFG_BASE \
++ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
++#define AR71XX_PCI_CFG_SIZE 0x100
++
+ #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+ #define AR7240_USB_CTRL_SIZE 0x100
+ #define AR7240_OHCI_BASE 0x1b000000
+ #define AR7240_OHCI_SIZE 0x1000
+
++#define AR724X_PCI_MEM_BASE 0x10000000
++#define AR724X_PCI_MEM_SIZE 0x04000000
++
++#define AR724X_PCI_CFG_BASE 0x14000000
++#define AR724X_PCI_CFG_SIZE 0x1000
++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
++#define AR724X_PCI_CTRL_SIZE 0x100
++
+ #define AR724X_EHCI_BASE 0x1b000000
+ #define AR724X_EHCI_SIZE 0x1000
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -25,22 +25,6 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/pci.h>
+
+-#define AR71XX_PCI_MEM_BASE 0x10000000
+-#define AR71XX_PCI_MEM_SIZE 0x07000000
+-
+-#define AR71XX_PCI_WIN0_OFFS 0x10000000
+-#define AR71XX_PCI_WIN1_OFFS 0x11000000
+-#define AR71XX_PCI_WIN2_OFFS 0x12000000
+-#define AR71XX_PCI_WIN3_OFFS 0x13000000
+-#define AR71XX_PCI_WIN4_OFFS 0x14000000
+-#define AR71XX_PCI_WIN5_OFFS 0x15000000
+-#define AR71XX_PCI_WIN6_OFFS 0x16000000
+-#define AR71XX_PCI_WIN7_OFFS 0x07000000
+-
+-#define AR71XX_PCI_CFG_BASE \
+- (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
+-#define AR71XX_PCI_CFG_SIZE 0x100
+-
+ #define AR71XX_PCI_REG_CRP_AD_CBE 0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA 0x04
+ #define AR71XX_PCI_REG_CRP_RDDATA 0x08
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -17,14 +17,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+
+-#define AR724X_PCI_CFG_BASE 0x14000000
+-#define AR724X_PCI_CFG_SIZE 0x1000
+-#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
+-#define AR724X_PCI_CTRL_SIZE 0x100
+-
+-#define AR724X_PCI_MEM_BASE 0x10000000
+-#define AR724X_PCI_MEM_SIZE 0x04000000
+-
+ #define AR724X_PCI_REG_RESET 0x18
+ #define AR724X_PCI_REG_INT_STATUS 0x4c
+ #define AR724X_PCI_REG_INT_MASK 0x50
--- /dev/null
+From 87cdbe4315e4c72c2bc8568d1258e1207e1c772b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 11:44:24 +0000
+Subject: [PATCH] MIPS: ath79: register platform devices for the PCI
+ controllers
+
+commit 9fc1ca5b73a82daedffa2d1d5daa48dd2093c39a upstream.
+
+The pci-ar71xx and pci-ar724x drivers were converted
+into platform drivers. Register the corresponding
+platform devices for the PCI controllers instead
+of using the ar7{1x,24}x_pcibios_init functions.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4908/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 78 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,8 @@
+
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <linux/resource.h>
++#include <linux/platform_device.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
+ ath79_pci_plat_dev_init = func;
+ }
+
+-int __init ath79_register_pci(void)
++static struct platform_device *
++ath79_register_pci_ar71xx(void)
+ {
+- if (soc_is_ar71xx())
+- return ar71xx_pcibios_init();
++ struct platform_device *pdev;
++ struct resource res[2];
++
++ memset(res, 0, sizeof(res));
+
+- if (soc_is_ar724x())
+- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
++ res[0].name = "cfg_base";
++ res[0].flags = IORESOURCE_MEM;
++ res[0].start = AR71XX_PCI_CFG_BASE;
++ res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
++
++ res[1].flags = IORESOURCE_IRQ;
++ res[1].start = ATH79_CPU_IRQ_IP2;
++ res[1].end = ATH79_CPU_IRQ_IP2;
++
++ pdev = platform_device_register_simple("ar71xx-pci", -1,
++ res, ARRAY_SIZE(res));
++ return pdev;
++}
+
+- if (soc_is_ar9342() || soc_is_ar9344()) {
++static struct platform_device *
++ath79_register_pci_ar724x(int id,
++ unsigned long cfg_base,
++ unsigned long ctrl_base,
++ int irq)
++{
++ struct platform_device *pdev;
++ struct resource res[3];
++
++ memset(res, 0, sizeof(res));
++
++ res[0].name = "cfg_base";
++ res[0].flags = IORESOURCE_MEM;
++ res[0].start = cfg_base;
++ res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
++
++ res[1].name = "ctrl_base";
++ res[1].flags = IORESOURCE_MEM;
++ res[1].start = ctrl_base;
++ res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
++
++ res[2].flags = IORESOURCE_IRQ;
++ res[2].start = irq;
++ res[2].end = irq;
++
++ pdev = platform_device_register_simple("ar724x-pci", id,
++ res, ARRAY_SIZE(res));
++ return pdev;
++}
++
++int __init ath79_register_pci(void)
++{
++ struct platform_device *pdev = NULL;
++
++ if (soc_is_ar71xx()) {
++ pdev = ath79_register_pci_ar71xx();
++ } else if (soc_is_ar724x()) {
++ pdev = ath79_register_pci_ar724x(-1,
++ AR724X_PCI_CFG_BASE,
++ AR724X_PCI_CTRL_BASE,
++ ATH79_CPU_IRQ_IP2);
++ } else if (soc_is_ar9342() ||
++ soc_is_ar9344()) {
+ u32 bootstrap;
+
+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+- if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
+- return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
++ if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
++ return -ENODEV;
++
++ pdev = ath79_register_pci_ar724x(-1,
++ AR724X_PCI_CFG_BASE,
++ AR724X_PCI_CTRL_BASE,
++ ATH79_IP2_IRQ(0));
++ } else {
++ /* No PCI support */
++ return -ENODEV;
+ }
+
+- return -ENODEV;
++ if (!pdev)
++ pr_err("unable to register PCI controller device\n");
++
++ return pdev ? 0 : -ENODEV;
+ }
--- /dev/null
+From db36c9d6a6be232bdee245407fc8ccde53ea69c6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 4 Feb 2013 11:58:49 +0100
+Subject: [PATCH] MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init
+ functions
+
+commit 6e783865b4e60f2ecf7708f8ea24db5c5ea07ced upstream.
+
+The functions are unused now, so remove them.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4909/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c | 1 -
+ arch/mips/include/asm/mach-ath79/pci.h | 28 ----------------------------
+ arch/mips/pci/pci-ar71xx.c | 26 --------------------------
+ arch/mips/pci/pci-ar724x.c | 32 --------------------------------
+ 4 files changed, 87 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -19,7 +19,6 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+-#include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+
+ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ /dev/null
+@@ -1,28 +0,0 @@
+-/*
+- * Atheros AR71XX/AR724X PCI support
+- *
+- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef __ASM_MACH_ATH79_PCI_H
+-#define __ASM_MACH_ATH79_PCI_H
+-
+-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
+-int ar71xx_pcibios_init(void);
+-#else
+-static inline int ar71xx_pcibios_init(void) { return 0; }
+-#endif
+-
+-#if defined(CONFIG_PCI_AR724X)
+-int ar724x_pcibios_init(int irq);
+-#else
+-static inline int ar724x_pcibios_init(int irq) { return 0; }
+-#endif
+-
+-#endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -23,7 +23,6 @@
+
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/pci.h>
+
+ #define AR71XX_PCI_REG_CRP_AD_CBE 0x00
+ #define AR71XX_PCI_REG_CRP_WRDATA 0x04
+@@ -335,31 +334,6 @@ static void ar71xx_pci_reset(void)
+ mdelay(100);
+ }
+
+-__init int ar71xx_pcibios_init(void)
+-{
+- u32 t;
+-
+- ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
+- if (ar71xx_pcicfg_base == NULL)
+- return -ENOMEM;
+-
+- ar71xx_pci_reset();
+-
+- /* setup COMMAND register */
+- t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+- | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+- ar71xx_pci_local_write(PCI_COMMAND, 4, t);
+-
+- /* clear bus errors */
+- ar71xx_pci_check_error(1);
+-
+- ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
+-
+- register_pci_controller(&ar71xx_pci_controller);
+-
+- return 0;
+-}
+-
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+ struct resource *res;
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -15,7 +15,6 @@
+ #include <linux/platform_device.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+-#include <asm/mach-ath79/pci.h>
+
+ #define AR724X_PCI_REG_RESET 0x18
+ #define AR724X_PCI_REG_INT_STATUS 0x4c
+@@ -276,37 +275,6 @@ static void ar724x_pci_irq_init(int irq)
+ irq_set_chained_handler(irq, ar724x_pci_irq_handler);
+ }
+
+-int ar724x_pcibios_init(int irq)
+-{
+- int ret;
+-
+- ret = -ENOMEM;
+-
+- ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
+- AR724X_PCI_CFG_SIZE);
+- if (ar724x_pci_devcfg_base == NULL)
+- goto err;
+-
+- ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
+- AR724X_PCI_CTRL_SIZE);
+- if (ar724x_pci_ctrl_base == NULL)
+- goto err_unmap_devcfg;
+-
+- ar724x_pci_link_up = ar724x_pci_check_link();
+- if (!ar724x_pci_link_up)
+- pr_warn("ar724x: PCIe link is down\n");
+-
+- ar724x_pci_irq_init(irq);
+- register_pci_controller(&ar724x_pci_controller);
+-
+- return PCIBIOS_SUCCESSFUL;
+-
+-err_unmap_devcfg:
+- iounmap(ar724x_pci_devcfg_base);
+-err:
+- return ret;
+-}
+-
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ struct resource *res;
--- /dev/null
+From 4da85831c8eaf2de2cadae6723e8231068c313b7 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 2 Feb 2013 13:18:54 +0000
+Subject: [PATCH] MIPS: avoid possible resource conflict in
+ register_pci_controller
+
+commit 222831787704c9ad9215f6b56f975b233968607c upstream.
+
+The IO and memory resources of a PCI controller
+might already have a parent resource set when
+they are passed to 'register_pci_controller'.
+
+If the parent resource is set, the request_resource
+call will fail due to resource conflict and the
+current code will not be able to register the
+PCI controller.
+
+Use the parent resource if it is available in the
+request_resource call to avoid the isssue.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4910/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci.c | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci.c
++++ b/arch/mips/pci/pci.c
+@@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex);
+
+ void register_pci_controller(struct pci_controller *hose)
+ {
+- if (request_resource(&iomem_resource, hose->mem_resource) < 0)
++ struct resource *parent;
++
++ parent = hose->mem_resource->parent;
++ if (!parent)
++ parent = &iomem_resource;
++
++ if (request_resource(parent, hose->mem_resource) < 0)
+ goto out;
+- if (request_resource(&ioport_resource, hose->io_resource) < 0) {
++
++ parent = hose->io_resource->parent;
++ if (!parent)
++ parent = &ioport_resource;
++
++ if (request_resource(parent, hose->io_resource) < 0) {
+ release_resource(hose->mem_resource);
+ goto out;
+ }
--- /dev/null
+From 53ba4919664636487155c810fb49781169780e0c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:58:37 +0000
+Subject: [PATCH] MIPS: ath79: allow to specify bus number in PCI IRQ maps
+
+commit 617fed41e98417f3ea3e9974be251e125c8796f2 upstream.
+
+This is needed for multiple PCI bus support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4913/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c | 4 +++-
+ arch/mips/ath79/pci.h | 1 +
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct
+ const struct ath79_pci_irq *entry;
+
+ entry = &ath79_pci_irq_map[i];
+- if (entry->slot == slot && entry->pin == pin) {
++ if (entry->bus == dev->bus->number &&
++ entry->slot == slot &&
++ entry->pin == pin) {
+ irq = entry->irq;
+ break;
+ }
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -14,6 +14,7 @@
+ #define _ATH79_PCI_H
+
+ struct ath79_pci_irq {
++ int bus;
+ u8 slot;
+ u8 pin;
+ int irq;
--- /dev/null
+From 21b3cafae425cf2e317a22292a9a5773ff0e2e5e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:58:38 +0000
+Subject: [PATCH] MIPS: pci-ar724x: use dynamically allocated PCI controller
+ structure
+
+commit 908339ef25b1d5e80f1c6fab22b9958174708b4a upstream.
+
+The current code uses static variables to store the
+PCI controller specific data. This works if the system
+contains one PCI controller only, however it becomes
+impractical when multiple PCI controllers are present.
+
+Move the variables into a dynamically allocated controller
+specific structure, and use that instead of the static
+variables.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4912/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c | 129 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 82 insertions(+), 47 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -9,6 +9,7 @@
+ * by the Free Software Foundation.
+ */
+
++#include <linux/spinlock.h>
+ #include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <linux/module.h>
+@@ -28,38 +29,56 @@
+
+ #define AR7240_BAR0_WAR_VALUE 0xffff
+
+-static DEFINE_SPINLOCK(ar724x_pci_lock);
+-static void __iomem *ar724x_pci_devcfg_base;
+-static void __iomem *ar724x_pci_ctrl_base;
+-
+-static u32 ar724x_pci_bar0_value;
+-static bool ar724x_pci_bar0_is_cached;
+-static bool ar724x_pci_link_up;
++struct ar724x_pci_controller {
++ void __iomem *devcfg_base;
++ void __iomem *ctrl_base;
+
+-static inline bool ar724x_pci_check_link(void)
++ int irq;
++
++ bool link_up;
++ bool bar0_is_cached;
++ u32 bar0_value;
++
++ spinlock_t lock;
++
++ struct pci_controller pci_controller;
++};
++
++static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+ u32 reset;
+
+- reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
++ reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
+ return reset & AR724X_PCI_RESET_LINK_UP;
+ }
+
++static inline struct ar724x_pci_controller *
++pci_bus_to_ar724x_controller(struct pci_bus *bus)
++{
++ struct pci_controller *hose;
++
++ hose = (struct pci_controller *) bus->sysdata;
++ return container_of(hose, struct ar724x_pci_controller, pci_controller);
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+ {
++ struct ar724x_pci_controller *apc;
+ unsigned long flags;
+ void __iomem *base;
+ u32 data;
+
+- if (!ar724x_pci_link_up)
++ apc = pci_bus_to_ar724x_controller(bus);
++ if (!apc->link_up)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- base = ar724x_pci_devcfg_base;
++ base = apc->devcfg_base;
+
+- spin_lock_irqsave(&ar724x_pci_lock, flags);
++ spin_lock_irqsave(&apc->lock, flags);
+ data = __raw_readl(base + (where & ~3));
+
+ switch (size) {
+@@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bu
+ case 4:
+ break;
+ default:
+- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++ spin_unlock_irqrestore(&apc->lock, flags);
+
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
+- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++ spin_unlock_irqrestore(&apc->lock, flags);
+
+ if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
+- ar724x_pci_bar0_is_cached) {
++ apc->bar0_is_cached) {
+ /* use the cached value */
+- *value = ar724x_pci_bar0_value;
++ *value = apc->bar0_value;
+ } else {
+ *value = data;
+ }
+@@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bu
+ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t value)
+ {
++ struct ar724x_pci_controller *apc;
+ unsigned long flags;
+ void __iomem *base;
+ u32 data;
+ int s;
+
+- if (!ar724x_pci_link_up)
++ apc = pci_bus_to_ar724x_controller(bus);
++ if (!apc->link_up)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (devfn)
+@@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_b
+ * BAR0 register in order to make the device memory
+ * accessible.
+ */
+- ar724x_pci_bar0_is_cached = true;
+- ar724x_pci_bar0_value = value;
++ apc->bar0_is_cached = true;
++ apc->bar0_value = value;
+
+ value = AR7240_BAR0_WAR_VALUE;
+ } else {
+- ar724x_pci_bar0_is_cached = false;
++ apc->bar0_is_cached = false;
+ }
+ }
+
+- base = ar724x_pci_devcfg_base;
++ base = apc->devcfg_base;
+
+- spin_lock_irqsave(&ar724x_pci_lock, flags);
++ spin_lock_irqsave(&apc->lock, flags);
+ data = __raw_readl(base + (where & ~3));
+
+ switch (size) {
+@@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_b
+ data = value;
+ break;
+ default:
+- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++ spin_unlock_irqrestore(&apc->lock, flags);
+
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+@@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_b
+ __raw_writel(data, base + (where & ~3));
+ /* flush write */
+ __raw_readl(base + (where & ~3));
+- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++ spin_unlock_irqrestore(&apc->lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+ }
+@@ -183,18 +204,14 @@ static struct resource ar724x_mem_resour
+ .flags = IORESOURCE_MEM,
+ };
+
+-static struct pci_controller ar724x_pci_controller = {
+- .pci_ops = &ar724x_pci_ops,
+- .io_resource = &ar724x_io_resource,
+- .mem_resource = &ar724x_mem_resource,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+ u32 pending;
+
+- base = ar724x_pci_ctrl_base;
++ apc = irq_get_handler_data(irq);
++ base = apc->ctrl_base;
+
+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+@@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsig
+
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
++ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+ u32 t;
+
+- base = ar724x_pci_ctrl_base;
++ apc = irq_data_get_irq_chip_data(d);
++ base = apc->ctrl_base;
+
+ switch (d->irq) {
+ case ATH79_PCI_IRQ(0):
+@@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct
+
+ static void ar724x_pci_irq_mask(struct irq_data *d)
+ {
++ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+ u32 t;
+
+- base = ar724x_pci_ctrl_base;
++ apc = irq_data_get_irq_chip_data(d);
++ base = apc->ctrl_base;
+
+ switch (d->irq) {
+ case ATH79_PCI_IRQ(0):
+@@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_ch
+ .irq_mask_ack = ar724x_pci_irq_mask,
+ };
+
+-static void ar724x_pci_irq_init(int irq)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
+ {
+ void __iomem *base;
+ int i;
+
+- base = ar724x_pci_ctrl_base;
++ base = apc->ctrl_base;
+
+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+@@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq)
+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
+
+ for (i = ATH79_PCI_IRQ_BASE;
+- i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
++ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+ handle_level_irq);
++ irq_set_chip_data(i, apc);
++ }
+
+- irq_set_chained_handler(irq, ar724x_pci_irq_handler);
++ irq_set_handler_data(apc->irq, apc);
++ irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
+ }
+
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
++ struct ar724x_pci_controller *apc;
+ struct resource *res;
+- int irq;
++
++ apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
++ GFP_KERNEL);
++ if (!apc)
++ return -ENOMEM;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
+ if (!res)
+ return -EINVAL;
+
+- ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
+- if (ar724x_pci_ctrl_base == NULL)
++ apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (apc->ctrl_base == NULL)
+ return -EBUSY;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+ if (!res)
+ return -EINVAL;
+
+- ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
+- if (!ar724x_pci_devcfg_base)
++ apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!apc->devcfg_base)
+ return -EBUSY;
+
+- irq = platform_get_irq(pdev, 0);
+- if (irq < 0)
++ apc->irq = platform_get_irq(pdev, 0);
++ if (apc->irq < 0)
+ return -EINVAL;
+
+- ar724x_pci_link_up = ar724x_pci_check_link();
+- if (!ar724x_pci_link_up)
++ spin_lock_init(&apc->lock);
++
++ apc->pci_controller.pci_ops = &ar724x_pci_ops;
++ apc->pci_controller.io_resource = &ar724x_io_resource;
++ apc->pci_controller.mem_resource = &ar724x_mem_resource;
++
++ apc->link_up = ar724x_pci_check_link(apc);
++ if (!apc->link_up)
+ dev_warn(&pdev->dev, "PCIe link is down\n");
+
+- ar724x_pci_irq_init(irq);
++ ar724x_pci_irq_init(apc);
+
+- register_pci_controller(&ar724x_pci_controller);
++ register_pci_controller(&apc->pci_controller);
+
+ return 0;
+ }
--- /dev/null
+From d80b05d19c2772ded40403d578d8e90d38c85257 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 09:59:45 +0000
+Subject: [PATCH] MIPS: pci-ar724x: remove static PCI IO/MEM resources
+
+commit 34b134aebda89888b6985b7a3139e9cbdf209236 upstream.
+
+Static resources become impractical when multiple
+PCI controllers are present. Move the resources
+into the platform device registration code and
+change the probe routine to get those from there
+platform device's resources.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4914/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c | 21 ++++++++++++++++++++-
+ arch/mips/pci/pci-ar724x.c | 40 ++++++++++++++++++++++++----------------
+ 2 files changed, 44 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -139,10 +139,13 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+ unsigned long cfg_base,
+ unsigned long ctrl_base,
++ unsigned long mem_base,
++ unsigned long mem_size,
++ unsigned long io_base,
+ int irq)
+ {
+ struct platform_device *pdev;
+- struct resource res[3];
++ struct resource res[5];
+
+ memset(res, 0, sizeof(res));
+
+@@ -160,6 +163,16 @@ ath79_register_pci_ar724x(int id,
+ res[2].start = irq;
+ res[2].end = irq;
+
++ res[3].name = "mem_base";
++ res[3].flags = IORESOURCE_MEM;
++ res[3].start = mem_base;
++ res[3].end = mem_base + mem_size - 1;
++
++ res[4].name = "io_base";
++ res[4].flags = IORESOURCE_IO;
++ res[4].start = io_base;
++ res[4].end = io_base;
++
+ pdev = platform_device_register_simple("ar724x-pci", id,
+ res, ARRAY_SIZE(res));
+ return pdev;
+@@ -175,6 +188,9 @@ int __init ath79_register_pci(void)
+ pdev = ath79_register_pci_ar724x(-1,
+ AR724X_PCI_CFG_BASE,
+ AR724X_PCI_CTRL_BASE,
++ AR724X_PCI_MEM_BASE,
++ AR724X_PCI_MEM_SIZE,
++ 0,
+ ATH79_CPU_IRQ_IP2);
+ } else if (soc_is_ar9342() ||
+ soc_is_ar9344()) {
+@@ -187,6 +203,9 @@ int __init ath79_register_pci(void)
+ pdev = ath79_register_pci_ar724x(-1,
+ AR724X_PCI_CFG_BASE,
+ AR724X_PCI_CTRL_BASE,
++ AR724X_PCI_MEM_BASE,
++ AR724X_PCI_MEM_SIZE,
++ 0,
+ ATH79_IP2_IRQ(0));
+ } else {
+ /* No PCI support */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -42,6 +42,8 @@ struct ar724x_pci_controller {
+ spinlock_t lock;
+
+ struct pci_controller pci_controller;
++ struct resource io_res;
++ struct resource mem_res;
+ };
+
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+@@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = {
+ .write = ar724x_pci_write,
+ };
+
+-static struct resource ar724x_io_resource = {
+- .name = "PCI IO space",
+- .start = 0,
+- .end = 0,
+- .flags = IORESOURCE_IO,
+-};
+-
+-static struct resource ar724x_mem_resource = {
+- .name = "PCI memory space",
+- .start = AR724X_PCI_MEM_BASE,
+- .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+-};
+-
+ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ struct ar724x_pci_controller *apc;
+@@ -331,9 +319,29 @@ static int ar724x_pci_probe(struct platf
+
+ spin_lock_init(&apc->lock);
+
++ res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++ if (!res)
++ return -EINVAL;
++
++ apc->io_res.parent = res;
++ apc->io_res.name = "PCI IO space";
++ apc->io_res.start = res->start;
++ apc->io_res.end = res->end;
++ apc->io_res.flags = IORESOURCE_IO;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++ if (!res)
++ return -EINVAL;
++
++ apc->mem_res.parent = res;
++ apc->mem_res.name = "PCI memory space";
++ apc->mem_res.start = res->start;
++ apc->mem_res.end = res->end;
++ apc->mem_res.flags = IORESOURCE_MEM;
++
+ apc->pci_controller.pci_ops = &ar724x_pci_ops;
+- apc->pci_controller.io_resource = &ar724x_io_resource;
+- apc->pci_controller.mem_resource = &ar724x_mem_resource;
++ apc->pci_controller.io_resource = &apc->io_res;
++ apc->pci_controller.mem_resource = &apc->mem_res;
+
+ apc->link_up = ar724x_pci_check_link(apc);
+ if (!apc->link_up)
--- /dev/null
+From d85015ff3ab6df0e776c2aefc51f2da023c1edcf Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 10:00:16 +0000
+Subject: [PATCH] MIPS: pci-ar724x: use per-controller IRQ base
+
+commit 8b66d461187ff61c5755001af7296e6edde48423 upstream.
+
+Change to the code to use per-controller IRQ base.
+This is needed for multiple PCI controller support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4915/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar724x.c | 31 +++++++++++++++++++++----------
+ 1 file changed, 21 insertions(+), 10 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -34,6 +34,7 @@ struct ar724x_pci_controller {
+ void __iomem *ctrl_base;
+
+ int irq;
++ int irq_base;
+
+ bool link_up;
+ bool bar0_is_cached;
+@@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig
+ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+
+ if (pending & AR724X_PCI_INT_DEV0)
+- generic_handle_irq(ATH79_PCI_IRQ(0));
++ generic_handle_irq(apc->irq_base + 0);
+
+ else
+ spurious_interrupt();
+@@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct
+ {
+ struct ar724x_pci_controller *apc;
+ void __iomem *base;
++ int offset;
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+ base = apc->ctrl_base;
++ offset = apc->irq_base - d->irq;
+
+- switch (d->irq) {
+- case ATH79_PCI_IRQ(0):
++ switch (offset) {
++ case 0:
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(t | AR724X_PCI_INT_DEV0,
+ base + AR724X_PCI_REG_INT_MASK);
+@@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i
+ {
+ struct ar724x_pci_controller *apc;
+ void __iomem *base;
++ int offset;
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+ base = apc->ctrl_base;
++ offset = apc->irq_base - d->irq;
+
+- switch (d->irq) {
+- case ATH79_PCI_IRQ(0):
++ switch (offset) {
++ case 0:
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
+ base + AR724X_PCI_REG_INT_MASK);
+@@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch
+ .irq_mask_ack = ar724x_pci_irq_mask,
+ };
+
+-static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
++static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
++ int id)
+ {
+ void __iomem *base;
+ int i;
+@@ -274,10 +280,10 @@ static void ar724x_pci_irq_init(struct a
+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+
+- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
++ apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+
+- for (i = ATH79_PCI_IRQ_BASE;
+- i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
++ for (i = apc->irq_base;
++ i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(i, apc);
+@@ -291,6 +297,11 @@ static int ar724x_pci_probe(struct platf
+ {
+ struct ar724x_pci_controller *apc;
+ struct resource *res;
++ int id;
++
++ id = pdev->id;
++ if (id == -1)
++ id = 0;
+
+ apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
+ GFP_KERNEL);
+@@ -347,7 +358,7 @@ static int ar724x_pci_probe(struct platf
+ if (!apc->link_up)
+ dev_warn(&pdev->dev, "PCIe link is down\n");
+
+- ar724x_pci_irq_init(apc);
++ ar724x_pci_irq_init(apc, id);
+
+ register_pci_controller(&apc->pci_controller);
+
--- /dev/null
+From 5e079d9b7ac5dda3be9f215f8440333597f57b26 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 3 Feb 2013 14:52:47 +0000
+Subject: [PATCH] MIPS: pci-ar724x: setup command register of the PCI
+ controller
+
+commit 12401fc28d40aa5bf8bda6991a96b6d7a3dae3ac upstream.
+
+The command register of the PCI controller is
+not initialized correctly by the bootloader on
+some boards and this leads to non working PCI
+bus.
+
+Add code to initialize the command register
+from the Linux code to avoid this.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4916/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c | 10 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +
+ arch/mips/pci/pci-ar724x.c | 63 ++++++++++++++++++++++++
+ 3 files changed, 74 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -139,13 +139,14 @@ static struct platform_device *
+ ath79_register_pci_ar724x(int id,
+ unsigned long cfg_base,
+ unsigned long ctrl_base,
++ unsigned long crp_base,
+ unsigned long mem_base,
+ unsigned long mem_size,
+ unsigned long io_base,
+ int irq)
+ {
+ struct platform_device *pdev;
+- struct resource res[5];
++ struct resource res[6];
+
+ memset(res, 0, sizeof(res));
+
+@@ -173,6 +174,11 @@ ath79_register_pci_ar724x(int id,
+ res[4].start = io_base;
+ res[4].end = io_base;
+
++ res[5].name = "crp_base";
++ res[5].flags = IORESOURCE_MEM;
++ res[5].start = crp_base;
++ res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
++
+ pdev = platform_device_register_simple("ar724x-pci", id,
+ res, ARRAY_SIZE(res));
+ return pdev;
+@@ -188,6 +194,7 @@ int __init ath79_register_pci(void)
+ pdev = ath79_register_pci_ar724x(-1,
+ AR724X_PCI_CFG_BASE,
+ AR724X_PCI_CTRL_BASE,
++ AR724X_PCI_CRP_BASE,
+ AR724X_PCI_MEM_BASE,
+ AR724X_PCI_MEM_SIZE,
+ 0,
+@@ -203,6 +210,7 @@ int __init ath79_register_pci(void)
+ pdev = ath79_register_pci_ar724x(-1,
+ AR724X_PCI_CFG_BASE,
+ AR724X_PCI_CTRL_BASE,
++ AR724X_PCI_CRP_BASE,
+ AR724X_PCI_MEM_BASE,
+ AR724X_PCI_MEM_SIZE,
+ 0,
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -67,6 +67,8 @@
+
+ #define AR724X_PCI_CFG_BASE 0x14000000
+ #define AR724X_PCI_CFG_SIZE 0x1000
++#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
++#define AR724X_PCI_CRP_SIZE 0x1000
+ #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
+ #define AR724X_PCI_CTRL_SIZE 0x100
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -29,9 +29,17 @@
+
+ #define AR7240_BAR0_WAR_VALUE 0xffff
+
++#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
++ PCI_COMMAND_MASTER | \
++ PCI_COMMAND_INVALIDATE | \
++ PCI_COMMAND_PARITY | \
++ PCI_COMMAND_SERR | \
++ PCI_COMMAND_FAST_BACK)
++
+ struct ar724x_pci_controller {
+ void __iomem *devcfg_base;
+ void __iomem *ctrl_base;
++ void __iomem *crp_base;
+
+ int irq;
+ int irq_base;
+@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
+ return container_of(hose, struct ar724x_pci_controller, pci_controller);
+ }
+
++static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
++ int where, int size, u32 value)
++{
++ unsigned long flags;
++ void __iomem *base;
++ u32 data;
++ int s;
++
++ WARN_ON(where & (size - 1));
++
++ if (!apc->link_up)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ base = apc->crp_base;
++
++ spin_lock_irqsave(&apc->lock, flags);
++ data = __raw_readl(base + (where & ~3));
++
++ switch (size) {
++ case 1:
++ s = ((where & 3) * 8);
++ data &= ~(0xff << s);
++ data |= ((value & 0xff) << s);
++ break;
++ case 2:
++ s = ((where & 2) * 8);
++ data &= ~(0xffff << s);
++ data |= ((value & 0xffff) << s);
++ break;
++ case 4:
++ data = value;
++ break;
++ default:
++ spin_unlock_irqrestore(&apc->lock, flags);
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ __raw_writel(data, base + (where & ~3));
++ /* flush write */
++ __raw_readl(base + (where & ~3));
++ spin_unlock_irqrestore(&apc->lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+ {
+@@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
+ if (!apc->devcfg_base)
+ return -EBUSY;
+
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
++ if (!res)
++ return -EINVAL;
++
++ apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (apc->crp_base == NULL)
++ return -EBUSY;
++
+ apc->irq = platform_get_irq(pdev, 0);
+ if (apc->irq < 0)
+ return -EINVAL;
+@@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
+
+ ar724x_pci_irq_init(apc, id);
+
++ ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
++
+ register_pci_controller(&apc->pci_controller);
+
+ return 0;
--- /dev/null
+From 0f0f7d810226c734141a20de85289dbb0dda8f96 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:28:14 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: use dynamically allocated PCI controller
+ structure
+
+commit f18118a868f1f7e7bdfea176a204fcc44fae2985 upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4926/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 84 ++++++++++++++++++++++++++++----------------
+ 1 file changed, 53 insertions(+), 31 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -48,8 +48,12 @@
+
+ #define AR71XX_PCI_IRQ_COUNT 5
+
+-static DEFINE_SPINLOCK(ar71xx_pci_lock);
+-static void __iomem *ar71xx_pcicfg_base;
++struct ar71xx_pci_controller {
++ void __iomem *cfg_base;
++ spinlock_t lock;
++ int irq;
++ struct pci_controller pci_ctrl;
++};
+
+ /* Byte lane enable bits */
+ static const u8 ar71xx_pci_ble_table[4][4] = {
+@@ -92,9 +96,18 @@ static inline u32 ar71xx_pci_bus_addr(st
+ return ret;
+ }
+
+-static int ar71xx_pci_check_error(int quiet)
++static inline struct ar71xx_pci_controller *
++pci_bus_to_ar71xx_controller(struct pci_bus *bus)
+ {
+- void __iomem *base = ar71xx_pcicfg_base;
++ struct pci_controller *hose;
++
++ hose = (struct pci_controller *) bus->sysdata;
++ return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
++}
++
++static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
++{
++ void __iomem *base = apc->cfg_base;
+ u32 pci_err;
+ u32 ahb_err;
+
+@@ -129,9 +142,10 @@ static int ar71xx_pci_check_error(int qu
+ return !!(ahb_err | pci_err);
+ }
+
+-static inline void ar71xx_pci_local_write(int where, int size, u32 value)
++static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
++ int where, int size, u32 value)
+ {
+- void __iomem *base = ar71xx_pcicfg_base;
++ void __iomem *base = apc->cfg_base;
+ u32 ad_cbe;
+
+ value = value << (8 * (where & 3));
+@@ -147,7 +161,8 @@ static inline int ar71xx_pci_set_cfgaddr
+ unsigned int devfn,
+ int where, int size, u32 cmd)
+ {
+- void __iomem *base = ar71xx_pcicfg_base;
++ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++ void __iomem *base = apc->cfg_base;
+ u32 addr;
+
+ addr = ar71xx_pci_bus_addr(bus, devfn, where);
+@@ -156,13 +171,14 @@ static inline int ar71xx_pci_set_cfgaddr
+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
+ base + AR71XX_PCI_REG_CFG_CBE);
+
+- return ar71xx_pci_check_error(1);
++ return ar71xx_pci_check_error(apc, 1);
+ }
+
+ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *value)
+ {
+- void __iomem *base = ar71xx_pcicfg_base;
++ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++ void __iomem *base = apc->cfg_base;
+ unsigned long flags;
+ u32 data;
+ int err;
+@@ -171,7 +187,7 @@ static int ar71xx_pci_read_config(struct
+ ret = PCIBIOS_SUCCESSFUL;
+ data = ~0;
+
+- spin_lock_irqsave(&ar71xx_pci_lock, flags);
++ spin_lock_irqsave(&apc->lock, flags);
+
+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+ AR71XX_PCI_CFG_CMD_READ);
+@@ -180,7 +196,7 @@ static int ar71xx_pci_read_config(struct
+ else
+ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
+
+- spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++ spin_unlock_irqrestore(&apc->lock, flags);
+
+ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
+
+@@ -190,7 +206,8 @@ static int ar71xx_pci_read_config(struct
+ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 value)
+ {
+- void __iomem *base = ar71xx_pcicfg_base;
++ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
++ void __iomem *base = apc->cfg_base;
+ unsigned long flags;
+ int err;
+ int ret;
+@@ -198,7 +215,7 @@ static int ar71xx_pci_write_config(struc
+ value = value << (8 * (where & 3));
+ ret = PCIBIOS_SUCCESSFUL;
+
+- spin_lock_irqsave(&ar71xx_pci_lock, flags);
++ spin_lock_irqsave(&apc->lock, flags);
+
+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
+ AR71XX_PCI_CFG_CMD_WRITE);
+@@ -207,7 +224,7 @@ static int ar71xx_pci_write_config(struc
+ else
+ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
+
+- spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++ spin_unlock_irqrestore(&apc->lock, flags);
+
+ return ret;
+ }
+@@ -231,12 +248,6 @@ static struct resource ar71xx_pci_mem_re
+ .flags = IORESOURCE_MEM
+ };
+
+-static struct pci_controller ar71xx_pci_controller = {
+- .pci_ops = &ar71xx_pci_ops,
+- .mem_resource = &ar71xx_pci_mem_resource,
+- .io_resource = &ar71xx_pci_io_resource,
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ void __iomem *base = ath79_reset_base;
+@@ -294,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_ch
+ .irq_mask_ack = ar71xx_pci_irq_mask,
+ };
+
+-static void ar71xx_pci_irq_init(int irq)
++static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+ void __iomem *base = ath79_reset_base;
+ int i;
+@@ -309,7 +320,7 @@ static void ar71xx_pci_irq_init(int irq)
+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ handle_level_irq);
+
+- irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
++ irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+
+ static void ar71xx_pci_reset(void)
+@@ -336,20 +347,27 @@ static void ar71xx_pci_reset(void)
+
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
++ struct ar71xx_pci_controller *apc;
+ struct resource *res;
+- int irq;
+ u32 t;
+
++ apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
++ GFP_KERNEL);
++ if (!apc)
++ return -ENOMEM;
++
++ spin_lock_init(&apc->lock);
++
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
+ if (!res)
+ return -EINVAL;
+
+- ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
+- if (!ar71xx_pcicfg_base)
++ apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!apc->cfg_base)
+ return -ENOMEM;
+
+- irq = platform_get_irq(pdev, 0);
+- if (irq < 0)
++ apc->irq = platform_get_irq(pdev, 0);
++ if (apc->irq < 0)
+ return -EINVAL;
+
+ ar71xx_pci_reset();
+@@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platf
+ /* setup COMMAND register */
+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
+- ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++ ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
+
+ /* clear bus errors */
+- ar71xx_pci_check_error(1);
++ ar71xx_pci_check_error(apc, 1);
++
++ ar71xx_pci_irq_init(apc);
+
+- ar71xx_pci_irq_init(irq);
++ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
++ apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
++ apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
+
+- register_pci_controller(&ar71xx_pci_controller);
++ register_pci_controller(&apc->pci_ctrl);
+
+ return 0;
+ }
--- /dev/null
+From f073cb029873ed487e14784d3682b6aa25afe997 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:28:15 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: remove static PCI IO/MEM resources
+
+commit 42cb60d1fab4c81ef24876d985e08fc5bb899e41 upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4927/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ath79/pci.c | 12 +++++++++++-
+ arch/mips/pci/pci-ar71xx.c | 40 ++++++++++++++++++++++++----------------
+ 2 files changed, 35 insertions(+), 17 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -117,7 +117,7 @@ static struct platform_device *
+ ath79_register_pci_ar71xx(void)
+ {
+ struct platform_device *pdev;
+- struct resource res[2];
++ struct resource res[4];
+
+ memset(res, 0, sizeof(res));
+
+@@ -130,6 +130,16 @@ ath79_register_pci_ar71xx(void)
+ res[1].start = ATH79_CPU_IRQ_IP2;
+ res[1].end = ATH79_CPU_IRQ_IP2;
+
++ res[2].name = "io_base";
++ res[2].flags = IORESOURCE_IO;
++ res[2].start = 0;
++ res[2].end = 0;
++
++ res[3].name = "mem_base";
++ res[3].flags = IORESOURCE_MEM;
++ res[3].start = AR71XX_PCI_MEM_BASE;
++ res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
++
+ pdev = platform_device_register_simple("ar71xx-pci", -1,
+ res, ARRAY_SIZE(res));
+ return pdev;
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -53,6 +53,8 @@ struct ar71xx_pci_controller {
+ spinlock_t lock;
+ int irq;
+ struct pci_controller pci_ctrl;
++ struct resource io_res;
++ struct resource mem_res;
+ };
+
+ /* Byte lane enable bits */
+@@ -234,20 +236,6 @@ static struct pci_ops ar71xx_pci_ops = {
+ .write = ar71xx_pci_write_config,
+ };
+
+-static struct resource ar71xx_pci_io_resource = {
+- .name = "PCI IO space",
+- .start = 0,
+- .end = 0,
+- .flags = IORESOURCE_IO,
+-};
+-
+-static struct resource ar71xx_pci_mem_resource = {
+- .name = "PCI memory space",
+- .start = AR71XX_PCI_MEM_BASE,
+- .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
+- .flags = IORESOURCE_MEM
+-};
+-
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+ void __iomem *base = ath79_reset_base;
+@@ -370,6 +358,26 @@ static int ar71xx_pci_probe(struct platf
+ if (apc->irq < 0)
+ return -EINVAL;
+
++ res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
++ if (!res)
++ return -EINVAL;
++
++ apc->io_res.parent = res;
++ apc->io_res.name = "PCI IO space";
++ apc->io_res.start = res->start;
++ apc->io_res.end = res->end;
++ apc->io_res.flags = IORESOURCE_IO;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
++ if (!res)
++ return -EINVAL;
++
++ apc->mem_res.parent = res;
++ apc->mem_res.name = "PCI memory space";
++ apc->mem_res.start = res->start;
++ apc->mem_res.end = res->end;
++ apc->mem_res.flags = IORESOURCE_MEM;
++
+ ar71xx_pci_reset();
+
+ /* setup COMMAND register */
+@@ -383,8 +391,8 @@ static int ar71xx_pci_probe(struct platf
+ ar71xx_pci_irq_init(apc);
+
+ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+- apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
+- apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
++ apc->pci_ctrl.mem_resource = &apc->mem_res;
++ apc->pci_ctrl.io_resource = &apc->io_res;
+
+ register_pci_controller(&apc->pci_ctrl);
+
--- /dev/null
+From bec8339e917651e51592dd57ed005f8ccd9b0e8d Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 7 Feb 2013 19:29:38 +0000
+Subject: [PATCH] MIPS: pci-ar71xx: move irq base to the controller structure
+
+commit 326e8d17d73fdf213f6334917ef46b2ba7b1354a upstream.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/4928/
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 32 ++++++++++++++++++++++++--------
+ 1 file changed, 24 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -52,6 +52,7 @@ struct ar71xx_pci_controller {
+ void __iomem *cfg_base;
+ spinlock_t lock;
+ int irq;
++ int irq_base;
+ struct pci_controller pci_ctrl;
+ struct resource io_res;
+ struct resource mem_res;
+@@ -238,23 +239,26 @@ static struct pci_ops ar71xx_pci_ops = {
+
+ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
++ struct ar71xx_pci_controller *apc;
+ void __iomem *base = ath79_reset_base;
+ u32 pending;
+
++ apc = irq_get_handler_data(irq);
++
+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+ if (pending & AR71XX_PCI_INT_DEV0)
+- generic_handle_irq(ATH79_PCI_IRQ(0));
++ generic_handle_irq(apc->irq_base + 0);
+
+ else if (pending & AR71XX_PCI_INT_DEV1)
+- generic_handle_irq(ATH79_PCI_IRQ(1));
++ generic_handle_irq(apc->irq_base + 1);
+
+ else if (pending & AR71XX_PCI_INT_DEV2)
+- generic_handle_irq(ATH79_PCI_IRQ(2));
++ generic_handle_irq(apc->irq_base + 2);
+
+ else if (pending & AR71XX_PCI_INT_CORE)
+- generic_handle_irq(ATH79_PCI_IRQ(4));
++ generic_handle_irq(apc->irq_base + 4);
+
+ else
+ spurious_interrupt();
+@@ -262,10 +266,14 @@ static void ar71xx_pci_irq_handler(unsig
+
+ static void ar71xx_pci_irq_unmask(struct irq_data *d)
+ {
+- unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++ struct ar71xx_pci_controller *apc;
++ unsigned int irq;
+ void __iomem *base = ath79_reset_base;
+ u32 t;
+
++ apc = irq_data_get_irq_chip_data(d);
++ irq = d->irq - apc->irq_base;
++
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+@@ -275,10 +283,14 @@ static void ar71xx_pci_irq_unmask(struct
+
+ static void ar71xx_pci_irq_mask(struct irq_data *d)
+ {
+- unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++ struct ar71xx_pci_controller *apc;
++ unsigned int irq;
+ void __iomem *base = ath79_reset_base;
+ u32 t;
+
++ apc = irq_data_get_irq_chip_data(d);
++ irq = d->irq - apc->irq_base;
++
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+@@ -303,11 +315,15 @@ static void ar71xx_pci_irq_init(struct a
+
+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
+
+- for (i = ATH79_PCI_IRQ_BASE;
+- i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
++ apc->irq_base = ATH79_PCI_IRQ_BASE;
++ for (i = apc->irq_base;
++ i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+ handle_level_irq);
++ irq_set_chip_data(i, apc);
++ }
+
++ irq_set_handler_data(apc->irq, apc);
+ irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
+ }
+
+++ /dev/null
-From f2d2d928c3900b67a5f95e53b86de5b61a3ab12c Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 11 Jun 2012 13:19:44 +0200
-Subject: [PATCH 04/34] MIPS: pci-ar724x: convert to a platform driver
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci-ar724x.c | 57 ++++++++++++++++++++++++++++++++++++++++++-
- 1 files changed, 55 insertions(+), 2 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -11,6 +11,8 @@
-
- #include <linux/irq.h>
- #include <linux/pci.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/pci.h>
-@@ -262,7 +264,7 @@ static struct irq_chip ar724x_pci_irq_ch
- .irq_mask_ack = ar724x_pci_irq_mask,
- };
-
--static void __init ar724x_pci_irq_init(int irq)
-+static void ar724x_pci_irq_init(int irq)
- {
- void __iomem *base;
- int i;
-@@ -282,7 +284,7 @@ static void __init ar724x_pci_irq_init(i
- irq_set_chained_handler(irq, ar724x_pci_irq_handler);
- }
-
--int __init ar724x_pcibios_init(int irq)
-+int ar724x_pcibios_init(int irq)
- {
- int ret;
-
-@@ -312,3 +314,54 @@ err_unmap_devcfg:
- err:
- return ret;
- }
-+
-+static int ar724x_pci_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ int irq;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
-+ if (!res)
-+ return -EINVAL;
-+
-+ ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (ar724x_pci_ctrl_base == NULL)
-+ return -EBUSY;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
-+ if (!res)
-+ return -EINVAL;
-+
-+ ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!ar724x_pci_devcfg_base)
-+ return -EBUSY;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return -EINVAL;
-+
-+ ar724x_pci_link_up = ar724x_pci_check_link();
-+ if (!ar724x_pci_link_up)
-+ dev_warn(&pdev->dev, "PCIe link is down\n");
-+
-+ ar724x_pci_irq_init(irq);
-+
-+ register_pci_controller(&ar724x_pci_controller);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar724x_pci_driver = {
-+ .probe = ar724x_pci_probe,
-+ .driver = {
-+ .name = "ar724x-pci",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init ar724x_pci_init(void)
-+{
-+ return platform_driver_register(&ar724x_pci_driver);
-+}
-+
-+postcore_initcall(ar724x_pci_init);
+++ /dev/null
-From d1a22e73f991145a4abd7d0c37bcf318703c89ed Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 11 Jun 2012 13:24:55 +0200
-Subject: [PATCH 05/34] MIPS: pci-ar71xx: convert to a platform driver
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci-ar71xx.c | 60 +++++++++++++++++++++++++++++++++++++++++---
- 1 files changed, 56 insertions(+), 4 deletions(-)
-
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -18,6 +18,8 @@
- #include <linux/pci.h>
- #include <linux/pci_regs.h>
- #include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
-@@ -309,7 +311,7 @@ static struct irq_chip ar71xx_pci_irq_ch
- .irq_mask_ack = ar71xx_pci_irq_mask,
- };
-
--static __init void ar71xx_pci_irq_init(void)
-+static void ar71xx_pci_irq_init(int irq)
- {
- void __iomem *base = ath79_reset_base;
- int i;
-@@ -324,10 +326,10 @@ static __init void ar71xx_pci_irq_init(v
- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
- handle_level_irq);
-
-- irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
-+ irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
- }
-
--static __init void ar71xx_pci_reset(void)
-+static void ar71xx_pci_reset(void)
- {
- void __iomem *ddr_base = ath79_ddr_base;
-
-@@ -367,9 +369,59 @@ __init int ar71xx_pcibios_init(void)
- /* clear bus errors */
- ar71xx_pci_check_error(1);
-
-- ar71xx_pci_irq_init();
-+ ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
-
- register_pci_controller(&ar71xx_pci_controller);
-
- return 0;
- }
-+
-+static int ar71xx_pci_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ int irq;
-+ u32 t;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
-+ if (!res)
-+ return -EINVAL;
-+
-+ ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!ar71xx_pcicfg_base)
-+ return -ENOMEM;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return -EINVAL;
-+
-+ ar71xx_pci_reset();
-+
-+ /* setup COMMAND register */
-+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
-+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-+ ar71xx_pci_local_write(PCI_COMMAND, 4, t);
-+
-+ /* clear bus errors */
-+ ar71xx_pci_check_error(1);
-+
-+ ar71xx_pci_irq_init(irq);
-+
-+ register_pci_controller(&ar71xx_pci_controller);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ar71xx_pci_driver = {
-+ .probe = ar71xx_pci_probe,
-+ .driver = {
-+ .name = "ar71xx-pci",
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+static int __init ar71xx_pci_init(void)
-+{
-+ return platform_driver_register(&ar71xx_pci_driver);
-+}
-+
-+postcore_initcall(ar71xx_pci_init);
+++ /dev/null
-From c3a8b5fa196cedc4b940c1e5ec482dd875aa3180 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 11 Jun 2012 13:38:06 +0200
-Subject: [PATCH 06/34] MIPS: ath79: move global PCI defines into a common header
-
-The constants will be used by a subsequent patch.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 24 ++++++++++++++++++++++++
- arch/mips/pci/pci-ar71xx.c | 16 ----------------
- arch/mips/pci/pci-ar724x.c | 8 --------
- 3 files changed, 24 insertions(+), 24 deletions(-)
-
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -41,11 +41,35 @@
- #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
- #define AR71XX_RESET_SIZE 0x100
-
-+#define AR71XX_PCI_MEM_BASE 0x10000000
-+#define AR71XX_PCI_MEM_SIZE 0x07000000
-+
-+#define AR71XX_PCI_WIN0_OFFS 0x10000000
-+#define AR71XX_PCI_WIN1_OFFS 0x11000000
-+#define AR71XX_PCI_WIN2_OFFS 0x12000000
-+#define AR71XX_PCI_WIN3_OFFS 0x13000000
-+#define AR71XX_PCI_WIN4_OFFS 0x14000000
-+#define AR71XX_PCI_WIN5_OFFS 0x15000000
-+#define AR71XX_PCI_WIN6_OFFS 0x16000000
-+#define AR71XX_PCI_WIN7_OFFS 0x07000000
-+
-+#define AR71XX_PCI_CFG_BASE \
-+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
-+#define AR71XX_PCI_CFG_SIZE 0x100
-+
- #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
- #define AR7240_USB_CTRL_SIZE 0x100
- #define AR7240_OHCI_BASE 0x1b000000
- #define AR7240_OHCI_SIZE 0x1000
-
-+#define AR724X_PCI_MEM_BASE 0x10000000
-+#define AR724X_PCI_MEM_SIZE 0x04000000
-+
-+#define AR724X_PCI_CFG_BASE 0x14000000
-+#define AR724X_PCI_CFG_SIZE 0x1000
-+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
-+#define AR724X_PCI_CTRL_SIZE 0x100
-+
- #define AR724X_EHCI_BASE 0x1b000000
- #define AR724X_EHCI_SIZE 0x1000
-
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -25,22 +25,6 @@
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/pci.h>
-
--#define AR71XX_PCI_MEM_BASE 0x10000000
--#define AR71XX_PCI_MEM_SIZE 0x07000000
--
--#define AR71XX_PCI_WIN0_OFFS 0x10000000
--#define AR71XX_PCI_WIN1_OFFS 0x11000000
--#define AR71XX_PCI_WIN2_OFFS 0x12000000
--#define AR71XX_PCI_WIN3_OFFS 0x13000000
--#define AR71XX_PCI_WIN4_OFFS 0x14000000
--#define AR71XX_PCI_WIN5_OFFS 0x15000000
--#define AR71XX_PCI_WIN6_OFFS 0x16000000
--#define AR71XX_PCI_WIN7_OFFS 0x07000000
--
--#define AR71XX_PCI_CFG_BASE \
-- (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
--#define AR71XX_PCI_CFG_SIZE 0x100
--
- #define AR71XX_PCI_REG_CRP_AD_CBE 0x00
- #define AR71XX_PCI_REG_CRP_WRDATA 0x04
- #define AR71XX_PCI_REG_CRP_RDDATA 0x08
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -17,14 +17,6 @@
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/pci.h>
-
--#define AR724X_PCI_CFG_BASE 0x14000000
--#define AR724X_PCI_CFG_SIZE 0x1000
--#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
--#define AR724X_PCI_CTRL_SIZE 0x100
--
--#define AR724X_PCI_MEM_BASE 0x10000000
--#define AR724X_PCI_MEM_SIZE 0x04000000
--
- #define AR724X_PCI_REG_RESET 0x18
- #define AR724X_PCI_REG_INT_STATUS 0x4c
- #define AR724X_PCI_REG_INT_MASK 0x50
+++ /dev/null
-From 2fdf8dcff3ffaa806e9f9d7f1c1bd876222cff4d Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 11 Jun 2012 13:39:32 +0200
-Subject: [PATCH 07/34] MIPS: ath79: register platform devices for the PCI controllers
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/pci.c | 87 +++++++++++++++++++++++++++++++++++++++++++-----
- 1 files changed, 78 insertions(+), 9 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -14,6 +14,8 @@
-
- #include <linux/init.h>
- #include <linux/pci.h>
-+#include <linux/resource.h>
-+#include <linux/platform_device.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/irq.h>
-@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
- ath79_pci_plat_dev_init = func;
- }
-
--int __init ath79_register_pci(void)
-+static struct platform_device *
-+ath79_register_pci_ar71xx(void)
- {
-- if (soc_is_ar71xx())
-- return ar71xx_pcibios_init();
-+ struct platform_device *pdev;
-+ struct resource res[2];
-+
-+ memset(res, 0, sizeof(res));
-
-- if (soc_is_ar724x())
-- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
-+ res[0].name = "cfg_base";
-+ res[0].flags = IORESOURCE_MEM;
-+ res[0].start = AR71XX_PCI_CFG_BASE;
-+ res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
-+
-+ res[1].flags = IORESOURCE_IRQ;
-+ res[1].start = ATH79_CPU_IRQ_IP2;
-+ res[1].end = ATH79_CPU_IRQ_IP2;
-+
-+ pdev = platform_device_register_simple("ar71xx-pci", -1,
-+ res, ARRAY_SIZE(res));
-+ return pdev;
-+}
-
-- if (soc_is_ar9342() || soc_is_ar9344()) {
-+static struct platform_device *
-+ath79_register_pci_ar724x(int id,
-+ unsigned long cfg_base,
-+ unsigned long ctrl_base,
-+ int irq)
-+{
-+ struct platform_device *pdev;
-+ struct resource res[3];
-+
-+ memset(res, 0, sizeof(res));
-+
-+ res[0].name = "cfg_base";
-+ res[0].flags = IORESOURCE_MEM;
-+ res[0].start = cfg_base;
-+ res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
-+
-+ res[1].name = "ctrl_base";
-+ res[1].flags = IORESOURCE_MEM;
-+ res[1].start = ctrl_base;
-+ res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
-+
-+ res[2].flags = IORESOURCE_IRQ;
-+ res[2].start = irq;
-+ res[2].end = irq;
-+
-+ pdev = platform_device_register_simple("ar724x-pci", id,
-+ res, ARRAY_SIZE(res));
-+ return pdev;
-+}
-+
-+int __init ath79_register_pci(void)
-+{
-+ struct platform_device *pdev = NULL;
-+
-+ if (soc_is_ar71xx()) {
-+ pdev = ath79_register_pci_ar71xx();
-+ } else if (soc_is_ar724x()) {
-+ pdev = ath79_register_pci_ar724x(-1,
-+ AR724X_PCI_CFG_BASE,
-+ AR724X_PCI_CTRL_BASE,
-+ ATH79_CPU_IRQ_IP2);
-+ } else if (soc_is_ar9342() ||
-+ soc_is_ar9344()) {
- u32 bootstrap;
-
- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-- if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
-- return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
-+ if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
-+ return -ENODEV;
-+
-+ pdev = ath79_register_pci_ar724x(-1,
-+ AR724X_PCI_CFG_BASE,
-+ AR724X_PCI_CTRL_BASE,
-+ ATH79_IP2_IRQ(0));
-+ } else {
-+ /* No PCI support */
-+ return -ENODEV;
- }
-
-- return -ENODEV;
-+ if (!pdev)
-+ pr_err("unable to register PCI controller device\n");
-+
-+ return pdev ? 0 : -ENODEV;
- }
+++ /dev/null
-From 07224e2fa5f889162ee0560c6ab1eb8cd16a8dd2 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 11 Jun 2012 14:59:39 +0200
-Subject: [PATCH 08/34] MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init functions
-
-The functions are unused now, so remove them.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/pci.c | 1 -
- arch/mips/include/asm/mach-ath79/pci.h | 28 ----------------------------
- arch/mips/pci/pci-ar71xx.c | 26 --------------------------
- arch/mips/pci/pci-ar724x.c | 32 --------------------------------
- 4 files changed, 0 insertions(+), 87 deletions(-)
- delete mode 100644 arch/mips/include/asm/mach-ath79/pci.h
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -19,7 +19,6 @@
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/irq.h>
--#include <asm/mach-ath79/pci.h>
- #include "pci.h"
-
- static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
---- a/arch/mips/include/asm/mach-ath79/pci.h
-+++ /dev/null
-@@ -1,28 +0,0 @@
--/*
-- * Atheros AR71XX/AR724X PCI support
-- *
-- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
-- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-- *
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- */
--
--#ifndef __ASM_MACH_ATH79_PCI_H
--#define __ASM_MACH_ATH79_PCI_H
--
--#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
--int ar71xx_pcibios_init(void);
--#else
--static inline int ar71xx_pcibios_init(void) { return 0; }
--#endif
--
--#if defined(CONFIG_PCI_AR724X)
--int ar724x_pcibios_init(int irq);
--#else
--static inline int ar724x_pcibios_init(int irq) { return 0; }
--#endif
--
--#endif /* __ASM_MACH_ATH79_PCI_H */
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -23,7 +23,6 @@
-
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
--#include <asm/mach-ath79/pci.h>
-
- #define AR71XX_PCI_REG_CRP_AD_CBE 0x00
- #define AR71XX_PCI_REG_CRP_WRDATA 0x04
-@@ -335,31 +334,6 @@ static void ar71xx_pci_reset(void)
- mdelay(100);
- }
-
--__init int ar71xx_pcibios_init(void)
--{
-- u32 t;
--
-- ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
-- if (ar71xx_pcicfg_base == NULL)
-- return -ENOMEM;
--
-- ar71xx_pci_reset();
--
-- /* setup COMMAND register */
-- t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
-- | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-- ar71xx_pci_local_write(PCI_COMMAND, 4, t);
--
-- /* clear bus errors */
-- ar71xx_pci_check_error(1);
--
-- ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2);
--
-- register_pci_controller(&ar71xx_pci_controller);
--
-- return 0;
--}
--
- static int ar71xx_pci_probe(struct platform_device *pdev)
- {
- struct resource *res;
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -15,7 +15,6 @@
- #include <linux/platform_device.h>
- #include <asm/mach-ath79/ath79.h>
- #include <asm/mach-ath79/ar71xx_regs.h>
--#include <asm/mach-ath79/pci.h>
-
- #define AR724X_PCI_REG_RESET 0x18
- #define AR724X_PCI_REG_INT_STATUS 0x4c
-@@ -276,37 +275,6 @@ static void ar724x_pci_irq_init(int irq)
- irq_set_chained_handler(irq, ar724x_pci_irq_handler);
- }
-
--int ar724x_pcibios_init(int irq)
--{
-- int ret;
--
-- ret = -ENOMEM;
--
-- ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
-- AR724X_PCI_CFG_SIZE);
-- if (ar724x_pci_devcfg_base == NULL)
-- goto err;
--
-- ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
-- AR724X_PCI_CTRL_SIZE);
-- if (ar724x_pci_ctrl_base == NULL)
-- goto err_unmap_devcfg;
--
-- ar724x_pci_link_up = ar724x_pci_check_link();
-- if (!ar724x_pci_link_up)
-- pr_warn("ar724x: PCIe link is down\n");
--
-- ar724x_pci_irq_init(irq);
-- register_pci_controller(&ar724x_pci_controller);
--
-- return PCIBIOS_SUCCESSFUL;
--
--err_unmap_devcfg:
-- iounmap(ar724x_pci_devcfg_base);
--err:
-- return ret;
--}
--
- static int ar724x_pci_probe(struct platform_device *pdev)
- {
- struct resource *res;
+++ /dev/null
-From a018b28d3953a32008de839d997a992a724ae314 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 24 Jun 2012 17:40:45 +0200
-Subject: [PATCH 09/34] MIPS: avoid possible resource conflict in register_pci_controller
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci.c | 15 +++++++++++++--
- 1 files changed, 13 insertions(+), 2 deletions(-)
-
---- a/arch/mips/pci/pci.c
-+++ b/arch/mips/pci/pci.c
-@@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex);
-
- void register_pci_controller(struct pci_controller *hose)
- {
-- if (request_resource(&iomem_resource, hose->mem_resource) < 0)
-+ struct resource *parent;
-+
-+ parent = hose->mem_resource->parent;
-+ if (!parent)
-+ parent = &iomem_resource;
-+
-+ if (request_resource(parent, hose->mem_resource) < 0)
- goto out;
-- if (request_resource(&ioport_resource, hose->io_resource) < 0) {
-+
-+ parent = hose->io_resource->parent;
-+ if (!parent)
-+ parent = &ioport_resource;
-+
-+ if (request_resource(parent, hose->io_resource) < 0) {
- release_resource(hose->mem_resource);
- goto out;
- }
+++ /dev/null
-From 242aedf3246dc5085271aca56134ac455bfb64b5 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 24 Jun 2012 11:51:34 +0200
-Subject: [PATCH 10/34] MIPS: pci-ar724x: use dynamically allocated PCI controller structure
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci-ar724x.c | 129 ++++++++++++++++++++++++++++----------------
- 1 files changed, 82 insertions(+), 47 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -9,6 +9,7 @@
- * by the Free Software Foundation.
- */
-
-+#include <linux/spinlock.h>
- #include <linux/irq.h>
- #include <linux/pci.h>
- #include <linux/module.h>
-@@ -28,38 +29,56 @@
-
- #define AR7240_BAR0_WAR_VALUE 0xffff
-
--static DEFINE_SPINLOCK(ar724x_pci_lock);
--static void __iomem *ar724x_pci_devcfg_base;
--static void __iomem *ar724x_pci_ctrl_base;
--
--static u32 ar724x_pci_bar0_value;
--static bool ar724x_pci_bar0_is_cached;
--static bool ar724x_pci_link_up;
-+struct ar724x_pci_controller {
-+ void __iomem *devcfg_base;
-+ void __iomem *ctrl_base;
-
--static inline bool ar724x_pci_check_link(void)
-+ int irq;
-+
-+ bool link_up;
-+ bool bar0_is_cached;
-+ u32 bar0_value;
-+
-+ spinlock_t lock;
-+
-+ struct pci_controller pci_controller;
-+};
-+
-+static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
- {
- u32 reset;
-
-- reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
-+ reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
- return reset & AR724X_PCI_RESET_LINK_UP;
- }
-
-+static inline struct ar724x_pci_controller *
-+pci_bus_to_ar724x_controller(struct pci_bus *bus)
-+{
-+ struct pci_controller *hose;
-+
-+ hose = (struct pci_controller *) bus->sysdata;
-+ return container_of(hose, struct ar724x_pci_controller, pci_controller);
-+}
-+
- static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
- {
-+ struct ar724x_pci_controller *apc;
- unsigned long flags;
- void __iomem *base;
- u32 data;
-
-- if (!ar724x_pci_link_up)
-+ apc = pci_bus_to_ar724x_controller(bus);
-+ if (!apc->link_up)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (devfn)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
-- base = ar724x_pci_devcfg_base;
-+ base = apc->devcfg_base;
-
-- spin_lock_irqsave(&ar724x_pci_lock, flags);
-+ spin_lock_irqsave(&apc->lock, flags);
- data = __raw_readl(base + (where & ~3));
-
- switch (size) {
-@@ -78,17 +97,17 @@ static int ar724x_pci_read(struct pci_bu
- case 4:
- break;
- default:
-- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&apc->lock, flags);
-
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-
-- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&apc->lock, flags);
-
- if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
-- ar724x_pci_bar0_is_cached) {
-+ apc->bar0_is_cached) {
- /* use the cached value */
-- *value = ar724x_pci_bar0_value;
-+ *value = apc->bar0_value;
- } else {
- *value = data;
- }
-@@ -99,12 +118,14 @@ static int ar724x_pci_read(struct pci_bu
- static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t value)
- {
-+ struct ar724x_pci_controller *apc;
- unsigned long flags;
- void __iomem *base;
- u32 data;
- int s;
-
-- if (!ar724x_pci_link_up)
-+ apc = pci_bus_to_ar724x_controller(bus);
-+ if (!apc->link_up)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (devfn)
-@@ -122,18 +143,18 @@ static int ar724x_pci_write(struct pci_b
- * BAR0 register in order to make the device memory
- * accessible.
- */
-- ar724x_pci_bar0_is_cached = true;
-- ar724x_pci_bar0_value = value;
-+ apc->bar0_is_cached = true;
-+ apc->bar0_value = value;
-
- value = AR7240_BAR0_WAR_VALUE;
- } else {
-- ar724x_pci_bar0_is_cached = false;
-+ apc->bar0_is_cached = false;
- }
- }
-
-- base = ar724x_pci_devcfg_base;
-+ base = apc->devcfg_base;
-
-- spin_lock_irqsave(&ar724x_pci_lock, flags);
-+ spin_lock_irqsave(&apc->lock, flags);
- data = __raw_readl(base + (where & ~3));
-
- switch (size) {
-@@ -151,7 +172,7 @@ static int ar724x_pci_write(struct pci_b
- data = value;
- break;
- default:
-- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&apc->lock, flags);
-
- return PCIBIOS_BAD_REGISTER_NUMBER;
- }
-@@ -159,7 +180,7 @@ static int ar724x_pci_write(struct pci_b
- __raw_writel(data, base + (where & ~3));
- /* flush write */
- __raw_readl(base + (where & ~3));
-- spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-+ spin_unlock_irqrestore(&apc->lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
- }
-@@ -183,18 +204,14 @@ static struct resource ar724x_mem_resour
- .flags = IORESOURCE_MEM,
- };
-
--static struct pci_controller ar724x_pci_controller = {
-- .pci_ops = &ar724x_pci_ops,
-- .io_resource = &ar724x_io_resource,
-- .mem_resource = &ar724x_mem_resource,
--};
--
- static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
- {
-+ struct ar724x_pci_controller *apc;
- void __iomem *base;
- u32 pending;
-
-- base = ar724x_pci_ctrl_base;
-+ apc = irq_get_handler_data(irq);
-+ base = apc->ctrl_base;
-
- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-@@ -208,10 +225,12 @@ static void ar724x_pci_irq_handler(unsig
-
- static void ar724x_pci_irq_unmask(struct irq_data *d)
- {
-+ struct ar724x_pci_controller *apc;
- void __iomem *base;
- u32 t;
-
-- base = ar724x_pci_ctrl_base;
-+ apc = irq_data_get_irq_chip_data(d);
-+ base = apc->ctrl_base;
-
- switch (d->irq) {
- case ATH79_PCI_IRQ(0):
-@@ -225,10 +244,12 @@ static void ar724x_pci_irq_unmask(struct
-
- static void ar724x_pci_irq_mask(struct irq_data *d)
- {
-+ struct ar724x_pci_controller *apc;
- void __iomem *base;
- u32 t;
-
-- base = ar724x_pci_ctrl_base;
-+ apc = irq_data_get_irq_chip_data(d);
-+ base = apc->ctrl_base;
-
- switch (d->irq) {
- case ATH79_PCI_IRQ(0):
-@@ -255,12 +276,12 @@ static struct irq_chip ar724x_pci_irq_ch
- .irq_mask_ack = ar724x_pci_irq_mask,
- };
-
--static void ar724x_pci_irq_init(int irq)
-+static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
- {
- void __iomem *base;
- int i;
-
-- base = ar724x_pci_ctrl_base;
-+ base = apc->ctrl_base;
-
- __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
-@@ -268,45 +289,59 @@ static void ar724x_pci_irq_init(int irq)
- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
-
- for (i = ATH79_PCI_IRQ_BASE;
-- i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
-+ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
- handle_level_irq);
-+ irq_set_chip_data(i, apc);
-+ }
-
-- irq_set_chained_handler(irq, ar724x_pci_irq_handler);
-+ irq_set_handler_data(apc->irq, apc);
-+ irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
- }
-
- static int ar724x_pci_probe(struct platform_device *pdev)
- {
-+ struct ar724x_pci_controller *apc;
- struct resource *res;
-- int irq;
-+
-+ apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
-+ GFP_KERNEL);
-+ if (!apc)
-+ return -ENOMEM;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
- if (!res)
- return -EINVAL;
-
-- ar724x_pci_ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
-- if (ar724x_pci_ctrl_base == NULL)
-+ apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (apc->ctrl_base == NULL)
- return -EBUSY;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
- if (!res)
- return -EINVAL;
-
-- ar724x_pci_devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
-- if (!ar724x_pci_devcfg_base)
-+ apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!apc->devcfg_base)
- return -EBUSY;
-
-- irq = platform_get_irq(pdev, 0);
-- if (irq < 0)
-+ apc->irq = platform_get_irq(pdev, 0);
-+ if (apc->irq < 0)
- return -EINVAL;
-
-- ar724x_pci_link_up = ar724x_pci_check_link();
-- if (!ar724x_pci_link_up)
-+ spin_lock_init(&apc->lock);
-+
-+ apc->pci_controller.pci_ops = &ar724x_pci_ops;
-+ apc->pci_controller.io_resource = &ar724x_io_resource;
-+ apc->pci_controller.mem_resource = &ar724x_mem_resource;
-+
-+ apc->link_up = ar724x_pci_check_link(apc);
-+ if (!apc->link_up)
- dev_warn(&pdev->dev, "PCIe link is down\n");
-
-- ar724x_pci_irq_init(irq);
-+ ar724x_pci_irq_init(apc);
-
-- register_pci_controller(&ar724x_pci_controller);
-+ register_pci_controller(&apc->pci_controller);
-
- return 0;
- }
+++ /dev/null
-From f1c3a7dadf7b77809cda7f77df4b1ba3b24fbfa3 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Wed, 27 Jun 2012 10:12:50 +0200
-Subject: [PATCH 11/34] MIPS: pci-ar724x: remove static PCI resources
-
-Get those from the platform device instead.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/pci.c | 21 ++++++++++++++++++++-
- arch/mips/pci/pci-ar724x.c | 40 ++++++++++++++++++++++++----------------
- 2 files changed, 44 insertions(+), 17 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -137,10 +137,13 @@ static struct platform_device *
- ath79_register_pci_ar724x(int id,
- unsigned long cfg_base,
- unsigned long ctrl_base,
-+ unsigned long mem_base,
-+ unsigned long mem_size,
-+ unsigned long io_base,
- int irq)
- {
- struct platform_device *pdev;
-- struct resource res[3];
-+ struct resource res[5];
-
- memset(res, 0, sizeof(res));
-
-@@ -158,6 +161,16 @@ ath79_register_pci_ar724x(int id,
- res[2].start = irq;
- res[2].end = irq;
-
-+ res[3].name = "mem_base";
-+ res[3].flags = IORESOURCE_MEM;
-+ res[3].start = mem_base;
-+ res[3].end = mem_base + mem_size - 1;
-+
-+ res[4].name = "io_base";
-+ res[4].flags = IORESOURCE_IO;
-+ res[4].start = io_base;
-+ res[4].end = io_base;
-+
- pdev = platform_device_register_simple("ar724x-pci", id,
- res, ARRAY_SIZE(res));
- return pdev;
-@@ -173,6 +186,9 @@ int __init ath79_register_pci(void)
- pdev = ath79_register_pci_ar724x(-1,
- AR724X_PCI_CFG_BASE,
- AR724X_PCI_CTRL_BASE,
-+ AR724X_PCI_MEM_BASE,
-+ AR724X_PCI_MEM_SIZE,
-+ 0,
- ATH79_CPU_IRQ_IP2);
- } else if (soc_is_ar9342() ||
- soc_is_ar9344()) {
-@@ -185,6 +201,9 @@ int __init ath79_register_pci(void)
- pdev = ath79_register_pci_ar724x(-1,
- AR724X_PCI_CFG_BASE,
- AR724X_PCI_CTRL_BASE,
-+ AR724X_PCI_MEM_BASE,
-+ AR724X_PCI_MEM_SIZE,
-+ 0,
- ATH79_IP2_IRQ(0));
- } else {
- /* No PCI support */
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -42,6 +42,8 @@ struct ar724x_pci_controller {
- spinlock_t lock;
-
- struct pci_controller pci_controller;
-+ struct resource io_res;
-+ struct resource mem_res;
- };
-
- static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
-@@ -190,20 +192,6 @@ static struct pci_ops ar724x_pci_ops = {
- .write = ar724x_pci_write,
- };
-
--static struct resource ar724x_io_resource = {
-- .name = "PCI IO space",
-- .start = 0,
-- .end = 0,
-- .flags = IORESOURCE_IO,
--};
--
--static struct resource ar724x_mem_resource = {
-- .name = "PCI memory space",
-- .start = AR724X_PCI_MEM_BASE,
-- .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
-- .flags = IORESOURCE_MEM,
--};
--
- static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
- {
- struct ar724x_pci_controller *apc;
-@@ -331,9 +319,29 @@ static int ar724x_pci_probe(struct platf
-
- spin_lock_init(&apc->lock);
-
-+ res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
-+ if (!res)
-+ return -EINVAL;
-+
-+ apc->io_res.parent = res;
-+ apc->io_res.name = "PCI IO space";
-+ apc->io_res.start = res->start;
-+ apc->io_res.end = res->end;
-+ apc->io_res.flags = IORESOURCE_IO;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
-+ if (!res)
-+ return -EINVAL;
-+
-+ apc->mem_res.parent = res;
-+ apc->mem_res.name = "PCI memory space";
-+ apc->mem_res.start = res->start;
-+ apc->mem_res.end = res->end;
-+ apc->mem_res.flags = IORESOURCE_MEM;
-+
- apc->pci_controller.pci_ops = &ar724x_pci_ops;
-- apc->pci_controller.io_resource = &ar724x_io_resource;
-- apc->pci_controller.mem_resource = &ar724x_mem_resource;
-+ apc->pci_controller.io_resource = &apc->io_res;
-+ apc->pci_controller.mem_resource = &apc->mem_res;
-
- apc->link_up = ar724x_pci_check_link(apc);
- if (!apc->link_up)
+++ /dev/null
-From d258929cd4c8c495f619f0e66d9d1c23f3f9246f Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Tue, 26 Jun 2012 11:59:45 +0200
-Subject: [PATCH 12/34] MIPS: pci-ar724x: use per-controller IRQ base
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci-ar724x.c | 31 +++++++++++++++++++++----------
- 1 files changed, 21 insertions(+), 10 deletions(-)
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -34,6 +34,7 @@ struct ar724x_pci_controller {
- void __iomem *ctrl_base;
-
- int irq;
-+ int irq_base;
-
- bool link_up;
- bool bar0_is_cached;
-@@ -205,7 +206,7 @@ static void ar724x_pci_irq_handler(unsig
- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-
- if (pending & AR724X_PCI_INT_DEV0)
-- generic_handle_irq(ATH79_PCI_IRQ(0));
-+ generic_handle_irq(apc->irq_base + 0);
-
- else
- spurious_interrupt();
-@@ -215,13 +216,15 @@ static void ar724x_pci_irq_unmask(struct
- {
- struct ar724x_pci_controller *apc;
- void __iomem *base;
-+ int offset;
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
- base = apc->ctrl_base;
-+ offset = apc->irq_base - d->irq;
-
-- switch (d->irq) {
-- case ATH79_PCI_IRQ(0):
-+ switch (offset) {
-+ case 0:
- t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(t | AR724X_PCI_INT_DEV0,
- base + AR724X_PCI_REG_INT_MASK);
-@@ -234,13 +237,15 @@ static void ar724x_pci_irq_mask(struct i
- {
- struct ar724x_pci_controller *apc;
- void __iomem *base;
-+ int offset;
- u32 t;
-
- apc = irq_data_get_irq_chip_data(d);
- base = apc->ctrl_base;
-+ offset = apc->irq_base - d->irq;
-
-- switch (d->irq) {
-- case ATH79_PCI_IRQ(0):
-+ switch (offset) {
-+ case 0:
- t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(t & ~AR724X_PCI_INT_DEV0,
- base + AR724X_PCI_REG_INT_MASK);
-@@ -264,7 +269,8 @@ static struct irq_chip ar724x_pci_irq_ch
- .irq_mask_ack = ar724x_pci_irq_mask,
- };
-
--static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc)
-+static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
-+ int id)
- {
- void __iomem *base;
- int i;
-@@ -274,10 +280,10 @@ static void ar724x_pci_irq_init(struct a
- __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
- __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
-
-- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
-+ apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
-
-- for (i = ATH79_PCI_IRQ_BASE;
-- i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) {
-+ for (i = apc->irq_base;
-+ i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
- handle_level_irq);
- irq_set_chip_data(i, apc);
-@@ -291,6 +297,11 @@ static int ar724x_pci_probe(struct platf
- {
- struct ar724x_pci_controller *apc;
- struct resource *res;
-+ int id;
-+
-+ id = pdev->id;
-+ if (id == -1)
-+ id = 0;
-
- apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
- GFP_KERNEL);
-@@ -347,7 +358,7 @@ static int ar724x_pci_probe(struct platf
- if (!apc->link_up)
- dev_warn(&pdev->dev, "PCIe link is down\n");
-
-- ar724x_pci_irq_init(apc);
-+ ar724x_pci_irq_init(apc, id);
-
- register_pci_controller(&apc->pci_controller);
-
+++ /dev/null
-From 93824983ceb36d4ce1f4a644031ec6fb5f332f1d Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Tue, 26 Jun 2012 15:14:47 +0200
-Subject: [PATCH 13/34] MIPS: pci-ar724x: setup command register of the PCI controller
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/pci.c | 10 +++-
- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +
- arch/mips/pci/pci-ar724x.c | 63 ++++++++++++++++++++++++
- 3 files changed, 74 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -137,13 +137,14 @@ static struct platform_device *
- ath79_register_pci_ar724x(int id,
- unsigned long cfg_base,
- unsigned long ctrl_base,
-+ unsigned long crp_base,
- unsigned long mem_base,
- unsigned long mem_size,
- unsigned long io_base,
- int irq)
- {
- struct platform_device *pdev;
-- struct resource res[5];
-+ struct resource res[6];
-
- memset(res, 0, sizeof(res));
-
-@@ -171,6 +172,11 @@ ath79_register_pci_ar724x(int id,
- res[4].start = io_base;
- res[4].end = io_base;
-
-+ res[5].name = "crp_base";
-+ res[5].flags = IORESOURCE_MEM;
-+ res[5].start = crp_base;
-+ res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
-+
- pdev = platform_device_register_simple("ar724x-pci", id,
- res, ARRAY_SIZE(res));
- return pdev;
-@@ -186,6 +192,7 @@ int __init ath79_register_pci(void)
- pdev = ath79_register_pci_ar724x(-1,
- AR724X_PCI_CFG_BASE,
- AR724X_PCI_CTRL_BASE,
-+ AR724X_PCI_CRP_BASE,
- AR724X_PCI_MEM_BASE,
- AR724X_PCI_MEM_SIZE,
- 0,
-@@ -201,6 +208,7 @@ int __init ath79_register_pci(void)
- pdev = ath79_register_pci_ar724x(-1,
- AR724X_PCI_CFG_BASE,
- AR724X_PCI_CTRL_BASE,
-+ AR724X_PCI_CRP_BASE,
- AR724X_PCI_MEM_BASE,
- AR724X_PCI_MEM_SIZE,
- 0,
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -67,6 +67,8 @@
-
- #define AR724X_PCI_CFG_BASE 0x14000000
- #define AR724X_PCI_CFG_SIZE 0x1000
-+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
-+#define AR724X_PCI_CRP_SIZE 0x1000
- #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
- #define AR724X_PCI_CTRL_SIZE 0x100
-
---- a/arch/mips/pci/pci-ar724x.c
-+++ b/arch/mips/pci/pci-ar724x.c
-@@ -29,9 +29,17 @@
-
- #define AR7240_BAR0_WAR_VALUE 0xffff
-
-+#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
-+ PCI_COMMAND_MASTER | \
-+ PCI_COMMAND_INVALIDATE | \
-+ PCI_COMMAND_PARITY | \
-+ PCI_COMMAND_SERR | \
-+ PCI_COMMAND_FAST_BACK)
-+
- struct ar724x_pci_controller {
- void __iomem *devcfg_base;
- void __iomem *ctrl_base;
-+ void __iomem *crp_base;
-
- int irq;
- int irq_base;
-@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
- return container_of(hose, struct ar724x_pci_controller, pci_controller);
- }
-
-+static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
-+ int where, int size, u32 value)
-+{
-+ unsigned long flags;
-+ void __iomem *base;
-+ u32 data;
-+ int s;
-+
-+ WARN_ON(where & (size - 1));
-+
-+ if (!apc->link_up)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ base = apc->crp_base;
-+
-+ spin_lock_irqsave(&apc->lock, flags);
-+ data = __raw_readl(base + (where & ~3));
-+
-+ switch (size) {
-+ case 1:
-+ s = ((where & 3) * 8);
-+ data &= ~(0xff << s);
-+ data |= ((value & 0xff) << s);
-+ break;
-+ case 2:
-+ s = ((where & 2) * 8);
-+ data &= ~(0xffff << s);
-+ data |= ((value & 0xffff) << s);
-+ break;
-+ case 4:
-+ data = value;
-+ break;
-+ default:
-+ spin_unlock_irqrestore(&apc->lock, flags);
-+ return PCIBIOS_BAD_REGISTER_NUMBER;
-+ }
-+
-+ __raw_writel(data, base + (where & ~3));
-+ /* flush write */
-+ __raw_readl(base + (where & ~3));
-+ spin_unlock_irqrestore(&apc->lock, flags);
-+
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
- static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
- int size, uint32_t *value)
- {
-@@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
- if (!apc->devcfg_base)
- return -EBUSY;
-
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
-+ if (!res)
-+ return -EINVAL;
-+
-+ apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (apc->crp_base == NULL)
-+ return -EBUSY;
-+
- apc->irq = platform_get_irq(pdev, 0);
- if (apc->irq < 0)
- return -EINVAL;
-@@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
-
- ar724x_pci_irq_init(apc, id);
-
-+ ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
-+
- register_pci_controller(&apc->pci_controller);
-
- return 0;
+++ /dev/null
-From 6c3ef689e4364dca74eaaecd72384be09e5a6bc8 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 25 Jun 2012 09:19:08 +0200
-Subject: [PATCH 14/34] MIPS: pci-ar71xx: use dynamically allocated PCI controller structure
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci-ar71xx.c | 84 +++++++++++++++++++++++++++----------------
- 1 files changed, 53 insertions(+), 31 deletions(-)
-
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -20,6 +20,7 @@
- #include <linux/interrupt.h>
- #include <linux/module.h>
- #include <linux/platform_device.h>
-+#include <linux/slab.h>
-
- #include <asm/mach-ath79/ar71xx_regs.h>
- #include <asm/mach-ath79/ath79.h>
-@@ -48,8 +49,12 @@
-
- #define AR71XX_PCI_IRQ_COUNT 5
-
--static DEFINE_SPINLOCK(ar71xx_pci_lock);
--static void __iomem *ar71xx_pcicfg_base;
-+struct ar71xx_pci_controller {
-+ void __iomem *cfg_base;
-+ spinlock_t lock;
-+ int irq;
-+ struct pci_controller pci_ctrl;
-+};
-
- /* Byte lane enable bits */
- static const u8 ar71xx_pci_ble_table[4][4] = {
-@@ -92,9 +97,18 @@ static inline u32 ar71xx_pci_bus_addr(st
- return ret;
- }
-
--static int ar71xx_pci_check_error(int quiet)
-+static inline struct ar71xx_pci_controller *
-+pci_bus_to_ar71xx_controller(struct pci_bus *bus)
- {
-- void __iomem *base = ar71xx_pcicfg_base;
-+ struct pci_controller *hose;
-+
-+ hose = (struct pci_controller *) bus->sysdata;
-+ return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
-+}
-+
-+static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
-+{
-+ void __iomem *base = apc->cfg_base;
- u32 pci_err;
- u32 ahb_err;
-
-@@ -129,9 +143,10 @@ static int ar71xx_pci_check_error(int qu
- return !!(ahb_err | pci_err);
- }
-
--static inline void ar71xx_pci_local_write(int where, int size, u32 value)
-+static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
-+ int where, int size, u32 value)
- {
-- void __iomem *base = ar71xx_pcicfg_base;
-+ void __iomem *base = apc->cfg_base;
- u32 ad_cbe;
-
- value = value << (8 * (where & 3));
-@@ -147,7 +162,8 @@ static inline int ar71xx_pci_set_cfgaddr
- unsigned int devfn,
- int where, int size, u32 cmd)
- {
-- void __iomem *base = ar71xx_pcicfg_base;
-+ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
-+ void __iomem *base = apc->cfg_base;
- u32 addr;
-
- addr = ar71xx_pci_bus_addr(bus, devfn, where);
-@@ -156,13 +172,14 @@ static inline int ar71xx_pci_set_cfgaddr
- __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
- base + AR71XX_PCI_REG_CFG_CBE);
-
-- return ar71xx_pci_check_error(1);
-+ return ar71xx_pci_check_error(apc, 1);
- }
-
- static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *value)
- {
-- void __iomem *base = ar71xx_pcicfg_base;
-+ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
-+ void __iomem *base = apc->cfg_base;
- unsigned long flags;
- u32 data;
- int err;
-@@ -171,7 +188,7 @@ static int ar71xx_pci_read_config(struct
- ret = PCIBIOS_SUCCESSFUL;
- data = ~0;
-
-- spin_lock_irqsave(&ar71xx_pci_lock, flags);
-+ spin_lock_irqsave(&apc->lock, flags);
-
- err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
- AR71XX_PCI_CFG_CMD_READ);
-@@ -180,7 +197,7 @@ static int ar71xx_pci_read_config(struct
- else
- data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
-
-- spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
-+ spin_unlock_irqrestore(&apc->lock, flags);
-
- *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
-
-@@ -190,7 +207,8 @@ static int ar71xx_pci_read_config(struct
- static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 value)
- {
-- void __iomem *base = ar71xx_pcicfg_base;
-+ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
-+ void __iomem *base = apc->cfg_base;
- unsigned long flags;
- int err;
- int ret;
-@@ -198,7 +216,7 @@ static int ar71xx_pci_write_config(struc
- value = value << (8 * (where & 3));
- ret = PCIBIOS_SUCCESSFUL;
-
-- spin_lock_irqsave(&ar71xx_pci_lock, flags);
-+ spin_lock_irqsave(&apc->lock, flags);
-
- err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
- AR71XX_PCI_CFG_CMD_WRITE);
-@@ -207,7 +225,7 @@ static int ar71xx_pci_write_config(struc
- else
- __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
-
-- spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
-+ spin_unlock_irqrestore(&apc->lock, flags);
-
- return ret;
- }
-@@ -231,12 +249,6 @@ static struct resource ar71xx_pci_mem_re
- .flags = IORESOURCE_MEM
- };
-
--static struct pci_controller ar71xx_pci_controller = {
-- .pci_ops = &ar71xx_pci_ops,
-- .mem_resource = &ar71xx_pci_mem_resource,
-- .io_resource = &ar71xx_pci_io_resource,
--};
--
- static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
- {
- void __iomem *base = ath79_reset_base;
-@@ -294,7 +306,7 @@ static struct irq_chip ar71xx_pci_irq_ch
- .irq_mask_ack = ar71xx_pci_irq_mask,
- };
-
--static void ar71xx_pci_irq_init(int irq)
-+static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
- {
- void __iomem *base = ath79_reset_base;
- int i;
-@@ -309,7 +321,7 @@ static void ar71xx_pci_irq_init(int irq)
- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
- handle_level_irq);
-
-- irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
-+ irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
- }
-
- static void ar71xx_pci_reset(void)
-@@ -336,20 +348,26 @@ static void ar71xx_pci_reset(void)
-
- static int ar71xx_pci_probe(struct platform_device *pdev)
- {
-+ struct ar71xx_pci_controller *apc;
- struct resource *res;
-- int irq;
- u32 t;
-
-+ apc = kzalloc(sizeof(struct ar71xx_pci_controller), GFP_KERNEL);
-+ if (!apc)
-+ return -ENOMEM;
-+
-+ spin_lock_init(&apc->lock);
-+
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
- if (!res)
- return -EINVAL;
-
-- ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
-- if (!ar71xx_pcicfg_base)
-+ apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!apc->cfg_base)
- return -ENOMEM;
-
-- irq = platform_get_irq(pdev, 0);
-- if (irq < 0)
-+ apc->irq = platform_get_irq(pdev, 0);
-+ if (apc->irq < 0)
- return -EINVAL;
-
- ar71xx_pci_reset();
-@@ -357,14 +375,18 @@ static int ar71xx_pci_probe(struct platf
- /* setup COMMAND register */
- t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
- | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-- ar71xx_pci_local_write(PCI_COMMAND, 4, t);
-+ ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
-
- /* clear bus errors */
-- ar71xx_pci_check_error(1);
-+ ar71xx_pci_check_error(apc, 1);
-+
-+ ar71xx_pci_irq_init(apc);
-
-- ar71xx_pci_irq_init(irq);
-+ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
-+ apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
-+ apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
-
-- register_pci_controller(&ar71xx_pci_controller);
-+ register_pci_controller(&apc->pci_ctrl);
-
- return 0;
- }
+++ /dev/null
-From 7dc3ccb5dc972b06c41b309653d132beaaedeb37 Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Mon, 25 Jun 2012 09:52:23 +0200
-Subject: [PATCH 15/34] MIPS: pci-ar71xx: remove static PCI controller resources
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/pci/pci-ar71xx.c | 30 ++++++++++++++----------------
- 1 files changed, 14 insertions(+), 16 deletions(-)
-
---- a/arch/mips/pci/pci-ar71xx.c
-+++ b/arch/mips/pci/pci-ar71xx.c
-@@ -54,6 +54,8 @@ struct ar71xx_pci_controller {
- spinlock_t lock;
- int irq;
- struct pci_controller pci_ctrl;
-+ struct resource io_res;
-+ struct resource mem_res;
- };
-
- /* Byte lane enable bits */
-@@ -235,20 +237,6 @@ static struct pci_ops ar71xx_pci_ops = {
- .write = ar71xx_pci_write_config,
- };
-
--static struct resource ar71xx_pci_io_resource = {
-- .name = "PCI IO space",
-- .start = 0,
-- .end = 0,
-- .flags = IORESOURCE_IO,
--};
--
--static struct resource ar71xx_pci_mem_resource = {
-- .name = "PCI memory space",
-- .start = AR71XX_PCI_MEM_BASE,
-- .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
-- .flags = IORESOURCE_MEM
--};
--
- static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
- {
- void __iomem *base = ath79_reset_base;
-@@ -370,6 +358,16 @@ static int ar71xx_pci_probe(struct platf
- if (apc->irq < 0)
- return -EINVAL;
-
-+ apc->io_res.name = "PCI IO space";
-+ apc->io_res.start = 0;
-+ apc->io_res.end = 0;
-+ apc->io_res.flags = IORESOURCE_IO;
-+
-+ apc->mem_res.name = "PCI memory space";
-+ apc->mem_res.start = AR71XX_PCI_MEM_BASE;
-+ apc->mem_res.end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
-+ apc->mem_res.flags = IORESOURCE_MEM;
-+
- ar71xx_pci_reset();
-
- /* setup COMMAND register */
-@@ -383,8 +381,8 @@ static int ar71xx_pci_probe(struct platf
- ar71xx_pci_irq_init(apc);
-
- apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
-- apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
-- apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
-+ apc->pci_ctrl.mem_resource = &apc->mem_res;
-+ apc->pci_ctrl.io_resource = &apc->io_res;
-
- register_pci_controller(&apc->pci_ctrl);
-
+++ /dev/null
-From 12c68e4fccadc22a0470177141a57892a76e4a2b Mon Sep 17 00:00:00 2001
-From: Gabor Juhos <juhosg@openwrt.org>
-Date: Sun, 24 Jun 2012 15:33:16 +0200
-Subject: [PATCH 25/34] MIPS: ath79: allow to specify bus number in PCI IRQ maps
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
----
- arch/mips/ath79/pci.c | 4 +++-
- arch/mips/ath79/pci.h | 1 +
- 2 files changed, 4 insertions(+), 1 deletions(-)
-
---- a/arch/mips/ath79/pci.c
-+++ b/arch/mips/ath79/pci.c
-@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct
- const struct ath79_pci_irq *entry;
-
- entry = &ath79_pci_irq_map[i];
-- if (entry->slot == slot && entry->pin == pin) {
-+ if (entry->bus == dev->bus->number &&
-+ entry->slot == slot &&
-+ entry->pin == pin) {
- irq = entry->irq;
- break;
- }
---- a/arch/mips/ath79/pci.h
-+++ b/arch/mips/ath79/pci.h
-@@ -14,6 +14,7 @@
- #define _ATH79_PCI_H
-
- struct ath79_pci_irq {
-+ int bus;
- u8 slot;
- u8 pin;
- int irq;
} else {
pr_crit("pci %s: invalid irq map\n",
pci_name((struct pci_dev *) dev));
-@@ -215,6 +233,24 @@ int __init ath79_register_pci(void)
+@@ -225,6 +243,24 @@ int __init ath79_register_pci(void)
AR724X_PCI_MEM_SIZE,
0,
ATH79_IP2_IRQ(0));
static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
{
.slot = 17,
-@@ -202,12 +206,50 @@ ath79_register_pci_ar724x(int id,
+@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id,
return pdev;
}
projects / openwrt / staging / wigyori.git / commitdiff