drm/amd/powerplay: add pstate mclk(uclk) support for navi10

add pstate mclk(uclk) support.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c382eb9011784959d78598666ec7fa9b14d7f12f..04132653e289368971dd61e6edff124f92cb46a5 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -136,6 +136,7 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
                return -EINVAL;
 
        switch (clk_type) {
+       case SMU_MCLK:
        case SMU_UCLK:
                if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
                        pr_warn("uclk dpm is not enabled\n");

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 4404528f969a60662bb014533c6f3b9527dc7f90..e25c1e3094efe5f3c1cfd4dbdc242e0495e4fc0f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -709,7 +709,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 {
        int ret = 0;
-       uint32_t min_sclk_freq = 0;
+       uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 
        ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
        if (ret)
@@ -717,6 +717,12 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
 
        smu->pstate_sclk = min_sclk_freq * 100;
 
+       ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
+       if (ret)
+               return ret;
+
+       smu->pstate_mclk = min_mclk_freq * 100;
+
        return ret;
 }