#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
-#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
-#define WDT_RESET 0x0002
+#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define WDT_RESET_OUT_EN 0x0002
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
/*
* Enable and issue soft reset
*/
- orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+ orion5x_setbits(RSTOUTn_MASK, (1 << 2));
orion5x_setbits(CPU_SOFT_RESET, 1);
}
/*
* Enable and issue soft reset
*/
- reg = readl(CPU_RESET_MASK);
+ reg = readl(RSTOUTn_MASK);
reg |= 1 << 2;
- writel(reg, CPU_RESET_MASK);
+ writel(reg, RSTOUTn_MASK);
reg = readl(CPU_SOFT_RESET);
reg |= 1;
writel(reg, TIMER_CTRL);
/* Enable reset on watchdog */
- reg = readl(CPU_RESET_MASK);
- reg |= WDT_RESET;
- writel(reg, CPU_RESET_MASK);
+ reg = readl(RSTOUTn_MASK);
+ reg |= WDT_RESET_OUT_EN;
+ writel(reg, RSTOUTn_MASK);
spin_unlock(&wdt_lock);
}
spin_lock(&wdt_lock);
/* Disable reset on watchdog */
- reg = readl(CPU_RESET_MASK);
- reg &= ~WDT_RESET;
- writel(reg, CPU_RESET_MASK);
+ reg = readl(RSTOUTn_MASK);
+ reg &= ~WDT_RESET_OUT_EN;
+ writel(reg, RSTOUTn_MASK);
/* Disable watchdog timer */
reg = readl(TIMER_CTRL);