MIPS: CPS: Copy EVA configuration when starting secondary VPs.

When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consistent virtual memory map.

The EVA configuration of secondary cores is dealt with when starting the
core via the CM.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13291/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 51b98dc371b39af01264328e6108f0995472c127..59476a607adda07c5be321b8f21653668c1555b8 100644 (file)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -441,6 +441,21 @@ LEAF(mips_cps_boot_vpes)
        mfc0    t0, CP0_CONFIG
        mttc0   t0, CP0_CONFIG
 
+       /*
+        * Copy the EVA config from this VPE if the CPU supports it.
+        * CONFIG3 must exist to be running MT startup - just read it.
+        */
+       mfc0    t0, CP0_CONFIG, 3
+       and     t0, t0, MIPS_CONF3_SC
+       beqz    t0, 3f
+        nop
+       mfc0    t0, CP0_SEGCTL0
+       mttc0   t0, CP0_SEGCTL0
+       mfc0    t0, CP0_SEGCTL1
+       mttc0   t0, CP0_SEGCTL1
+       mfc0    t0, CP0_SEGCTL2
+       mttc0   t0, CP0_SEGCTL2
+3:
        /* Ensure no software interrupts are pending */
        mttc0   zero, CP0_CAUSE
        mttc0   zero, CP0_STATUS