realtek: Fix RTL931X-specific Ethernet driver functions

Fix the update counter of the RX ring, add SDS access functions
for RTL931X.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>

diff --git a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
index ecec0fec2dce5cbb57a3acaac00de068ba959645..2d634b2fd3bcea65000c5a0589e60ecae91afb13 100644 (file)
--- a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
+++ b/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
@@ -337,30 +337,17 @@
 #define RTL931X_SMI_GLB_CTRL1          (0x0CBC)
 #define RTL931X_SMI_GLB_CTRL0          (0x0CC0)
 #define RTL931X_SMI_PORT_POLLING_CTRL  (0x0CCC)
+#define RTL931X_SMI_PORT_ADDR          (0x0C74)
+#define RTL931X_SMI_PORT_POLLING_SEL   (0x0C9C)
+#define RTL9310_SMI_PORT_POLLING_CTRL  (0x0CCC)
 #define RTL931X_SMI_INDRT_ACCESS_CTRL_0        (0x0C00)
 #define RTL931X_SMI_INDRT_ACCESS_CTRL_1        (0x0C04)
 #define RTL931X_SMI_INDRT_ACCESS_CTRL_2        (0x0C08)
 #define RTL931X_SMI_INDRT_ACCESS_CTRL_3        (0x0C10)
 #define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)
 #define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)
-
-#define RTL930X_SMI_GLB_CTRL           (0xCA00)
-#define RTL930X_SMI_POLL_CTRL          (0xca90)
-#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
-#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
-#define RTL930X_SMI_PORT0_5_ADDR       (0xCB80)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_0  (0xCB70)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_1  (0xCB74)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_2  (0xCB78)
-#define RTL930X_SMI_ACCESS_PHY_CTRL_3  (0xCB7C)
-
-#define RTL931X_SMI_GLB_CTRL1          (0x0CBC)
-#define RTL931X_SMI_GLB_CTRL0          (0x0CC0)
-#define RTL931X_SMI_PORT_POLLING_CTRL  (0x0CCC)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_0        (0x0C00)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_1        (0x0C04)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_2        (0x0C08)
-#define RTL931X_SMI_INDRT_ACCESS_CTRL_3        (0x0C10)
+#define RTL931X_MAC_L2_GLOBAL_CTRL2    (0x1358)
+#define RTL931X_MAC_L2_GLOBAL_CTRL1    (0x5548)
 
 /*
  * Switch interrupts
@@ -395,6 +382,9 @@
 #define RTL9300_FAMILY_ID   (0x9300)
 #define RTL9310_FAMILY_ID   (0x9310)
 
+/* SPI Support */
+#define RTL931X_SPI_CTRL0              (0x103C)
+
 /* Basic SoC Features */
 #define RTL838X_CPU_PORT                       28
 #define RTL839X_CPU_PORT                       52

diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index cdfc2148e80468f5088089e8ab42ca8497e1bec6..3d845519404a1fbace357f5cd2f45294db240433 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -165,6 +165,13 @@ static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
        }
 }
 
+static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
+{
+       h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload
+       h->cpu_tag[2] |= (vlan >> 8) & 0xf;
+       h->cpu_tag[3] |= (vlan & 0xff) << 8;
+}
+
 struct rtl838x_rx_q {
        int id;
        struct rtl838x_eth_priv *priv;
@@ -189,6 +196,7 @@ struct rtl838x_eth_priv {
        u16 rxringlen;
        u8 smi_bus[MAX_PORTS];
        u8 smi_addr[MAX_PORTS];
+       u32 sds_id[MAX_PORTS];
        bool smi_bus_isc45[MAX_SMI_BUSSES];
        bool phy_is_internal[MAX_PORTS];
 };
@@ -199,8 +207,12 @@ extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);
 extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);
 extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);
 extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
+extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);
+extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
 extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
 extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
+extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);
+extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);
 
 /*
  * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of 
@@ -234,8 +246,11 @@ void rtl931x_update_cntr(int r, int released)
 {
        int pos = (r % 3) * 10;
        u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);
+       u32 v = sw_r32(reg);
 
+       v = (v >> pos) & 0x3ff;
        sw_w32_mask(0x3ff << pos, released << pos, reg);
+       sw_w32(v, reg);
 }
 
 struct dsa_tag {
@@ -302,8 +317,9 @@ bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)
        t->port = (h->cpu_tag[0] >> 8) & 0x3f;
        t->crc_error = h->cpu_tag[1] & BIT(6);
 
-       pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue);
-       if (t->reason >= 19 && t->reason <= 27)
+       if (t->reason != 63)
+               pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue);
+       if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA
                t->l2_offloaded = 0;
        else
                t->l2_offloaded = 1;
@@ -1722,16 +1738,6 @@ static int rtl839x_mdio_reset(struct mii_bus *bus)
        return 0;
 }
 
-static int rtl931x_mdio_reset(struct mii_bus *bus)
-{
-       sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL);
-       sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL + 4);
-
-       pr_debug("%s called\n", __func__);
-
-       return 0;
-}
-
 static int rtl930x_mdio_reset(struct mii_bus *bus)
 {
        int i;
@@ -1849,6 +1855,12 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
                        smi_addr[1] = pn;
                }
 
+               if (of_property_read_u32(dn, "sds", &priv->sds_id[pn]))
+                       priv->sds_id[pn] = -1;
+               else {
+                       pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]);
+               }
+
                if (pn < MAX_PORTS) {
                        priv->smi_bus[pn] = smi_addr[0];
                        priv->smi_addr[pn] = smi_addr[1];

diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h
index ab7dcd22ebc31de18d5c84ed070ba4ad777bad7b..223b42fa247931b6797dab005fdcbce254fab8c7 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h
@@ -134,6 +134,7 @@
 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL       (0xaa08)
 
 #define RTL930X_L2_UNKN_UC_FLD_PMSK            (0x9064)
+#define RTL931X_L2_UNKN_UC_FLD_PMSK            (0xC8F4)
 
 #define RTL839X_MAC_GLB_CTRL                   (0x02a8)
 #define RTL839X_SCHED_LB_TICK_TKN_CTRL         (0x60f8)
@@ -182,6 +183,7 @@
 #define RTL930X_RMA_CTRL_1                     (0x9E64)
 #define RTL930X_RMA_CTRL_2                     (0x9E68)
 
+#define RTL931X_VLAN_APP_PKT_CTRL              (0x96b0)
 #define RTL931X_RMA_CTRL_0                     (0x8800)
 #define RTL931X_RMA_CTRL_1                     (0x8804)
 #define RTL931X_RMA_CTRL_2                     (0x8808)
@@ -195,6 +197,19 @@
 /* Registers of the internal Serdes of the 8390 */
 #define RTL839X_SDS12_13_XSG0                  (0xB800)
 
+/* Chip configuration registers of the RTL9310 */
+#define RTL931X_MEM_ENCAP_INIT                 (0x4854)
+#define RTL931X_MEM_MIB_INIT                   (0x7E18)
+#define RTL931X_MEM_ACL_INIT                   (0x40BC)
+#define RTL931X_MEM_ALE_INIT_0                 (0x83F0)
+#define RTL931X_MEM_ALE_INIT_1                 (0x83F4)
+#define RTL931X_MEM_ALE_INIT_2                 (0x82E4)
+#define RTL931X_MDX_CTRL_RSVD                  (0x0fcc)
+#define RTL931X_PS_SOC_CTRL                    (0x13f8)
+#define RTL931X_SMI_10GPHY_POLLING_SEL2                (0xCF8)
+#define RTL931X_SMI_10GPHY_POLLING_SEL3                (0xCFC)
+#define RTL931X_SMI_10GPHY_POLLING_SEL4                (0xD00)
+
 /* Registers of the internal Serdes of the 8380 */
 #define RTL838X_SDS4_FIB_REG0                  (0xF800)