drm/amdgpu: gmc handle ras resume

During S3/S4 bootloader will re-init ras state behind us.
Resume might fail or raise a gpu reset.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1e1ef46715da0f985b9f528f8a9d6c302f4e8e0e..94d67b7f92177205e88ad7e41de38bbd59e9cc86 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -686,8 +686,25 @@ static int gmc_v9_0_ecc_late_init(void *handle)
                return 0;
        }
        /* handle resume path. */
-       if (*ras_if)
+       if (*ras_if) {
+               /* resend ras TA enable cmd during resume.
+                * prepare to handle failure.
+                */
+               ih_info.head = **ras_if;
+               r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
+               if (r) {
+                       if (r == -EAGAIN) {
+                               /* request a gpu reset. will run again. */
+                               amdgpu_ras_request_reset_on_boot(adev,
+                                               AMDGPU_RAS_BLOCK__UMC);
+                               return 0;
+                       }
+                       /* fail to enable ras, cleanup all. */
+                       goto irq;
+               }
+               /* enable successfully. continue. */
                goto resume;
+       }
 
        *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
        if (!*ras_if)