perf_counter: add comment to barrier
authorPeter Zijlstra <a.p.zijlstra@chello.nl>
Fri, 13 Mar 2009 11:21:30 +0000 (12:21 +0100)
committerIngo Molnar <mingo@elte.hu>
Mon, 6 Apr 2009 07:29:32 +0000 (09:29 +0200)
We need to ensure the enabled=0 write happens before we
start disabling the actual counters, so that a pcm_amd_enable()
will not enable one underneath us.

I think the race is impossible anyway, we always balance the
ops within any one context and perform enable() with IRQs disabled.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_counter.c

index 1cedc3468ce5b85f1a91db1938631f882c4de64c..a2e3b76bfdc1504985d216ca8d01b6b1a58d0018 100644 (file)
@@ -247,6 +247,10 @@ static u64 pmc_amd_save_disable_all(void)
 
        enabled = cpuc->enabled;
        cpuc->enabled = 0;
+       /*
+        * ensure we write the disable before we start disabling the
+        * counters proper, so that pcm_amd_enable() does the right thing.
+        */
        barrier();
 
        for (idx = 0; idx < nr_counters_generic; idx++) {