MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
/* setup max frame length */
- ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, ag->max_frame_len);
/* setup FIFO configuration registers */
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
{
+ struct ag71xx *ag = netdev_priv(dev);
+
if (new_mtu < 68 ||
- new_mtu > AG71XX_TX_MTU_LEN - ETH_HLEN - ETH_FCS_LEN)
+ new_mtu > ag->max_frame_len - ETH_HLEN - ETH_FCS_LEN)
return -EINVAL;
dev->mtu = new_mtu;
ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
+ ag->max_frame_len = AG71XX_TX_MTU_LEN;
+
ag->stop_desc = dma_alloc_coherent(NULL,
sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);