ARM: davinci: move SoC sources to mach-davinci
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Fri, 20 Feb 2015 08:04:05 +0000 (17:04 +0900)
committerTom Rini <trini@ti.com>
Sat, 21 Feb 2015 13:23:51 +0000 (08:23 -0500)
Move
arch/arm/cpu/arm926ejs/davinci/* -> arch/arm/mach-davinci/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
49 files changed:
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/cpu/arm926ejs/Makefile
arch/arm/cpu/arm926ejs/davinci/Kconfig [deleted file]
arch/arm/cpu/arm926ejs/davinci/Makefile [deleted file]
arch/arm/cpu/arm926ejs/davinci/config.mk [deleted file]
arch/arm/cpu/arm926ejs/davinci/cpu.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/dm355.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/dm365.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/dm644x.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/dm646x.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/dp83848.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/et1011c.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/ksz8873.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S [deleted file]
arch/arm/cpu/arm926ejs/davinci/lxt972.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/misc.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/pinmux.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/psc.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/reset.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/spl.c [deleted file]
arch/arm/cpu/arm926ejs/davinci/timer.c [deleted file]
arch/arm/mach-davinci/Kconfig [new file with mode: 0644]
arch/arm/mach-davinci/Makefile [new file with mode: 0644]
arch/arm/mach-davinci/config.mk [new file with mode: 0644]
arch/arm/mach-davinci/cpu.c [new file with mode: 0644]
arch/arm/mach-davinci/da830_pinmux.c [new file with mode: 0644]
arch/arm/mach-davinci/da850_lowlevel.c [new file with mode: 0644]
arch/arm/mach-davinci/da850_pinmux.c [new file with mode: 0644]
arch/arm/mach-davinci/dm355.c [new file with mode: 0644]
arch/arm/mach-davinci/dm365.c [new file with mode: 0644]
arch/arm/mach-davinci/dm365_lowlevel.c [new file with mode: 0644]
arch/arm/mach-davinci/dm644x.c [new file with mode: 0644]
arch/arm/mach-davinci/dm646x.c [new file with mode: 0644]
arch/arm/mach-davinci/dp83848.c [new file with mode: 0644]
arch/arm/mach-davinci/et1011c.c [new file with mode: 0644]
arch/arm/mach-davinci/ksz8873.c [new file with mode: 0644]
arch/arm/mach-davinci/lowlevel_init.S [new file with mode: 0644]
arch/arm/mach-davinci/lxt972.c [new file with mode: 0644]
arch/arm/mach-davinci/misc.c [new file with mode: 0644]
arch/arm/mach-davinci/pinmux.c [new file with mode: 0644]
arch/arm/mach-davinci/psc.c [new file with mode: 0644]
arch/arm/mach-davinci/reset.c [new file with mode: 0644]
arch/arm/mach-davinci/spl.c [new file with mode: 0644]
arch/arm/mach-davinci/timer.c [new file with mode: 0644]

index adecafcad1cc9a20d13080c17c23c8ff78d97aa2..887c0d5b6ee1673c012c122df6c8182c3629b436 100644 (file)
@@ -716,7 +716,7 @@ endchoice
 
 source "arch/arm/mach-at91/Kconfig"
 
-source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
+source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/cpu/arm1176/bcm2835/Kconfig"
 
index f1ae929154c432b7266885103c82647e95fff717..e321057a0edcad2b9b54e72673dd10ea994f5b84 100644 (file)
@@ -5,6 +5,7 @@
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)            += at91
+machine-$(CONFIG_ARCH_DAVINCI)         += davinci
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 machine-$(CONFIG_TEGRA)                        += tegra
 
index f41357aaeb42fa0b7730c5a9e0f4da61aaedf58c..27b4353a9dea36de7ae5d5670edd9d7f7b973a0d 100644 (file)
@@ -15,7 +15,6 @@ endif
 endif
 
 obj-$(CONFIG_ARMADA100) += armada100/
-obj-$(CONFIG_ARCH_DAVINCI) += davinci/
 obj-$(CONFIG_KIRKWOOD) += kirkwood/
 obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
 obj-$(CONFIG_MB86R0x) += mb86r0x/
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
deleted file mode 100644 (file)
index 613f04d..0000000
+++ /dev/null
@@ -1,78 +0,0 @@
-if ARCH_DAVINCI
-
-choice
-       prompt "DaVinci board select"
-
-config TARGET_ENBW_CMC
-       bool "EnBW CMC board"
-
-config TARGET_IPAM390
-       bool "IPAM390 board"
-       select SUPPORT_SPL
-
-config TARGET_DA830EVM
-       bool "DA830 EVM board"
-
-config TARGET_DA850EVM
-       bool "DA850 EVM board"
-       select SUPPORT_SPL
-
-config TARGET_CAM_ENC_4XX
-       bool "CAM ENC 4xx board"
-       select SUPPORT_SPL
-
-config TARGET_HAWKBOARD
-       bool "Hawkboard"
-       select SUPPORT_SPL
-
-config TARGET_DAVINCI_DM355EVM
-       bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
-       bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
-       bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
-       bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
-       bool "DVEVM board"
-
-config TARGET_EA20
-       bool "EA20 board"
-
-config TARGET_DAVINCI_SCHMOOGIE
-       bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
-       bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
-       bool "Sonata board"
-
-config TARGET_CALIMAIN
-       bool "Calimain board"
-
-endchoice
-
-config SYS_SOC
-       default "davinci"
-
-source "board/enbw/enbw_cmc/Kconfig"
-source "board/ait/cam_enc_4xx/Kconfig"
-source "board/Barix/ipam390/Kconfig"
-source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
-source "board/omicron/calimain/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
deleted file mode 100644 (file)
index 7d67191..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y                          += cpu.o misc.o timer.o psc.o pinmux.o reset.o
-obj-$(CONFIG_DA850_LOWLEVEL)   += da850_lowlevel.o
-obj-$(CONFIG_SOC_DM355)        += dm355.o
-obj-$(CONFIG_SOC_DM365)        += dm365.o
-obj-$(CONFIG_SOC_DM644X)       += dm644x.o
-obj-$(CONFIG_SOC_DM646X)       += dm646x.o
-obj-$(CONFIG_SOC_DA830)        += da830_pinmux.o
-obj-$(CONFIG_SOC_DA850)        += da850_pinmux.o
-obj-$(CONFIG_DRIVER_TI_EMAC)   += lxt972.o dp83848.o et1011c.o ksz8873.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_FRAMEWORK)    += spl.o
-obj-$(CONFIG_SOC_DM365)        += dm365_lowlevel.o
-obj-$(CONFIG_SOC_DA8XX)        += da850_lowlevel.o
-endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y  += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk
deleted file mode 100644 (file)
index 69e9d5a..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-$(CONFIG_SPL_FRAMEWORK)    += u-boot.ais
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
deleted file mode 100644 (file)
index ff61147..0000000
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL    0x100
-#define PLLC_PLLM      0x110
-#define PLLC_PREDIV    0x114
-#define PLLC_PLLDIV1   0x118
-#define PLLC_PLLDIV2   0x11c
-#define PLLC_PLLDIV3   0x120
-#define PLLC_POSTDIV   0x128
-#define PLLC_BPDIV     0x12c
-#define PLLC_PLLDIV4   0x160
-#define PLLC_PLLDIV5   0x164
-#define PLLC_PLLDIV6   0x168
-#define PLLC_PLLDIV7   0x16c
-#define PLLC_PLLDIV8   0x170
-#define PLLC_PLLDIV9   0x174
-
-#define BIT(x)         (1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV     PLLC_PLLDIV1
-#define DDR_PLLDIV     PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV     PLLC_PLLDIV2
-#define DSP_PLLDIV     PLLC_PLLDIV1
-#define DDR_PLLDIV     PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV     PLLC_PLLDIV1
-#define ARM_PLLDIV     PLLC_PLLDIV2
-#define DDR_PLLDIV     PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-unsigned int sysdiv[9] = {
-       PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
-       PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
-       int pre_div;
-       int pllm;
-       int post_div;
-       int pll_out;
-       unsigned int pll_base;
-
-       pll_out = CONFIG_SYS_OSCIN_FREQ;
-
-       if (id == DAVINCI_AUXCLK_CLKID)
-               goto out;
-
-       if ((id >> 16) == 1)
-               pll_base = (unsigned int)davinci_pllc1_regs;
-       else
-               pll_base = (unsigned int)davinci_pllc0_regs;
-
-       id &= 0xFFFF;
-
-       /*
-        * Lets keep this simple. Combining operations can result in
-        * unexpected approximations
-        */
-       pre_div = (readl(pll_base + PLLC_PREDIV) &
-               DAVINCI_PLLC_DIV_MASK) + 1;
-       pllm = readl(pll_base + PLLC_PLLM) + 1;
-
-       pll_out /= pre_div;
-       pll_out *= pllm;
-
-       if (id == DAVINCI_PLLM_CLKID)
-               goto out;
-
-       post_div = (readl(pll_base + PLLC_POSTDIV) &
-               DAVINCI_PLLC_DIV_MASK) + 1;
-
-       pll_out /= post_div;
-
-       if (id == DAVINCI_PLLC_CLKID)
-               goto out;
-
-       pll_out /= (readl(pll_base + sysdiv[id - 1]) &
-               DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
-       return pll_out;
-}
-
-int set_cpu_clk_info(void)
-{
-       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
-       /* DDR PHY uses an x2 input clock */
-       gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
-                               (clk_get(DAVINCI_DDR_CLKID) / 1000000);
-       gd->bd->bi_dsp_freq = 0;
-       return 0;
-}
-
-#else /* CONFIG_SOC_DA8XX */
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
-       u32     div;
-
-       div = REG(pllbase + offset);
-       return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
-       /* this register read seems to fail on pll0 */
-       if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-               return 8;
-       else
-               return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
-       return pll_div(pllbase, PLLC_PREDIV);
-#endif
-       return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
-       return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
-       if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
-               return pll_div(pllbase, PLLC_POSTDIV);
-#endif
-       return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
-       volatile void   *pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
-       unsigned        base = CONFIG_REFCLK_FREQ / 1000;
-#else
-       unsigned        base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
-       /* the PLL might be bypassed */
-       if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
-               base /= pll_prediv(pllbase);
-#if defined(CONFIG_SOC_DM365)
-               base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
-#else
-               base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-#endif
-               base /= pll_postdiv(pllbase);
-       }
-       return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
-       return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
-       return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
-#endif
-
-int set_cpu_clk_info(void)
-{
-       unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#if defined(CONFIG_SOC_DM365)
-       pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#endif
-       gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
-
-#ifdef DSP_PLLDIV
-       gd->bd->bi_dsp_freq =
-               pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
-#else
-       gd->bd->bi_dsp_freq = 0;
-#endif
-
-       pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#if defined(CONFIG_SOC_DM365)
-       pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#endif
-       gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-
-       return 0;
-}
-
-#endif /* !CONFIG_SOC_DA8XX */
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_DRIVER_TI_EMAC)
-       davinci_emac_initialize();
-#endif
-       return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
deleted file mode 100644 (file)
index edaab45..0000000
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Pinmux configurations for the DA830 SoCs
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI0 pin muxer settings */
-const struct pinmux_config spi0_pins_base[] = {
-       { pinmux(7), 1, 3 },  /* SPI0_SOMI */
-       { pinmux(7), 1, 4 },  /* SPI0_SIMO */
-       { pinmux(7), 1, 6 }   /* SPI0_CLK */
-};
-
-const struct pinmux_config spi0_pins_scs0[] = {
-       { pinmux(7), 1, 7 }   /* SPI0_SCS[0] */
-};
-
-const struct pinmux_config spi0_pins_ena[] = {
-       { pinmux(7), 1, 5 }   /* SPI0_ENA */
-};
-
-/* NAND pin muxer settings */
-const struct pinmux_config emifa_pins_cs0[] = {
-       { pinmux(18), 1, 2 }   /* EMA_CS[0] */
-};
-
-const struct pinmux_config emifa_pins_cs2[] = {
-       { pinmux(18), 1, 3 }   /* EMA_CS[2] */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
-       { pinmux(18), 1, 4 }   /* EMA_CS[3] */
-};
-
-#ifdef CONFIG_USE_NAND
-const struct pinmux_config emifa_pins[] = {
-       { pinmux(13), 1, 6 },  /* EMA_D[0] */
-       { pinmux(13), 1, 7 },  /* EMA_D[1] */
-       { pinmux(14), 1, 0 },  /* EMA_D[2] */
-       { pinmux(14), 1, 1 },  /* EMA_D[3] */
-       { pinmux(14), 1, 2 },  /* EMA_D[4] */
-       { pinmux(14), 1, 3 },  /* EMA_D[5] */
-       { pinmux(14), 1, 4 },  /* EMA_D[6] */
-       { pinmux(14), 1, 5 },  /* EMA_D[7] */
-       { pinmux(14), 1, 6 },  /* EMA_D[8] */
-       { pinmux(14), 1, 7 },  /* EMA_D[9] */
-       { pinmux(15), 1, 0 },  /* EMA_D[10] */
-       { pinmux(15), 1, 1 },  /* EMA_D[11] */
-       { pinmux(15), 1, 2 },  /* EMA_D[12] */
-       { pinmux(15), 1, 3 },  /* EMA_D[13] */
-       { pinmux(15), 1, 4 },  /* EMA_D[14] */
-       { pinmux(15), 1, 5 },  /* EMA_D[15] */
-       { pinmux(15), 1, 6 },  /* EMA_A[0] */
-       { pinmux(15), 1, 7 },  /* EMA_A[1] */
-       { pinmux(16), 1, 0 },  /* EMA_A[2] */
-       { pinmux(16), 1, 1 },  /* EMA_A[3] */
-       { pinmux(16), 1, 2 },  /* EMA_A[4] */
-       { pinmux(16), 1, 3 },  /* EMA_A[5] */
-       { pinmux(16), 1, 4 },  /* EMA_A[6] */
-       { pinmux(16), 1, 5 },  /* EMA_A[7] */
-       { pinmux(16), 1, 6 },  /* EMA_A[8] */
-       { pinmux(16), 1, 7 },  /* EMA_A[9] */
-       { pinmux(17), 1, 0 },  /* EMA_A[10] */
-       { pinmux(17), 1, 1 },  /* EMA_A[11] */
-       { pinmux(17), 1, 2 },  /* EMA_A[12] */
-       { pinmux(17), 1, 3 },  /* EMA_BA[1] */
-       { pinmux(17), 1, 4 },  /* EMA_BA[0] */
-       { pinmux(17), 1, 5 },  /* EMA_CLK */
-       { pinmux(17), 1, 6 },  /* EMA_SDCKE */
-       { pinmux(17), 1, 7 },  /* EMA_CAS */
-       { pinmux(18), 1, 0 },  /* EMA_CAS */
-       { pinmux(18), 1, 1 },  /* EMA_WE */
-       { pinmux(18), 1, 5 },  /* EMA_OE */
-       { pinmux(18), 1, 6 },  /* EMA_WE_DQM[1] */
-       { pinmux(18), 1, 7 },  /* EMA_WE_DQM[0] */
-       { pinmux(10), 1, 0 }   /* Tristate */
-};
-#endif
-
-/* EMAC PHY interface pins */
-const struct pinmux_config emac_pins_rmii[] = {
-       { pinmux(10), 2, 1 },  /* RMII_TXD[0] */
-       { pinmux(10), 2, 2 },  /* RMII_TXD[1] */
-       { pinmux(10), 2, 3 },  /* RMII_TXEN */
-       { pinmux(10), 2, 4 },  /* RMII_CRS_DV */
-       { pinmux(10), 2, 5 },  /* RMII_RXD[0] */
-       { pinmux(10), 2, 6 },  /* RMII_RXD[1] */
-       { pinmux(10), 2, 7 }   /* RMII_RXER */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
-       { pinmux(11), 2, 0 },  /* MDIO_CLK */
-       { pinmux(11), 2, 1 }   /* MDIO_D */
-};
-
-const struct pinmux_config emac_pins_rmii_clk_source[] = {
-       { pinmux(9), 0, 5 }    /* ref.clk from external source */
-};
-
-/* UART2 pin muxer settings */
-const struct pinmux_config uart2_pins_txrx[] = {
-       { pinmux(8), 2, 7 },   /* UART2_RXD */
-       { pinmux(9), 2, 0 }    /* UART2_TXD */
-};
-
-/* I2C0 pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
-       { pinmux(8), 2, 3 },   /* I2C0_SDA */
-       { pinmux(8), 2, 4 }    /* I2C0_SCL */
-};
-
-/* USB0_DRVVBUS pin muxer settings */
-const struct pinmux_config usb_pins[] = {
-       { pinmux(9), 1, 1 }    /* USB0_DRVVBUS */
-};
-
-#ifdef CONFIG_DAVINCI_MMC
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins_8bit[] = {
-       { pinmux(15), 2, 7 },  /* MMCSD0_CLK */
-       { pinmux(16), 2, 0 },  /* MMCSD0_CMD */
-       { pinmux(13), 2, 6 },  /* MMCSD0_DAT_0 */
-       { pinmux(13), 2, 7 },  /* MMCSD0_DAT_1 */
-       { pinmux(14), 2, 0 },  /* MMCSD0_DAT_2 */
-       { pinmux(14), 2, 1 },  /* MMCSD0_DAT_3 */
-       { pinmux(14), 2, 2 },  /* MMCSD0_DAT_4 */
-       { pinmux(14), 2, 3 },  /* MMCSD0_DAT_5 */
-       { pinmux(14), 2, 4 },  /* MMCSD0_DAT_6 */
-       { pinmux(14), 2, 5 }   /* MMCSD0_DAT_7 */
-       /* DA830 supports 8-bit mode */
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
deleted file mode 100644 (file)
index 19730ce..0000000
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * SoC-specific lowlevel code for DA850
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/pll_defs.h>
-
-void davinci_enable_uart0(void)
-{
-       lpsc_on(DAVINCI_LPSC_UART0);
-
-       /* Bringup UART0 out of reset */
-       REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-#if defined(CONFIG_SYS_DA850_PLL_INIT)
-static void da850_waitloop(unsigned long loopcnt)
-{
-       unsigned long   i;
-
-       for (i = 0; i < loopcnt; i++)
-               asm("   NOP");
-}
-
-static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
-{
-       if (reg == davinci_pllc0_regs)
-               /* Unlock PLL registers. */
-               clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
-
-       /*
-        * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
-        * through MMR
-        */
-       clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
-       /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
-       clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
-
-       /* Set PLLEN=0 => PLL BYPASS MODE */
-       clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
-
-       da850_waitloop(150);
-
-       if (reg == davinci_pllc0_regs) {
-               /*
-                * Select the Clock Mode bit 8 as External Clock or On Chip
-                * Oscilator
-                */
-               dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
-               setbits_le32(&reg->pllctl,
-                       (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
-       }
-
-       /* Clear PLLRST bit to reset the PLL */
-       clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
-
-       /* Disable the PLL output */
-       setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
-
-       /* PLL initialization sequence */
-       /*
-        * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
-        * power down bit
-        */
-       clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
-
-       /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
-       clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
-
-#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
-       /* program the prediv */
-       if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
-               writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
-                       &reg->prediv);
-#endif
-
-       /* Program the required multiplier value in PLLM */
-       writel(pllmult, &reg->pllm);
-
-       /* program the postdiv */
-       if (reg == davinci_pllc0_regs)
-               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
-                       &reg->postdiv);
-       else
-               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
-                       &reg->postdiv);
-
-       /*
-        * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
-        * no GO operation is currently in progress
-        */
-       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
-               ;
-
-       if (reg == davinci_pllc0_regs) {
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
-               writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
-       } else {
-               writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
-               writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
-               writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
-       }
-
-       /*
-        * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
-        * transition.
-        */
-       setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
-
-       /*
-        * Wait for the GOSTAT bit in PLLSTAT to clear to 0
-        * (completion of phase alignment).
-        */
-       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
-               ;
-
-       /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
-       da850_waitloop(200);
-
-       /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
-       setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
-
-       /* Wait for PLL to lock. See PLL spec for PLL lock time */
-       da850_waitloop(2400);
-
-       /*
-        * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
-        * mode
-        */
-       setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
-
-
-       /*
-        * clear EMIFA and EMIFB clock source settings, let them
-        * run off SYSCLK
-        */
-       if (reg == davinci_pllc0_regs)
-               dv_maskbits(&davinci_syscfg_regs->cfgchip3,
-                       ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
-
-       return 0;
-}
-#endif /* CONFIG_SYS_DA850_PLL_INIT */
-
-#if defined(CONFIG_SYS_DA850_DDR_INIT)
-static int da850_ddr_setup(void)
-{
-       unsigned long   tmp;
-
-       /* Enable the Clock to DDR2/mDDR */
-       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
-       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-       if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
-               /* Begin VTP Calibration */
-               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-
-               /* Polling READY bit to see when VTP calibration is done */
-               tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-               while ((tmp & VTP_READY) != VTP_READY)
-                       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-       }
-       setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
-       writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
-       if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
-               /* DDR2 */
-               clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
-                       (1 << DDR_SLEW_DDR_PDENA_BIT) |
-                       (1 << DDR_SLEW_CMOSEN_BIT));
-       } else {
-               /* MOBILE DDR */
-               setbits_le32(&davinci_syscfg1_regs->ddr_slew,
-                       (1 << DDR_SLEW_DDR_PDENA_BIT) |
-                       (1 << DDR_SLEW_CMOSEN_BIT));
-       }
-
-       /*
-        * SDRAM Configuration Register (SDCR):
-        * First set the BOOTUNLOCK bit to make configuration bits
-        * writeable.
-        */
-       setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
-
-       /*
-        * Write the new value of these bits and clear BOOTUNLOCK.
-        * At the same time, set the TIMUNLOCK bit to allow changing
-        * the timing registers
-        */
-       tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
-       tmp &= ~DV_DDR_BOOTUNLOCK;
-       tmp |= DV_DDR_TIMUNLOCK;
-       writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
-
-       /* write memory configuration and timing */
-       if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
-               /* MOBILE DDR only*/
-               writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
-                       &dv_ddr2_regs_ctrl->sdbcr2);
-       }
-       writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-       writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
-       /* clear the TIMUNLOCK bit and write the value of the CL field */
-       tmp &= ~DV_DDR_TIMUNLOCK;
-       writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
-
-       /*
-        * LPMODEN and MCLKSTOPEN must be set!
-        * Without this bits set, PSC don;t switch states !!
-        */
-       writel(CONFIG_SYS_DA850_DDR2_SDRCR |
-               (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
-               (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
-               &dv_ddr2_regs_ctrl->sdrcr);
-
-       /* SyncReset the Clock to EMIF3A SDRAM */
-       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
-       /* Enable the Clock to EMIF3A SDRAM */
-       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
-       /* disable self refresh */
-       clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
-               DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
-       writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
-       return 0;
-}
-#endif /* CONFIG_SYS_DA850_DDR_INIT */
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
-       return;
-}
-
-int arch_cpu_init(void)
-{
-       /* Unlock kick registers */
-       writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
-       writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
-
-       dv_maskbits(&davinci_syscfg_regs->suspsrc,
-               CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
-
-       /* configure pinmux settings */
-       if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
-               return 1;
-
-#if defined(CONFIG_SYS_DA850_PLL_INIT)
-       /* PLL setup */
-       da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
-       da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
-#endif
-       /* setup CSn config */
-#if defined(CONFIG_SYS_DA850_CS2CFG)
-       writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
-#endif
-#if defined(CONFIG_SYS_DA850_CS3CFG)
-       writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
-#endif
-
-       da8xx_configure_lpsc_items(lpsc, lpsc_size);
-
-       /* GPIO setup */
-       board_gpio_init();
-
-
-       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
-                       CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
-       /*
-        * Fix Power and Emulation Management Register
-        * see sprufw3a.pdf page 37 Table 24
-        */
-       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
-               DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
-              &davinci_uart0_ctrl_regs->pwremu_mgmt);
-#else
-              &davinci_uart2_ctrl_regs->pwremu_mgmt);
-#endif
-
-#if defined(CONFIG_SYS_DA850_DDR_INIT)
-       da850_ddr_setup();
-#endif
-
-       return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
deleted file mode 100644 (file)
index 6105f63..0000000
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Pinmux configurations for the DA850 SoCs
- *
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI pin muxer settings */
-const struct pinmux_config spi1_pins_base[] = {
-       { pinmux(5), 1, 2 }, /* SPI1_CLK */
-       { pinmux(5), 1, 4 }, /* SPI1_SOMI */
-       { pinmux(5), 1, 5 }, /* SPI1_SIMO */
-};
-
-const struct pinmux_config spi1_pins_scs0[] = {
-       { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
-};
-
-/* UART pin muxer settings */
-const struct pinmux_config uart0_pins_txrx[] = {
-       { pinmux(3), 2, 4 }, /* UART0_RXD */
-       { pinmux(3), 2, 5 }, /* UART0_TXD */
-};
-
-const struct pinmux_config uart0_pins_rtscts[] = {
-       { pinmux(3), 2, 6 },
-       { pinmux(3), 2, 7 },
-};
-
-const struct pinmux_config uart1_pins_txrx[] = {
-       { pinmux(4), 2, 6 }, /* UART1_RXD */
-       { pinmux(4), 2, 7 }, /* UART1_TXD */
-};
-
-const struct pinmux_config uart2_pins_txrx[] = {
-       { pinmux(4), 2, 4 }, /* UART2_RXD */
-       { pinmux(4), 2, 5 }, /* UART2_TXD */
-};
-
-const struct pinmux_config uart2_pins_rtscts[] = {
-       { pinmux(0), 4, 6 }, /* UART2_RTS */
-       { pinmux(0), 4, 7 }, /* UART2_CTS */
-};
-
-/* EMAC pin muxer settings*/
-const struct pinmux_config emac_pins_rmii[] = {
-       { pinmux(14), 8, 2 }, /* RMII_TXD[1] */
-       { pinmux(14), 8, 3 }, /* RMII_TXD[0] */
-       { pinmux(14), 8, 4 }, /* RMII_TXEN */
-       { pinmux(14), 8, 5 }, /* RMII_RXD[1] */
-       { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
-       { pinmux(14), 8, 7 }, /* RMII_RXER */
-       { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */
-       { pinmux(15), 8, 1 }, /* RMII_CRS_DV */
-};
-
-const struct pinmux_config emac_pins_mii[] = {
-       { pinmux(2), 8, 1 }, /* MII_TXEN */
-       { pinmux(2), 8, 2 }, /* MII_TXCLK */
-       { pinmux(2), 8, 3 }, /* MII_COL */
-       { pinmux(2), 8, 4 }, /* MII_TXD[3] */
-       { pinmux(2), 8, 5 }, /* MII_TXD[2] */
-       { pinmux(2), 8, 6 }, /* MII_TXD[1] */
-       { pinmux(2), 8, 7 }, /* MII_TXD[0] */
-       { pinmux(3), 8, 0 }, /* MII_RXCLK */
-       { pinmux(3), 8, 1 }, /* MII_RXDV */
-       { pinmux(3), 8, 2 }, /* MII_RXER */
-       { pinmux(3), 8, 3 }, /* MII_CRS */
-       { pinmux(3), 8, 4 }, /* MII_RXD[3] */
-       { pinmux(3), 8, 5 }, /* MII_RXD[2] */
-       { pinmux(3), 8, 6 }, /* MII_RXD[1] */
-       { pinmux(3), 8, 7 }, /* MII_RXD[0] */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
-       { pinmux(4), 8, 0 }, /* MDIO_CLK */
-       { pinmux(4), 8, 1 }, /* MDIO_D */
-};
-
-/* I2C pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
-       { pinmux(4), 2, 2 }, /* I2C0_SCL */
-       { pinmux(4), 2, 3 }, /* I2C0_SDA */
-};
-
-const struct pinmux_config i2c1_pins[] = {
-       { pinmux(4), 4, 4 }, /* I2C1_SCL */
-       { pinmux(4), 4, 5 }, /* I2C1_SDA */
-};
-
-/* EMIFA pin muxer settings */
-const struct pinmux_config emifa_pins_cs2[] = {
-       { pinmux(7), 1, 0 }, /* EMA_CS2 */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
-       { pinmux(7), 1, 1 }, /* EMA_CS[3] */
-};
-
-const struct pinmux_config emifa_pins_cs4[] = {
-       { pinmux(7), 1, 2 }, /* EMA_CS[4] */
-};
-
-const struct pinmux_config emifa_pins_nand[] = {
-       { pinmux(7), 1, 4 },  /* EMA_WE */
-       { pinmux(7), 1, 5 },  /* EMA_OE */
-       { pinmux(9), 1, 0 },  /* EMA_D[7] */
-       { pinmux(9), 1, 1 },  /* EMA_D[6] */
-       { pinmux(9), 1, 2 },  /* EMA_D[5] */
-       { pinmux(9), 1, 3 },  /* EMA_D[4] */
-       { pinmux(9), 1, 4 },  /* EMA_D[3] */
-       { pinmux(9), 1, 5 },  /* EMA_D[2] */
-       { pinmux(9), 1, 6 },  /* EMA_D[1] */
-       { pinmux(9), 1, 7 },  /* EMA_D[0] */
-       { pinmux(12), 1, 5 }, /* EMA_A[2] */
-       { pinmux(12), 1, 6 }, /* EMA_A[1] */
-};
-
-/* NOR pin muxer settings */
-const struct pinmux_config emifa_pins_nor[] = {
-       { pinmux(5), 1, 6 },  /* EMA_BA[1] */
-       { pinmux(6), 1, 6 },  /* EMA_WAIT[1] */
-       { pinmux(7), 1, 4 },  /* EMA_WE */
-       { pinmux(7), 1, 5 },  /* EMA_OE */
-       { pinmux(8), 1, 0 },  /* EMA_D[15] */
-       { pinmux(8), 1, 1 },  /* EMA_D[14] */
-       { pinmux(8), 1, 2 },  /* EMA_D[13] */
-       { pinmux(8), 1, 3 },  /* EMA_D[12] */
-       { pinmux(8), 1, 4 },  /* EMA_D[11] */
-       { pinmux(8), 1, 5 },  /* EMA_D[10] */
-       { pinmux(8), 1, 6 },  /* EMA_D[9] */
-       { pinmux(8), 1, 7 },  /* EMA_D[8] */
-       { pinmux(9), 1, 0 },  /* EMA_D[7] */
-       { pinmux(9), 1, 1 },  /* EMA_D[6] */
-       { pinmux(9), 1, 2 },  /* EMA_D[5] */
-       { pinmux(9), 1, 3 },  /* EMA_D[4] */
-       { pinmux(9), 1, 4 },  /* EMA_D[3] */
-       { pinmux(9), 1, 5 },  /* EMA_D[2] */
-       { pinmux(9), 1, 6 },  /* EMA_D[1] */
-       { pinmux(9), 1, 7 },  /* EMA_D[0] */
-       { pinmux(10), 1, 1 }, /* EMA_A[22] */
-       { pinmux(10), 1, 2 }, /* EMA_A[21] */
-       { pinmux(10), 1, 3 }, /* EMA_A[20] */
-       { pinmux(10), 1, 4 }, /* EMA_A[19] */
-       { pinmux(10), 1, 5 }, /* EMA_A[18] */
-       { pinmux(10), 1, 6 }, /* EMA_A[17] */
-       { pinmux(10), 1, 7 }, /* EMA_A[16] */
-       { pinmux(11), 1, 0 }, /* EMA_A[15] */
-       { pinmux(11), 1, 1 }, /* EMA_A[14] */
-       { pinmux(11), 1, 2 }, /* EMA_A[13] */
-       { pinmux(11), 1, 3 }, /* EMA_A[12] */
-       { pinmux(11), 1, 4 }, /* EMA_A[11] */
-       { pinmux(11), 1, 5 }, /* EMA_A[10] */
-       { pinmux(11), 1, 6 }, /* EMA_A[9] */
-       { pinmux(11), 1, 7 }, /* EMA_A[8] */
-       { pinmux(12), 1, 0 }, /* EMA_A[7] */
-       { pinmux(12), 1, 1 }, /* EMA_A[6] */
-       { pinmux(12), 1, 2 }, /* EMA_A[5] */
-       { pinmux(12), 1, 3 }, /* EMA_A[4] */
-       { pinmux(12), 1, 4 }, /* EMA_A[3] */
-       { pinmux(12), 1, 5 }, /* EMA_A[2] */
-       { pinmux(12), 1, 6 }, /* EMA_A[1] */
-       { pinmux(12), 1, 7 }, /* EMA_A[0] */
-};
-
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins[] = {
-       { pinmux(10), 2, 0 },   /* MMCSD0_CLK */
-       { pinmux(10), 2, 1 },   /* MMCSD0_CMD */
-       { pinmux(10), 2, 2 },   /* MMCSD0_DAT_0 */
-       { pinmux(10), 2, 3 },   /* MMCSD0_DAT_1 */
-       { pinmux(10), 2, 4 },   /* MMCSD0_DAT_2 */
-       { pinmux(10), 2, 5 },   /* MMCSD0_DAT_3 */
-       /* DA850 supports only 4-bit mode, remaining pins are not configured */
-};
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c
deleted file mode 100644 (file)
index f9550a1..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
-       lpsc_on(DAVINCI_LPSC_UART0);
-
-       /* Bringup UART0 out of reset */
-       REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-       lpsc_on(DAVINCI_LPSC_I2C);
-
-       /* Enable I2C pin Mux */
-       REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c
deleted file mode 100644 (file)
index f6ca527..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SoC-specific code for tms320dm365 and similar chips
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-       lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-       lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
deleted file mode 100644 (file)
index c8b4498..0000000
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- * Actually used for booting from NAND with nand_spl.
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <asm/arch/hardware.h>
-
-void dm365_waitloop(unsigned long loopcnt)
-{
-       unsigned long   i;
-
-       for (i = 0; i < loopcnt; i++)
-               asm("   NOP");
-}
-
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
-{
-       unsigned int clksrc = 0x0;
-
-       /* Power up the PLL */
-       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
-
-       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
-       setbits_le32(&dv_pll0_regs->pllctl,
-               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
-       /*
-        * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
-        * through MMR
-        */
-       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
-
-       /* Set PLLEN=0 => PLL BYPASS MODE */
-       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
-       dm365_waitloop(150);
-
-        /* PLLRST=1(reset assert) */
-       setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
-       dm365_waitloop(300);
-
-       /*Bring PLL out of Reset*/
-       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
-       /* Program the Multiper and Pre-Divider for PLL1 */
-       writel(pllmult, &dv_pll0_regs->pllm);
-       writel(prediv, &dv_pll0_regs->prediv);
-
-       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
-       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
-               PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
-       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
-               &dv_pll0_regs->secctl);
-       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
-       writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
-       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
-       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-
-       /* Program the PostDiv for PLL1 */
-       writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
-
-       /* Post divider setting for PLL1 */
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
-       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
-
-       dm365_waitloop(300);
-
-       /* Set the GOSET bit */
-       writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
-
-       dm365_waitloop(300);
-
-       /* Wait for PLL to LOCK */
-       while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
-               == PLL0_LOCK))
-               ;
-
-       /* Enable the PLL Bit of PLLCTL*/
-       setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
-       return 0;
-}
-
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
-{
-       unsigned int clksrc = 0x0;
-
-       /* Power up the PLL*/
-       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
-
-       /*
-        * Select the Clock Mode as Onchip Oscilator or External Clock on
-        * MXI pin
-        * VDB has input on MXI pin
-        */
-       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
-       setbits_le32(&dv_pll1_regs->pllctl,
-               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
-       /*
-        * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
-        * through MMR
-        */
-       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
-
-       /* Set PLLEN=0 => PLL BYPASS MODE */
-       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
-       dm365_waitloop(50);
-
-        /* PLLRST=1(reset assert) */
-       setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
-       dm365_waitloop(300);
-
-       /* Bring PLL out of Reset */
-       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
-       /* Program the Multiper and Pre-Divider for PLL2 */
-       writel(pllm, &dv_pll1_regs->pllm);
-       writel(prediv, &dv_pll1_regs->prediv);
-
-       writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
-
-       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
-       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
-               PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
-       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
-               &dv_pll1_regs->secctl);
-       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
-       writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
-       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
-       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-
-       /* Post divider setting for PLL2 */
-       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
-       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
-       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
-       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
-       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
-
-       /* GoCmd for PostDivider to take effect */
-       writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
-
-       dm365_waitloop(150);
-
-       /* Wait for PLL to LOCK */
-       while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
-               == PLL1_LOCK))
-               ;
-
-       dm365_waitloop(4100);
-
-       /* Enable the PLL2 */
-       setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
-       /* do this after PLL's have been set up */
-       writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
-               &dv_sys_module_regs->peri_clkctl);
-
-       return 0;
-}
-
-int dm365_ddr_setup(void)
-{
-       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-       clrbits_le32(&dv_sys_module_regs->vtpiocr,
-               VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
-
-       /* Set bit CLRZ (bit 13) */
-       setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
-
-       /* Check VTP READY Status */
-       while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
-               ;
-
-       /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
-       setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
-
-       /* Set bit LOCK(bit7) */
-       setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
-
-       /*
-        * Powerdown VTP as it is locked (bit 6)
-        * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
-        */
-       setbits_le32(&dv_sys_module_regs->vtpiocr,
-               VPTIO_IOPWRDN | VPTIO_PWRDN);
-
-       /* Wait for calibration to complete */
-       dm365_waitloop(150);
-
-       /* Set the DDR2 to synreset, then enable it again */
-       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
-       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
-       writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
-       /* Program SDRAM Bank Config Register */
-       writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
-               &dv_ddr2_regs_ctrl->sdbcr);
-       writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
-               &dv_ddr2_regs_ctrl->sdbcr);
-
-       /* Program SDRAM Timing Control Register1 */
-       writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
-       /* Program SDRAM Timing Control Register2 */
-       writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
-       writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
-       writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
-
-       /* Program SDRAM Refresh Control Register */
-       writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
-
-       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
-       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
-       return 0;
-}
-
-static void dm365_vpss_sync_reset(void)
-{
-       unsigned int PdNum = 0;
-
-       /* VPSS_CLKMD 1:1 */
-       setbits_le32(&dv_sys_module_regs->vpss_clkctl,
-               VPSS_CLK_CTL_VPSS_CLKMD);
-
-       /* LPSC SyncReset DDR Clock Enable */
-       writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
-               ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
-               &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
-
-       writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
-       while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
-               ;
-       while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
-               PSC_MD_STATE_MSK) == PSC_SYNCRESET))
-               ;
-}
-
-static void dm365_por_reset(void)
-{
-       struct davinci_timer *wdog =
-               (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
-       if (readl(&dv_pll0_regs->rstype) &
-               (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
-               dm365_vpss_sync_reset();
-
-               writel(DV_TMPBUF_VAL, TMPBUF);
-               setbits_le32(TMPSTATUS, FLAG_PORRST);
-               writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
-               writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
-               while (1);
-       }
-}
-
-static void dm365_wdt_reset(void)
-{
-       struct davinci_timer *wdog =
-               (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
-       if (readl(TMPBUF) != DV_TMPBUF_VAL) {
-               writel(DV_TMPBUF_VAL, TMPBUF);
-               setbits_le32(TMPSTATUS, FLAG_PORRST);
-               setbits_le32(TMPSTATUS, FLAG_FLGOFF);
-
-               dm365_waitloop(100);
-
-               dm365_vpss_sync_reset();
-
-               writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
-               writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
-               while (1);
-       }
-}
-
-static void dm365_wdt_flag_on(void)
-{
-       /* VPSS_CLKMD 1:2 */
-       clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
-               VPSS_CLK_CTL_VPSS_CLKMD);
-       writel(0, TMPBUF);
-       setbits_le32(TMPSTATUS, FLAG_FLGON);
-}
-
-void dm365_psc_init(void)
-{
-       unsigned char i = 0;
-       unsigned char lpsc_start;
-       unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
-       unsigned int  PdNum = 0;
-
-       lpscmin = 0;
-       lpscmax = 2;
-
-       for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
-               if (lpscgroup == 0) {
-                       /* Enabling LPSC 3 to 28 SCR first */
-                       lpsc_start = DAVINCI_LPSC_VPSSMSTR;
-                       lpsc_end   = DAVINCI_LPSC_TIMER1;
-               } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
-                       lpsc_start = DAVINCI_LPSC_CFG5;
-                       lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
-               } else {
-                       lpsc_start = DAVINCI_LPSC_MJCP;
-                       lpsc_end   = DAVINCI_LPSC_HDVICP;
-               }
-
-               /* NEXT=0x3, Enable LPSC's */
-               for (i = lpsc_start; i <= lpsc_end; i++)
-                       setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
-
-               /*
-                * Program goctl to start transition sequence for LPSCs
-                * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
-                * Domain 0 Modules
-                */
-               writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
-               /*
-                * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
-                */
-               while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
-                       == 0))
-                       ;
-
-               /* Wait for MODSTAT = ENABLE from LPSC's */
-               for (i = lpsc_start; i <= lpsc_end; i++)
-                       while (!((readl(&dv_psc_regs->mdstat[i]) &
-                               PSC_MD_STATE_MSK) == PSC_ENABLE))
-                               ;
-       }
-}
-
-static void dm365_emif_init(void)
-{
-       writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
-       writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
-
-       setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
-
-       writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
-
-       return;
-}
-
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
-       unsigned long value)
-{
-       clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
-       setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
-       return;
-}
-
-#if defined(CONFIG_POST)
-int post_log(char *format, ...)
-{
-       return 0;
-}
-#endif
-
-void dm36x_lowlevel_init(ulong bootflag)
-{
-       struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
-               (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
-               DAVINCI_UART_CTRL_BASE);
-
-       /* Mask all interrupts */
-       writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
-       writel(0x0, &dv_aintc_regs->eabase);
-       writel(0x0, &dv_aintc_regs->eint0);
-       writel(0x0, &dv_aintc_regs->eint1);
-
-       /* Clear all interrupts */
-       writel(0xffffffff, &dv_aintc_regs->fiq0);
-       writel(0xffffffff, &dv_aintc_regs->fiq1);
-       writel(0xffffffff, &dv_aintc_regs->irq0);
-       writel(0xffffffff, &dv_aintc_regs->irq1);
-
-       dm365_por_reset();
-       dm365_wdt_reset();
-
-       /* System PSC setup - enable all */
-       dm365_psc_init();
-
-       /* Setup Pinmux */
-       dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
-       dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
-       dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
-       dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
-       dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
-
-       /* PLL setup */
-       dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
-               CONFIG_SYS_DM36x_PLL1_PREDIV);
-       dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
-               CONFIG_SYS_DM36x_PLL2_PREDIV);
-
-       /* GPIO setup */
-       board_gpio_init();
-
-       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
-                       CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
-       /*
-        * Fix Power and Emulation Management Register
-        * see sprufh2.pdf page 38 Table 22
-        */
-       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
-               DAVINCI_UART_PWREMU_MGMT_UTRST),
-              &davinci_uart_ctrl_regs->pwremu_mgmt);
-
-       puts("ddr init\n");
-       dm365_ddr_setup();
-
-       puts("emif init\n");
-       dm365_emif_init();
-
-       dm365_wdt_flag_on();
-
-#if defined(CONFIG_POST)
-       /*
-        * Do memory tests, calls arch_memory_failure_handle()
-        * if error detected.
-        */
-       memory_post_test(0);
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c
deleted file mode 100644 (file)
index c58e271..0000000
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
-
-void davinci_enable_uart0(void)
-{
-       lpsc_on(DAVINCI_LPSC_UART0);
-
-       /* Bringup UART0 out of reset */
-       REG(UART0_PWREMU_MGMT) = 0x00006001;
-
-       /* Enable UART0 MUX lines */
-       REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-       lpsc_on(DAVINCI_LPSC_EMAC);
-       lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-       lpsc_on(DAVINCI_LPSC_MDIO);
-
-       /* Enable GIO3.3V cells used for EMAC */
-       REG(VDD3P3V_PWDN) = 0;
-
-       /* Enable EMAC. */
-       REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-       lpsc_on(DAVINCI_LPSC_I2C);
-
-       /* Enable I2C pin Mux */
-       REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
-       /*
-        * Workaround for TMS320DM6446 errata 1.3.22:
-        *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-        *   Revision(s) Affected: 1.3 and earlier
-        */
-       REG(PSC_SILVER_BULLET) = 0;
-
-       /*
-        * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-        * as suggested in TMS320DM6446 errata 2.1.2:
-        *
-        * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-        * low priority modules can occupy the bus and prevent high priority
-        * modules like the VPSS from getting the required DDR2 throughput.
-        * A hex value of 0x20 should provide a good ARM (cache enabled)
-        * performance and still allow good utilization by the VPSS or other
-        * modules.
-        */
-       REG(VBPR) = 0x20;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c
deleted file mode 100644 (file)
index cfea830..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SoC-specific code for TMS320DM646x chips
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
-       lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-       lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
-       lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c
deleted file mode 100644 (file)
index 603d507..0000000
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <dp83848.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int dp83848_is_phy_connected(int phy_addr)
-{
-       u_int16_t       id1, id2;
-
-       if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
-               return(0);
-       if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
-               return(0);
-
-       if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
-               return(1);
-
-       return(0);
-}
-
-int dp83848_get_link_speed(int phy_addr)
-{
-       u_int16_t               tmp;
-       volatile emac_regs*     emac = (emac_regs *)EMAC_BASE_ADDR;
-
-       if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
-               return(0);
-
-       if (!(tmp & DP83848_LINK_STATUS))       /* link up? */
-               return(0);
-
-       if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
-               return(0);
-
-       /* Speed doesn't matter, there is no setting for it in EMAC... */
-       if (tmp & DP83848_DUPLEX) {
-               /* set DM644x EMAC for Full Duplex  */
-               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
-                       EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-       } else {
-               /*set DM644x EMAC for Half Duplex  */
-               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-       }
-
-       return(1);
-}
-
-
-int dp83848_init_phy(int phy_addr)
-{
-       int     ret = 1;
-
-       if (!dp83848_get_link_speed(phy_addr)) {
-               /* Try another time */
-               udelay(100000);
-               ret = dp83848_get_link_speed(phy_addr);
-       }
-
-       /* Disable PHY Interrupts */
-       davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
-
-       return(ret);
-}
-
-
-int dp83848_auto_negotiate(int phy_addr)
-{
-       u_int16_t       tmp;
-
-
-       if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
-               return(0);
-
-       /* Restart Auto_negotiation  */
-       tmp &= ~DP83848_AUTONEG;        /* remove autonegotiation enable */
-       tmp |= DP83848_ISOLATE;         /* Electrically isolate PHY */
-       davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-       /* Set the Auto_negotiation Advertisement Register
-        * MII advertising for Next page, 100BaseTxFD and HD,
-        * 10BaseTFD and HD, IEEE 802.3
-        */
-       tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
-               DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
-       davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
-
-
-       /* Read Control Register */
-       if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
-               return(0);
-
-       tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
-       davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-       /* Restart Auto_negotiation  */
-       tmp |= DP83848_RESTART_AUTONEG;
-       davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
-       /*check AutoNegotiate complete */
-       udelay(10000);
-       if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
-               return(0);
-
-       if (!(tmp & DP83848_AUTONEG_COMP))
-               return(0);
-
-       return (dp83848_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
deleted file mode 100644 (file)
index 9d53875..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
-
-#define MII_PHY_CONFIG_REG             22
-
-/* PHY Config bits */
-#define PHY_SYS_CLK_EN                 (1 << 4)
-
-int et1011c_get_link_speed(int phy_addr)
-{
-       u_int16_t       data;
-
-       if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
-               davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
-               /* Enable 125MHz clock sourced from PHY */
-               davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
-                       data | PHY_SYS_CLK_EN);
-               return (1);
-       }
-       return (0);
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
deleted file mode 100644 (file)
index 4af5dd2..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Micrel KSZ8873 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2011 Heiko Schocher <hsdenx.de>
- *
- * based on:
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-int ksz8873_is_phy_connected(int phy_addr)
-{
-       u_int16_t       dummy;
-
-       return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
-}
-
-int ksz8873_get_link_speed(int phy_addr)
-{
-       emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
-       /* we always have a link to the switch, 100 FD */
-       writel((EMAC_MACCONTROL_MIIEN_ENABLE |
-               EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
-              &emac->MACCONTROL);
-       return 1;
-}
-
-
-int ksz8873_init_phy(int phy_addr)
-{
-       return 1;
-}
-
-
-int ksz8873_auto_negotiate(int phy_addr)
-{
-       return dp83848_get_link_speed(phy_addr);
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
deleted file mode 100644 (file)
index e916234..0000000
+++ /dev/null
@@ -1,693 +0,0 @@
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE   0x3f
-
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
-       /*-------------------------------------------------------*
-        * Mask all IRQs by setting all bits in the EINT default *
-        *-------------------------------------------------------*/
-       mov     r1, $0
-       ldr     r0, =EINT_ENABLE0
-       str     r1, [r0]
-       ldr     r0, =EINT_ENABLE1
-       str     r1, [r0]
-
-       /*------------------------------------------------------*
-        * Put the GEM in reset                                 *
-        *------------------------------------------------------*/
-
-       /* Put the GEM in reset */
-       ldr     r8, PSC_GEM_FLAG_CLEAR
-       ldr     r6, MDCTL_GEM
-       ldr     r7, [r6]
-       and     r7, r7, r8
-       str     r7, [r6]
-
-       /* Enable the Power Domain Transition Command */
-       ldr     r6, PTCMD
-       ldr     r7, [r6]
-       orr     r7, r7, $0x02
-       str     r7, [r6]
-
-       /* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
-       ldr     r6, PTSTAT
-       ldr     r7, [r6]
-       ands    r7, r7, $0x02
-       bne     checkStatClkStopGem
-
-       /* Check for GEM Reset Completion */
-checkGemStatClkStop:
-       ldr     r6, MDSTAT_GEM
-       ldr     r7, [r6]
-       ands    r7, r7, $0x100
-       bne     checkGemStatClkStop
-
-       /* Do this for enabling a WDT initiated reset this is a workaround
-          for a chip bug.  Not required under normal situations */
-       ldr     r6, P1394
-       mov     r10, $0
-       str     r10, [r6]
-
-       /*------------------------------------------------------*
-        * Enable L1 & L2 Memories in Fast mode                 *
-        *------------------------------------------------------*/
-       ldr     r6, DFT_ENABLE
-       mov     r10, $0x01
-       str     r10, [r6]
-
-       ldr     r6, MMARG_BRF0
-       ldr     r10, MMARG_BRF0_VAL
-       str     r10, [r6]
-
-       ldr     r6, DFT_ENABLE
-       mov     r10, $0
-       str     r10, [r6]
-
-       /*------------------------------------------------------*
-        * DDR2 PLL Initialization                              *
-        *------------------------------------------------------*/
-
-       /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-       mov     r10, $0
-       ldr     r6, PLL2_CTL
-       ldr     r7, PLL_CLKSRC_MASK
-       ldr     r8, [r6]
-       and     r8, r8, r7
-       mov     r9, r10, lsl $8
-       orr     r8, r8, r9
-       str     r8, [r6]
-
-       /* Select the PLLEN source */
-       ldr     r7, PLL_ENSRC_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Bypass the PLL */
-       ldr     r7, PLL_BYPASS_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-       mov     r10, $0x20
-WaitPPL2Loop:
-       subs    r10, r10, $1
-       bne     WaitPPL2Loop
-
-       /* Reset the PLL */
-       ldr     r7, PLL_RESET_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Power up the PLL */
-       ldr     r7, PLL_PWRUP_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Enable the PLL from Disable Mode */
-       ldr     r7, PLL_DISABLE_ENABLE_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Program the PLL Multiplier */
-       ldr     r6, PLL2_PLLM
-       mov     r2, $0x17       /* 162 MHz */
-       str     r2, [r6]
-
-       /* Program the PLL2 Divisor Value */
-       ldr     r6, PLL2_DIV2
-       mov     r3, $0x01
-       str     r3, [r6]
-
-       /* Program the PLL2 Divisor Value */
-       ldr     r6, PLL2_DIV1
-       mov     r4, $0x0b       /* 54 MHz */
-       str     r4, [r6]
-
-       /* PLL2 DIV2 MMR */
-       ldr     r8, PLL2_DIV_MASK
-       ldr     r6, PLL2_DIV2
-       ldr     r9, [r6]
-       and     r8, r8, r9
-       mov     r9, $0x01
-       mov     r9, r9, lsl $15
-       orr     r8, r8, r9
-       str     r8, [r6]
-
-       /* Program the GOSET bit to take new divider values */
-       ldr     r6, PLL2_PLLCMD
-       ldr     r7, [r6]
-       orr     r7, r7, $0x01
-       str     r7, [r6]
-
-       /* Wait for Done */
-       ldr     r6, PLL2_PLLSTAT
-doneLoop_0:
-       ldr     r7, [r6]
-       ands    r7, r7, $0x01
-       bne     doneLoop_0
-
-       /* PLL2 DIV1 MMR */
-       ldr     r8, PLL2_DIV_MASK
-       ldr     r6, PLL2_DIV1
-       ldr     r9, [r6]
-       and     r8, r8, r9
-       mov     r9, $0x01
-       mov     r9, r9, lsl $15
-       orr     r8, r8, r9
-       str     r8, [r6]
-
-       /* Program the GOSET bit to take new divider values */
-       ldr     r6, PLL2_PLLCMD
-       ldr     r7, [r6]
-       orr     r7, r7, $0x01
-       str     r7, [r6]
-
-       /* Wait for Done */
-       ldr     r6, PLL2_PLLSTAT
-doneLoop:
-       ldr     r7, [r6]
-       ands    r7, r7, $0x01
-       bne     doneLoop
-
-       /* Wait for PLL to Reset Properly */
-       mov     r10, $0x218
-ResetPPL2Loop:
-       subs    r10, r10, $1
-       bne     ResetPPL2Loop
-
-       /* Bring PLL out of Reset */
-       ldr     r6, PLL2_CTL
-       ldr     r8, [r6]
-       orr     r8, r8, $0x08
-       str     r8, [r6]
-
-       /* Wait for PLL to Lock */
-       ldr     r10, PLL_LOCK_COUNT
-PLL2Lock:
-       subs    r10, r10, $1
-       bne     PLL2Lock
-
-       /* Enable the PLL */
-       ldr     r6, PLL2_CTL
-       ldr     r8, [r6]
-       orr     r8, r8, $0x01
-       str     r8, [r6]
-
-       /*------------------------------------------------------*
-        * Issue Soft Reset to DDR Module                       *
-        *------------------------------------------------------*/
-
-       /* Shut down the DDR2 LPSC Module */
-       ldr     r8, PSC_FLAG_CLEAR
-       ldr     r6, MDCTL_DDR2
-       ldr     r7, [r6]
-       and     r7, r7, r8
-       orr     r7, r7, $0x03
-       str     r7, [r6]
-
-       /* Enable the Power Domain Transition Command */
-       ldr     r6, PTCMD
-       ldr     r7, [r6]
-       orr     r7, r7, $0x01
-       str     r7, [r6]
-
-       /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
-       ldr     r6, PTSTAT
-       ldr     r7, [r6]
-       ands    r7, r7, $0x01
-       bne     checkStatClkStop
-
-       /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
-       ldr     r6, MDSTAT_DDR2
-       ldr     r7, [r6]
-       and     r7, r7, $MDSTAT_STATE
-       cmp     r7, $0x03
-       bne     checkDDRStatClkStop
-
-       /*------------------------------------------------------*
-        * Program DDR2 MMRs for 162MHz Setting                 *
-        *------------------------------------------------------*/
-
-       /* Program PHY Control Register */
-       ldr     r6, DDRCTL
-       ldr     r7, DDRCTL_VAL
-       str     r7, [r6]
-
-       /* Program SDRAM Bank Config Register */
-       ldr     r6, SDCFG
-       ldr     r7, SDCFG_VAL
-       str     r7, [r6]
-
-       /* Program SDRAM TIM-0 Config Register */
-       ldr     r6, SDTIM0
-       ldr     r7, SDTIM0_VAL_162MHz
-       str     r7, [r6]
-
-       /* Program SDRAM TIM-1 Config Register */
-       ldr     r6, SDTIM1
-       ldr     r7, SDTIM1_VAL_162MHz
-       str     r7, [r6]
-
-       /* Program the SDRAM Bank Config Control Register */
-       ldr     r10, MASK_VAL
-       ldr     r8, SDCFG
-       ldr     r9, SDCFG_VAL
-       and     r9, r9, r10
-       str     r9, [r8]
-
-       /* Program SDRAM SDREF Config Register */
-       ldr     r6, SDREF
-       ldr     r7, SDREF_VAL
-       str     r7, [r6]
-
-       /*------------------------------------------------------*
-        * Issue Soft Reset to DDR Module                       *
-        *------------------------------------------------------*/
-
-       /* Issue a Dummy DDR2 read/write */
-       ldr     r8, DDR2_START_ADDR
-       ldr     r7, DUMMY_VAL
-       str     r7, [r8]
-       ldr     r7, [r8]
-
-       /* Shut down the DDR2 LPSC Module */
-       ldr     r8, PSC_FLAG_CLEAR
-       ldr     r6, MDCTL_DDR2
-       ldr     r7, [r6]
-       and     r7, r7, r8
-       orr     r7, r7, $0x01
-       str     r7, [r6]
-
-       /* Enable the Power Domain Transition Command */
-       ldr     r6, PTCMD
-       ldr     r7, [r6]
-       orr     r7, r7, $0x01
-       str     r7, [r6]
-
-       /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
-       ldr     r6, PTSTAT
-       ldr     r7, [r6]
-       ands    r7, r7, $0x01
-       bne     checkStatClkStop2
-
-       /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
-       ldr     r6, MDSTAT_DDR2
-       ldr     r7, [r6]
-       and     r7, r7, $MDSTAT_STATE
-       cmp     r7, $0x01
-       bne     checkDDRStatClkStop2
-
-       /*------------------------------------------------------*
-        * Turn DDR2 Controller Clocks On                       *
-        *------------------------------------------------------*/
-
-       /* Enable the DDR2 LPSC Module */
-       ldr     r6, MDCTL_DDR2
-       ldr     r7, [r6]
-       orr     r7, r7, $0x03
-       str     r7, [r6]
-
-       /* Enable the Power Domain Transition Command */
-       ldr     r6, PTCMD
-       ldr     r7, [r6]
-       orr     r7, r7, $0x01
-       str     r7, [r6]
-
-       /* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
-       ldr     r6, PTSTAT
-       ldr     r7, [r6]
-       ands    r7, r7, $0x01
-       bne     checkStatClkEn2
-
-       /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
-       ldr     r6, MDSTAT_DDR2
-       ldr     r7, [r6]
-       and     r7, r7, $MDSTAT_STATE
-       cmp     r7, $0x03
-       bne     checkDDRStatClkEn2
-
-       /*  DDR Writes and Reads */
-       ldr     r6, CFGTEST
-       mov     r3, $0x01
-       str     r3, [r6]
-
-       /*------------------------------------------------------*
-        * System PLL Initialization                            *
-        *------------------------------------------------------*/
-
-       /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-       mov     r2, $0
-       ldr     r6, PLL1_CTL
-       ldr     r7, PLL_CLKSRC_MASK
-       ldr     r8, [r6]
-       and     r8, r8, r7
-       mov     r9, r2, lsl $8
-       orr     r8, r8, r9
-       str     r8, [r6]
-
-       /* Select the PLLEN source */
-       ldr     r7, PLL_ENSRC_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Bypass the PLL */
-       ldr     r7, PLL_BYPASS_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-       mov     r10, $0x20
-
-WaitLoop:
-       subs    r10, r10, $1
-       bne     WaitLoop
-
-       /* Reset the PLL */
-       ldr     r7, PLL_RESET_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Disable the PLL */
-       orr     r8, r8, $0x10
-       str     r8, [r6]
-
-       /* Power up the PLL */
-       ldr     r7, PLL_PWRUP_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Enable the PLL from Disable Mode */
-       ldr     r7, PLL_DISABLE_ENABLE_MASK
-       and     r8, r8, r7
-       str     r8, [r6]
-
-       /* Program the PLL Multiplier */
-       ldr     r6, PLL1_PLLM
-       mov     r3, $0x15       /* For 594MHz */
-       str     r3, [r6]
-
-       /* Wait for PLL to Reset Properly */
-       mov     r10, $0xff
-
-ResetLoop:
-       subs    r10, r10, $1
-       bne     ResetLoop
-
-       /* Bring PLL out of Reset */
-       ldr     r6, PLL1_CTL
-       orr     r8, r8, $0x08
-       str     r8, [r6]
-
-       /* Wait for PLL to Lock */
-       ldr     r10, PLL_LOCK_COUNT
-
-PLL1Lock:
-       subs    r10, r10, $1
-       bne     PLL1Lock
-
-       /* Enable the PLL */
-       orr     r8, r8, $0x01
-       str     r8, [r6]
-
-       nop
-       nop
-       nop
-       nop
-
-       /*------------------------------------------------------*
-        * AEMIF configuration for NOR Flash (double check)     *
-        *------------------------------------------------------*/
-       ldr     r0, _PINMUX0
-       ldr     r1, _DEV_SETTING
-       str     r1, [r0]
-
-       ldr     r0, WAITCFG
-       ldr     r1, WAITCFG_VAL
-       ldr     r2, [r0]
-       orr     r2, r2, r1
-       str     r2, [r0]
-
-       ldr     r0, ACFG3
-       ldr     r1, ACFG3_VAL
-       ldr     r2, [r0]
-       and     r1, r2, r1
-       str     r1, [r0]
-
-       ldr     r0, ACFG4
-       ldr     r1, ACFG4_VAL
-       ldr     r2, [r0]
-       and     r1, r2, r1
-       str     r1, [r0]
-
-       ldr     r0, ACFG5
-       ldr     r1, ACFG5_VAL
-       ldr     r2, [r0]
-       and     r1, r2, r1
-       str     r1, [r0]
-
-       /*--------------------------------------*
-        * VTP manual Calibration               *
-        *--------------------------------------*/
-       ldr     r0, VTPIOCR
-       ldr     r1, VTP_MMR0
-       str     r1, [r0]
-
-       ldr     r0, VTPIOCR
-       ldr     r1, VTP_MMR1
-       str     r1, [r0]
-
-       /* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-       ldr     r10, VTP_LOCK_COUNT
-VTPLock:
-       subs    r10, r10, $1
-       bne     VTPLock
-
-       ldr     r6, DFT_ENABLE
-       mov     r10, $0x01
-       str     r10, [r6]
-
-       ldr     r6, DDRVTPR
-       ldr     r7, [r6]
-       mov     r8, r7, LSL #32-10
-       mov     r8, r8, LSR #32-10        /* grab low 10 bits  */
-       ldr     r7, VTP_RECAL
-       orr     r8, r7, r8
-       ldr     r7, VTP_EN
-       orr     r8, r7, r8
-       str     r8, [r0]
-
-
-       /* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-       ldr     r10, VTP_LOCK_COUNT
-VTP1Lock:
-       subs    r10, r10, $1
-       bne     VTP1Lock
-
-       ldr     r1, [r0]
-       ldr     r2, VTP_MASK
-       and     r2, r1, r2
-       str     r2, [r0]
-
-       ldr     r6, DFT_ENABLE
-       mov     r10, $0
-       str     r10, [r6]
-
-       /*
-        * Call board-specific lowlevel init.
-        * That MUST be present and THAT returns
-        * back to arch calling code with "mov pc, lr."
-        */
-       b       dv_board_init
-
-.ltorg
-
-_PINMUX0:
-       .word   0x01c40000              /* Device Configuration Registers */
-_PINMUX1:
-       .word   0x01c40004              /* Device Configuration Registers */
-
-_DEV_SETTING:
-       .word   0x00000c1f
-
-WAITCFG:
-       .word   0x01e00004
-WAITCFG_VAL:
-       .word   0
-ACFG3:
-       .word   0x01e00014
-ACFG3_VAL:
-       .word   0x3ffffffd
-ACFG4:
-       .word   0x01e00018
-ACFG4_VAL:
-       .word   0x3ffffffd
-ACFG5:
-       .word   0x01e0001c
-ACFG5_VAL:
-       .word   0x3ffffffd
-
-MDCTL_DDR2:
-       .word   0x01c41a34
-MDSTAT_DDR2:
-       .word   0x01c41834
-
-PTCMD:
-       .word   0x01c41120
-PTSTAT:
-       .word   0x01c41128
-
-EINT_ENABLE0:
-       .word   0x01c48018
-EINT_ENABLE1:
-       .word   0x01c4801c
-
-PSC_FLAG_CLEAR:
-       .word   0xffffffe0
-PSC_GEM_FLAG_CLEAR:
-       .word   0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
-       .word   0x200000e4
-DDRCTL_VAL:
-       .word   0x50006405
-SDREF:
-       .word   0x2000000c
-SDREF_VAL:
-       .word   0x000005c3
-SDCFG:
-       .word   0x20000008
-SDCFG_VAL:
-#ifdef DDR_4BANKS
-       .word   0x00178622
-#elif defined DDR_8BANKS
-       .word   0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
-       .word   0x20000010
-SDTIM0_VAL_162MHz:
-       .word   0x28923211
-SDTIM1:
-       .word   0x20000014
-SDTIM1_VAL_162MHz:
-       .word   0x0016c722
-VTPIOCR:
-       .word   0x200000f0      /* VTP IO Control register */
-DDRVTPR:
-       .word   0x01c42030      /* DDR VPTR MMR */
-VTP_MMR0:
-       .word   0x201f
-VTP_MMR1:
-       .word   0xa01f
-DFT_ENABLE:
-       .word   0x01c4004c
-VTP_LOCK_COUNT:
-       .word   0x5b0
-VTP_MASK:
-       .word   0xffffdfff
-VTP_RECAL:
-       .word   0x08000
-VTP_EN:
-       .word   0x02000
-CFGTEST:
-       .word   0x80010000
-MASK_VAL:
-       .word   0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
-       .word   0x01c41a9c
-MDSTAT_GEM:
-       .word   0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
-       .word   0x01c41a20
-
-PLL_CLKSRC_MASK:
-       .word   0xfffffeff      /* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
-       .word   0xffffffdf      /* Select the PLLEN source */
-PLL_BYPASS_MASK:
-       .word   0xfffffffe      /* Put the PLL in BYPASS */
-PLL_RESET_MASK:
-       .word   0xfffffff7      /* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
-       .word   0xfffffffd      /* PLL Power up Mask Bit  */
-PLL_DISABLE_ENABLE_MASK:
-       .word   0xffffffef      /* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
-       .word   0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
-       .word   0x01c40900
-PLL1_PLLM:
-       .word   0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
-       .word   0x01c40d00
-PLL2_PLLM:
-       .word   0x01c40d10
-PLL2_DIV1:
-       .word   0x01c40d18
-PLL2_DIV2:
-       .word   0x01c40d1c
-PLL2_PLLCMD:
-       .word   0x01c40d38
-PLL2_PLLSTAT:
-       .word   0x01c40d3c
-PLL2_DIV_MASK:
-       .word   0xffff7fff
-
-MMARG_BRF0:
-       .word   0x01c42010      /* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
-       .word   0x00444400
-
-DDR2_START_ADDR:
-       .word   0x80000000
-DUMMY_VAL:
-       .word   0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
-       mov pc, lr
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c
deleted file mode 100644 (file)
index c482fd9..0000000
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Intel LXT971/LXT972 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int lxt972_is_phy_connected(int phy_addr)
-{
-       u_int16_t id1, id2;
-
-       if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
-               return(0);
-       if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
-               return(0);
-
-       if ((id1 == (0x0013)) && ((id2  & 0xfff0) == 0x78e0))
-               return(1);
-
-       return(0);
-}
-
-int lxt972_get_link_speed(int phy_addr)
-{
-       u_int16_t stat1, tmp;
-       volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
-       if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
-               return(0);
-
-       if (!(stat1 & PHY_LXT971_STAT2_LINK))   /* link up? */
-               return(0);
-
-       if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
-               return(0);
-
-       tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
-
-       davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
-       /* Read back */
-       if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
-               return(0);
-
-       /* Speed doesn't matter, there is no setting for it in EMAC... */
-       if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-               /* set DM644x EMAC for Full Duplex  */
-               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
-                       EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
-       } else {
-               /*set DM644x EMAC for Half Duplex  */
-               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
-       }
-
-       return(1);
-}
-
-
-int lxt972_init_phy(int phy_addr)
-{
-       int ret = 1;
-
-       if (!lxt972_get_link_speed(phy_addr)) {
-               /* Try another time */
-               ret = lxt972_get_link_speed(phy_addr);
-       }
-
-       /* Disable PHY Interrupts */
-       davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
-
-       return(ret);
-}
-
-
-int lxt972_auto_negotiate(int phy_addr)
-{
-       u_int16_t tmp;
-
-       if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
-               return(0);
-
-       /* Restart Auto_negotiation  */
-       tmp |= BMCR_ANRESTART;
-       davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
-
-       /*check AutoNegotiate complete */
-       udelay (10000);
-       if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
-               return(0);
-
-       if (!(tmp & BMSR_ANEGCOMPLETE))
-               return(0);
-
-       return (lxt972_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c
deleted file mode 100644 (file)
index e18bdfc..0000000
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Miscelaneous DaVinci functions.
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_BUILD
-int dram_init(void)
-{
-       /* dram_init must store complete ramsize in gd->ram_size */
-       gd->ram_size = get_ram_size(
-                       (void *)CONFIG_SYS_SDRAM_BASE,
-                       CONFIG_MAX_RAM_BANK_SIZE);
-       return 0;
-}
-
-void dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = gd->ram_size;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
- * Returns 1 if found, 0 otherwise.
- */
-int dvevm_read_mac_address(uint8_t *buf)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
-       /* Read MAC address. */
-       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
-               CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
-               goto i2cerr;
-
-       /* Check that MAC address is valid. */
-       if (!is_valid_ether_addr(buf))
-               goto err;
-
-       return 1; /* Found */
-
-i2cerr:
-       printf("Read from EEPROM @ 0x%02x failed\n",
-               CONFIG_SYS_I2C_EEPROM_ADDR);
-err:
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
-
-       return 0;
-}
-
-/*
- * Set the mii mode as MII or RMII
- */
-#if defined(CONFIG_SOC_DA8XX)
-void davinci_emac_mii_mode_sel(int mode_sel)
-{
-       int val;
-
-       val = readl(&davinci_syscfg_regs->cfgchip3);
-       if (mode_sel == 0)
-               val &= ~(1 << 8);
-       else
-               val |= (1 << 8);
-       writel(val, &davinci_syscfg_regs->cfgchip3);
-}
-#endif
-/*
- * If there is no MAC address in the environment, then it will be initialized
- * (silently) from the value in the EEPROM.
- */
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
-{
-       uint8_t env_enetaddr[6];
-       int ret;
-
-       ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
-       if (!ret) {
-               /*
-                * There is no MAC address in the environment, so we
-                * initialize it from the value in the EEPROM.
-                */
-               debug("### Setting environment from EEPROM MAC address = "
-                       "\"%pM\"\n",
-                       env_enetaddr);
-               ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
-       }
-       if (!ret)
-               printf("Failed to set mac address from EEPROM: %d\n", ret);
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#if defined(CONFIG_SOC_DA8XX)
-#ifndef CONFIG_USE_IRQ
-void irq_init(void)
-{
-       /*
-        * Mask all IRQs by clearing the global enable and setting
-        * the enable clear for all the 90 interrupts.
-        */
-       writel(0, &davinci_aintc_regs->ger);
-
-       writel(0, &davinci_aintc_regs->hier);
-
-       writel(0xffffffff, &davinci_aintc_regs->ecr1);
-       writel(0xffffffff, &davinci_aintc_regs->ecr2);
-       writel(0xffffffff, &davinci_aintc_regs->ecr3);
-}
-#endif
-
-/*
- * Enable PSC for various peripherals.
- */
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
-                                   const int n_items)
-{
-       int i;
-
-       for (i = 0; i < n_items; i++)
-               lpsc_on(item[i].lpsc_no);
-
-       return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/cpu/arm926ejs/davinci/pinmux.c
deleted file mode 100644 (file)
index e9d8c87..0000000
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * DaVinci pinmux functions.
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-
-/*
- * Change the setting of a pin multiplexer field.
- *
- * Takes an array of pinmux settings similar to:
- *
- * struct pinmux_config uart_pins[] = {
- *     { &davinci_syscfg_regs->pinmux[8], 2, 7 },
- *     { &davinci_syscfg_regs->pinmux[9], 2, 0 }
- * };
- *
- * Stepping through the array, each pinmux[n] register has the given value
- * set in the pin mux field specified.
- *
- * The number of pins in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Returns 0 if all field numbers and values are in the correct range,
- * else returns -1.
- */
-int davinci_configure_pin_mux(const struct pinmux_config *pins,
-                             const int n_pins)
-{
-       int i;
-
-       /* check for invalid pinmux values */
-       for (i = 0; i < n_pins; i++) {
-               if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
-                   (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
-                       return -1;
-       }
-
-       /* configure the pinmuxes */
-       for (i = 0; i < n_pins; i++) {
-               const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
-               const unsigned int value = pins[i].value << offset;
-               const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
-               const dv_reg *mux = pins[i].mux;
-
-               writel(value | (readl(mux) & (~mask)), mux);
-       }
-
-       return 0;
-}
-
-/*
- * Configure multiple pinmux resources.
- *
- * Takes an pinmux_resource array of pinmux_config and pin counts:
- *
- * const struct pinmux_resource pinmuxes[] = {
- *     PINMUX_ITEM(uart_pins),
- *     PINMUX_ITEM(i2c_pins),
- * };
- *
- * The number of items in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Each item entry is configured in the defined order. If configuration
- * of any item fails, -1 is returned and none of the following items are
- * configured. On success, 0 is returned.
- */
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
-                                   const int n_items)
-{
-       int i;
-
-       for (i = 0; i < n_items; i++) {
-               if (davinci_configure_pin_mux(item[i].pins,
-                                             item[i].n_pins) != 0)
-                       return -1;
-       }
-
-       return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c
deleted file mode 100644 (file)
index 8d99e2e..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Power and Sleep Controller (PSC) functions.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/*
- * The PSC manages three inputs to a "module" which may be a peripheral or
- * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
- * its power domain.  For our purposes, we only care whether clock and power
- * are active, and the module is out of reset.
- *
- * DaVinci chips may include two separate power domains: "Always On" and "DSP".
- * Chips without a DSP generally have only one domain.
- *
- * The "Always On" power domain is always on when the chip is on, and is
- * powered by the VDD pins (on DM644X). The majority of DaVinci modules
- * lie within the "Always On" power domain.
- *
- * A separate domain called the "DSP" domain houses the C64x+ and other video
- * hardware such as VICP. In some chips, the "DSP" domain is not always on.
- * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
- */
-
-/* Works on Always On power domain only (no PD argument) */
-static void lpsc_transition(unsigned int id, unsigned int state)
-{
-       dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-#ifdef CONFIG_SOC_DA8XX
-       struct davinci_psc_regs *psc_regs;
-#endif
-
-#ifndef CONFIG_SOC_DA8XX
-       if (id >= DAVINCI_LPSC_GEM)
-               return;                 /* Don't work on DSP Power Domain */
-
-       mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-       mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-       ptstat = REG_P(PSC_PTSTAT);
-       ptcmd = REG_P(PSC_PTCMD);
-#else
-       if (id < DAVINCI_LPSC_PSC1_BASE) {
-               if (id >= PSC_PSC0_MODULE_ID_CNT)
-                       return;
-               psc_regs = davinci_psc0_regs;
-               mdstat = &psc_regs->psc0.mdstat[id];
-               mdctl = &psc_regs->psc0.mdctl[id];
-       } else {
-               id -= DAVINCI_LPSC_PSC1_BASE;
-               if (id >= PSC_PSC1_MODULE_ID_CNT)
-                       return;
-               psc_regs = davinci_psc1_regs;
-               mdstat = &psc_regs->psc1.mdstat[id];
-               mdctl = &psc_regs->psc1.mdctl[id];
-       }
-       ptstat = &psc_regs->ptstat;
-       ptcmd = &psc_regs->ptcmd;
-#endif
-
-       while (readl(ptstat) & 0x01)
-               continue;
-
-       if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
-               return; /* Already in that state */
-
-       writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
-
-       switch (id) {
-#ifdef CONFIG_SOC_DM644X
-       /* Special treatment for some modules as for sprue14 p.7.4.2 */
-       case DAVINCI_LPSC_VPSSSLV:
-       case DAVINCI_LPSC_EMAC:
-       case DAVINCI_LPSC_EMAC_WRAPPER:
-       case DAVINCI_LPSC_MDIO:
-       case DAVINCI_LPSC_USB:
-       case DAVINCI_LPSC_ATA:
-       case DAVINCI_LPSC_VLYNQ:
-       case DAVINCI_LPSC_UHPI:
-       case DAVINCI_LPSC_DDR_EMIF:
-       case DAVINCI_LPSC_AEMIF:
-       case DAVINCI_LPSC_MMC_SD:
-       case DAVINCI_LPSC_MEMSTICK:
-       case DAVINCI_LPSC_McBSP:
-       case DAVINCI_LPSC_GPIO:
-               writel(readl(mdctl) | 0x200, mdctl);
-               break;
-#endif
-       }
-
-       writel(0x01, ptcmd);
-
-       while (readl(ptstat) & 0x01)
-               continue;
-       while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
-               continue;
-}
-
-void lpsc_on(unsigned int id)
-{
-       lpsc_transition(id, 0x03);
-}
-
-void lpsc_syncreset(unsigned int id)
-{
-       lpsc_transition(id, 0x01);
-}
-
-void lpsc_disable(unsigned int id)
-{
-       lpsc_transition(id, 0x0);
-}
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
-       int i;
-
-       if (REG(PSC_PDSTAT1) & 0x1f)
-               return;                 /* Already on */
-
-       REG(PSC_GBLCTL) |= 0x01;
-       REG(PSC_PDCTL1) |= 0x01;
-       REG(PSC_PDCTL1) &= ~0x100;
-       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-       REG(PSC_PTCMD) = 0x02;
-
-       for (i = 0; i < 100; i++) {
-               if (REG(PSC_EPCPR) & 0x02)
-                       break;
-       }
-
-       REG(PSC_CHP_SHRTSW) = 0x01;
-       REG(PSC_PDCTL1) |= 0x100;
-       REG(PSC_EPCCR) = 0x02;
-
-       for (i = 0; i < 100; i++) {
-               if (!(REG(PSC_PTSTAT) & 0x02))
-                       break;
-       }
-
-       REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c
deleted file mode 100644 (file)
index 6b0f154..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  Processor reset using WDT.
- *
- * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer_defs.h>
-#include <asm/arch/hardware.h>
-
-void reset_cpu(unsigned long a)
-{
-       struct davinci_timer *const wdttimer =
-               (struct davinci_timer *)DAVINCI_WDOG_BASE;
-       writel(0x08, &wdttimer->tgcr);
-       writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
-       writel(0, &wdttimer->tim12);
-       writel(0, &wdttimer->tim34);
-       writel(0, &wdttimer->prd12);
-       writel(0, &wdttimer->prd34);
-       writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
-       writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
-       writel(0xa5c64000, &wdttimer->wdtcr);
-       writel(0xda7e4000, &wdttimer->wdtcr);
-       writel(0x4000, &wdttimer->wdtcr);
-       while (1)
-               /*nothing*/;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
deleted file mode 100644 (file)
index 49349da..0000000
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spi_flash.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
-void puts(const char *str)
-{
-       while (*str)
-               putc(*str++);
-}
-
-void putc(char c)
-{
-       if (c == '\n')
-               NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
-
-       NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
-}
-#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-
-void spl_board_init(void)
-{
-#ifdef CONFIG_SOC_DM365
-       dm36x_lowlevel_init(0);
-#endif
-#ifdef CONFIG_SOC_DA8XX
-       arch_cpu_init();
-#endif
-       preloader_console_init();
-}
-
-u32 spl_boot_mode(void)
-{
-       return MMCSD_MODE_RAW;
-}
-
-u32 spl_boot_device(void)
-{
-#ifdef CONFIG_SPL_NAND_SIMPLE
-       return BOOT_DEVICE_NAND;
-#elif defined(CONFIG_SPL_SPI_LOAD)
-       return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_SPL_MMC_LOAD)
-       return BOOT_DEVICE_MMC1;
-#else
-       puts("Unknown boot device\n");
-       hang();
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
deleted file mode 100644 (file)
index c7d0652..0000000
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer_defs.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct davinci_timer * const timer =
-       (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define TIM_CLK_DIV    16
-
-int timer_init(void)
-{
-       /* We are using timer34 in unchained 32-bit mode, full speed */
-       writel(0x0, &timer->tcr);
-       writel(0x0, &timer->tgcr);
-       writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
-       writel(0x0, &timer->tim34);
-       writel(TIMER_LOAD_VAL, &timer->prd34);
-       writel(2 << 22, &timer->tcr);
-       gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
-       gd->arch.timer_reset_value = 0;
-
-       return(0);
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
-       unsigned long now = readl(&timer->tim34);
-
-       /* increment tbu if tbl has rolled over */
-       if (now < gd->arch.tbl)
-               gd->arch.tbu++;
-       gd->arch.tbl = now;
-
-       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-ulong get_timer(ulong base)
-{
-       unsigned long long timer_diff;
-
-       timer_diff = get_ticks() - gd->arch.timer_reset_value;
-
-       return lldiv(timer_diff,
-                    (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
-}
-
-void __udelay(unsigned long usec)
-{
-       unsigned long long endtime;
-
-       endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
-                       1000000UL);
-       endtime += get_ticks();
-
-       while (get_ticks() < endtime)
-               ;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-       return gd->arch.timer_rate_hz;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-static struct davinci_timer * const wdttimer =
-       (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
-
-/*
- * See prufw2.pdf for using Timer as a WDT
- */
-void davinci_hw_watchdog_enable(void)
-{
-       writel(0x0, &wdttimer->tcr);
-       writel(0x0, &wdttimer->tgcr);
-       /* TIMMODE = 2h */
-       writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
-       writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
-       writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
-       writel(2 << 22, &wdttimer->tcr);
-       writel(0x0, &wdttimer->tim12);
-       writel(0x0, &wdttimer->tim34);
-       /* set WDEN bit, WDKEY 0xa5c6 */
-       writel(0xa5c64000, &wdttimer->wdtcr);
-       /* clear counter register */
-       writel(0xda7e4000, &wdttimer->wdtcr);
-}
-
-void davinci_hw_watchdog_reset(void)
-{
-       writel(0xa5c64000, &wdttimer->wdtcr);
-       writel(0xda7e4000, &wdttimer->wdtcr);
-}
-#endif
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
new file mode 100644 (file)
index 0000000..613f04d
--- /dev/null
@@ -0,0 +1,78 @@
+if ARCH_DAVINCI
+
+choice
+       prompt "DaVinci board select"
+
+config TARGET_ENBW_CMC
+       bool "EnBW CMC board"
+
+config TARGET_IPAM390
+       bool "IPAM390 board"
+       select SUPPORT_SPL
+
+config TARGET_DA830EVM
+       bool "DA830 EVM board"
+
+config TARGET_DA850EVM
+       bool "DA850 EVM board"
+       select SUPPORT_SPL
+
+config TARGET_CAM_ENC_4XX
+       bool "CAM ENC 4xx board"
+       select SUPPORT_SPL
+
+config TARGET_HAWKBOARD
+       bool "Hawkboard"
+       select SUPPORT_SPL
+
+config TARGET_DAVINCI_DM355EVM
+       bool "DM355 EVM board"
+
+config TARGET_DAVINCI_DM355LEOPARD
+       bool "DM355 Leopard board"
+
+config TARGET_DAVINCI_DM365EVM
+       bool "DM365 EVM board"
+
+config TARGET_DAVINCI_DM6467EVM
+       bool "DM6467 EVM board"
+
+config TARGET_DAVINCI_DVEVM
+       bool "DVEVM board"
+
+config TARGET_EA20
+       bool "EA20 board"
+
+config TARGET_DAVINCI_SCHMOOGIE
+       bool "Schmoogie board"
+
+config TARGET_DAVINCI_SFFSDR
+       bool "SFFSDR board"
+
+config TARGET_DAVINCI_SONATA
+       bool "Sonata board"
+
+config TARGET_CALIMAIN
+       bool "Calimain board"
+
+endchoice
+
+config SYS_SOC
+       default "davinci"
+
+source "board/enbw/enbw_cmc/Kconfig"
+source "board/ait/cam_enc_4xx/Kconfig"
+source "board/Barix/ipam390/Kconfig"
+source "board/davinci/da8xxevm/Kconfig"
+source "board/davinci/dm355evm/Kconfig"
+source "board/davinci/dm355leopard/Kconfig"
+source "board/davinci/dm365evm/Kconfig"
+source "board/davinci/dm6467evm/Kconfig"
+source "board/davinci/dvevm/Kconfig"
+source "board/davinci/ea20/Kconfig"
+source "board/davinci/schmoogie/Kconfig"
+source "board/davinci/sffsdr/Kconfig"
+source "board/davinci/sonata/Kconfig"
+source "board/omicron/calimain/Kconfig"
+
+endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
new file mode 100644 (file)
index 0000000..7d67191
--- /dev/null
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y                          += cpu.o misc.o timer.o psc.o pinmux.o reset.o
+obj-$(CONFIG_DA850_LOWLEVEL)   += da850_lowlevel.o
+obj-$(CONFIG_SOC_DM355)        += dm355.o
+obj-$(CONFIG_SOC_DM365)        += dm365.o
+obj-$(CONFIG_SOC_DM644X)       += dm644x.o
+obj-$(CONFIG_SOC_DM646X)       += dm646x.o
+obj-$(CONFIG_SOC_DA830)        += da830_pinmux.o
+obj-$(CONFIG_SOC_DA850)        += da850_pinmux.o
+obj-$(CONFIG_DRIVER_TI_EMAC)   += lxt972.o dp83848.o et1011c.o ksz8873.o
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_FRAMEWORK)    += spl.o
+obj-$(CONFIG_SOC_DM365)        += dm365_lowlevel.o
+obj-$(CONFIG_SOC_DA8XX)        += da850_lowlevel.o
+endif
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+obj-y  += lowlevel_init.o
+endif
diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk
new file mode 100644 (file)
index 0000000..69e9d5a
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+ifndef CONFIG_SPL_BUILD
+ALL-$(CONFIG_SPL_FRAMEWORK)    += u-boot.ais
+endif
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
new file mode 100644 (file)
index 0000000..ff61147
--- /dev/null
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2004 Texas Instruments.
+ * Copyright (C) 2009 David Brownell
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* offsets from PLL controller base */
+#define PLLC_PLLCTL    0x100
+#define PLLC_PLLM      0x110
+#define PLLC_PREDIV    0x114
+#define PLLC_PLLDIV1   0x118
+#define PLLC_PLLDIV2   0x11c
+#define PLLC_PLLDIV3   0x120
+#define PLLC_POSTDIV   0x128
+#define PLLC_BPDIV     0x12c
+#define PLLC_PLLDIV4   0x160
+#define PLLC_PLLDIV5   0x164
+#define PLLC_PLLDIV6   0x168
+#define PLLC_PLLDIV7   0x16c
+#define PLLC_PLLDIV8   0x170
+#define PLLC_PLLDIV9   0x174
+
+#define BIT(x)         (1 << (x))
+
+/* SOC-specific pll info */
+#ifdef CONFIG_SOC_DM355
+#define ARM_PLLDIV     PLLC_PLLDIV1
+#define DDR_PLLDIV     PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DM644X
+#define ARM_PLLDIV     PLLC_PLLDIV2
+#define DSP_PLLDIV     PLLC_PLLDIV1
+#define DDR_PLLDIV     PLLC_PLLDIV2
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+#define DSP_PLLDIV     PLLC_PLLDIV1
+#define ARM_PLLDIV     PLLC_PLLDIV2
+#define DDR_PLLDIV     PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DA8XX
+unsigned int sysdiv[9] = {
+       PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
+       PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
+};
+
+int clk_get(enum davinci_clk_ids id)
+{
+       int pre_div;
+       int pllm;
+       int post_div;
+       int pll_out;
+       unsigned int pll_base;
+
+       pll_out = CONFIG_SYS_OSCIN_FREQ;
+
+       if (id == DAVINCI_AUXCLK_CLKID)
+               goto out;
+
+       if ((id >> 16) == 1)
+               pll_base = (unsigned int)davinci_pllc1_regs;
+       else
+               pll_base = (unsigned int)davinci_pllc0_regs;
+
+       id &= 0xFFFF;
+
+       /*
+        * Lets keep this simple. Combining operations can result in
+        * unexpected approximations
+        */
+       pre_div = (readl(pll_base + PLLC_PREDIV) &
+               DAVINCI_PLLC_DIV_MASK) + 1;
+       pllm = readl(pll_base + PLLC_PLLM) + 1;
+
+       pll_out /= pre_div;
+       pll_out *= pllm;
+
+       if (id == DAVINCI_PLLM_CLKID)
+               goto out;
+
+       post_div = (readl(pll_base + PLLC_POSTDIV) &
+               DAVINCI_PLLC_DIV_MASK) + 1;
+
+       pll_out /= post_div;
+
+       if (id == DAVINCI_PLLC_CLKID)
+               goto out;
+
+       pll_out /= (readl(pll_base + sysdiv[id - 1]) &
+               DAVINCI_PLLC_DIV_MASK) + 1;
+
+out:
+       return pll_out;
+}
+
+int set_cpu_clk_info(void)
+{
+       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
+       /* DDR PHY uses an x2 input clock */
+       gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+                               (clk_get(DAVINCI_DDR_CLKID) / 1000000);
+       gd->bd->bi_dsp_freq = 0;
+       return 0;
+}
+
+#else /* CONFIG_SOC_DA8XX */
+
+static unsigned pll_div(volatile void *pllbase, unsigned offset)
+{
+       u32     div;
+
+       div = REG(pllbase + offset);
+       return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
+}
+
+static inline unsigned pll_prediv(volatile void *pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+       /* this register read seems to fail on pll0 */
+       if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+               return 8;
+       else
+               return pll_div(pllbase, PLLC_PREDIV);
+#elif defined(CONFIG_SOC_DM365)
+       return pll_div(pllbase, PLLC_PREDIV);
+#endif
+       return 1;
+}
+
+static inline unsigned pll_postdiv(volatile void *pllbase)
+{
+#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
+       return pll_div(pllbase, PLLC_POSTDIV);
+#elif defined(CONFIG_SOC_DM6446)
+       if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+               return pll_div(pllbase, PLLC_POSTDIV);
+#endif
+       return 1;
+}
+
+static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
+{
+       volatile void   *pllbase = (volatile void *) pll_addr;
+#ifdef CONFIG_SOC_DM646X
+       unsigned        base = CONFIG_REFCLK_FREQ / 1000;
+#else
+       unsigned        base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
+
+       /* the PLL might be bypassed */
+       if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
+               base /= pll_prediv(pllbase);
+#if defined(CONFIG_SOC_DM365)
+               base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
+#else
+               base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+#endif
+               base /= pll_postdiv(pllbase);
+       }
+       return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
+}
+
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+       return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+       return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
+
+int set_cpu_clk_info(void)
+{
+       unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#if defined(CONFIG_SOC_DM365)
+       pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#endif
+       gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
+
+#ifdef DSP_PLLDIV
+       gd->bd->bi_dsp_freq =
+               pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
+#else
+       gd->bd->bi_dsp_freq = 0;
+#endif
+
+       pllbase = DAVINCI_PLL_CNTRL1_BASE;
+#if defined(CONFIG_SOC_DM365)
+       pllbase = DAVINCI_PLL_CNTRL0_BASE;
+#endif
+       gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
+
+       return 0;
+}
+
+#endif /* !CONFIG_SOC_DA8XX */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_DRIVER_TI_EMAC)
+       davinci_emac_initialize();
+#endif
+       return 0;
+}
diff --git a/arch/arm/mach-davinci/da830_pinmux.c b/arch/arm/mach-davinci/da830_pinmux.c
new file mode 100644 (file)
index 0000000..edaab45
--- /dev/null
@@ -0,0 +1,139 @@
+/*
+ * Pinmux configurations for the DA830 SoCs
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI0 pin muxer settings */
+const struct pinmux_config spi0_pins_base[] = {
+       { pinmux(7), 1, 3 },  /* SPI0_SOMI */
+       { pinmux(7), 1, 4 },  /* SPI0_SIMO */
+       { pinmux(7), 1, 6 }   /* SPI0_CLK */
+};
+
+const struct pinmux_config spi0_pins_scs0[] = {
+       { pinmux(7), 1, 7 }   /* SPI0_SCS[0] */
+};
+
+const struct pinmux_config spi0_pins_ena[] = {
+       { pinmux(7), 1, 5 }   /* SPI0_ENA */
+};
+
+/* NAND pin muxer settings */
+const struct pinmux_config emifa_pins_cs0[] = {
+       { pinmux(18), 1, 2 }   /* EMA_CS[0] */
+};
+
+const struct pinmux_config emifa_pins_cs2[] = {
+       { pinmux(18), 1, 3 }   /* EMA_CS[2] */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+       { pinmux(18), 1, 4 }   /* EMA_CS[3] */
+};
+
+#ifdef CONFIG_USE_NAND
+const struct pinmux_config emifa_pins[] = {
+       { pinmux(13), 1, 6 },  /* EMA_D[0] */
+       { pinmux(13), 1, 7 },  /* EMA_D[1] */
+       { pinmux(14), 1, 0 },  /* EMA_D[2] */
+       { pinmux(14), 1, 1 },  /* EMA_D[3] */
+       { pinmux(14), 1, 2 },  /* EMA_D[4] */
+       { pinmux(14), 1, 3 },  /* EMA_D[5] */
+       { pinmux(14), 1, 4 },  /* EMA_D[6] */
+       { pinmux(14), 1, 5 },  /* EMA_D[7] */
+       { pinmux(14), 1, 6 },  /* EMA_D[8] */
+       { pinmux(14), 1, 7 },  /* EMA_D[9] */
+       { pinmux(15), 1, 0 },  /* EMA_D[10] */
+       { pinmux(15), 1, 1 },  /* EMA_D[11] */
+       { pinmux(15), 1, 2 },  /* EMA_D[12] */
+       { pinmux(15), 1, 3 },  /* EMA_D[13] */
+       { pinmux(15), 1, 4 },  /* EMA_D[14] */
+       { pinmux(15), 1, 5 },  /* EMA_D[15] */
+       { pinmux(15), 1, 6 },  /* EMA_A[0] */
+       { pinmux(15), 1, 7 },  /* EMA_A[1] */
+       { pinmux(16), 1, 0 },  /* EMA_A[2] */
+       { pinmux(16), 1, 1 },  /* EMA_A[3] */
+       { pinmux(16), 1, 2 },  /* EMA_A[4] */
+       { pinmux(16), 1, 3 },  /* EMA_A[5] */
+       { pinmux(16), 1, 4 },  /* EMA_A[6] */
+       { pinmux(16), 1, 5 },  /* EMA_A[7] */
+       { pinmux(16), 1, 6 },  /* EMA_A[8] */
+       { pinmux(16), 1, 7 },  /* EMA_A[9] */
+       { pinmux(17), 1, 0 },  /* EMA_A[10] */
+       { pinmux(17), 1, 1 },  /* EMA_A[11] */
+       { pinmux(17), 1, 2 },  /* EMA_A[12] */
+       { pinmux(17), 1, 3 },  /* EMA_BA[1] */
+       { pinmux(17), 1, 4 },  /* EMA_BA[0] */
+       { pinmux(17), 1, 5 },  /* EMA_CLK */
+       { pinmux(17), 1, 6 },  /* EMA_SDCKE */
+       { pinmux(17), 1, 7 },  /* EMA_CAS */
+       { pinmux(18), 1, 0 },  /* EMA_CAS */
+       { pinmux(18), 1, 1 },  /* EMA_WE */
+       { pinmux(18), 1, 5 },  /* EMA_OE */
+       { pinmux(18), 1, 6 },  /* EMA_WE_DQM[1] */
+       { pinmux(18), 1, 7 },  /* EMA_WE_DQM[0] */
+       { pinmux(10), 1, 0 }   /* Tristate */
+};
+#endif
+
+/* EMAC PHY interface pins */
+const struct pinmux_config emac_pins_rmii[] = {
+       { pinmux(10), 2, 1 },  /* RMII_TXD[0] */
+       { pinmux(10), 2, 2 },  /* RMII_TXD[1] */
+       { pinmux(10), 2, 3 },  /* RMII_TXEN */
+       { pinmux(10), 2, 4 },  /* RMII_CRS_DV */
+       { pinmux(10), 2, 5 },  /* RMII_RXD[0] */
+       { pinmux(10), 2, 6 },  /* RMII_RXD[1] */
+       { pinmux(10), 2, 7 }   /* RMII_RXER */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+       { pinmux(11), 2, 0 },  /* MDIO_CLK */
+       { pinmux(11), 2, 1 }   /* MDIO_D */
+};
+
+const struct pinmux_config emac_pins_rmii_clk_source[] = {
+       { pinmux(9), 0, 5 }    /* ref.clk from external source */
+};
+
+/* UART2 pin muxer settings */
+const struct pinmux_config uart2_pins_txrx[] = {
+       { pinmux(8), 2, 7 },   /* UART2_RXD */
+       { pinmux(9), 2, 0 }    /* UART2_TXD */
+};
+
+/* I2C0 pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+       { pinmux(8), 2, 3 },   /* I2C0_SDA */
+       { pinmux(8), 2, 4 }    /* I2C0_SCL */
+};
+
+/* USB0_DRVVBUS pin muxer settings */
+const struct pinmux_config usb_pins[] = {
+       { pinmux(9), 1, 1 }    /* USB0_DRVVBUS */
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins_8bit[] = {
+       { pinmux(15), 2, 7 },  /* MMCSD0_CLK */
+       { pinmux(16), 2, 0 },  /* MMCSD0_CMD */
+       { pinmux(13), 2, 6 },  /* MMCSD0_DAT_0 */
+       { pinmux(13), 2, 7 },  /* MMCSD0_DAT_1 */
+       { pinmux(14), 2, 0 },  /* MMCSD0_DAT_2 */
+       { pinmux(14), 2, 1 },  /* MMCSD0_DAT_3 */
+       { pinmux(14), 2, 2 },  /* MMCSD0_DAT_4 */
+       { pinmux(14), 2, 3 },  /* MMCSD0_DAT_5 */
+       { pinmux(14), 2, 4 },  /* MMCSD0_DAT_6 */
+       { pinmux(14), 2, 5 }   /* MMCSD0_DAT_7 */
+       /* DA830 supports 8-bit mode */
+};
+#endif
diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c
new file mode 100644 (file)
index 0000000..19730ce
--- /dev/null
@@ -0,0 +1,313 @@
+/*
+ * SoC-specific lowlevel code for DA850
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/arch/da850_lowlevel.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/pll_defs.h>
+
+void davinci_enable_uart0(void)
+{
+       lpsc_on(DAVINCI_LPSC_UART0);
+
+       /* Bringup UART0 out of reset */
+       REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
+static void da850_waitloop(unsigned long loopcnt)
+{
+       unsigned long   i;
+
+       for (i = 0; i < loopcnt; i++)
+               asm("   NOP");
+}
+
+static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
+{
+       if (reg == davinci_pllc0_regs)
+               /* Unlock PLL registers. */
+               clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
+
+       /*
+        * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
+        * through MMR
+        */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
+       /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
+       clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
+
+       /* Set PLLEN=0 => PLL BYPASS MODE */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
+
+       da850_waitloop(150);
+
+       if (reg == davinci_pllc0_regs) {
+               /*
+                * Select the Clock Mode bit 8 as External Clock or On Chip
+                * Oscilator
+                */
+               dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
+               setbits_le32(&reg->pllctl,
+                       (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
+       }
+
+       /* Clear PLLRST bit to reset the PLL */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
+
+       /* Disable the PLL output */
+       setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
+
+       /* PLL initialization sequence */
+       /*
+        * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
+        * power down bit
+        */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
+
+       /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
+       clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
+
+#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
+       /* program the prediv */
+       if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
+               writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
+                       &reg->prediv);
+#endif
+
+       /* Program the required multiplier value in PLLM */
+       writel(pllmult, &reg->pllm);
+
+       /* program the postdiv */
+       if (reg == davinci_pllc0_regs)
+               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
+                       &reg->postdiv);
+       else
+               writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
+                       &reg->postdiv);
+
+       /*
+        * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
+        * no GO operation is currently in progress
+        */
+       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+               ;
+
+       if (reg == davinci_pllc0_regs) {
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
+               writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
+       } else {
+               writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
+               writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
+               writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
+       }
+
+       /*
+        * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
+        * transition.
+        */
+       setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
+
+       /*
+        * Wait for the GOSTAT bit in PLLSTAT to clear to 0
+        * (completion of phase alignment).
+        */
+       while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
+               ;
+
+       /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
+       da850_waitloop(200);
+
+       /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
+       setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
+
+       /* Wait for PLL to lock. See PLL spec for PLL lock time */
+       da850_waitloop(2400);
+
+       /*
+        * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
+        * mode
+        */
+       setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
+
+
+       /*
+        * clear EMIFA and EMIFB clock source settings, let them
+        * run off SYSCLK
+        */
+       if (reg == davinci_pllc0_regs)
+               dv_maskbits(&davinci_syscfg_regs->cfgchip3,
+                       ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
+
+       return 0;
+}
+#endif /* CONFIG_SYS_DA850_PLL_INIT */
+
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
+static int da850_ddr_setup(void)
+{
+       unsigned long   tmp;
+
+       /* Enable the Clock to DDR2/mDDR */
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+       if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
+               /* Begin VTP Calibration */
+               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+               clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
+
+               /* Polling READY bit to see when VTP calibration is done */
+               tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+               while ((tmp & VTP_READY) != VTP_READY)
+                       tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
+
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
+               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
+       }
+       setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
+       writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+       if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+               /* DDR2 */
+               clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+                       (1 << DDR_SLEW_DDR_PDENA_BIT) |
+                       (1 << DDR_SLEW_CMOSEN_BIT));
+       } else {
+               /* MOBILE DDR */
+               setbits_le32(&davinci_syscfg1_regs->ddr_slew,
+                       (1 << DDR_SLEW_DDR_PDENA_BIT) |
+                       (1 << DDR_SLEW_CMOSEN_BIT));
+       }
+
+       /*
+        * SDRAM Configuration Register (SDCR):
+        * First set the BOOTUNLOCK bit to make configuration bits
+        * writeable.
+        */
+       setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
+
+       /*
+        * Write the new value of these bits and clear BOOTUNLOCK.
+        * At the same time, set the TIMUNLOCK bit to allow changing
+        * the timing registers
+        */
+       tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
+       tmp &= ~DV_DDR_BOOTUNLOCK;
+       tmp |= DV_DDR_TIMUNLOCK;
+       writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+       /* write memory configuration and timing */
+       if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+               /* MOBILE DDR only*/
+               writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+                       &dv_ddr2_regs_ctrl->sdbcr2);
+       }
+       writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+       writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+       /* clear the TIMUNLOCK bit and write the value of the CL field */
+       tmp &= ~DV_DDR_TIMUNLOCK;
+       writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
+
+       /*
+        * LPMODEN and MCLKSTOPEN must be set!
+        * Without this bits set, PSC don;t switch states !!
+        */
+       writel(CONFIG_SYS_DA850_DDR2_SDRCR |
+               (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
+               (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
+               &dv_ddr2_regs_ctrl->sdrcr);
+
+       /* SyncReset the Clock to EMIF3A SDRAM */
+       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+       /* Enable the Clock to EMIF3A SDRAM */
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+       /* disable self refresh */
+       clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
+               DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
+       writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+       return 0;
+}
+#endif /* CONFIG_SYS_DA850_DDR_INIT */
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+       return;
+}
+
+int arch_cpu_init(void)
+{
+       /* Unlock kick registers */
+       writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+       writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+       dv_maskbits(&davinci_syscfg_regs->suspsrc,
+               CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
+
+       /* configure pinmux settings */
+       if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
+               return 1;
+
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
+       /* PLL setup */
+       da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
+       da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
+#endif
+       /* setup CSn config */
+#if defined(CONFIG_SYS_DA850_CS2CFG)
+       writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
+#endif
+#if defined(CONFIG_SYS_DA850_CS3CFG)
+       writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
+#endif
+
+       da8xx_configure_lpsc_items(lpsc, lpsc_size);
+
+       /* GPIO setup */
+       board_gpio_init();
+
+
+       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+                       CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+       /*
+        * Fix Power and Emulation Management Register
+        * see sprufw3a.pdf page 37 Table 24
+        */
+       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+               DAVINCI_UART_PWREMU_MGMT_UTRST),
+#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
+              &davinci_uart0_ctrl_regs->pwremu_mgmt);
+#else
+              &davinci_uart2_ctrl_regs->pwremu_mgmt);
+#endif
+
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
+       da850_ddr_setup();
+#endif
+
+       return 0;
+}
diff --git a/arch/arm/mach-davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c
new file mode 100644 (file)
index 0000000..6105f63
--- /dev/null
@@ -0,0 +1,181 @@
+/*
+ * Pinmux configurations for the DA850 SoCs
+ *
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pinmux_defs.h>
+
+/* SPI pin muxer settings */
+const struct pinmux_config spi1_pins_base[] = {
+       { pinmux(5), 1, 2 }, /* SPI1_CLK */
+       { pinmux(5), 1, 4 }, /* SPI1_SOMI */
+       { pinmux(5), 1, 5 }, /* SPI1_SIMO */
+};
+
+const struct pinmux_config spi1_pins_scs0[] = {
+       { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
+};
+
+/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+       { pinmux(3), 2, 4 }, /* UART0_RXD */
+       { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
+const struct pinmux_config uart0_pins_rtscts[] = {
+       { pinmux(3), 2, 6 },
+       { pinmux(3), 2, 7 },
+};
+
+const struct pinmux_config uart1_pins_txrx[] = {
+       { pinmux(4), 2, 6 }, /* UART1_RXD */
+       { pinmux(4), 2, 7 }, /* UART1_TXD */
+};
+
+const struct pinmux_config uart2_pins_txrx[] = {
+       { pinmux(4), 2, 4 }, /* UART2_RXD */
+       { pinmux(4), 2, 5 }, /* UART2_TXD */
+};
+
+const struct pinmux_config uart2_pins_rtscts[] = {
+       { pinmux(0), 4, 6 }, /* UART2_RTS */
+       { pinmux(0), 4, 7 }, /* UART2_CTS */
+};
+
+/* EMAC pin muxer settings*/
+const struct pinmux_config emac_pins_rmii[] = {
+       { pinmux(14), 8, 2 }, /* RMII_TXD[1] */
+       { pinmux(14), 8, 3 }, /* RMII_TXD[0] */
+       { pinmux(14), 8, 4 }, /* RMII_TXEN */
+       { pinmux(14), 8, 5 }, /* RMII_RXD[1] */
+       { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
+       { pinmux(14), 8, 7 }, /* RMII_RXER */
+       { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */
+       { pinmux(15), 8, 1 }, /* RMII_CRS_DV */
+};
+
+const struct pinmux_config emac_pins_mii[] = {
+       { pinmux(2), 8, 1 }, /* MII_TXEN */
+       { pinmux(2), 8, 2 }, /* MII_TXCLK */
+       { pinmux(2), 8, 3 }, /* MII_COL */
+       { pinmux(2), 8, 4 }, /* MII_TXD[3] */
+       { pinmux(2), 8, 5 }, /* MII_TXD[2] */
+       { pinmux(2), 8, 6 }, /* MII_TXD[1] */
+       { pinmux(2), 8, 7 }, /* MII_TXD[0] */
+       { pinmux(3), 8, 0 }, /* MII_RXCLK */
+       { pinmux(3), 8, 1 }, /* MII_RXDV */
+       { pinmux(3), 8, 2 }, /* MII_RXER */
+       { pinmux(3), 8, 3 }, /* MII_CRS */
+       { pinmux(3), 8, 4 }, /* MII_RXD[3] */
+       { pinmux(3), 8, 5 }, /* MII_RXD[2] */
+       { pinmux(3), 8, 6 }, /* MII_RXD[1] */
+       { pinmux(3), 8, 7 }, /* MII_RXD[0] */
+};
+
+const struct pinmux_config emac_pins_mdio[] = {
+       { pinmux(4), 8, 0 }, /* MDIO_CLK */
+       { pinmux(4), 8, 1 }, /* MDIO_D */
+};
+
+/* I2C pin muxer settings */
+const struct pinmux_config i2c0_pins[] = {
+       { pinmux(4), 2, 2 }, /* I2C0_SCL */
+       { pinmux(4), 2, 3 }, /* I2C0_SDA */
+};
+
+const struct pinmux_config i2c1_pins[] = {
+       { pinmux(4), 4, 4 }, /* I2C1_SCL */
+       { pinmux(4), 4, 5 }, /* I2C1_SDA */
+};
+
+/* EMIFA pin muxer settings */
+const struct pinmux_config emifa_pins_cs2[] = {
+       { pinmux(7), 1, 0 }, /* EMA_CS2 */
+};
+
+const struct pinmux_config emifa_pins_cs3[] = {
+       { pinmux(7), 1, 1 }, /* EMA_CS[3] */
+};
+
+const struct pinmux_config emifa_pins_cs4[] = {
+       { pinmux(7), 1, 2 }, /* EMA_CS[4] */
+};
+
+const struct pinmux_config emifa_pins_nand[] = {
+       { pinmux(7), 1, 4 },  /* EMA_WE */
+       { pinmux(7), 1, 5 },  /* EMA_OE */
+       { pinmux(9), 1, 0 },  /* EMA_D[7] */
+       { pinmux(9), 1, 1 },  /* EMA_D[6] */
+       { pinmux(9), 1, 2 },  /* EMA_D[5] */
+       { pinmux(9), 1, 3 },  /* EMA_D[4] */
+       { pinmux(9), 1, 4 },  /* EMA_D[3] */
+       { pinmux(9), 1, 5 },  /* EMA_D[2] */
+       { pinmux(9), 1, 6 },  /* EMA_D[1] */
+       { pinmux(9), 1, 7 },  /* EMA_D[0] */
+       { pinmux(12), 1, 5 }, /* EMA_A[2] */
+       { pinmux(12), 1, 6 }, /* EMA_A[1] */
+};
+
+/* NOR pin muxer settings */
+const struct pinmux_config emifa_pins_nor[] = {
+       { pinmux(5), 1, 6 },  /* EMA_BA[1] */
+       { pinmux(6), 1, 6 },  /* EMA_WAIT[1] */
+       { pinmux(7), 1, 4 },  /* EMA_WE */
+       { pinmux(7), 1, 5 },  /* EMA_OE */
+       { pinmux(8), 1, 0 },  /* EMA_D[15] */
+       { pinmux(8), 1, 1 },  /* EMA_D[14] */
+       { pinmux(8), 1, 2 },  /* EMA_D[13] */
+       { pinmux(8), 1, 3 },  /* EMA_D[12] */
+       { pinmux(8), 1, 4 },  /* EMA_D[11] */
+       { pinmux(8), 1, 5 },  /* EMA_D[10] */
+       { pinmux(8), 1, 6 },  /* EMA_D[9] */
+       { pinmux(8), 1, 7 },  /* EMA_D[8] */
+       { pinmux(9), 1, 0 },  /* EMA_D[7] */
+       { pinmux(9), 1, 1 },  /* EMA_D[6] */
+       { pinmux(9), 1, 2 },  /* EMA_D[5] */
+       { pinmux(9), 1, 3 },  /* EMA_D[4] */
+       { pinmux(9), 1, 4 },  /* EMA_D[3] */
+       { pinmux(9), 1, 5 },  /* EMA_D[2] */
+       { pinmux(9), 1, 6 },  /* EMA_D[1] */
+       { pinmux(9), 1, 7 },  /* EMA_D[0] */
+       { pinmux(10), 1, 1 }, /* EMA_A[22] */
+       { pinmux(10), 1, 2 }, /* EMA_A[21] */
+       { pinmux(10), 1, 3 }, /* EMA_A[20] */
+       { pinmux(10), 1, 4 }, /* EMA_A[19] */
+       { pinmux(10), 1, 5 }, /* EMA_A[18] */
+       { pinmux(10), 1, 6 }, /* EMA_A[17] */
+       { pinmux(10), 1, 7 }, /* EMA_A[16] */
+       { pinmux(11), 1, 0 }, /* EMA_A[15] */
+       { pinmux(11), 1, 1 }, /* EMA_A[14] */
+       { pinmux(11), 1, 2 }, /* EMA_A[13] */
+       { pinmux(11), 1, 3 }, /* EMA_A[12] */
+       { pinmux(11), 1, 4 }, /* EMA_A[11] */
+       { pinmux(11), 1, 5 }, /* EMA_A[10] */
+       { pinmux(11), 1, 6 }, /* EMA_A[9] */
+       { pinmux(11), 1, 7 }, /* EMA_A[8] */
+       { pinmux(12), 1, 0 }, /* EMA_A[7] */
+       { pinmux(12), 1, 1 }, /* EMA_A[6] */
+       { pinmux(12), 1, 2 }, /* EMA_A[5] */
+       { pinmux(12), 1, 3 }, /* EMA_A[4] */
+       { pinmux(12), 1, 4 }, /* EMA_A[3] */
+       { pinmux(12), 1, 5 }, /* EMA_A[2] */
+       { pinmux(12), 1, 6 }, /* EMA_A[1] */
+       { pinmux(12), 1, 7 }, /* EMA_A[0] */
+};
+
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+       { pinmux(10), 2, 0 },   /* MMCSD0_CLK */
+       { pinmux(10), 2, 1 },   /* MMCSD0_CMD */
+       { pinmux(10), 2, 2 },   /* MMCSD0_DAT_0 */
+       { pinmux(10), 2, 3 },   /* MMCSD0_DAT_1 */
+       { pinmux(10), 2, 4 },   /* MMCSD0_DAT_2 */
+       { pinmux(10), 2, 5 },   /* MMCSD0_DAT_3 */
+       /* DA850 supports only 4-bit mode, remaining pins are not configured */
+};
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
new file mode 100644 (file)
index 0000000..f9550a1
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * SoC-specific code for tms320dm355 and similar chips
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+void davinci_enable_uart0(void)
+{
+       lpsc_on(DAVINCI_LPSC_UART0);
+
+       /* Bringup UART0 out of reset */
+       REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+       lpsc_on(DAVINCI_LPSC_I2C);
+
+       /* Enable I2C pin Mux */
+       REG(PINMUX3) |= (1 << 20) | (1 << 19);
+}
+#endif
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
new file mode 100644 (file)
index 0000000..f6ca527
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * SoC-specific code for tms320dm365 and similar chips
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void davinci_enable_uart0(void)
+{
+       lpsc_on(DAVINCI_LPSC_UART0);
+}
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+       lpsc_on(DAVINCI_LPSC_I2C);
+}
+#endif
diff --git a/arch/arm/mach-davinci/dm365_lowlevel.c b/arch/arm/mach-davinci/dm365_lowlevel.c
new file mode 100644 (file)
index 0000000..c8b4498
--- /dev/null
@@ -0,0 +1,460 @@
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ * Actually used for booting from NAND with nand_spl.
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <nand.h>
+#include <ns16550.h>
+#include <post.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <asm/arch/hardware.h>
+
+void dm365_waitloop(unsigned long loopcnt)
+{
+       unsigned long   i;
+
+       for (i = 0; i < loopcnt; i++)
+               asm("   NOP");
+}
+
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
+{
+       unsigned int clksrc = 0x0;
+
+       /* Power up the PLL */
+       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
+
+       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
+       setbits_le32(&dv_pll0_regs->pllctl,
+               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
+
+       /*
+        * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+        * through MMR
+        */
+       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
+
+       /* Set PLLEN=0 => PLL BYPASS MODE */
+       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+       dm365_waitloop(150);
+
+        /* PLLRST=1(reset assert) */
+       setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+       dm365_waitloop(300);
+
+       /*Bring PLL out of Reset*/
+       clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
+
+       /* Program the Multiper and Pre-Divider for PLL1 */
+       writel(pllmult, &dv_pll0_regs->pllm);
+       writel(prediv, &dv_pll0_regs->prediv);
+
+       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+               PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+               &dv_pll0_regs->secctl);
+       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+       writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
+       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
+
+       /* Program the PostDiv for PLL1 */
+       writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
+
+       /* Post divider setting for PLL1 */
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
+       writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
+
+       dm365_waitloop(300);
+
+       /* Set the GOSET bit */
+       writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
+
+       dm365_waitloop(300);
+
+       /* Wait for PLL to LOCK */
+       while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
+               == PLL0_LOCK))
+               ;
+
+       /* Enable the PLL Bit of PLLCTL*/
+       setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
+
+       return 0;
+}
+
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
+{
+       unsigned int clksrc = 0x0;
+
+       /* Power up the PLL*/
+       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
+
+       /*
+        * Select the Clock Mode as Onchip Oscilator or External Clock on
+        * MXI pin
+        * VDB has input on MXI pin
+        */
+       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
+       setbits_le32(&dv_pll1_regs->pllctl,
+               clksrc << PLLCTL_CLOCK_MODE_SHIFT);
+
+       /*
+        * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
+        * through MMR
+        */
+       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
+
+       /* Set PLLEN=0 => PLL BYPASS MODE */
+       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+       dm365_waitloop(50);
+
+        /* PLLRST=1(reset assert) */
+       setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+       dm365_waitloop(300);
+
+       /* Bring PLL out of Reset */
+       clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
+
+       /* Program the Multiper and Pre-Divider for PLL2 */
+       writel(pllm, &dv_pll1_regs->pllm);
+       writel(prediv, &dv_pll1_regs->prediv);
+
+       writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
+
+       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
+       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
+               PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+       /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
+       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
+               &dv_pll1_regs->secctl);
+       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
+       writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
+       /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
+       writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
+
+       /* Post divider setting for PLL2 */
+       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
+       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
+       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
+       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
+       writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
+
+       /* GoCmd for PostDivider to take effect */
+       writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
+
+       dm365_waitloop(150);
+
+       /* Wait for PLL to LOCK */
+       while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
+               == PLL1_LOCK))
+               ;
+
+       dm365_waitloop(4100);
+
+       /* Enable the PLL2 */
+       setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
+
+       /* do this after PLL's have been set up */
+       writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
+               &dv_sys_module_regs->peri_clkctl);
+
+       return 0;
+}
+
+int dm365_ddr_setup(void)
+{
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+       clrbits_le32(&dv_sys_module_regs->vtpiocr,
+               VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
+
+       /* Set bit CLRZ (bit 13) */
+       setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
+
+       /* Check VTP READY Status */
+       while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
+               ;
+
+       /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
+       setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
+
+       /* Set bit LOCK(bit7) */
+       setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
+
+       /*
+        * Powerdown VTP as it is locked (bit 6)
+        * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
+        */
+       setbits_le32(&dv_sys_module_regs->vtpiocr,
+               VPTIO_IOPWRDN | VPTIO_PWRDN);
+
+       /* Wait for calibration to complete */
+       dm365_waitloop(150);
+
+       /* Set the DDR2 to synreset, then enable it again */
+       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+       writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
+
+       /* Program SDRAM Bank Config Register */
+       writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
+               &dv_ddr2_regs_ctrl->sdbcr);
+       writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
+               &dv_ddr2_regs_ctrl->sdbcr);
+
+       /* Program SDRAM Timing Control Register1 */
+       writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
+       /* Program SDRAM Timing Control Register2 */
+       writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
+
+       writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
+
+       writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
+
+       /* Program SDRAM Refresh Control Register */
+       writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
+
+       lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
+       lpsc_on(DAVINCI_LPSC_DDR_EMIF);
+
+       return 0;
+}
+
+static void dm365_vpss_sync_reset(void)
+{
+       unsigned int PdNum = 0;
+
+       /* VPSS_CLKMD 1:1 */
+       setbits_le32(&dv_sys_module_regs->vpss_clkctl,
+               VPSS_CLK_CTL_VPSS_CLKMD);
+
+       /* LPSC SyncReset DDR Clock Enable */
+       writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
+               ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
+               &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
+
+       writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+       while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
+               ;
+       while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
+               PSC_MD_STATE_MSK) == PSC_SYNCRESET))
+               ;
+}
+
+static void dm365_por_reset(void)
+{
+       struct davinci_timer *wdog =
+               (struct davinci_timer *)DAVINCI_WDOG_BASE;
+
+       if (readl(&dv_pll0_regs->rstype) &
+               (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
+               dm365_vpss_sync_reset();
+
+               writel(DV_TMPBUF_VAL, TMPBUF);
+               setbits_le32(TMPSTATUS, FLAG_PORRST);
+               writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
+               writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
+
+               while (1);
+       }
+}
+
+static void dm365_wdt_reset(void)
+{
+       struct davinci_timer *wdog =
+               (struct davinci_timer *)DAVINCI_WDOG_BASE;
+
+       if (readl(TMPBUF) != DV_TMPBUF_VAL) {
+               writel(DV_TMPBUF_VAL, TMPBUF);
+               setbits_le32(TMPSTATUS, FLAG_PORRST);
+               setbits_le32(TMPSTATUS, FLAG_FLGOFF);
+
+               dm365_waitloop(100);
+
+               dm365_vpss_sync_reset();
+
+               writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
+               writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
+
+               while (1);
+       }
+}
+
+static void dm365_wdt_flag_on(void)
+{
+       /* VPSS_CLKMD 1:2 */
+       clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
+               VPSS_CLK_CTL_VPSS_CLKMD);
+       writel(0, TMPBUF);
+       setbits_le32(TMPSTATUS, FLAG_FLGON);
+}
+
+void dm365_psc_init(void)
+{
+       unsigned char i = 0;
+       unsigned char lpsc_start;
+       unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
+       unsigned int  PdNum = 0;
+
+       lpscmin = 0;
+       lpscmax = 2;
+
+       for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
+               if (lpscgroup == 0) {
+                       /* Enabling LPSC 3 to 28 SCR first */
+                       lpsc_start = DAVINCI_LPSC_VPSSMSTR;
+                       lpsc_end   = DAVINCI_LPSC_TIMER1;
+               } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
+                       lpsc_start = DAVINCI_LPSC_CFG5;
+                       lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
+               } else {
+                       lpsc_start = DAVINCI_LPSC_MJCP;
+                       lpsc_end   = DAVINCI_LPSC_HDVICP;
+               }
+
+               /* NEXT=0x3, Enable LPSC's */
+               for (i = lpsc_start; i <= lpsc_end; i++)
+                       setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
+
+               /*
+                * Program goctl to start transition sequence for LPSCs
+                * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
+                * Domain 0 Modules
+                */
+               writel((1 << PdNum), &dv_psc_regs->ptcmd);
+
+               /*
+                * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
+                */
+               while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
+                       == 0))
+                       ;
+
+               /* Wait for MODSTAT = ENABLE from LPSC's */
+               for (i = lpsc_start; i <= lpsc_end; i++)
+                       while (!((readl(&dv_psc_regs->mdstat[i]) &
+                               PSC_MD_STATE_MSK) == PSC_ENABLE))
+                               ;
+       }
+}
+
+static void dm365_emif_init(void)
+{
+       writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
+       writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
+
+       setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
+
+       writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
+
+       return;
+}
+
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+       unsigned long value)
+{
+       clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
+       setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
+}
+
+__attribute__((weak))
+void board_gpio_init(void)
+{
+       return;
+}
+
+#if defined(CONFIG_POST)
+int post_log(char *format, ...)
+{
+       return 0;
+}
+#endif
+
+void dm36x_lowlevel_init(ulong bootflag)
+{
+       struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
+               (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
+               DAVINCI_UART_CTRL_BASE);
+
+       /* Mask all interrupts */
+       writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
+       writel(0x0, &dv_aintc_regs->eabase);
+       writel(0x0, &dv_aintc_regs->eint0);
+       writel(0x0, &dv_aintc_regs->eint1);
+
+       /* Clear all interrupts */
+       writel(0xffffffff, &dv_aintc_regs->fiq0);
+       writel(0xffffffff, &dv_aintc_regs->fiq1);
+       writel(0xffffffff, &dv_aintc_regs->irq0);
+       writel(0xffffffff, &dv_aintc_regs->irq1);
+
+       dm365_por_reset();
+       dm365_wdt_reset();
+
+       /* System PSC setup - enable all */
+       dm365_psc_init();
+
+       /* Setup Pinmux */
+       dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
+       dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
+       dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
+       dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
+       dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
+
+       /* PLL setup */
+       dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
+               CONFIG_SYS_DM36x_PLL1_PREDIV);
+       dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
+               CONFIG_SYS_DM36x_PLL2_PREDIV);
+
+       /* GPIO setup */
+       board_gpio_init();
+
+       NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
+                       CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+
+       /*
+        * Fix Power and Emulation Management Register
+        * see sprufh2.pdf page 38 Table 22
+        */
+       writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+               DAVINCI_UART_PWREMU_MGMT_UTRST),
+              &davinci_uart_ctrl_regs->pwremu_mgmt);
+
+       puts("ddr init\n");
+       dm365_ddr_setup();
+
+       puts("emif init\n");
+       dm365_emif_init();
+
+       dm365_wdt_flag_on();
+
+#if defined(CONFIG_POST)
+       /*
+        * Do memory tests, calls arch_memory_failure_handle()
+        * if error detected.
+        */
+       memory_post_test(0);
+#endif
+}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
new file mode 100644 (file)
index 0000000..c58e271
--- /dev/null
@@ -0,0 +1,81 @@
+/*
+ * SoC-specific code for tms320dm644x chips
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+#define PINMUX0_EMACEN (1 << 31)
+#define PINMUX0_AECS5  (1 << 11)
+#define PINMUX0_AECS4  (1 << 10)
+
+#define PINMUX1_I2C    (1 <<  7)
+#define PINMUX1_UART1  (1 <<  1)
+#define PINMUX1_UART0  (1 <<  0)
+
+
+void davinci_enable_uart0(void)
+{
+       lpsc_on(DAVINCI_LPSC_UART0);
+
+       /* Bringup UART0 out of reset */
+       REG(UART0_PWREMU_MGMT) = 0x00006001;
+
+       /* Enable UART0 MUX lines */
+       REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+       lpsc_on(DAVINCI_LPSC_EMAC);
+       lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+       lpsc_on(DAVINCI_LPSC_MDIO);
+
+       /* Enable GIO3.3V cells used for EMAC */
+       REG(VDD3P3V_PWDN) = 0;
+
+       /* Enable EMAC. */
+       REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+       lpsc_on(DAVINCI_LPSC_I2C);
+
+       /* Enable I2C pin Mux */
+       REG(PINMUX1) |= PINMUX1_I2C;
+}
+#endif
+
+void davinci_errata_workarounds(void)
+{
+       /*
+        * Workaround for TMS320DM6446 errata 1.3.22:
+        *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
+        *   Revision(s) Affected: 1.3 and earlier
+        */
+       REG(PSC_SILVER_BULLET) = 0;
+
+       /*
+        * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
+        * as suggested in TMS320DM6446 errata 2.1.2:
+        *
+        * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
+        * low priority modules can occupy the bus and prevent high priority
+        * modules like the VPSS from getting the required DDR2 throughput.
+        * A hex value of 0x20 should provide a good ARM (cache enabled)
+        * performance and still allow good utilization by the VPSS or other
+        * modules.
+        */
+       REG(VBPR) = 0x20;
+}
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
new file mode 100644 (file)
index 0000000..cfea830
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * SoC-specific code for TMS320DM646x chips
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+
+void davinci_enable_uart0(void)
+{
+       lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+       lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_DAVINCI
+void davinci_enable_i2c(void)
+{
+       lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+}
+#endif
diff --git a/arch/arm/mach-davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c
new file mode 100644 (file)
index 0000000..6387e95
--- /dev/null
@@ -0,0 +1,128 @@
+/*
+ * National Semiconductor DP83848 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * --------------------------------------------------------
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <dp83848.h>
+#include <asm/arch/emac_defs.h>
+#include "../../../drivers/net/davinci_emac.h"
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+int dp83848_is_phy_connected(int phy_addr)
+{
+       u_int16_t       id1, id2;
+
+       if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
+               return(0);
+       if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
+               return(0);
+
+       if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
+               return(1);
+
+       return(0);
+}
+
+int dp83848_get_link_speed(int phy_addr)
+{
+       u_int16_t               tmp;
+       volatile emac_regs*     emac = (emac_regs *)EMAC_BASE_ADDR;
+
+       if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
+               return(0);
+
+       if (!(tmp & DP83848_LINK_STATUS))       /* link up? */
+               return(0);
+
+       if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
+               return(0);
+
+       /* Speed doesn't matter, there is no setting for it in EMAC... */
+       if (tmp & DP83848_DUPLEX) {
+               /* set DM644x EMAC for Full Duplex  */
+               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+                       EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+       } else {
+               /*set DM644x EMAC for Half Duplex  */
+               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
+       }
+
+       return(1);
+}
+
+
+int dp83848_init_phy(int phy_addr)
+{
+       int     ret = 1;
+
+       if (!dp83848_get_link_speed(phy_addr)) {
+               /* Try another time */
+               udelay(100000);
+               ret = dp83848_get_link_speed(phy_addr);
+       }
+
+       /* Disable PHY Interrupts */
+       davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
+
+       return(ret);
+}
+
+
+int dp83848_auto_negotiate(int phy_addr)
+{
+       u_int16_t       tmp;
+
+
+       if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
+               return(0);
+
+       /* Restart Auto_negotiation  */
+       tmp &= ~DP83848_AUTONEG;        /* remove autonegotiation enable */
+       tmp |= DP83848_ISOLATE;         /* Electrically isolate PHY */
+       davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
+
+       /* Set the Auto_negotiation Advertisement Register
+        * MII advertising for Next page, 100BaseTxFD and HD,
+        * 10BaseTFD and HD, IEEE 802.3
+        */
+       tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
+               DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
+       davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
+
+
+       /* Read Control Register */
+       if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
+               return(0);
+
+       tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
+       davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
+
+       /* Restart Auto_negotiation  */
+       tmp |= DP83848_RESTART_AUTONEG;
+       davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
+
+       /*check AutoNegotiate complete */
+       udelay(10000);
+       if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
+               return(0);
+
+       if (!(tmp & DP83848_AUTONEG_COMP))
+               return(0);
+
+       return (dp83848_get_link_speed(phy_addr));
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c
new file mode 100644 (file)
index 0000000..151020d
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/arch/emac_defs.h>
+#include "../../../drivers/net/davinci_emac.h"
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
+
+#define MII_PHY_CONFIG_REG             22
+
+/* PHY Config bits */
+#define PHY_SYS_CLK_EN                 (1 << 4)
+
+int et1011c_get_link_speed(int phy_addr)
+{
+       u_int16_t       data;
+
+       if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
+               davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
+               /* Enable 125MHz clock sourced from PHY */
+               davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
+                       data | PHY_SYS_CLK_EN);
+               return (1);
+       }
+       return (0);
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/mach-davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c
new file mode 100644 (file)
index 0000000..75af135
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Micrel KSZ8873 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2011 Heiko Schocher <hsdenx.de>
+ *
+ * based on:
+ * National Semiconductor DP83848 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * --------------------------------------------------------
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <net.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include "../../../drivers/net/davinci_emac.h"
+
+int ksz8873_is_phy_connected(int phy_addr)
+{
+       u_int16_t       dummy;
+
+       return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
+}
+
+int ksz8873_get_link_speed(int phy_addr)
+{
+       emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
+
+       /* we always have a link to the switch, 100 FD */
+       writel((EMAC_MACCONTROL_MIIEN_ENABLE |
+               EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
+              &emac->MACCONTROL);
+       return 1;
+}
+
+
+int ksz8873_init_phy(int phy_addr)
+{
+       return 1;
+}
+
+
+int ksz8873_auto_negotiate(int phy_addr)
+{
+       return dp83848_get_link_speed(phy_addr);
+}
diff --git a/arch/arm/mach-davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S
new file mode 100644 (file)
index 0000000..e916234
--- /dev/null
@@ -0,0 +1,693 @@
+/*
+ * Low-level board setup code for TI DaVinci SoC based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Partially based on TI sources, original copyrights follow:
+ */
+
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ *
+ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
+ *
+ * Modified for DV-EVM board by Swaminathan S, Nov 2005
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+
+#define MDSTAT_STATE   0x3f
+
+.globl lowlevel_init
+lowlevel_init:
+#ifdef CONFIG_SOC_DM644X
+
+       /*-------------------------------------------------------*
+        * Mask all IRQs by setting all bits in the EINT default *
+        *-------------------------------------------------------*/
+       mov     r1, $0
+       ldr     r0, =EINT_ENABLE0
+       str     r1, [r0]
+       ldr     r0, =EINT_ENABLE1
+       str     r1, [r0]
+
+       /*------------------------------------------------------*
+        * Put the GEM in reset                                 *
+        *------------------------------------------------------*/
+
+       /* Put the GEM in reset */
+       ldr     r8, PSC_GEM_FLAG_CLEAR
+       ldr     r6, MDCTL_GEM
+       ldr     r7, [r6]
+       and     r7, r7, r8
+       str     r7, [r6]
+
+       /* Enable the Power Domain Transition Command */
+       ldr     r6, PTCMD
+       ldr     r7, [r6]
+       orr     r7, r7, $0x02
+       str     r7, [r6]
+
+       /* Check for Transition Complete(PTSTAT) */
+checkStatClkStopGem:
+       ldr     r6, PTSTAT
+       ldr     r7, [r6]
+       ands    r7, r7, $0x02
+       bne     checkStatClkStopGem
+
+       /* Check for GEM Reset Completion */
+checkGemStatClkStop:
+       ldr     r6, MDSTAT_GEM
+       ldr     r7, [r6]
+       ands    r7, r7, $0x100
+       bne     checkGemStatClkStop
+
+       /* Do this for enabling a WDT initiated reset this is a workaround
+          for a chip bug.  Not required under normal situations */
+       ldr     r6, P1394
+       mov     r10, $0
+       str     r10, [r6]
+
+       /*------------------------------------------------------*
+        * Enable L1 & L2 Memories in Fast mode                 *
+        *------------------------------------------------------*/
+       ldr     r6, DFT_ENABLE
+       mov     r10, $0x01
+       str     r10, [r6]
+
+       ldr     r6, MMARG_BRF0
+       ldr     r10, MMARG_BRF0_VAL
+       str     r10, [r6]
+
+       ldr     r6, DFT_ENABLE
+       mov     r10, $0
+       str     r10, [r6]
+
+       /*------------------------------------------------------*
+        * DDR2 PLL Initialization                              *
+        *------------------------------------------------------*/
+
+       /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
+       mov     r10, $0
+       ldr     r6, PLL2_CTL
+       ldr     r7, PLL_CLKSRC_MASK
+       ldr     r8, [r6]
+       and     r8, r8, r7
+       mov     r9, r10, lsl $8
+       orr     r8, r8, r9
+       str     r8, [r6]
+
+       /* Select the PLLEN source */
+       ldr     r7, PLL_ENSRC_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Bypass the PLL */
+       ldr     r7, PLL_BYPASS_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
+       mov     r10, $0x20
+WaitPPL2Loop:
+       subs    r10, r10, $1
+       bne     WaitPPL2Loop
+
+       /* Reset the PLL */
+       ldr     r7, PLL_RESET_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Power up the PLL */
+       ldr     r7, PLL_PWRUP_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Enable the PLL from Disable Mode */
+       ldr     r7, PLL_DISABLE_ENABLE_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Program the PLL Multiplier */
+       ldr     r6, PLL2_PLLM
+       mov     r2, $0x17       /* 162 MHz */
+       str     r2, [r6]
+
+       /* Program the PLL2 Divisor Value */
+       ldr     r6, PLL2_DIV2
+       mov     r3, $0x01
+       str     r3, [r6]
+
+       /* Program the PLL2 Divisor Value */
+       ldr     r6, PLL2_DIV1
+       mov     r4, $0x0b       /* 54 MHz */
+       str     r4, [r6]
+
+       /* PLL2 DIV2 MMR */
+       ldr     r8, PLL2_DIV_MASK
+       ldr     r6, PLL2_DIV2
+       ldr     r9, [r6]
+       and     r8, r8, r9
+       mov     r9, $0x01
+       mov     r9, r9, lsl $15
+       orr     r8, r8, r9
+       str     r8, [r6]
+
+       /* Program the GOSET bit to take new divider values */
+       ldr     r6, PLL2_PLLCMD
+       ldr     r7, [r6]
+       orr     r7, r7, $0x01
+       str     r7, [r6]
+
+       /* Wait for Done */
+       ldr     r6, PLL2_PLLSTAT
+doneLoop_0:
+       ldr     r7, [r6]
+       ands    r7, r7, $0x01
+       bne     doneLoop_0
+
+       /* PLL2 DIV1 MMR */
+       ldr     r8, PLL2_DIV_MASK
+       ldr     r6, PLL2_DIV1
+       ldr     r9, [r6]
+       and     r8, r8, r9
+       mov     r9, $0x01
+       mov     r9, r9, lsl $15
+       orr     r8, r8, r9
+       str     r8, [r6]
+
+       /* Program the GOSET bit to take new divider values */
+       ldr     r6, PLL2_PLLCMD
+       ldr     r7, [r6]
+       orr     r7, r7, $0x01
+       str     r7, [r6]
+
+       /* Wait for Done */
+       ldr     r6, PLL2_PLLSTAT
+doneLoop:
+       ldr     r7, [r6]
+       ands    r7, r7, $0x01
+       bne     doneLoop
+
+       /* Wait for PLL to Reset Properly */
+       mov     r10, $0x218
+ResetPPL2Loop:
+       subs    r10, r10, $1
+       bne     ResetPPL2Loop
+
+       /* Bring PLL out of Reset */
+       ldr     r6, PLL2_CTL
+       ldr     r8, [r6]
+       orr     r8, r8, $0x08
+       str     r8, [r6]
+
+       /* Wait for PLL to Lock */
+       ldr     r10, PLL_LOCK_COUNT
+PLL2Lock:
+       subs    r10, r10, $1
+       bne     PLL2Lock
+
+       /* Enable the PLL */
+       ldr     r6, PLL2_CTL
+       ldr     r8, [r6]
+       orr     r8, r8, $0x01
+       str     r8, [r6]
+
+       /*------------------------------------------------------*
+        * Issue Soft Reset to DDR Module                       *
+        *------------------------------------------------------*/
+
+       /* Shut down the DDR2 LPSC Module */
+       ldr     r8, PSC_FLAG_CLEAR
+       ldr     r6, MDCTL_DDR2
+       ldr     r7, [r6]
+       and     r7, r7, r8
+       orr     r7, r7, $0x03
+       str     r7, [r6]
+
+       /* Enable the Power Domain Transition Command */
+       ldr     r6, PTCMD
+       ldr     r7, [r6]
+       orr     r7, r7, $0x01
+       str     r7, [r6]
+
+       /* Check for Transition Complete(PTSTAT) */
+checkStatClkStop:
+       ldr     r6, PTSTAT
+       ldr     r7, [r6]
+       ands    r7, r7, $0x01
+       bne     checkStatClkStop
+
+       /* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkStop:
+       ldr     r6, MDSTAT_DDR2
+       ldr     r7, [r6]
+       and     r7, r7, $MDSTAT_STATE
+       cmp     r7, $0x03
+       bne     checkDDRStatClkStop
+
+       /*------------------------------------------------------*
+        * Program DDR2 MMRs for 162MHz Setting                 *
+        *------------------------------------------------------*/
+
+       /* Program PHY Control Register */
+       ldr     r6, DDRCTL
+       ldr     r7, DDRCTL_VAL
+       str     r7, [r6]
+
+       /* Program SDRAM Bank Config Register */
+       ldr     r6, SDCFG
+       ldr     r7, SDCFG_VAL
+       str     r7, [r6]
+
+       /* Program SDRAM TIM-0 Config Register */
+       ldr     r6, SDTIM0
+       ldr     r7, SDTIM0_VAL_162MHz
+       str     r7, [r6]
+
+       /* Program SDRAM TIM-1 Config Register */
+       ldr     r6, SDTIM1
+       ldr     r7, SDTIM1_VAL_162MHz
+       str     r7, [r6]
+
+       /* Program the SDRAM Bank Config Control Register */
+       ldr     r10, MASK_VAL
+       ldr     r8, SDCFG
+       ldr     r9, SDCFG_VAL
+       and     r9, r9, r10
+       str     r9, [r8]
+
+       /* Program SDRAM SDREF Config Register */
+       ldr     r6, SDREF
+       ldr     r7, SDREF_VAL
+       str     r7, [r6]
+
+       /*------------------------------------------------------*
+        * Issue Soft Reset to DDR Module                       *
+        *------------------------------------------------------*/
+
+       /* Issue a Dummy DDR2 read/write */
+       ldr     r8, DDR2_START_ADDR
+       ldr     r7, DUMMY_VAL
+       str     r7, [r8]
+       ldr     r7, [r8]
+
+       /* Shut down the DDR2 LPSC Module */
+       ldr     r8, PSC_FLAG_CLEAR
+       ldr     r6, MDCTL_DDR2
+       ldr     r7, [r6]
+       and     r7, r7, r8
+       orr     r7, r7, $0x01
+       str     r7, [r6]
+
+       /* Enable the Power Domain Transition Command */
+       ldr     r6, PTCMD
+       ldr     r7, [r6]
+       orr     r7, r7, $0x01
+       str     r7, [r6]
+
+       /* Check for Transition Complete(PTSTAT) */
+checkStatClkStop2:
+       ldr     r6, PTSTAT
+       ldr     r7, [r6]
+       ands    r7, r7, $0x01
+       bne     checkStatClkStop2
+
+       /* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkStop2:
+       ldr     r6, MDSTAT_DDR2
+       ldr     r7, [r6]
+       and     r7, r7, $MDSTAT_STATE
+       cmp     r7, $0x01
+       bne     checkDDRStatClkStop2
+
+       /*------------------------------------------------------*
+        * Turn DDR2 Controller Clocks On                       *
+        *------------------------------------------------------*/
+
+       /* Enable the DDR2 LPSC Module */
+       ldr     r6, MDCTL_DDR2
+       ldr     r7, [r6]
+       orr     r7, r7, $0x03
+       str     r7, [r6]
+
+       /* Enable the Power Domain Transition Command */
+       ldr     r6, PTCMD
+       ldr     r7, [r6]
+       orr     r7, r7, $0x01
+       str     r7, [r6]
+
+       /* Check for Transition Complete(PTSTAT) */
+checkStatClkEn2:
+       ldr     r6, PTSTAT
+       ldr     r7, [r6]
+       ands    r7, r7, $0x01
+       bne     checkStatClkEn2
+
+       /* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkEn2:
+       ldr     r6, MDSTAT_DDR2
+       ldr     r7, [r6]
+       and     r7, r7, $MDSTAT_STATE
+       cmp     r7, $0x03
+       bne     checkDDRStatClkEn2
+
+       /*  DDR Writes and Reads */
+       ldr     r6, CFGTEST
+       mov     r3, $0x01
+       str     r3, [r6]
+
+       /*------------------------------------------------------*
+        * System PLL Initialization                            *
+        *------------------------------------------------------*/
+
+       /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
+       mov     r2, $0
+       ldr     r6, PLL1_CTL
+       ldr     r7, PLL_CLKSRC_MASK
+       ldr     r8, [r6]
+       and     r8, r8, r7
+       mov     r9, r2, lsl $8
+       orr     r8, r8, r9
+       str     r8, [r6]
+
+       /* Select the PLLEN source */
+       ldr     r7, PLL_ENSRC_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Bypass the PLL */
+       ldr     r7, PLL_BYPASS_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
+       mov     r10, $0x20
+
+WaitLoop:
+       subs    r10, r10, $1
+       bne     WaitLoop
+
+       /* Reset the PLL */
+       ldr     r7, PLL_RESET_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Disable the PLL */
+       orr     r8, r8, $0x10
+       str     r8, [r6]
+
+       /* Power up the PLL */
+       ldr     r7, PLL_PWRUP_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Enable the PLL from Disable Mode */
+       ldr     r7, PLL_DISABLE_ENABLE_MASK
+       and     r8, r8, r7
+       str     r8, [r6]
+
+       /* Program the PLL Multiplier */
+       ldr     r6, PLL1_PLLM
+       mov     r3, $0x15       /* For 594MHz */
+       str     r3, [r6]
+
+       /* Wait for PLL to Reset Properly */
+       mov     r10, $0xff
+
+ResetLoop:
+       subs    r10, r10, $1
+       bne     ResetLoop
+
+       /* Bring PLL out of Reset */
+       ldr     r6, PLL1_CTL
+       orr     r8, r8, $0x08
+       str     r8, [r6]
+
+       /* Wait for PLL to Lock */
+       ldr     r10, PLL_LOCK_COUNT
+
+PLL1Lock:
+       subs    r10, r10, $1
+       bne     PLL1Lock
+
+       /* Enable the PLL */
+       orr     r8, r8, $0x01
+       str     r8, [r6]
+
+       nop
+       nop
+       nop
+       nop
+
+       /*------------------------------------------------------*
+        * AEMIF configuration for NOR Flash (double check)     *
+        *------------------------------------------------------*/
+       ldr     r0, _PINMUX0
+       ldr     r1, _DEV_SETTING
+       str     r1, [r0]
+
+       ldr     r0, WAITCFG
+       ldr     r1, WAITCFG_VAL
+       ldr     r2, [r0]
+       orr     r2, r2, r1
+       str     r2, [r0]
+
+       ldr     r0, ACFG3
+       ldr     r1, ACFG3_VAL
+       ldr     r2, [r0]
+       and     r1, r2, r1
+       str     r1, [r0]
+
+       ldr     r0, ACFG4
+       ldr     r1, ACFG4_VAL
+       ldr     r2, [r0]
+       and     r1, r2, r1
+       str     r1, [r0]
+
+       ldr     r0, ACFG5
+       ldr     r1, ACFG5_VAL
+       ldr     r2, [r0]
+       and     r1, r2, r1
+       str     r1, [r0]
+
+       /*--------------------------------------*
+        * VTP manual Calibration               *
+        *--------------------------------------*/
+       ldr     r0, VTPIOCR
+       ldr     r1, VTP_MMR0
+       str     r1, [r0]
+
+       ldr     r0, VTPIOCR
+       ldr     r1, VTP_MMR1
+       str     r1, [r0]
+
+       /* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
+       ldr     r10, VTP_LOCK_COUNT
+VTPLock:
+       subs    r10, r10, $1
+       bne     VTPLock
+
+       ldr     r6, DFT_ENABLE
+       mov     r10, $0x01
+       str     r10, [r6]
+
+       ldr     r6, DDRVTPR
+       ldr     r7, [r6]
+       mov     r8, r7, LSL #32-10
+       mov     r8, r8, LSR #32-10        /* grab low 10 bits  */
+       ldr     r7, VTP_RECAL
+       orr     r8, r7, r8
+       ldr     r7, VTP_EN
+       orr     r8, r7, r8
+       str     r8, [r0]
+
+
+       /* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
+       ldr     r10, VTP_LOCK_COUNT
+VTP1Lock:
+       subs    r10, r10, $1
+       bne     VTP1Lock
+
+       ldr     r1, [r0]
+       ldr     r2, VTP_MASK
+       and     r2, r1, r2
+       str     r2, [r0]
+
+       ldr     r6, DFT_ENABLE
+       mov     r10, $0
+       str     r10, [r6]
+
+       /*
+        * Call board-specific lowlevel init.
+        * That MUST be present and THAT returns
+        * back to arch calling code with "mov pc, lr."
+        */
+       b       dv_board_init
+
+.ltorg
+
+_PINMUX0:
+       .word   0x01c40000              /* Device Configuration Registers */
+_PINMUX1:
+       .word   0x01c40004              /* Device Configuration Registers */
+
+_DEV_SETTING:
+       .word   0x00000c1f
+
+WAITCFG:
+       .word   0x01e00004
+WAITCFG_VAL:
+       .word   0
+ACFG3:
+       .word   0x01e00014
+ACFG3_VAL:
+       .word   0x3ffffffd
+ACFG4:
+       .word   0x01e00018
+ACFG4_VAL:
+       .word   0x3ffffffd
+ACFG5:
+       .word   0x01e0001c
+ACFG5_VAL:
+       .word   0x3ffffffd
+
+MDCTL_DDR2:
+       .word   0x01c41a34
+MDSTAT_DDR2:
+       .word   0x01c41834
+
+PTCMD:
+       .word   0x01c41120
+PTSTAT:
+       .word   0x01c41128
+
+EINT_ENABLE0:
+       .word   0x01c48018
+EINT_ENABLE1:
+       .word   0x01c4801c
+
+PSC_FLAG_CLEAR:
+       .word   0xffffffe0
+PSC_GEM_FLAG_CLEAR:
+       .word   0xfffffeff
+
+/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+DDRCTL:
+       .word   0x200000e4
+DDRCTL_VAL:
+       .word   0x50006405
+SDREF:
+       .word   0x2000000c
+SDREF_VAL:
+       .word   0x000005c3
+SDCFG:
+       .word   0x20000008
+SDCFG_VAL:
+#ifdef DDR_4BANKS
+       .word   0x00178622
+#elif defined DDR_8BANKS
+       .word   0x00178632
+#else
+#error "Unknown DDR configuration!!!"
+#endif
+SDTIM0:
+       .word   0x20000010
+SDTIM0_VAL_162MHz:
+       .word   0x28923211
+SDTIM1:
+       .word   0x20000014
+SDTIM1_VAL_162MHz:
+       .word   0x0016c722
+VTPIOCR:
+       .word   0x200000f0      /* VTP IO Control register */
+DDRVTPR:
+       .word   0x01c42030      /* DDR VPTR MMR */
+VTP_MMR0:
+       .word   0x201f
+VTP_MMR1:
+       .word   0xa01f
+DFT_ENABLE:
+       .word   0x01c4004c
+VTP_LOCK_COUNT:
+       .word   0x5b0
+VTP_MASK:
+       .word   0xffffdfff
+VTP_RECAL:
+       .word   0x08000
+VTP_EN:
+       .word   0x02000
+CFGTEST:
+       .word   0x80010000
+MASK_VAL:
+       .word   0x00000fff
+
+/* GEM Power Up & LPSC Control Register */
+MDCTL_GEM:
+       .word   0x01c41a9c
+MDSTAT_GEM:
+       .word   0x01c4189c
+
+/* For WDT reset chip bug */
+P1394:
+       .word   0x01c41a20
+
+PLL_CLKSRC_MASK:
+       .word   0xfffffeff      /* Mask the Clock Mode bit */
+PLL_ENSRC_MASK:
+       .word   0xffffffdf      /* Select the PLLEN source */
+PLL_BYPASS_MASK:
+       .word   0xfffffffe      /* Put the PLL in BYPASS */
+PLL_RESET_MASK:
+       .word   0xfffffff7      /* Put the PLL in Reset Mode */
+PLL_PWRUP_MASK:
+       .word   0xfffffffd      /* PLL Power up Mask Bit  */
+PLL_DISABLE_ENABLE_MASK:
+       .word   0xffffffef      /* Enable the PLL from Disable */
+PLL_LOCK_COUNT:
+       .word   0x2000
+
+/* PLL1-SYSTEM PLL MMRs */
+PLL1_CTL:
+       .word   0x01c40900
+PLL1_PLLM:
+       .word   0x01c40910
+
+/* PLL2-SYSTEM PLL MMRs */
+PLL2_CTL:
+       .word   0x01c40d00
+PLL2_PLLM:
+       .word   0x01c40d10
+PLL2_DIV1:
+       .word   0x01c40d18
+PLL2_DIV2:
+       .word   0x01c40d1c
+PLL2_PLLCMD:
+       .word   0x01c40d38
+PLL2_PLLSTAT:
+       .word   0x01c40d3c
+PLL2_DIV_MASK:
+       .word   0xffff7fff
+
+MMARG_BRF0:
+       .word   0x01c42010      /* BRF margin mode 0 (R/W)*/
+MMARG_BRF0_VAL:
+       .word   0x00444400
+
+DDR2_START_ADDR:
+       .word   0x80000000
+DUMMY_VAL:
+       .word   0xa55aa55a
+#else /* CONFIG_SOC_DM644X */
+       mov pc, lr
+#endif
diff --git a/arch/arm/mach-davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c
new file mode 100644 (file)
index 0000000..a7356f9
--- /dev/null
@@ -0,0 +1,113 @@
+/*
+ * Intel LXT971/LXT972 PHY Driver for TI DaVinci
+ * (TMS320DM644x) based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * --------------------------------------------------------
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <miiphy.h>
+#include <lxt971a.h>
+#include <asm/arch/emac_defs.h>
+#include "../../../drivers/net/davinci_emac.h"
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_CMD_NET
+
+int lxt972_is_phy_connected(int phy_addr)
+{
+       u_int16_t id1, id2;
+
+       if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
+               return(0);
+       if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
+               return(0);
+
+       if ((id1 == (0x0013)) && ((id2  & 0xfff0) == 0x78e0))
+               return(1);
+
+       return(0);
+}
+
+int lxt972_get_link_speed(int phy_addr)
+{
+       u_int16_t stat1, tmp;
+       volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
+
+       if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
+               return(0);
+
+       if (!(stat1 & PHY_LXT971_STAT2_LINK))   /* link up? */
+               return(0);
+
+       if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
+               return(0);
+
+       tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
+
+       davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
+       /* Read back */
+       if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
+               return(0);
+
+       /* Speed doesn't matter, there is no setting for it in EMAC... */
+       if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+               /* set DM644x EMAC for Full Duplex  */
+               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+                       EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+       } else {
+               /*set DM644x EMAC for Half Duplex  */
+               emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
+       }
+
+       return(1);
+}
+
+
+int lxt972_init_phy(int phy_addr)
+{
+       int ret = 1;
+
+       if (!lxt972_get_link_speed(phy_addr)) {
+               /* Try another time */
+               ret = lxt972_get_link_speed(phy_addr);
+       }
+
+       /* Disable PHY Interrupts */
+       davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
+
+       return(ret);
+}
+
+
+int lxt972_auto_negotiate(int phy_addr)
+{
+       u_int16_t tmp;
+
+       if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
+               return(0);
+
+       /* Restart Auto_negotiation  */
+       tmp |= BMCR_ANRESTART;
+       davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
+
+       /*check AutoNegotiate complete */
+       udelay (10000);
+       if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
+               return(0);
+
+       if (!(tmp & BMSR_ANEGCOMPLETE))
+               return(0);
+
+       return (lxt972_get_link_speed(phy_addr));
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
new file mode 100644 (file)
index 0000000..e18bdfc
--- /dev/null
@@ -0,0 +1,138 @@
+/*
+ * Miscelaneous DaVinci functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+int dram_init(void)
+{
+       /* dram_init must store complete ramsize in gd->ram_size */
+       gd->ram_size = get_ram_size(
+                       (void *)CONFIG_SYS_SDRAM_BASE,
+                       CONFIG_MAX_RAM_BANK_SIZE);
+       return 0;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].size = gd->ram_size;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
+ * Returns 1 if found, 0 otherwise.
+ */
+int dvevm_read_mac_address(uint8_t *buf)
+{
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+       /* Read MAC address. */
+       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
+               CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
+               goto i2cerr;
+
+       /* Check that MAC address is valid. */
+       if (!is_valid_ether_addr(buf))
+               goto err;
+
+       return 1; /* Found */
+
+i2cerr:
+       printf("Read from EEPROM @ 0x%02x failed\n",
+               CONFIG_SYS_I2C_EEPROM_ADDR);
+err:
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
+
+       return 0;
+}
+
+/*
+ * Set the mii mode as MII or RMII
+ */
+#if defined(CONFIG_SOC_DA8XX)
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+       int val;
+
+       val = readl(&davinci_syscfg_regs->cfgchip3);
+       if (mode_sel == 0)
+               val &= ~(1 << 8);
+       else
+               val |= (1 << 8);
+       writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+#endif
+/*
+ * If there is no MAC address in the environment, then it will be initialized
+ * (silently) from the value in the EEPROM.
+ */
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
+{
+       uint8_t env_enetaddr[6];
+       int ret;
+
+       ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
+       if (!ret) {
+               /*
+                * There is no MAC address in the environment, so we
+                * initialize it from the value in the EEPROM.
+                */
+               debug("### Setting environment from EEPROM MAC address = "
+                       "\"%pM\"\n",
+                       env_enetaddr);
+               ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
+       }
+       if (!ret)
+               printf("Failed to set mac address from EEPROM: %d\n", ret);
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#if defined(CONFIG_SOC_DA8XX)
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+       /*
+        * Mask all IRQs by clearing the global enable and setting
+        * the enable clear for all the 90 interrupts.
+        */
+       writel(0, &davinci_aintc_regs->ger);
+
+       writel(0, &davinci_aintc_regs->hier);
+
+       writel(0xffffffff, &davinci_aintc_regs->ecr1);
+       writel(0xffffffff, &davinci_aintc_regs->ecr2);
+       writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+/*
+ * Enable PSC for various peripherals.
+ */
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+                                   const int n_items)
+{
+       int i;
+
+       for (i = 0; i < n_items; i++)
+               lpsc_on(item[i].lpsc_no);
+
+       return 0;
+}
+#endif
diff --git a/arch/arm/mach-davinci/pinmux.c b/arch/arm/mach-davinci/pinmux.c
new file mode 100644 (file)
index 0000000..e9d8c87
--- /dev/null
@@ -0,0 +1,90 @@
+/*
+ * DaVinci pinmux functions.
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+
+/*
+ * Change the setting of a pin multiplexer field.
+ *
+ * Takes an array of pinmux settings similar to:
+ *
+ * struct pinmux_config uart_pins[] = {
+ *     { &davinci_syscfg_regs->pinmux[8], 2, 7 },
+ *     { &davinci_syscfg_regs->pinmux[9], 2, 0 }
+ * };
+ *
+ * Stepping through the array, each pinmux[n] register has the given value
+ * set in the pin mux field specified.
+ *
+ * The number of pins in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Returns 0 if all field numbers and values are in the correct range,
+ * else returns -1.
+ */
+int davinci_configure_pin_mux(const struct pinmux_config *pins,
+                             const int n_pins)
+{
+       int i;
+
+       /* check for invalid pinmux values */
+       for (i = 0; i < n_pins; i++) {
+               if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
+                   (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
+                       return -1;
+       }
+
+       /* configure the pinmuxes */
+       for (i = 0; i < n_pins; i++) {
+               const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
+               const unsigned int value = pins[i].value << offset;
+               const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
+               const dv_reg *mux = pins[i].mux;
+
+               writel(value | (readl(mux) & (~mask)), mux);
+       }
+
+       return 0;
+}
+
+/*
+ * Configure multiple pinmux resources.
+ *
+ * Takes an pinmux_resource array of pinmux_config and pin counts:
+ *
+ * const struct pinmux_resource pinmuxes[] = {
+ *     PINMUX_ITEM(uart_pins),
+ *     PINMUX_ITEM(i2c_pins),
+ * };
+ *
+ * The number of items in the array must be passed (ARRAY_SIZE can provide
+ * this value conveniently).
+ *
+ * Each item entry is configured in the defined order. If configuration
+ * of any item fails, -1 is returned and none of the following items are
+ * configured. On success, 0 is returned.
+ */
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+                                   const int n_items)
+{
+       int i;
+
+       for (i = 0; i < n_items; i++) {
+               if (davinci_configure_pin_mux(item[i].pins,
+                                             item[i].n_pins) != 0)
+                       return -1;
+       }
+
+       return 0;
+}
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
new file mode 100644 (file)
index 0000000..8d99e2e
--- /dev/null
@@ -0,0 +1,160 @@
+/*
+ * Power and Sleep Controller (PSC) functions.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * The PSC manages three inputs to a "module" which may be a peripheral or
+ * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
+ * its power domain.  For our purposes, we only care whether clock and power
+ * are active, and the module is out of reset.
+ *
+ * DaVinci chips may include two separate power domains: "Always On" and "DSP".
+ * Chips without a DSP generally have only one domain.
+ *
+ * The "Always On" power domain is always on when the chip is on, and is
+ * powered by the VDD pins (on DM644X). The majority of DaVinci modules
+ * lie within the "Always On" power domain.
+ *
+ * A separate domain called the "DSP" domain houses the C64x+ and other video
+ * hardware such as VICP. In some chips, the "DSP" domain is not always on.
+ * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
+ */
+
+/* Works on Always On power domain only (no PD argument) */
+static void lpsc_transition(unsigned int id, unsigned int state)
+{
+       dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+#ifdef CONFIG_SOC_DA8XX
+       struct davinci_psc_regs *psc_regs;
+#endif
+
+#ifndef CONFIG_SOC_DA8XX
+       if (id >= DAVINCI_LPSC_GEM)
+               return;                 /* Don't work on DSP Power Domain */
+
+       mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+       mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+       ptstat = REG_P(PSC_PTSTAT);
+       ptcmd = REG_P(PSC_PTCMD);
+#else
+       if (id < DAVINCI_LPSC_PSC1_BASE) {
+               if (id >= PSC_PSC0_MODULE_ID_CNT)
+                       return;
+               psc_regs = davinci_psc0_regs;
+               mdstat = &psc_regs->psc0.mdstat[id];
+               mdctl = &psc_regs->psc0.mdctl[id];
+       } else {
+               id -= DAVINCI_LPSC_PSC1_BASE;
+               if (id >= PSC_PSC1_MODULE_ID_CNT)
+                       return;
+               psc_regs = davinci_psc1_regs;
+               mdstat = &psc_regs->psc1.mdstat[id];
+               mdctl = &psc_regs->psc1.mdctl[id];
+       }
+       ptstat = &psc_regs->ptstat;
+       ptcmd = &psc_regs->ptcmd;
+#endif
+
+       while (readl(ptstat) & 0x01)
+               continue;
+
+       if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+               return; /* Already in that state */
+
+       writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
+
+       switch (id) {
+#ifdef CONFIG_SOC_DM644X
+       /* Special treatment for some modules as for sprue14 p.7.4.2 */
+       case DAVINCI_LPSC_VPSSSLV:
+       case DAVINCI_LPSC_EMAC:
+       case DAVINCI_LPSC_EMAC_WRAPPER:
+       case DAVINCI_LPSC_MDIO:
+       case DAVINCI_LPSC_USB:
+       case DAVINCI_LPSC_ATA:
+       case DAVINCI_LPSC_VLYNQ:
+       case DAVINCI_LPSC_UHPI:
+       case DAVINCI_LPSC_DDR_EMIF:
+       case DAVINCI_LPSC_AEMIF:
+       case DAVINCI_LPSC_MMC_SD:
+       case DAVINCI_LPSC_MEMSTICK:
+       case DAVINCI_LPSC_McBSP:
+       case DAVINCI_LPSC_GPIO:
+               writel(readl(mdctl) | 0x200, mdctl);
+               break;
+#endif
+       }
+
+       writel(0x01, ptcmd);
+
+       while (readl(ptstat) & 0x01)
+               continue;
+       while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
+               continue;
+}
+
+void lpsc_on(unsigned int id)
+{
+       lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+       lpsc_transition(id, 0x01);
+}
+
+void lpsc_disable(unsigned int id)
+{
+       lpsc_transition(id, 0x0);
+}
+
+/* Not all DaVinci chips have a DSP power domain. */
+#ifdef CONFIG_SOC_DM644X
+
+/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+void dsp_on(void)
+{
+       int i;
+
+       if (REG(PSC_PDSTAT1) & 0x1f)
+               return;                 /* Already on */
+
+       REG(PSC_GBLCTL) |= 0x01;
+       REG(PSC_PDCTL1) |= 0x01;
+       REG(PSC_PDCTL1) &= ~0x100;
+       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+       REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+       REG(PSC_PTCMD) = 0x02;
+
+       for (i = 0; i < 100; i++) {
+               if (REG(PSC_EPCPR) & 0x02)
+                       break;
+       }
+
+       REG(PSC_CHP_SHRTSW) = 0x01;
+       REG(PSC_PDCTL1) |= 0x100;
+       REG(PSC_EPCCR) = 0x02;
+
+       for (i = 0; i < 100; i++) {
+               if (!(REG(PSC_PTSTAT) & 0x02))
+                       break;
+       }
+
+       REG(PSC_GBLCTL) &= ~0x1f;
+}
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+#endif /* have a DSP */
diff --git a/arch/arm/mach-davinci/reset.c b/arch/arm/mach-davinci/reset.c
new file mode 100644 (file)
index 0000000..6b0f154
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ *  Processor reset using WDT.
+ *
+ * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/arch/hardware.h>
+
+void reset_cpu(unsigned long a)
+{
+       struct davinci_timer *const wdttimer =
+               (struct davinci_timer *)DAVINCI_WDOG_BASE;
+       writel(0x08, &wdttimer->tgcr);
+       writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
+       writel(0, &wdttimer->tim12);
+       writel(0, &wdttimer->tim34);
+       writel(0, &wdttimer->prd12);
+       writel(0, &wdttimer->prd34);
+       writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
+       writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
+       writel(0xa5c64000, &wdttimer->wdtcr);
+       writel(0xda7e4000, &wdttimer->wdtcr);
+       writel(0x4000, &wdttimer->wdtcr);
+       while (1)
+               /*nothing*/;
+}
diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c
new file mode 100644 (file)
index 0000000..49349da
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <spl.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <asm/arch/dm365_lowlevel.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <spi_flash.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
+void puts(const char *str)
+{
+       while (*str)
+               putc(*str++);
+}
+
+void putc(char c)
+{
+       if (c == '\n')
+               NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
+
+       NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
+}
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
+void spl_board_init(void)
+{
+#ifdef CONFIG_SOC_DM365
+       dm36x_lowlevel_init(0);
+#endif
+#ifdef CONFIG_SOC_DA8XX
+       arch_cpu_init();
+#endif
+       preloader_console_init();
+}
+
+u32 spl_boot_mode(void)
+{
+       return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_NAND_SIMPLE
+       return BOOT_DEVICE_NAND;
+#elif defined(CONFIG_SPL_SPI_LOAD)
+       return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_SPL_MMC_LOAD)
+       return BOOT_DEVICE_MMC1;
+#else
+       puts("Unknown boot device\n");
+       hang();
+#endif
+}
diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c
new file mode 100644 (file)
index 0000000..c7d0652
--- /dev/null
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct davinci_timer * const timer =
+       (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+#define TIM_CLK_DIV    16
+
+int timer_init(void)
+{
+       /* We are using timer34 in unchained 32-bit mode, full speed */
+       writel(0x0, &timer->tcr);
+       writel(0x0, &timer->tgcr);
+       writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+       writel(0x0, &timer->tim34);
+       writel(TIMER_LOAD_VAL, &timer->prd34);
+       writel(2 << 22, &timer->tcr);
+       gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+       gd->arch.timer_reset_value = 0;
+
+       return(0);
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+       unsigned long now = readl(&timer->tim34);
+
+       /* increment tbu if tbl has rolled over */
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
+
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+ulong get_timer(ulong base)
+{
+       unsigned long long timer_diff;
+
+       timer_diff = get_ticks() - gd->arch.timer_reset_value;
+
+       return lldiv(timer_diff,
+                    (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+       unsigned long long endtime;
+
+       endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+                       1000000UL);
+       endtime += get_ticks();
+
+       while (get_ticks() < endtime)
+               ;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return gd->arch.timer_rate_hz;
+}
+
+#ifdef CONFIG_HW_WATCHDOG
+static struct davinci_timer * const wdttimer =
+       (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
+
+/*
+ * See prufw2.pdf for using Timer as a WDT
+ */
+void davinci_hw_watchdog_enable(void)
+{
+       writel(0x0, &wdttimer->tcr);
+       writel(0x0, &wdttimer->tgcr);
+       /* TIMMODE = 2h */
+       writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
+       writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
+       writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
+       writel(2 << 22, &wdttimer->tcr);
+       writel(0x0, &wdttimer->tim12);
+       writel(0x0, &wdttimer->tim34);
+       /* set WDEN bit, WDKEY 0xa5c6 */
+       writel(0xa5c64000, &wdttimer->wdtcr);
+       /* clear counter register */
+       writel(0xda7e4000, &wdttimer->wdtcr);
+}
+
+void davinci_hw_watchdog_reset(void)
+{
+       writel(0xa5c64000, &wdttimer->wdtcr);
+       writel(0xda7e4000, &wdttimer->wdtcr);
+}
+#endif