OMAP3: set the core dpll clk rate in its set_rate function
authorAvinash H.M <avinashhm@ti.com>
Mon, 9 May 2011 12:29:40 +0000 (12:29 +0000)
committerTony Lindgren <tony@atomide.com>
Fri, 13 May 2011 14:08:18 +0000 (07:08 -0700)
The debug l3_ick/rate is not displaying the actual rate of the clock in
hardware. This is because, the core dpll set_rate function doesn't update the
clk.rate. After fixing, the l3_ick/rate is displaying proper values.

Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
Signed-off-by: Avinash.H.M <avinashhm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Wamsley <paul@pwsan.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/clkt34xx_dpll3m2.c

index b2b1e37bb6bba3cefa5961f39d026c1a5f616d53..d6e34dd9e7e75c6dde4de60a004e319dd7f02547 100644 (file)
@@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                  0, 0, 0, 0);
+       clk->rate = rate;
 
        return 0;
 }