* Add ->mwdma_mask and ->swdma_mask to ide_pci_device_t.
* Set ide_hwif_t DMA masks using DMA masks from ide_pci_device_t in
setup-pci.c::ide_pci_setup_ports() (iff DMA base is valid and ->init_hwif
method may still override them).
* Convert IDE PCI host drivers to use ide_pci_device_t DMA masks.
While at it:
* Use ATA_{UDMA,MWDMA,SWDMA}* defines.
* hpt34x.c: add separate ide_pci_device_t instances for HPT343 and HPT345.
* serverworks.c: fix DMA masks being set before checking DMA base.
v2:
* Add missing masks to DECLARE_GENERIC_PCI_DEV() macro.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = hwif->cds->udma_mask;
- hwif->mwdma_mask = 0x07;
-
hwif->dma_lost_irq = &aec62xx_dma_lost_irq;
if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x07, /* udma0-2 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
},{ /* 1 */
.name = "AEC6260",
.init_setup = init_setup_aec62xx,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x1f, /* udma0-4 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
},{ /* 2 */
.name = "AEC6260R",
.init_setup = init_setup_aec62xx,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_NO_ATAPI_DMA,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x1f, /* udma0-4 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
},{ /* 3 */
.name = "AEC6280",
.init_setup = init_setup_aec6x80,
.init_hwif = init_hwif_aec62xx,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 4 */
.name = "AEC6280R",
.init_setup = init_setup_aec6x80,
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
}
};
if (m5229_revision <= 0x20)
hwif->ultra_mask = 0x00; /* no udma */
else if (m5229_revision < 0xC2)
- hwif->ultra_mask = 0x07; /* udma0-2 */
+ hwif->ultra_mask = ATA_UDMA2;
else if (m5229_revision == 0xC2 || m5229_revision == 0xC3)
- hwif->ultra_mask = 0x1f; /* udma0-4 */
+ hwif->ultra_mask = ATA_UDMA4;
else if (m5229_revision == 0xC4)
- hwif->ultra_mask = 0x3f; /* udma0-5 */
+ hwif->ultra_mask = ATA_UDMA5;
else
- hwif->ultra_mask = 0x7f; /* udma0-6 */
-
- hwif->mwdma_mask = 0x07;
- hwif->swdma_mask = 0x07;
+ hwif->ultra_mask = ATA_UDMA6;
hwif->dma_setup = &ali15x3_dma_setup;
.init_dma = init_dma_ali15x3,
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
};
/**
return;
hwif->ultra_mask = amd_config->udma_mask;
- hwif->mwdma_mask = 0x07;
- if ((amd_config->flags & AMD_BAD_SWDMA) == 0)
- hwif->swdma_mask = 0x07;
+ if (amd_config->flags & AMD_BAD_SWDMA)
+ hwif->swdma_mask = 0x00;
if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
if ((amd_80w >> hwif->channel) & 1)
IDE_HFLAG_POST_SET_MODE | \
IDE_HFLAG_BOOTABLE, \
.pio_mask = ATA_PIO5, \
+ .swdma_mask = ATA_SWDMA2, \
+ .mwdma_mask = ATA_MWDMA2, \
}
#define DECLARE_NV_DEV(name_str) \
IDE_HFLAG_POST_SET_MODE | \
IDE_HFLAG_BOOTABLE, \
.pio_mask = ATA_PIO5, \
+ .swdma_mask = ATA_SWDMA2, \
+ .mwdma_mask = ATA_MWDMA2, \
}
static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
if (!hwif->dma_base)
return;
- hwif->ultra_mask = 0x3f;
- hwif->mwdma_mask = 0x07;
-
pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 1 */
.name = "SB600_PATA",
.init_hwif = init_hwif_atiixp,
.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},
};
if (!hwif->dma_base)
return;
- hwif->mwdma_mask = 0x07;
- hwif->ultra_mask = hwif->cds->udma_mask;
-
/*
* UltraDMA only supported on PCI646U and PCI646U2, which
* correspond to revisions 0x03, 0x05 and 0x07 respectively.
.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
.host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
+ .mwdma_mask = ATA_MWDMA2,
.udma_mask = 0x00, /* no udma */
},{ /* 1 */
.name = "CMD646",
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
.host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
- .udma_mask = 0x07, /* udma0-2 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
},{ /* 2 */
.name = "CMD648",
.init_setup = init_setup_cmd64x,
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
.host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
- .udma_mask = 0x1f, /* udma0-4 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
},{ /* 3 */
.name = "CMD649",
.init_setup = init_setup_cmd64x,
.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
.host_flags = IDE_HFLAG_ABUSE_PREFETCH | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
}
};
}
hwif->ide_dma_on = &cs5520_dma_on;
-
- hwif->ultra_mask = 0;
- hwif->swdma_mask = 0;
- hwif->mwdma_mask = 0;
}
#define DECLARE_CS_DEV(name_str) \
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = 0x07;
- hwif->mwdma_mask = 0x07;
-
hwif->udma_filter = cs5530_udma_filter;
}
.init_hwif = init_hwif_cs5530,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
};
static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = 0x1F;
- hwif->mwdma_mask = 0x07;
-
hwif->cbl = cs5535_cable_detect(hwif->pci_dev);
}
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
};
static int __devinit cs5535_init_one(struct pci_dev *dev,
return;
}
- hwif->mwdma_mask = 0x04;
- hwif->swdma_mask = 0x04;
-
hwif->ide_dma_on = &cy82c693_ide_dma_on;
}
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .swdma_mask = ATA_SWDMA2_ONLY,
+ .mwdma_mask = ATA_MWDMA2_ONLY,
};
static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
default:
break;
}
-
- if (!(hwif->dma_base))
- return;
-
- hwif->ultra_mask = 0x7f;
- hwif->mwdma_mask = 0x07;
- hwif->swdma_mask = 0x07;
}
#define DECLARE_GENERIC_PCI_DEV(name_str, dma_setting) \
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | \
dma_setting | \
IDE_HFLAG_BOOTABLE, \
+ .swdma_mask = ATA_SWDMA2, \
+ .mwdma_mask = ATA_MWDMA2, \
+ .udma_mask = ATA_UDMA6, \
}
static ide_pci_device_t generic_chipsets[] __devinitdata = {
.enablebits = {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_BOOTABLE,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
},
/* 2 */ DECLARE_GENERIC_PCI_DEV("SAMURAI", 0),
.init_hwif = init_hwif_generic,
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_OFF_BOARD,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
},
/* 11 */ DECLARE_GENERIC_PCI_DEV("Piccolo0102", IDE_HFLAG_NO_AUTODMA),
.init_hwif = init_hwif_generic,
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_OFF_BOARD,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
}
};
static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
{
- u16 pcicmd = 0;
-
hwif->set_pio_mode = &hpt34x_set_pio_mode;
hwif->set_dma_mode = &hpt34x_set_mode;
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
+}
- pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
-
- if (!hwif->dma_base)
- return;
-
+static ide_pci_device_t hpt34x_chipsets[] __devinitdata = {
+ { /* 0 */
+ .name = "HPT343",
+ .init_chipset = init_chipset_hpt34x,
+ .init_hwif = init_hwif_hpt34x,
+ .extra = 16,
+ .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
+ IDE_HFLAG_NO_AUTODMA,
+ .pio_mask = ATA_PIO5,
+ },
+ { /* 1 */
+ .name = "HPT345",
+ .init_chipset = init_chipset_hpt34x,
+ .init_hwif = init_hwif_hpt34x,
+ .extra = 16,
+ .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
+ IDE_HFLAG_NO_AUTODMA |
+ IDE_HFLAG_OFF_BOARD,
+ .pio_mask = ATA_PIO5,
#ifdef CONFIG_HPT34X_AUTODMA
- if ((pcicmd & PCI_COMMAND_MEMORY) == 0)
- return;
-
- hwif->ultra_mask = 0x07;
- hwif->mwdma_mask = 0x07;
- hwif->swdma_mask = 0x07;
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
#endif
-}
-
-static ide_pci_device_t hpt34x_chipset __devinitdata = {
- .name = "HPT34X",
- .init_chipset = init_chipset_hpt34x,
- .init_hwif = init_hwif_hpt34x,
- .extra = 16,
- .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA,
- .pio_mask = ATA_PIO5,
+ }
};
static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
- ide_pci_device_t *d = &hpt34x_chipset;
- static char *chipset_names[] = {"HPT343", "HPT345"};
+ ide_pci_device_t *d;
u16 pcicmd = 0;
pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
- d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
- if (pcicmd & PCI_COMMAND_MEMORY)
- d->host_flags |= IDE_HFLAG_OFF_BOARD;
- else
- d->host_flags &= ~IDE_HFLAG_OFF_BOARD;
+ d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
return ide_setup_pci_device(dev, d);
}
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = hwif->cds->udma_mask;
- hwif->mwdma_mask = 0x07;
-
/*
* The HPT37x uses the CBLID pins as outputs for MA15/MA16
* address lines to access an external EEPROM. To read valid
.extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 1 */
.name = "HPT372A",
.init_setup = init_setup_hpt372a,
.extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 2 */
.name = "HPT302",
.init_setup = init_setup_hpt302,
.extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 3 */
.name = "HPT371",
.init_setup = init_setup_hpt371,
.extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 4 */
.name = "HPT374",
.init_setup = init_setup_hpt374,
.extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 5 */
.name = "HPT372N",
.init_setup = init_setup_hpt372n,
.extra = 240,
.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
}
};
if (!hwif->dma_base)
return;
- hwif->ultra_mask = 0x7f;
- hwif->mwdma_mask = 0x06;
- hwif->swdma_mask = 0x04;
-
pci_read_config_byte(hwif->pci_dev, 0x42, ®42h);
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
.host_flags = IDE_HFLAG_SINGLE | \
IDE_HFLAG_BOOTABLE, \
.pio_mask = ATA_PIO4, \
+ .swdma_mask = ATA_SWDMA2_ONLY, \
+ .mwdma_mask = ATA_MWDMA12_ONLY, \
+ .udma_mask = ATA_UDMA6, \
}
static ide_pci_device_t it8213_chipsets[] __devinitdata = {
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = 0x7f;
- hwif->mwdma_mask = 0x07;
+ hwif->ultra_mask = ATA_UDMA6;
+ hwif->mwdma_mask = ATA_MWDMA2;
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = ata66_it821x(hwif);
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = 0x7f;
- hwif->mwdma_mask = 0x07;
-
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = ata66_jmicron(hwif);
}
.host_flags = IDE_HFLAG_BOOTABLE,
.enablebits = { { 0x40, 0x01, 0x01 }, { 0x40, 0x10, 0x10 } },
.pio_mask = ATA_PIO5,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
};
/**
hwif->drives[1].drive_data = PIO_DONT_KNOW;
hwif->set_pio_mode = &opti621_set_pio_mode;
-
- if (!(hwif->dma_base))
- return;
-
- hwif->mwdma_mask = 0x07;
- hwif->swdma_mask = 0x07;
}
static ide_pci_device_t opti621_chipsets[] __devinitdata = {
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO3,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 1 */
.name = "OPTI621X",
.init_hwif = init_hwif_opti621,
.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO3,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
}
};
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = hwif->cds->udma_mask;
- hwif->mwdma_mask = 0x07;
-
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = pdcnew_cable_detect(hwif);
}
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 1 */
.name = "PDC20269",
.init_setup = init_setup_pdcnew,
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x7f, /* udma0-6*/
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
},{ /* 2 */
.name = "PDC20270",
.init_setup = init_setup_pdc20270,
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 3 */
.name = "PDC20271",
.init_setup = init_setup_pdcnew,
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x7f, /* udma0-6*/
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
},{ /* 4 */
.name = "PDC20275",
.init_setup = init_setup_pdcnew,
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x7f, /* udma0-6*/
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
},{ /* 5 */
.name = "PDC20276",
.init_setup = init_setup_pdc20276,
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x7f, /* udma0-6*/
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
},{ /* 6 */
.name = "PDC20277",
.init_setup = init_setup_pdcnew,
.init_hwif = init_hwif_pdc202new,
.host_flags = IDE_HFLAG_POST_SET_MODE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x7f, /* udma0-6*/
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA6,
}
};
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = hwif->cds->udma_mask;
- hwif->mwdma_mask = 0x07;
-
hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
hwif->dma_timeout = &pdc202xx_dma_timeout;
.extra = 16,
.host_flags = IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x07, /* udma0-2 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
},{ /* 1 */
.name = "PDC20262",
.init_setup = init_setup_pdc202ata4,
.extra = 48,
.host_flags = IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x1f, /* udma0-4 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
},{ /* 2 */
.name = "PDC20263",
.init_setup = init_setup_pdc202ata4,
.extra = 48,
.host_flags = IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x1f, /* udma0-4 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
},{ /* 3 */
.name = "PDC20265",
.init_setup = init_setup_pdc20265,
.extra = 48,
.host_flags = IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 4 */
.name = "PDC20267",
.init_setup = init_setup_pdc202xx,
.extra = 48,
.host_flags = IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
- .udma_mask = 0x3f, /* udma0-5 */
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
}
};
if (piix_is_ichx(hwif->pci_dev))
hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
- hwif->ultra_mask = hwif->cds->udma_mask;
- hwif->mwdma_mask = 0x06;
- hwif->swdma_mask = 0x04;
-
if (hwif->ultra_mask & 0x78) {
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = piix_cable_detect(hwif);
.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
.host_flags = IDE_HFLAG_BOOTABLE, \
.pio_mask = ATA_PIO4, \
+ .swdma_mask = ATA_SWDMA2_ONLY, \
+ .mwdma_mask = ATA_MWDMA12_ONLY, \
.udma_mask = udma, \
}
static ide_pci_device_t piix_pci_info[] __devinitdata = {
- /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
- /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
+ /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
+ /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
/* 2 */
{ /*
.pio_mask = ATA_PIO4,
},
- /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
- /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
- /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */
- /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
- /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */
- /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */
- /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
- /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */
- /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */
- /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */
- /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */
- /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
- /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
- /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */
- /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
- /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */
- /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
- /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */
- /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */
- /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
- /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */
- /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */
+ /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
+ /* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
+ /* 5 */ DECLARE_PIIX_DEV("ICH0", ATA_UDMA2),
+ /* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
+ /* 7 */ DECLARE_PIIX_DEV("ICH", ATA_UDMA4),
+ /* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
+ /* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
+ /* 10 */ DECLARE_PIIX_DEV("ICH2", ATA_UDMA5),
+ /* 11 */ DECLARE_PIIX_DEV("ICH2M", ATA_UDMA5),
+ /* 12 */ DECLARE_PIIX_DEV("ICH3M", ATA_UDMA5),
+ /* 13 */ DECLARE_PIIX_DEV("ICH3", ATA_UDMA5),
+ /* 14 */ DECLARE_PIIX_DEV("ICH4", ATA_UDMA5),
+ /* 15 */ DECLARE_PIIX_DEV("ICH5", ATA_UDMA5),
+ /* 16 */ DECLARE_PIIX_DEV("C-ICH", ATA_UDMA5),
+ /* 17 */ DECLARE_PIIX_DEV("ICH4", ATA_UDMA5),
+ /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", ATA_UDMA5),
+ /* 19 */ DECLARE_PIIX_DEV("ICH5", ATA_UDMA5),
+ /* 20 */ DECLARE_PIIX_DEV("ICH6", ATA_UDMA5),
+ /* 21 */ DECLARE_PIIX_DEV("ICH7", ATA_UDMA5),
+ /* 22 */ DECLARE_PIIX_DEV("ICH4", ATA_UDMA5),
+ /* 23 */ DECLARE_PIIX_DEV("ESB2", ATA_UDMA5),
+ /* 24 */ DECLARE_PIIX_DEV("ICH8M", ATA_UDMA5),
};
/**
hwif->udma_filter = sc1200_udma_filter;
hwif->ide_dma_end = &sc1200_ide_dma_end;
-
- hwif->ultra_mask = 0x07;
- hwif->mwdma_mask = 0x07;
}
static ide_pci_device_t sc1200_chipset __devinitdata = {
.host_flags = IDE_HFLAG_ABUSE_DMA_MODES | IDE_HFLAG_POST_SET_MODE |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA2,
};
static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
if ((drive->media != ide_disk) && (mask & 0xE0)) {
printk(KERN_INFO "%s: limit %s to UDMA4\n",
SCC_PATA_NAME, drive->name);
- mask = 0x1F;
+ mask = ATA_UDMA4;
}
return mask;
hwif->drives[0].autotune = IDE_TUNE_AUTO;
hwif->drives[1].autotune = IDE_TUNE_AUTO;
- if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
- hwif->ultra_mask = 0x7f; /* 133MHz */
- } else {
- hwif->ultra_mask = 0x3f; /* 100MHz */
- }
- hwif->mwdma_mask = 0x00;
- hwif->swdma_mask = 0x00;
+ if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
+ hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
+ else
+ hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
/* we support 80c cable only. */
hwif->cbl = ATA_CBL_PATA80;
hwif->set_dma_mode = &svwks_set_dma_mode;
hwif->udma_filter = &svwks_udma_filter;
- if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
- hwif->ultra_mask = 0x3f;
-
- hwif->mwdma_mask = 0x07;
-
hwif->drives[0].autotune = 1;
hwif->drives[1].autotune = 1;
.init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
},{ /* 1 */
.name = "SvrWks CSB5",
.init_setup = init_setup_svwks,
.init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 2 */
.name = "SvrWks CSB6",
.init_setup = init_setup_csb6,
.init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 3 */
.name = "SvrWks CSB6",
.init_setup = init_setup_csb6,
.init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
},{ /* 4 */
.name = "SvrWks HT1000",
.init_setup = init_setup_svwks,
.init_hwif = init_hwif_svwks,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA5,
}
};
if (hwif->dma_base == 0)
return;
- hwif->mwdma_mask = 0x04;
+ hwif->mwdma_mask = ATA_MWDMA2_ONLY;
hwif->dma_setup = &sgiioc4_ide_dma_setup;
hwif->dma_start = &sgiioc4_ide_dma_start;
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = 0x7f;
- hwif->mwdma_mask = 0x07;
-
if (is_sata(hwif))
hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
.fixup = siimage_fixup, \
.host_flags = IDE_HFLAG_BOOTABLE, \
.pio_mask = ATA_PIO4, \
+ .mwdma_mask = ATA_MWDMA2, \
+ .udma_mask = ATA_UDMA6, \
}
static ide_pci_device_t siimage_chipsets[] __devinitdata = {
return;
hwif->ultra_mask = udma_rates[chipset_family];
- hwif->mwdma_mask = 0x07;
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = ata66_sis5513(hwif);
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
.host_flags = IDE_HFLAG_NO_AUTODMA | IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
};
static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
return;
}
- hwif->mwdma_mask = 0x07;
+ hwif->mwdma_mask = ATA_MWDMA2;
hwif->ide_dma_on = &sl82c105_ide_dma_on;
hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
if (hwif->dma_base == 0)
return;
- hwif->ultra_mask = 0x1f;
- hwif->mwdma_mask = 0x06;
- hwif->swdma_mask = 0x04;
-
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
/* bit[0(1)]: 0:80, 1:40 */
hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .swdma_mask = ATA_SWDMA2_ONLY,
+ .mwdma_mask = ATA_MWDMA12_ONLY,
+ .udma_mask = ATA_UDMA4,
};
static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
/* Sector Count Register limit */
hwif->rqsize = 0xffff;
- hwif->ultra_mask = 0x1f;
- hwif->mwdma_mask = 0x07;
-
hwif->dma_start = &tc86c001_dma_start;
if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
.init_hwif = init_hwif_tc86c001,
.host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD,
.pio_mask = ATA_PIO4,
+ .mwdma_mask = ATA_MWDMA2,
+ .udma_mask = ATA_UDMA4,
};
static int __devinit tc86c001_init_one(struct pci_dev *dev,
{
hwif->set_pio_mode = &triflex_set_pio_mode;
hwif->set_dma_mode = &triflex_set_mode;
-
- if (hwif->dma_base == 0)
- return;
-
- hwif->mwdma_mask = 0x07;
- hwif->swdma_mask = 0x07;
}
static ide_pci_device_t triflex_device __devinitdata = {
.enablebits = {{0x80, 0x01, 0x01}, {0x80, 0x02, 0x02}},
.host_flags = IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO4,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
};
static int __devinit triflex_init_one(struct pci_dev *dev,
return;
hwif->ultra_mask = vdev->via_config->udma_mask;
- hwif->mwdma_mask = 0x07;
- hwif->swdma_mask = 0x07;
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = via82cxxx_cable_detect(hwif);
IDE_HFLAG_NO_AUTODMA |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
},{ /* 1 */
.name = "VP_IDE",
.init_chipset = init_chipset_via82cxxx,
IDE_HFLAG_POST_SET_MODE |
IDE_HFLAG_BOOTABLE,
.pio_mask = ATA_PIO5,
+ .swdma_mask = ATA_SWDMA2,
+ .mwdma_mask = ATA_MWDMA2,
}
};
hwif->host_flags = d->host_flags;
hwif->pio_mask = d->pio_mask;
+ if (hwif->dma_base) {
+ hwif->swdma_mask = d->swdma_mask;
+ hwif->mwdma_mask = d->mwdma_mask;
+ hwif->ultra_mask = d->udma_mask;
+ }
+
if (d->init_hwif)
/* Call chipset-specific routine
* for each enabled hwif
struct ide_pci_device_s *next;
u32 host_flags;
u8 pio_mask;
+ u8 swdma_mask;
+ u8 mwdma_mask;
u8 udma_mask;
} ide_pci_device_t;