--- /dev/null
+From 5e396bb05b89e23e98e6d75749b77502e68210a4 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 22 Aug 2020 18:19:20 +0200
+Subject: [PATCH] ARM: dts: BCM5301X: Specify uart2 in the DT
+
+The BCM53016 in the Meraki MR32 utilizes the third "uart2"
+to connect to a on-board Bluetooth-LE 4.0 BCM20732 chip.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Reviewed-by: Scott Branden <scott.branden@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -392,6 +392,15 @@
+ reg = <0x18105000 0x1000>;
+ };
+
++ uart2: serial@18008000 {
++ compatible = "ns16550a";
++ reg = <0x18008000 0x20>;
++ clocks = <&iprocslow>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
+ i2c0: i2c@18009000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x18009000 0x50>;
--- /dev/null
+From c4cd6fcae46fd14aed8665b7cf66d0954765a873 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sat, 22 Aug 2020 18:19:21 +0200
+Subject: [PATCH] ARM: dts: BCM5301X: Specify pcie2 in the DT
+
+The SoC supports three pcie ports. Currently, only
+pcie0 and pcie1 are enabled. This patch adds the
+pcie2 port as well.
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Reviewed-by: Scott Branden <scott.branden@broadcom.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -252,6 +252,10 @@
+ reg = <0x00013000 0x1000>;
+ };
+
++ pcie2: pcie@14000 {
++ reg = <0x00014000 0x1000>;
++ };
++
+ usb2: usb2@21000 {
+ reg = <0x00021000 0x1000>;
+