drm/amdgpu: rename amdgpu_gpu_recover
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Dec 2017 21:40:49 +0000 (16:40 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 18 Dec 2017 15:59:58 +0000 (10:59 -0500)
add device to the name for consistency.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

index d4abb7f04a86f4f42231e39b2a767fc148e29742..04e5498929c3ef68b84ced5363b43a000d9ab588 100644 (file)
@@ -1887,7 +1887,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 
 /* Common functions */
-int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job, bool force);
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+                             struct amdgpu_job* job, bool force);
 bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
 bool amdgpu_device_need_post(struct amdgpu_device *adev);
index 0080776c493641a6db925dbcd7fa7e0d274bdf60..cfeceab292249bfc63275423a11d33f08ccfcf2f 100644 (file)
@@ -2611,7 +2611,7 @@ error:
 }
 
 /**
- * amdgpu_gpu_recover - reset the asic and recover scheduler
+ * amdgpu_device_gpu_recover - reset the asic and recover scheduler
  *
  * @adev: amdgpu device pointer
  * @job: which job trigger hang
@@ -2620,7 +2620,8 @@ error:
  * Attempt to reset the GPU if it has hung (all asics).
  * Returns 0 for success or an error on failure.
  */
-int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job, bool force)
+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+                             struct amdgpu_job *job, bool force)
 {
        struct drm_atomic_state *state = NULL;
        uint64_t reset_flags = 0;
index da1510f65ee073f7bd228026942644d64b49aa58..008e1984b7e39b9d51a9021c0df5762d889d6506 100644 (file)
@@ -693,7 +693,7 @@ static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
        struct amdgpu_device *adev = dev->dev_private;
 
        seq_printf(m, "gpu recover\n");
-       amdgpu_gpu_recover(adev, NULL, true);
+       amdgpu_device_gpu_recover(adev, NULL, true);
 
        return 0;
 }
index c43643e8c8c885a4ed741749944063bd667ffc4a..56bcd59c3399a0a912ea1fa8f869c105b8827327 100644 (file)
@@ -88,7 +88,7 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work)
                                                  reset_work);
 
        if (!amdgpu_sriov_vf(adev))
-               amdgpu_gpu_recover(adev, NULL, false);
+               amdgpu_device_gpu_recover(adev, NULL, false);
 }
 
 /* Disable *all* interrupts */
index be8a437fad544924320de5f8edbdfcba1b917e01..56d9ee5013a99af8428b74d31ae9f2ab342f9b3b 100644 (file)
@@ -37,7 +37,7 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
                  atomic_read(&job->ring->fence_drv.last_seq),
                  job->ring->fence_drv.sync_seq);
 
-       amdgpu_gpu_recover(job->adev, job, false);
+       amdgpu_device_gpu_recover(job->adev, job, false);
 }
 
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
index 43e74ec93147aafc314c27f6739fa760354ae027..271452d3999a1d04b571a8ebc3e075a11b1f5db9 100644 (file)
@@ -253,7 +253,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
        }
 
        /* Trigger recovery due to world switch failure */
-       amdgpu_gpu_recover(adev, NULL, false);
+       amdgpu_device_gpu_recover(adev, NULL, false);
 }
 
 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
index af2d47e9abdc131197b8cb792d348f48bb0a56cd..9fc1c37344cebeaa468941d15552fe5e15b102e8 100644 (file)
@@ -521,7 +521,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
        }
 
        /* Trigger recovery due to world switch failure */
-       amdgpu_gpu_recover(adev, NULL, false);
+       amdgpu_device_gpu_recover(adev, NULL, false);
 }
 
 static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,