ramips: Fix for gpio falling interrupt mask

This patch fixes a wrong mask operation for the rt2880-compatible ralink devices.
The mask operation reads the actual flags and then logical combines it with the pin flag it want to set.
Unfortunally, for rising as for falling interrupt flags the actual flag status of the rising interrupts was used.
That caused a problem if you want to use more than one falling GPIO interrupt.
Now the correct (seperated) actual status is used for both, falling and rising.

Signed-off-by: Jonas Arndt <info@greenwire-elektronik.de>
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 43882

diff --git a/target/linux/ramips/patches-3.14/999-gpi_irq.patch b/target/linux/ramips/patches-3.14/999-gpi_irq.patch
new file mode 100644 (file)
index 0000000..a421570
--- /dev/null
+++ b/target/linux/ramips/patches-3.14/999-gpi_irq.patch
@@ -0,0 +1,42 @@
+--- a/drivers/gpio/gpio-ralink.c
++++ b/drivers/gpio/gpio-ralink.c
+@@ -148,14 +148,15 @@
+ {
+       struct ralink_gpio_chip *rg;
+       unsigned long flags;
+-      u32 val;
++      u32 rise, fall;
+ 
+       rg = (struct ralink_gpio_chip *) d->domain->host_data;
+-      val = rt_gpio_r32(rg, GPIO_REG_RENA);
++      rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++      fall = rt_gpio_r32(rg, GPIO_REG_FENA);
+ 
+       spin_lock_irqsave(&rg->lock, flags);
+-      rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
+-      rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
++      rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
++      rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
+       spin_unlock_irqrestore(&rg->lock, flags);
+ }
+ 
+@@ -163,14 +164,15 @@
+ {
+       struct ralink_gpio_chip *rg;
+       unsigned long flags;
+-      u32 val;
++      u32 rise, fall;
+ 
+       rg = (struct ralink_gpio_chip *) d->domain->host_data;
+-      val = rt_gpio_r32(rg, GPIO_REG_RENA);
++      rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++      fall = rt_gpio_r32(rg, GPIO_REG_FENA);
+ 
+       spin_lock_irqsave(&rg->lock, flags);
+-      rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
+-      rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
++      rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
++      rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
+       spin_unlock_irqrestore(&rg->lock, flags);
+ }
+